2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
138 #include "intel_drv.h"
140 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_ALIGN 4096
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define CTX_LRI_HEADER_0 0x01
160 #define CTX_CONTEXT_CONTROL 0x02
161 #define CTX_RING_HEAD 0x04
162 #define CTX_RING_TAIL 0x06
163 #define CTX_RING_BUFFER_START 0x08
164 #define CTX_RING_BUFFER_CONTROL 0x0a
165 #define CTX_BB_HEAD_U 0x0c
166 #define CTX_BB_HEAD_L 0x0e
167 #define CTX_BB_STATE 0x10
168 #define CTX_SECOND_BB_HEAD_U 0x12
169 #define CTX_SECOND_BB_HEAD_L 0x14
170 #define CTX_SECOND_BB_STATE 0x16
171 #define CTX_BB_PER_CTX_PTR 0x18
172 #define CTX_RCS_INDIRECT_CTX 0x1a
173 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
174 #define CTX_LRI_HEADER_1 0x21
175 #define CTX_CTX_TIMESTAMP 0x22
176 #define CTX_PDP3_UDW 0x24
177 #define CTX_PDP3_LDW 0x26
178 #define CTX_PDP2_UDW 0x28
179 #define CTX_PDP2_LDW 0x2a
180 #define CTX_PDP1_UDW 0x2c
181 #define CTX_PDP1_LDW 0x2e
182 #define CTX_PDP0_UDW 0x30
183 #define CTX_PDP0_LDW 0x32
184 #define CTX_LRI_HEADER_2 0x41
185 #define CTX_R_PWR_CLK_STATE 0x42
186 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
188 #define GEN8_CTX_VALID (1<<0)
189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
190 #define GEN8_CTX_FORCE_RESTORE (1<<2)
191 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
192 #define GEN8_CTX_PRIVILEGE (1<<8)
194 ADVANCED_CONTEXT = 0,
199 #define GEN8_CTX_MODE_SHIFT 3
202 FAULT_AND_HALT, /* Debug only */
204 FAULT_AND_CONTINUE /* Unsupported */
206 #define GEN8_CTX_ID_SHIFT 32
209 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
211 * @enable_execlists: value of i915.enable_execlists module parameter.
213 * Only certain platforms support Execlists (the prerequisites being
214 * support for Logical Ring Contexts and Aliasing PPGTT or better),
215 * and only when enabled via module parameter.
217 * Return: 1 if Execlists is supported and has to be enabled.
219 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
221 WARN_ON(i915.enable_ppgtt == -1);
223 if (enable_execlists == 0)
226 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
227 i915.use_mmio_flip >= 0)
234 * intel_execlists_ctx_id() - get the Execlists Context ID
235 * @ctx_obj: Logical Ring Context backing object.
237 * Do not confuse with ctx->id! Unfortunately we have a name overload
238 * here: the old context ID we pass to userspace as a handler so that
239 * they can refer to a context, and the new context ID we pass to the
240 * ELSP so that the GPU can inform us of the context status via
243 * Return: 20-bits globally unique context ID.
245 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
247 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
249 /* LRCA is required to be 4K aligned so the more significant 20 bits
250 * are globally unique */
254 static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
257 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
259 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
261 desc = GEN8_CTX_VALID;
262 desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
263 desc |= GEN8_CTX_L3LLC_COHERENT;
264 desc |= GEN8_CTX_PRIVILEGE;
266 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
268 /* TODO: WaDisableLiteRestore when we start using semaphore
269 * signalling between Command Streamers */
270 /* desc |= GEN8_CTX_FORCE_RESTORE; */
275 static void execlists_elsp_write(struct intel_engine_cs *ring,
276 struct drm_i915_gem_object *ctx_obj0,
277 struct drm_i915_gem_object *ctx_obj1)
279 struct drm_i915_private *dev_priv = ring->dev->dev_private;
283 /* XXX: You must always write both descriptors in the order below. */
285 temp = execlists_ctx_descriptor(ctx_obj1);
288 desc[1] = (u32)(temp >> 32);
291 temp = execlists_ctx_descriptor(ctx_obj0);
292 desc[3] = (u32)(temp >> 32);
295 /* Set Force Wakeup bit to prevent GT from entering C6 while ELSP writes
298 * The other problem is that we can't just call gen6_gt_force_wake_get()
299 * because that function calls intel_runtime_pm_get(), which might sleep.
300 * Instead, we do the runtime_pm_get/put when creating/destroying requests.
302 lockmgr(&dev_priv->uncore.lock, LK_EXCLUSIVE);
303 if (IS_CHERRYVIEW(dev_priv->dev)) {
304 if (dev_priv->uncore.fw_rendercount++ == 0)
305 dev_priv->uncore.funcs.force_wake_get(dev_priv,
307 if (dev_priv->uncore.fw_mediacount++ == 0)
308 dev_priv->uncore.funcs.force_wake_get(dev_priv,
311 if (dev_priv->uncore.forcewake_count++ == 0)
312 dev_priv->uncore.funcs.force_wake_get(dev_priv,
315 lockmgr(&dev_priv->uncore.lock, LK_RELEASE);
317 I915_WRITE(RING_ELSP(ring), desc[1]);
318 I915_WRITE(RING_ELSP(ring), desc[0]);
319 I915_WRITE(RING_ELSP(ring), desc[3]);
320 /* The context is automatically loaded after the following */
321 I915_WRITE(RING_ELSP(ring), desc[2]);
323 /* ELSP is a wo register, so use another nearby reg for posting instead */
324 POSTING_READ(RING_EXECLIST_STATUS(ring));
326 /* Release Force Wakeup (see the big comment above). */
327 lockmgr(&dev_priv->uncore.lock, LK_EXCLUSIVE);
328 if (IS_CHERRYVIEW(dev_priv->dev)) {
329 if (--dev_priv->uncore.fw_rendercount == 0)
330 dev_priv->uncore.funcs.force_wake_put(dev_priv,
332 if (--dev_priv->uncore.fw_mediacount == 0)
333 dev_priv->uncore.funcs.force_wake_put(dev_priv,
336 if (--dev_priv->uncore.forcewake_count == 0)
337 dev_priv->uncore.funcs.force_wake_put(dev_priv,
341 lockmgr(&dev_priv->uncore.lock, LK_RELEASE);
344 static int execlists_ctx_write_tail(struct drm_i915_gem_object *ctx_obj, u32 tail)
346 struct vm_page *page;
349 page = i915_gem_object_get_page(ctx_obj, 1);
350 reg_state = kmap_atomic(page);
352 reg_state[CTX_RING_TAIL+1] = tail;
354 kunmap_atomic(reg_state);
359 static int execlists_submit_context(struct intel_engine_cs *ring,
360 struct intel_context *to0, u32 tail0,
361 struct intel_context *to1, u32 tail1)
363 struct drm_i915_gem_object *ctx_obj0;
364 struct drm_i915_gem_object *ctx_obj1 = NULL;
366 ctx_obj0 = to0->engine[ring->id].state;
368 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0));
370 execlists_ctx_write_tail(ctx_obj0, tail0);
373 ctx_obj1 = to1->engine[ring->id].state;
375 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1));
377 execlists_ctx_write_tail(ctx_obj1, tail1);
380 execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
385 static void execlists_context_unqueue(struct intel_engine_cs *ring)
387 struct intel_ctx_submit_request *req0 = NULL, *req1 = NULL;
388 struct intel_ctx_submit_request *cursor = NULL, *tmp = NULL;
389 struct drm_i915_private *dev_priv = ring->dev->dev_private;
391 assert_spin_locked(&ring->execlist_lock);
393 if (list_empty(&ring->execlist_queue))
396 /* Try to read in pairs */
397 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
401 } else if (req0->ctx == cursor->ctx) {
402 /* Same ctx: ignore first request, as second request
403 * will update tail past first request's workload */
404 cursor->elsp_submitted = req0->elsp_submitted;
405 list_del(&req0->execlist_link);
406 queue_work(dev_priv->wq, &req0->work);
414 WARN_ON(req1 && req1->elsp_submitted);
416 WARN_ON(execlists_submit_context(ring, req0->ctx, req0->tail,
417 req1 ? req1->ctx : NULL,
418 req1 ? req1->tail : 0));
420 req0->elsp_submitted++;
422 req1->elsp_submitted++;
425 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
428 struct drm_i915_private *dev_priv = ring->dev->dev_private;
429 struct intel_ctx_submit_request *head_req;
431 assert_spin_locked(&ring->execlist_lock);
433 head_req = list_first_entry_or_null(&ring->execlist_queue,
434 struct intel_ctx_submit_request,
437 if (head_req != NULL) {
438 struct drm_i915_gem_object *ctx_obj =
439 head_req->ctx->engine[ring->id].state;
440 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
441 WARN(head_req->elsp_submitted == 0,
442 "Never submitted head request\n");
444 if (--head_req->elsp_submitted <= 0) {
445 list_del(&head_req->execlist_link);
446 queue_work(dev_priv->wq, &head_req->work);
456 * intel_execlists_handle_ctx_events() - handle Context Switch interrupts
457 * @ring: Engine Command Streamer to handle.
459 * Check the unread Context Status Buffers and manage the submission of new
460 * contexts to the ELSP accordingly.
462 void intel_execlists_handle_ctx_events(struct intel_engine_cs *ring)
464 struct drm_i915_private *dev_priv = ring->dev->dev_private;
470 u32 submit_contexts = 0;
472 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
474 read_pointer = ring->next_context_status_buffer;
475 write_pointer = status_pointer & 0x07;
476 if (read_pointer > write_pointer)
479 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE);
481 while (read_pointer < write_pointer) {
483 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
484 (read_pointer % 6) * 8);
485 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
486 (read_pointer % 6) * 8 + 4);
488 if (status & GEN8_CTX_STATUS_PREEMPTED) {
489 if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
490 if (execlists_check_remove_request(ring, status_id))
491 WARN(1, "Lite Restored request removed from queue\n");
493 WARN(1, "Preemption without Lite Restore\n");
496 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
497 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
498 if (execlists_check_remove_request(ring, status_id))
503 if (submit_contexts != 0)
504 execlists_context_unqueue(ring);
506 lockmgr(&ring->execlist_lock, LK_RELEASE);
508 WARN(submit_contexts > 2, "More than two context complete events?\n");
509 ring->next_context_status_buffer = write_pointer % 6;
511 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
512 ((u32)ring->next_context_status_buffer & 0x07) << 8);
515 static void execlists_free_request_task(struct work_struct *work)
517 struct intel_ctx_submit_request *req =
518 container_of(work, struct intel_ctx_submit_request, work);
519 struct drm_device *dev = req->ring->dev;
520 struct drm_i915_private *dev_priv = dev->dev_private;
522 intel_runtime_pm_put(dev_priv);
524 mutex_lock(&dev->struct_mutex);
525 i915_gem_context_unreference(req->ctx);
526 mutex_unlock(&dev->struct_mutex);
531 static int execlists_context_queue(struct intel_engine_cs *ring,
532 struct intel_context *to,
535 struct intel_ctx_submit_request *req = NULL, *cursor;
536 struct drm_i915_private *dev_priv = ring->dev->dev_private;
537 int num_elements = 0;
539 req = kzalloc(sizeof(*req), GFP_KERNEL);
543 i915_gem_context_reference(req->ctx);
546 INIT_WORK(&req->work, execlists_free_request_task);
548 intel_runtime_pm_get(dev_priv);
550 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE);
552 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
553 if (++num_elements > 2)
556 if (num_elements > 2) {
557 struct intel_ctx_submit_request *tail_req;
559 tail_req = list_last_entry(&ring->execlist_queue,
560 struct intel_ctx_submit_request,
563 if (to == tail_req->ctx) {
564 WARN(tail_req->elsp_submitted != 0,
565 "More than 2 already-submitted reqs queued\n");
566 list_del(&tail_req->execlist_link);
567 queue_work(dev_priv->wq, &tail_req->work);
571 list_add_tail(&req->execlist_link, &ring->execlist_queue);
572 if (num_elements == 0)
573 execlists_context_unqueue(ring);
575 lockmgr(&ring->execlist_lock, LK_RELEASE);
580 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf)
582 struct intel_engine_cs *ring = ringbuf->ring;
583 uint32_t flush_domains;
587 if (ring->gpu_caches_dirty)
588 flush_domains = I915_GEM_GPU_DOMAINS;
590 ret = ring->emit_flush(ringbuf, I915_GEM_GPU_DOMAINS, flush_domains);
594 ring->gpu_caches_dirty = false;
598 static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
599 struct list_head *vmas)
601 struct intel_engine_cs *ring = ringbuf->ring;
602 struct i915_vma *vma;
603 uint32_t flush_domains = 0;
604 bool flush_chipset = false;
607 list_for_each_entry(vma, vmas, exec_list) {
608 struct drm_i915_gem_object *obj = vma->obj;
610 ret = i915_gem_object_sync(obj, ring);
614 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
615 flush_chipset |= i915_gem_clflush_object(obj, false);
617 flush_domains |= obj->base.write_domain;
620 if (flush_domains & I915_GEM_DOMAIN_GTT)
623 /* Unconditionally invalidate gpu caches and ensure that we do flush
624 * any residual writes from the previous batch.
626 return logical_ring_invalidate_all_caches(ringbuf);
630 * execlists_submission() - submit a batchbuffer for execution, Execlists style
633 * @ring: Engine Command Streamer to submit to.
634 * @ctx: Context to employ for this submission.
635 * @args: execbuffer call arguments.
636 * @vmas: list of vmas.
637 * @batch_obj: the batchbuffer to submit.
638 * @exec_start: batchbuffer start virtual address pointer.
639 * @flags: translated execbuffer call flags.
641 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
642 * away the submission details of the execbuffer ioctl call.
644 * Return: non-zero if the submission fails.
646 int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
647 struct intel_engine_cs *ring,
648 struct intel_context *ctx,
649 struct drm_i915_gem_execbuffer2 *args,
650 struct list_head *vmas,
651 struct drm_i915_gem_object *batch_obj,
652 u64 exec_start, u32 flags)
654 struct drm_i915_private *dev_priv = dev->dev_private;
655 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
660 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
661 instp_mask = I915_EXEC_CONSTANTS_MASK;
662 switch (instp_mode) {
663 case I915_EXEC_CONSTANTS_REL_GENERAL:
664 case I915_EXEC_CONSTANTS_ABSOLUTE:
665 case I915_EXEC_CONSTANTS_REL_SURFACE:
666 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
667 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
671 if (instp_mode != dev_priv->relative_constants_mode) {
672 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
673 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
677 /* The HW changed the meaning on this bit on gen6 */
678 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
682 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
686 if (args->num_cliprects != 0) {
687 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
690 if (args->DR4 == 0xffffffff) {
691 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
695 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
696 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
701 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
702 DRM_DEBUG("sol reset is gen7 only\n");
706 ret = execlists_move_to_gpu(ringbuf, vmas);
710 if (ring == &dev_priv->ring[RCS] &&
711 instp_mode != dev_priv->relative_constants_mode) {
712 ret = intel_logical_ring_begin(ringbuf, 4);
716 intel_logical_ring_emit(ringbuf, MI_NOOP);
717 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
718 intel_logical_ring_emit(ringbuf, INSTPM);
719 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
720 intel_logical_ring_advance(ringbuf);
722 dev_priv->relative_constants_mode = instp_mode;
725 ret = ring->emit_bb_start(ringbuf, exec_start, flags);
729 i915_gem_execbuffer_move_to_active(vmas, ring);
730 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
735 void intel_logical_ring_stop(struct intel_engine_cs *ring)
737 struct drm_i915_private *dev_priv = ring->dev->dev_private;
740 if (!intel_ring_initialized(ring))
743 ret = intel_ring_idle(ring);
744 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
745 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
748 /* TODO: Is this correct with Execlists enabled? */
749 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
750 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
751 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
754 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
757 int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf)
759 struct intel_engine_cs *ring = ringbuf->ring;
762 if (!ring->gpu_caches_dirty)
765 ret = ring->emit_flush(ringbuf, 0, I915_GEM_GPU_DOMAINS);
769 ring->gpu_caches_dirty = false;
774 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
775 * @ringbuf: Logical Ringbuffer to advance.
777 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
778 * really happens during submission is that the context and current tail will be placed
779 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
780 * point, the tail *inside* the context is updated and the ELSP written to.
782 void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf)
784 struct intel_engine_cs *ring = ringbuf->ring;
785 struct intel_context *ctx = ringbuf->FIXME_lrc_ctx;
787 intel_logical_ring_advance(ringbuf);
789 if (intel_ring_stopped(ring))
792 execlists_context_queue(ring, ctx, ringbuf->tail);
795 static int logical_ring_alloc_seqno(struct intel_engine_cs *ring,
796 struct intel_context *ctx)
798 if (ring->outstanding_lazy_seqno)
801 if (ring->preallocated_lazy_request == NULL) {
802 struct drm_i915_gem_request *request;
804 request = kmalloc(sizeof(*request), M_DRM, M_WAITOK);
808 /* Hold a reference to the context this request belongs to
809 * (we will need it when the time comes to emit/retire the
813 i915_gem_context_reference(request->ctx);
815 ring->preallocated_lazy_request = request;
818 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
821 static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf,
824 struct intel_engine_cs *ring = ringbuf->ring;
825 struct drm_i915_gem_request *request;
829 if (ringbuf->last_retired_head != -1) {
830 ringbuf->head = ringbuf->last_retired_head;
831 ringbuf->last_retired_head = -1;
833 ringbuf->space = intel_ring_space(ringbuf);
834 if (ringbuf->space >= bytes)
838 list_for_each_entry(request, &ring->request_list, list) {
839 if (__intel_ring_space(request->tail, ringbuf->tail,
840 ringbuf->size) >= bytes) {
841 seqno = request->seqno;
849 ret = i915_wait_seqno(ring, seqno);
853 i915_gem_retire_requests_ring(ring);
854 ringbuf->head = ringbuf->last_retired_head;
855 ringbuf->last_retired_head = -1;
857 ringbuf->space = intel_ring_space(ringbuf);
861 static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
864 struct intel_engine_cs *ring = ringbuf->ring;
865 struct drm_device *dev = ring->dev;
866 struct drm_i915_private *dev_priv = dev->dev_private;
870 ret = logical_ring_wait_request(ringbuf, bytes);
874 /* Force the context submission in case we have been skipping it */
875 intel_logical_ring_advance_and_submit(ringbuf);
877 /* With GEM the hangcheck timer should kick us out of the loop,
878 * leaving it early runs the risk of corrupting GEM state (due
879 * to running on almost untested codepaths). But on resume
880 * timers don't work yet, so prevent a complete hang in that
881 * case by choosing an insanely large timeout. */
882 end = jiffies + 60 * HZ;
885 ringbuf->head = I915_READ_HEAD(ring);
886 ringbuf->space = intel_ring_space(ringbuf);
887 if (ringbuf->space >= bytes) {
894 if (dev_priv->mm.interruptible && signal_pending(curthread->td_lwp)) {
899 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
900 dev_priv->mm.interruptible);
904 if (time_after(jiffies, end)) {
913 static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf)
915 uint32_t __iomem *virt;
916 int rem = ringbuf->size - ringbuf->tail;
918 if (ringbuf->space < rem) {
919 int ret = logical_ring_wait_for_space(ringbuf, rem);
925 virt = (unsigned int *)((char *)ringbuf->virtual_start + ringbuf->tail);
928 iowrite32(MI_NOOP, virt++);
931 ringbuf->space = intel_ring_space(ringbuf);
936 static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, int bytes)
940 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
941 ret = logical_ring_wrap_buffer(ringbuf);
946 if (unlikely(ringbuf->space < bytes)) {
947 ret = logical_ring_wait_for_space(ringbuf, bytes);
956 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
958 * @ringbuf: Logical ringbuffer.
959 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
961 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
962 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
963 * and also preallocates a request (every workload submission is still mediated through
964 * requests, same as it did with legacy ringbuffer submission).
966 * Return: non-zero if the ringbuffer is not ready to be written to.
968 int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords)
970 struct intel_engine_cs *ring = ringbuf->ring;
971 struct drm_device *dev = ring->dev;
972 struct drm_i915_private *dev_priv = dev->dev_private;
975 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
976 dev_priv->mm.interruptible);
980 ret = logical_ring_prepare(ringbuf, num_dwords * sizeof(uint32_t));
984 /* Preallocate the olr before touching the ring */
985 ret = logical_ring_alloc_seqno(ring, ringbuf->FIXME_lrc_ctx);
989 ringbuf->space -= num_dwords * sizeof(uint32_t);
993 static int gen8_init_common_ring(struct intel_engine_cs *ring)
995 struct drm_device *dev = ring->dev;
996 struct drm_i915_private *dev_priv = dev->dev_private;
998 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
999 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1001 I915_WRITE(RING_MODE_GEN7(ring),
1002 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1003 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1004 POSTING_READ(RING_MODE_GEN7(ring));
1005 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1007 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1012 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1014 struct drm_device *dev = ring->dev;
1015 struct drm_i915_private *dev_priv = dev->dev_private;
1018 ret = gen8_init_common_ring(ring);
1022 /* We need to disable the AsyncFlip performance optimisations in order
1023 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1024 * programmed to '1' on all products.
1026 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1028 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1030 ret = intel_init_pipe_control(ring);
1034 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1039 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
1040 u64 offset, unsigned flags)
1042 bool ppgtt = !(flags & I915_DISPATCH_SECURE);
1045 ret = intel_logical_ring_begin(ringbuf, 4);
1049 /* FIXME(BDW): Address space and security selectors. */
1050 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1051 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1052 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1053 intel_logical_ring_emit(ringbuf, MI_NOOP);
1054 intel_logical_ring_advance(ringbuf);
1059 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1061 struct drm_device *dev = ring->dev;
1062 struct drm_i915_private *dev_priv = dev->dev_private;
1064 if (!dev->irq_enabled)
1067 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1068 if (ring->irq_refcount++ == 0) {
1069 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1070 POSTING_READ(RING_IMR(ring->mmio_base));
1072 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1077 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1079 struct drm_device *dev = ring->dev;
1080 struct drm_i915_private *dev_priv = dev->dev_private;
1082 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1083 if (--ring->irq_refcount == 0) {
1084 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1085 POSTING_READ(RING_IMR(ring->mmio_base));
1087 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1090 static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
1091 u32 invalidate_domains,
1094 struct intel_engine_cs *ring = ringbuf->ring;
1095 struct drm_device *dev = ring->dev;
1096 struct drm_i915_private *dev_priv = dev->dev_private;
1100 ret = intel_logical_ring_begin(ringbuf, 4);
1104 cmd = MI_FLUSH_DW + 1;
1106 if (ring == &dev_priv->ring[VCS]) {
1107 if (invalidate_domains & I915_GEM_GPU_DOMAINS)
1108 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1109 MI_FLUSH_DW_STORE_INDEX |
1110 MI_FLUSH_DW_OP_STOREDW;
1112 if (invalidate_domains & I915_GEM_DOMAIN_RENDER)
1113 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1114 MI_FLUSH_DW_OP_STOREDW;
1117 intel_logical_ring_emit(ringbuf, cmd);
1118 intel_logical_ring_emit(ringbuf,
1119 I915_GEM_HWS_SCRATCH_ADDR |
1120 MI_FLUSH_DW_USE_GTT);
1121 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1122 intel_logical_ring_emit(ringbuf, 0); /* value */
1123 intel_logical_ring_advance(ringbuf);
1128 static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
1129 u32 invalidate_domains,
1132 struct intel_engine_cs *ring = ringbuf->ring;
1133 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1137 flags |= PIPE_CONTROL_CS_STALL;
1139 if (flush_domains) {
1140 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1141 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1144 if (invalidate_domains) {
1145 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1146 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1147 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1148 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1149 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1150 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1151 flags |= PIPE_CONTROL_QW_WRITE;
1152 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1155 ret = intel_logical_ring_begin(ringbuf, 6);
1159 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1160 intel_logical_ring_emit(ringbuf, flags);
1161 intel_logical_ring_emit(ringbuf, scratch_addr);
1162 intel_logical_ring_emit(ringbuf, 0);
1163 intel_logical_ring_emit(ringbuf, 0);
1164 intel_logical_ring_emit(ringbuf, 0);
1165 intel_logical_ring_advance(ringbuf);
1170 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1172 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1175 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1177 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1180 static int gen8_emit_request(struct intel_ringbuffer *ringbuf)
1182 struct intel_engine_cs *ring = ringbuf->ring;
1186 ret = intel_logical_ring_begin(ringbuf, 6);
1190 cmd = MI_STORE_DWORD_IMM_GEN8;
1191 cmd |= MI_GLOBAL_GTT;
1193 intel_logical_ring_emit(ringbuf, cmd);
1194 intel_logical_ring_emit(ringbuf,
1195 (ring->status_page.gfx_addr +
1196 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1197 intel_logical_ring_emit(ringbuf, 0);
1198 intel_logical_ring_emit(ringbuf, ring->outstanding_lazy_seqno);
1199 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1200 intel_logical_ring_emit(ringbuf, MI_NOOP);
1201 intel_logical_ring_advance_and_submit(ringbuf);
1207 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1209 * @ring: Engine Command Streamer.
1212 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1214 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1216 if (!intel_ring_initialized(ring))
1219 intel_logical_ring_stop(ring);
1220 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1221 ring->preallocated_lazy_request = NULL;
1222 ring->outstanding_lazy_seqno = 0;
1225 ring->cleanup(ring);
1227 i915_cmd_parser_fini_ring(ring);
1229 if (ring->status_page.obj) {
1230 kunmap(ring->status_page.obj->pages[0]);
1231 ring->status_page.obj = NULL;
1235 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1239 /* Intentionally left blank. */
1240 ring->buffer = NULL;
1243 INIT_LIST_HEAD(&ring->active_list);
1244 INIT_LIST_HEAD(&ring->request_list);
1245 init_waitqueue_head(&ring->irq_queue);
1247 INIT_LIST_HEAD(&ring->execlist_queue);
1248 lockinit(&ring->execlist_lock, "i915el", 0, LK_CANRECURSE);
1249 ring->next_context_status_buffer = 0;
1251 ret = i915_cmd_parser_init_ring(ring);
1256 ret = ring->init(ring);
1261 ret = intel_lr_context_deferred_create(ring->default_context, ring);
1266 static int logical_render_ring_init(struct drm_device *dev)
1268 struct drm_i915_private *dev_priv = dev->dev_private;
1269 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1271 ring->name = "render ring";
1273 ring->mmio_base = RENDER_RING_BASE;
1274 ring->irq_enable_mask =
1275 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1276 ring->irq_keep_mask =
1277 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1278 if (HAS_L3_DPF(dev))
1279 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1281 ring->init = gen8_init_render_ring;
1282 ring->cleanup = intel_fini_pipe_control;
1283 ring->get_seqno = gen8_get_seqno;
1284 ring->set_seqno = gen8_set_seqno;
1285 ring->emit_request = gen8_emit_request;
1286 ring->emit_flush = gen8_emit_flush_render;
1287 ring->irq_get = gen8_logical_ring_get_irq;
1288 ring->irq_put = gen8_logical_ring_put_irq;
1289 ring->emit_bb_start = gen8_emit_bb_start;
1291 return logical_ring_init(dev, ring);
1294 static int logical_bsd_ring_init(struct drm_device *dev)
1296 struct drm_i915_private *dev_priv = dev->dev_private;
1297 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1299 ring->name = "bsd ring";
1301 ring->mmio_base = GEN6_BSD_RING_BASE;
1302 ring->irq_enable_mask =
1303 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1304 ring->irq_keep_mask =
1305 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1307 ring->init = gen8_init_common_ring;
1308 ring->get_seqno = gen8_get_seqno;
1309 ring->set_seqno = gen8_set_seqno;
1310 ring->emit_request = gen8_emit_request;
1311 ring->emit_flush = gen8_emit_flush;
1312 ring->irq_get = gen8_logical_ring_get_irq;
1313 ring->irq_put = gen8_logical_ring_put_irq;
1314 ring->emit_bb_start = gen8_emit_bb_start;
1316 return logical_ring_init(dev, ring);
1319 static int logical_bsd2_ring_init(struct drm_device *dev)
1321 struct drm_i915_private *dev_priv = dev->dev_private;
1322 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1324 ring->name = "bds2 ring";
1326 ring->mmio_base = GEN8_BSD2_RING_BASE;
1327 ring->irq_enable_mask =
1328 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1329 ring->irq_keep_mask =
1330 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1332 ring->init = gen8_init_common_ring;
1333 ring->get_seqno = gen8_get_seqno;
1334 ring->set_seqno = gen8_set_seqno;
1335 ring->emit_request = gen8_emit_request;
1336 ring->emit_flush = gen8_emit_flush;
1337 ring->irq_get = gen8_logical_ring_get_irq;
1338 ring->irq_put = gen8_logical_ring_put_irq;
1339 ring->emit_bb_start = gen8_emit_bb_start;
1341 return logical_ring_init(dev, ring);
1344 static int logical_blt_ring_init(struct drm_device *dev)
1346 struct drm_i915_private *dev_priv = dev->dev_private;
1347 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1349 ring->name = "blitter ring";
1351 ring->mmio_base = BLT_RING_BASE;
1352 ring->irq_enable_mask =
1353 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1354 ring->irq_keep_mask =
1355 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1357 ring->init = gen8_init_common_ring;
1358 ring->get_seqno = gen8_get_seqno;
1359 ring->set_seqno = gen8_set_seqno;
1360 ring->emit_request = gen8_emit_request;
1361 ring->emit_flush = gen8_emit_flush;
1362 ring->irq_get = gen8_logical_ring_get_irq;
1363 ring->irq_put = gen8_logical_ring_put_irq;
1364 ring->emit_bb_start = gen8_emit_bb_start;
1366 return logical_ring_init(dev, ring);
1369 static int logical_vebox_ring_init(struct drm_device *dev)
1371 struct drm_i915_private *dev_priv = dev->dev_private;
1372 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1374 ring->name = "video enhancement ring";
1376 ring->mmio_base = VEBOX_RING_BASE;
1377 ring->irq_enable_mask =
1378 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1379 ring->irq_keep_mask =
1380 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1382 ring->init = gen8_init_common_ring;
1383 ring->get_seqno = gen8_get_seqno;
1384 ring->set_seqno = gen8_set_seqno;
1385 ring->emit_request = gen8_emit_request;
1386 ring->emit_flush = gen8_emit_flush;
1387 ring->irq_get = gen8_logical_ring_get_irq;
1388 ring->irq_put = gen8_logical_ring_put_irq;
1389 ring->emit_bb_start = gen8_emit_bb_start;
1391 return logical_ring_init(dev, ring);
1395 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1398 * This function inits the engines for an Execlists submission style (the equivalent in the
1399 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1400 * those engines that are present in the hardware.
1402 * Return: non-zero if the initialization failed.
1404 int intel_logical_rings_init(struct drm_device *dev)
1406 struct drm_i915_private *dev_priv = dev->dev_private;
1409 ret = logical_render_ring_init(dev);
1414 ret = logical_bsd_ring_init(dev);
1416 goto cleanup_render_ring;
1420 ret = logical_blt_ring_init(dev);
1422 goto cleanup_bsd_ring;
1425 if (HAS_VEBOX(dev)) {
1426 ret = logical_vebox_ring_init(dev);
1428 goto cleanup_blt_ring;
1431 if (HAS_BSD2(dev)) {
1432 ret = logical_bsd2_ring_init(dev);
1434 goto cleanup_vebox_ring;
1437 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
1439 goto cleanup_bsd2_ring;
1444 intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
1446 intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
1448 intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
1450 intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
1451 cleanup_render_ring:
1452 intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
1457 int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
1458 struct intel_context *ctx)
1460 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1461 struct render_state so;
1462 struct drm_i915_file_private *file_priv = ctx->file_priv;
1463 struct drm_file *file = file_priv ? file_priv->file : NULL;
1466 ret = i915_gem_render_state_prepare(ring, &so);
1470 if (so.rodata == NULL)
1473 ret = ring->emit_bb_start(ringbuf,
1475 I915_DISPATCH_SECURE);
1479 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
1481 ret = __i915_add_request(ring, file, so.obj, NULL);
1482 /* intel_logical_ring_add_request moves object to inactive if it
1485 i915_gem_render_state_fini(&so);
1490 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
1491 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
1493 struct drm_device *dev = ring->dev;
1494 struct drm_i915_private *dev_priv = dev->dev_private;
1495 struct drm_i915_gem_object *ring_obj = ringbuf->obj;
1496 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1497 struct vm_page *page;
1498 uint32_t *reg_state;
1502 ppgtt = dev_priv->mm.aliasing_ppgtt;
1504 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1506 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1510 ret = i915_gem_object_get_pages(ctx_obj);
1512 DRM_DEBUG_DRIVER("Could not get object pages\n");
1516 i915_gem_object_pin_pages(ctx_obj);
1518 /* The second page of the context object contains some fields which must
1519 * be set up prior to the first execution. */
1520 page = i915_gem_object_get_page(ctx_obj, 1);
1521 reg_state = kmap_atomic(page);
1523 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1524 * commands followed by (reg, value) pairs. The values we are setting here are
1525 * only for the first context restore: on a subsequent save, the GPU will
1526 * recreate this batchbuffer with new values (including all the missing
1527 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1528 if (ring->id == RCS)
1529 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
1531 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
1532 reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
1533 reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
1534 reg_state[CTX_CONTEXT_CONTROL+1] =
1535 _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT);
1536 reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
1537 reg_state[CTX_RING_HEAD+1] = 0;
1538 reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
1539 reg_state[CTX_RING_TAIL+1] = 0;
1540 reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
1541 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
1542 reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
1543 reg_state[CTX_RING_BUFFER_CONTROL+1] =
1544 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
1545 reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
1546 reg_state[CTX_BB_HEAD_U+1] = 0;
1547 reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
1548 reg_state[CTX_BB_HEAD_L+1] = 0;
1549 reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
1550 reg_state[CTX_BB_STATE+1] = (1<<5);
1551 reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
1552 reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
1553 reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
1554 reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
1555 reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
1556 reg_state[CTX_SECOND_BB_STATE+1] = 0;
1557 if (ring->id == RCS) {
1558 /* TODO: according to BSpec, the register state context
1559 * for CHV does not have these. OTOH, these registers do
1560 * exist in CHV. I'm waiting for a clarification */
1561 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
1562 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
1563 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
1564 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
1565 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
1566 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
1568 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
1569 reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
1570 reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
1571 reg_state[CTX_CTX_TIMESTAMP+1] = 0;
1572 reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
1573 reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
1574 reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
1575 reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
1576 reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
1577 reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
1578 reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
1579 reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
1580 reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]);
1581 reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]);
1582 reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]);
1583 reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]);
1584 reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]);
1585 reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]);
1586 reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]);
1587 reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]);
1588 if (ring->id == RCS) {
1589 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
1590 reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8;
1591 reg_state[CTX_R_PWR_CLK_STATE+1] = 0;
1594 kunmap_atomic(reg_state);
1597 set_page_dirty(page);
1598 i915_gem_object_unpin_pages(ctx_obj);
1604 * intel_lr_context_free() - free the LRC specific bits of a context
1605 * @ctx: the LR context to free.
1607 * The real context freeing is done in i915_gem_context_free: this only
1608 * takes care of the bits that are LRC related: the per-engine backing
1609 * objects and the logical ringbuffer.
1611 void intel_lr_context_free(struct intel_context *ctx)
1615 for (i = 0; i < I915_NUM_RINGS; i++) {
1616 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
1617 struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf;
1620 intel_destroy_ringbuffer_obj(ringbuf);
1622 i915_gem_object_ggtt_unpin(ctx_obj);
1623 drm_gem_object_unreference(&ctx_obj->base);
1628 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
1632 WARN_ON(INTEL_INFO(ring->dev)->gen != 8);
1636 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
1642 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
1650 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1651 * @ctx: LR context to create.
1652 * @ring: engine to be used with the context.
1654 * This function can be called more than once, with different engines, if we plan
1655 * to use the context with them. The context backing objects and the ringbuffers
1656 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1657 * the creation is a deferred call: it's better to make sure first that we need to use
1658 * a given ring with the context.
1660 * Return: non-zero on eror.
1662 int intel_lr_context_deferred_create(struct intel_context *ctx,
1663 struct intel_engine_cs *ring)
1665 struct drm_device *dev = ring->dev;
1666 struct drm_i915_gem_object *ctx_obj;
1667 uint32_t context_size;
1668 struct intel_ringbuffer *ringbuf;
1671 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
1672 if (ctx->engine[ring->id].state)
1675 context_size = round_up(get_lr_context_size(ring), 4096);
1677 ctx_obj = i915_gem_alloc_context_obj(dev, context_size);
1678 if (IS_ERR(ctx_obj)) {
1679 ret = PTR_ERR(ctx_obj);
1680 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret);
1684 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
1686 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", ret);
1687 drm_gem_object_unreference(&ctx_obj->base);
1691 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1693 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1695 i915_gem_object_ggtt_unpin(ctx_obj);
1696 drm_gem_object_unreference(&ctx_obj->base);
1701 ringbuf->ring = ring;
1702 ringbuf->FIXME_lrc_ctx = ctx;
1704 ringbuf->size = 32 * PAGE_SIZE;
1705 ringbuf->effective_size = ringbuf->size;
1708 ringbuf->space = ringbuf->size;
1709 ringbuf->last_retired_head = -1;
1711 /* TODO: For now we put this in the mappable region so that we can reuse
1712 * the existing ringbuffer code which ioremaps it. When we start
1713 * creating many contexts, this will no longer work and we must switch
1714 * to a kmapish interface.
1716 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1718 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer obj %s: %d\n",
1723 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
1725 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
1726 intel_destroy_ringbuffer_obj(ringbuf);
1730 ctx->engine[ring->id].ringbuf = ringbuf;
1731 ctx->engine[ring->id].state = ctx_obj;
1733 if (ctx == ring->default_context) {
1734 /* The status page is offset 0 from the default context object
1736 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(ctx_obj);
1737 ring->status_page.page_addr =
1738 kmap(ctx_obj->pages[0]);
1739 if (ring->status_page.page_addr == NULL)
1741 ring->status_page.obj = ctx_obj;
1744 if (ring->id == RCS && !ctx->rcs_initialized) {
1745 ret = intel_lr_context_render_state_init(ring, ctx);
1747 DRM_ERROR("Init render state failed: %d\n", ret);
1748 ctx->engine[ring->id].ringbuf = NULL;
1749 ctx->engine[ring->id].state = NULL;
1750 intel_destroy_ringbuffer_obj(ringbuf);
1753 ctx->rcs_initialized = true;
1760 i915_gem_object_ggtt_unpin(ctx_obj);
1761 drm_gem_object_unreference(&ctx_obj->base);