3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2008, 2009 Rui Paulo <rpaulo@FreeBSD.org>
6 * Copyright (c) 2009 Norikatsu Shigemura <nork@FreeBSD.org>
7 * Copyright (c) 2009-2012 Jung-uk Kim <jkim@FreeBSD.org>
9 * Copyright (c) 2017-2020 Conrad Meyer <cem@FreeBSD.org>. All rights reserved.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
23 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
24 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
26 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
29 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
34 * Driver for the AMD CPU on-die thermal sensors.
35 * Initially based on the k8temp Linux driver.
40 #include <sys/cdefs.h>
41 //__FBSDID("$FreeBSD$");
44 #include <sys/param.h>
47 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/sysctl.h>
50 #include <sys/systm.h>
52 #include <machine/cpufunc.h>
53 #include <machine/md_var.h>
54 #include <machine/specialreg.h>
56 #include <bus/pci/pcivar.h>
57 #include <bus/pci/pci_cfgreg.h>
59 #include <dev/powermng/amdsmn/amdsmn.h>
78 NUM_CCDS = CCD_MAX - CCD_BASE + 1,
81 struct amdtemp_softc {
85 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */
86 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */
87 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */
89 int32_t (*sc_gettemp)(device_t, amdsensor_t);
90 struct sysctl_oid *sc_sysctl_cpu[MAXCPU];
91 struct intr_config_hook sc_ich;
96 * N.B. The numbers in macro names below are significant and represent CPU
97 * family and model numbers. Do not make up fictitious family or model numbers
98 * when adding support for new devices.
100 #define VENDORID_AMD 0x1022
101 #define DEVICEID_AMD_MISC0F 0x1103
102 #define DEVICEID_AMD_MISC10 0x1203
103 #define DEVICEID_AMD_MISC11 0x1303
104 #define DEVICEID_AMD_MISC14 0x1703
105 #define DEVICEID_AMD_MISC15 0x1603
106 #define DEVICEID_AMD_MISC15_M10H 0x1403
107 #define DEVICEID_AMD_MISC15_M30H 0x141d
108 #define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576
109 #define DEVICEID_AMD_MISC16 0x1533
110 #define DEVICEID_AMD_MISC16_M30H 0x1583
111 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450
112 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0
113 #define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70h. */
115 static const struct amdtemp_product {
116 uint16_t amdtemp_vendorid;
117 uint16_t amdtemp_deviceid;
119 * 0xFC register is only valid on the D18F3 PCI device; SMN temp
120 * drivers do not attach to that device.
122 bool amdtemp_has_cpuid;
123 } amdtemp_products[] = {
124 { VENDORID_AMD, DEVICEID_AMD_MISC0F, true },
125 { VENDORID_AMD, DEVICEID_AMD_MISC10, true },
126 { VENDORID_AMD, DEVICEID_AMD_MISC11, true },
127 { VENDORID_AMD, DEVICEID_AMD_MISC14, true },
128 { VENDORID_AMD, DEVICEID_AMD_MISC15, true },
129 { VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true },
130 { VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true },
131 { VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false },
132 { VENDORID_AMD, DEVICEID_AMD_MISC16, true },
133 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true },
134 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false },
135 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false },
136 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false },
140 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h.
142 #define AMDTEMP_REPTMP_CTRL 0xa4
144 #define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff
145 #define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21
146 #define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3
147 #define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16
150 * Reported Temperature, Family 15h, M60+
152 * Same register bit definitions as other Family 15h CPUs, but access is
153 * indirect via SMN, like Family 17h.
155 #define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4
158 * Reported Temperature, Family 17h
160 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register
161 * provide the current temp. bit 19, when clear, means the temp is reported in
162 * a range 0.."225C" (probable typo for 255C), and when set changes the range
165 #define AMDTEMP_17H_CUR_TMP 0x59800
166 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1u << 19)
168 * The following register set was discovered experimentally by Ondrej Čerman
169 * and collaborators, but is not (yet) documented in a PPR/OSRR (other than
170 * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to
171 * SMU::THM). It seems plausible and the Linux sensor folks have adopted it.
173 #define AMDTEMP_17H_CCD_TMP_BASE 0x59954
174 #define AMDTEMP_17H_CCD_TMP_VALID (1u << 11)
177 * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius).
179 #define AMDTEMP_CURTMP_RANGE_ADJUST 490
182 * Thermaltrip Status Register (Family 0Fh only)
184 #define AMDTEMP_THERMTP_STAT 0xe4
185 #define AMDTEMP_TTSR_SELCORE 0x04
186 #define AMDTEMP_TTSR_SELSENSOR 0x40
189 * DRAM Configuration High Register
191 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */
192 #define AMDTEMP_DRAM_MODE_DDR3 0x0100
195 * CPU Family/Model Register
197 #define AMDTEMP_CPUID 0xfc
202 static void amdtemp_identify(driver_t *driver, device_t parent);
203 static int amdtemp_probe(device_t dev);
204 static int amdtemp_attach(device_t dev);
205 static void amdtemp_intrhook(void *arg);
206 static int amdtemp_detach(device_t dev);
207 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor);
208 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor);
209 static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor);
210 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor);
211 static void amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model);
212 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS);
214 static device_method_t amdtemp_methods[] = {
215 /* Device interface */
216 DEVMETHOD(device_identify, amdtemp_identify),
217 DEVMETHOD(device_probe, amdtemp_probe),
218 DEVMETHOD(device_attach, amdtemp_attach),
219 DEVMETHOD(device_detach, amdtemp_detach),
224 static driver_t amdtemp_driver = {
227 sizeof(struct amdtemp_softc),
230 static devclass_t amdtemp_devclass;
231 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, amdtemp_devclass, NULL, NULL);
232 MODULE_VERSION(amdtemp, 1);
233 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1);
234 #if !defined(__DragonFly__)
235 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products,
236 nitems(amdtemp_products));
240 amdtemp_match(device_t dev, const struct amdtemp_product **product_out)
243 uint16_t vendor, devid;
245 vendor = pci_get_vendor(dev);
246 devid = pci_get_device(dev);
248 for (i = 0; i < nitems(amdtemp_products); i++) {
249 if (vendor == amdtemp_products[i].amdtemp_vendorid &&
250 devid == amdtemp_products[i].amdtemp_deviceid) {
251 if (product_out != NULL)
252 *product_out = &amdtemp_products[i];
260 amdtemp_identify(driver_t *driver, device_t parent)
264 /* Make sure we're not being doubly invoked. */
265 if (device_find_child(parent, "amdtemp", -1) != NULL)
268 if (amdtemp_match(parent, NULL)) {
269 child = device_add_child(parent, "amdtemp", -1);
271 device_printf(parent, "add amdtemp child failed\n");
276 amdtemp_probe(device_t dev)
278 uint32_t family, model;
280 if (resource_disabled("amdtemp", 0))
282 if (!amdtemp_match(device_get_parent(dev), NULL))
285 family = CPUID_TO_FAMILY(cpu_id);
286 model = CPUID_TO_MODEL(cpu_id);
290 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) ||
291 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1))
305 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors");
307 return (BUS_PROBE_GENERIC);
311 amdtemp_attach(device_t dev)
315 const struct amdtemp_product *product;
316 struct amdtemp_softc *sc;
317 struct sysctl_ctx_list *sysctlctx;
318 struct sysctl_oid *sysctlnode;
319 uint32_t cpuid, family, model;
321 int erratum319, unit;
324 sc = device_get_softc(dev);
328 if (!amdtemp_match(device_get_parent(dev), &product))
332 family = CPUID_TO_FAMILY(cpuid);
333 model = CPUID_TO_MODEL(cpuid);
336 * This checks for the byzantine condition of running a heterogenous
337 * revision multi-socket system where the attach thread is potentially
338 * probing a remote socket's PCI device.
340 * Currently, such scenarios are unsupported on models using the SMN
341 * (because on those models, amdtemp(4) attaches to a different PCI
342 * device than the one that contains AMDTEMP_CPUID).
344 * The ancient 0x0F family of devices only supports this register from
347 if (product->amdtemp_has_cpuid && (family > 0x0f ||
348 (family == 0x0f && model >= 0x40))) {
349 cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID,
351 family = CPUID_TO_FAMILY(cpuid);
352 model = CPUID_TO_MODEL(cpuid);
358 * Thermaltrip Status Register
360 * - ThermSenseCoreSel
362 * Revision F & G: 0 - Core1, 1 - Core0
363 * Other: 0 - Core0, 1 - Core1
367 * Revision G: bits 23-14
370 * XXX According to the BKDG, CurTmp, ThermSenseSel and
371 * ThermSenseCoreSel bits were introduced in Revision F
372 * but CurTmp seems working fine as early as Revision C.
373 * However, it is not clear whether ThermSenseSel and/or
374 * ThermSenseCoreSel work in undocumented cases as well.
375 * In fact, the Linux driver suggests it may not work but
376 * we just assume it does until we find otherwise.
378 * XXX According to Linux, CurTmp starts at -28C on
379 * Socket AM2 Revision G processors, which is not
380 * documented anywhere.
383 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP;
384 if (model >= 0x60 && model != 0xc1) {
385 do_cpuid(0x80000001, regs);
386 bid = (regs[1] >> 9) & 0x1f;
388 case 0x68: /* Socket S1g1 */
392 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */
393 if (bid != 0x0b && bid != 0x0c)
395 AMDTEMP_FLAG_ALT_OFFSET;
397 case 0x6f: /* Socket AM2 and ASB1 (1 core) */
399 if (bid != 0x07 && bid != 0x09 &&
402 AMDTEMP_FLAG_ALT_OFFSET;
405 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET;
407 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT;
411 * There are two sensors per core.
415 sc->sc_gettemp = amdtemp_gettemp0f;
419 * Erratum 319 Inaccurate Temperature Measurement
421 * http://support.amd.com/us/Processor_TechDocs/41322.pdf
423 do_cpuid(0x80000001, regs);
424 switch ((regs[1] >> 28) & 0xf) {
425 case 0: /* Socket F */
428 case 1: /* Socket AM2+ or AM3 */
429 if ((pci_cfgregread(pci_get_bus(dev),
430 pci_get_slot(dev), 2, AMDTEMP_DRAM_CONF_HIGH, 2) &
431 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 ||
432 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3))
434 /* XXX 00100F42h (RB-C2) exists in both formats. */
446 * Some later (60h+) models of family 15h use a similar SMN
447 * network as family 17h. (However, the register index differs
448 * from 17h and the decoding matches other 10h-15h models,
449 * which differ from 17h.)
451 if (family == 0x15 && model >= 0x60) {
452 sc->sc_gettemp = amdtemp_gettemp15hm60h;
455 sc->sc_gettemp = amdtemp_gettemp;
459 sc->sc_gettemp = amdtemp_gettemp17h;
463 device_printf(dev, "Bogus family 0x%x\n", family);
468 sc->sc_smn = device_find_child(
469 device_get_parent(dev), "amdsmn", -1);
470 if (sc->sc_smn == NULL) {
472 device_printf(dev, "No SMN device found\n");
477 /* Find number of cores per package. */
478 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ?
479 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1;
480 if (sc->sc_ncores > MAXCPU)
485 "Erratum 319: temperature measurement may be inaccurate\n");
487 device_printf(dev, "Found %d cores and %d sensors.\n",
489 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1);
492 * dev.amdtemp.N tree.
494 unit = device_get_unit(dev);
495 ksnprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit);
496 TUNABLE_INT_FETCH(tn, &sc->sc_offset);
498 sysctlctx = device_get_sysctl_ctx(dev);
499 SYSCTL_ADD_INT(sysctlctx,
500 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
501 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0,
502 "Temperature sensor offset");
503 sysctlnode = SYSCTL_ADD_NODE(sysctlctx,
504 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
505 "core0", CTLFLAG_RD, 0, "Core 0");
507 SYSCTL_ADD_PROC(sysctlctx,
508 SYSCTL_CHILDREN(sysctlnode),
510 CTLTYPE_INT | CTLFLAG_RD,
511 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK",
512 "Core 0 / Sensor 0 temperature");
515 amdtemp_probe_ccd_sensors17h(dev, model);
516 else if (sc->sc_ntemps > 1) {
517 SYSCTL_ADD_PROC(sysctlctx,
518 SYSCTL_CHILDREN(sysctlnode),
520 CTLTYPE_INT | CTLFLAG_RD,
521 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK",
522 "Core 0 / Sensor 1 temperature");
524 if (sc->sc_ncores > 1) {
525 sysctlnode = SYSCTL_ADD_NODE(sysctlctx,
526 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
527 OID_AUTO, "core1", CTLFLAG_RD,
530 SYSCTL_ADD_PROC(sysctlctx,
531 SYSCTL_CHILDREN(sysctlnode),
533 CTLTYPE_INT | CTLFLAG_RD,
534 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK",
535 "Core 1 / Sensor 0 temperature");
537 SYSCTL_ADD_PROC(sysctlctx,
538 SYSCTL_CHILDREN(sysctlnode),
540 CTLTYPE_INT | CTLFLAG_RD,
541 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK",
542 "Core 1 / Sensor 1 temperature");
547 * Try to create dev.cpu sysctl entries and setup intrhook function.
548 * This is needed because the cpu driver may be loaded late on boot,
551 amdtemp_intrhook(dev);
552 sc->sc_ich.ich_func = amdtemp_intrhook;
553 sc->sc_ich.ich_arg = dev;
554 if (config_intrhook_establish(&sc->sc_ich) != 0) {
555 device_printf(dev, "config_intrhook_establish failed!\n");
563 amdtemp_intrhook(void *arg)
565 struct amdtemp_softc *sc;
566 struct sysctl_ctx_list *sysctlctx;
567 device_t dev = (device_t)arg;
568 device_t acpi, cpu, nexus;
572 sc = device_get_softc(dev);
575 * dev.cpu.N.temperature.
577 nexus = device_find_child(root_bus, "nexus", 0);
578 acpi = device_find_child(nexus, "acpi", 0);
580 for (i = 0; i < sc->sc_ncores; i++) {
581 if (sc->sc_sysctl_cpu[i] != NULL)
583 cpu = device_find_child(acpi, "cpu",
584 device_get_unit(dev) * sc->sc_ncores + i);
586 sysctlctx = device_get_sysctl_ctx(cpu);
588 sensor = sc->sc_ntemps > 1 ?
589 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0;
590 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx,
591 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)),
592 OID_AUTO, "temperature",
593 CTLTYPE_INT | CTLFLAG_RD,
594 dev, sensor, amdtemp_sysctl, "IK",
595 "Current temparature");
598 if (sc->sc_ich.ich_arg != NULL)
599 config_intrhook_disestablish(&sc->sc_ich);
603 amdtemp_detach(device_t dev)
605 struct amdtemp_softc *sc = device_get_softc(dev);
608 for (i = 0; i < sc->sc_ncores; i++)
609 if (sc->sc_sysctl_cpu[i] != NULL)
610 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0);
612 /* NewBus removes the dev.amdtemp.N tree by itself. */
618 amdtemp_sysctl(SYSCTL_HANDLER_ARGS)
620 device_t dev = (device_t)arg1;
621 struct amdtemp_softc *sc = device_get_softc(dev);
622 amdsensor_t sensor = (amdsensor_t)arg2;
623 int32_t auxtemp[2], temp;
628 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0);
629 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1);
630 temp = imax(auxtemp[0], auxtemp[1]);
633 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0);
634 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1);
635 temp = imax(auxtemp[0], auxtemp[1]);
638 temp = sc->sc_gettemp(dev, sensor);
641 error = sysctl_handle_int(oidp, &temp, 0, req);
646 #define AMDTEMP_ZERO_C_TO_K 2731
649 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor)
651 struct amdtemp_softc *sc = device_get_softc(dev);
652 uint32_t mask, offset, temp;
654 /* Set Sensor/Core selector. */
655 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1);
656 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR);
659 temp |= AMDTEMP_TTSR_SELSENSOR;
663 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0)
664 temp |= AMDTEMP_TTSR_SELCORE;
667 temp |= AMDTEMP_TTSR_SELSENSOR;
671 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0)
672 temp |= AMDTEMP_TTSR_SELCORE;
675 __builtin_unreachable();
677 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1);
679 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc;
680 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49;
681 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4);
682 temp = ((temp >> 14) & mask) * 5 / 2;
683 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10;
689 amdtemp_decode_fam10h_to_17h(int32_t sc_offset, uint32_t val, bool minus49)
693 /* Convert raw register subfield units (0.125C) to units of 0.1C. */
694 temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4;
697 temp -= AMDTEMP_CURTMP_RANGE_ADJUST;
699 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10;
704 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val)
709 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is
710 * adjusted down by 49.0 degrees Celsius. (This adjustment is not
711 * documented in BKDGs prior to family 15h model 00h.)
713 minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 &&
714 ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) &
715 AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3);
717 return (amdtemp_decode_fam10h_to_17h(sc_offset,
718 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49));
722 amdtemp_decode_fam17h_tctl(int32_t sc_offset, uint32_t val)
726 minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0);
727 return (amdtemp_decode_fam10h_to_17h(sc_offset,
728 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49));
732 amdtemp_gettemp(device_t dev, amdsensor_t sensor)
734 struct amdtemp_softc *sc = device_get_softc(dev);
737 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4);
738 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp));
742 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor)
744 struct amdtemp_softc *sc = device_get_softc(dev);
748 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val);
749 KASSERT(error == 0, ("amdsmn_read"));
750 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val));
754 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor)
756 struct amdtemp_softc *sc = device_get_softc(dev);
763 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val);
764 KASSERT(error == 0, ("amdsmn_read"));
765 return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val));
766 case CCD_BASE ... CCD_MAX:
768 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE +
769 (((int)sensor - CCD_BASE) * sizeof(val)), &val);
770 KASSERT(error == 0, ("amdsmn_read2"));
771 KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0,
772 ("sensor %d: not valid", (int)sensor));
773 return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true));
775 __builtin_unreachable();
780 amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model)
782 char sensor_name[16], sensor_descr[32];
783 struct amdtemp_softc *sc;
784 uint32_t maxreg, i, val;
788 case 0x00 ... 0x1f: /* Zen1, Zen+ */
791 case 0x30 ... 0x3f: /* Zen2 TR/Epyc */
792 case 0x70 ... 0x7f: /* Zen2 Ryzen */
794 _Static_assert((int)NUM_CCDS >= 8, "");
798 "Unrecognized Family 17h Model: %02xh\n", model);
802 sc = device_get_softc(dev);
803 for (i = 0; i < maxreg; i++) {
804 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE +
805 (i * sizeof(val)), &val);
808 if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0)
811 ksnprintf(sensor_name, sizeof(sensor_name), "ccd%u", i);
812 ksnprintf(sensor_descr, sizeof(sensor_descr),
813 "CCD %u temperature (Tccd%u)", i, i);
815 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
816 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
817 sensor_name, CTLTYPE_INT | CTLFLAG_RD,
818 dev, CCD_BASE + i, amdtemp_sysctl, "IK", sensor_descr);