2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
38 * $DragonFly: src/sys/platform/pc32/isa/clock.c,v 1.26 2005/06/01 22:25:11 dillon Exp $
42 * Routines to handle clock hardware.
46 * inittodr, settodr and support routines written
47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
54 #include "opt_clock.h"
56 #include <sys/param.h>
57 #include <sys/systm.h>
59 #include <sys/kernel.h>
64 #include <sys/sysctl.h>
66 #include <sys/systimer.h>
67 #include <sys/globaldata.h>
68 #include <sys/thread2.h>
69 #include <sys/systimer.h>
71 #include <machine/clock.h>
72 #ifdef CLK_CALIBRATION_LOOP
74 #include <machine/cputypes.h>
75 #include <machine/frame.h>
76 #include <machine/ipl.h>
77 #include <machine/limits.h>
78 #include <machine/md_var.h>
79 #include <machine/psl.h>
81 #include <machine/segments.h>
83 #if defined(SMP) || defined(APIC_IO)
84 #include <machine/smp.h>
85 #endif /* SMP || APIC_IO */
86 #include <machine/specialreg.h>
88 #include <i386/isa/icu.h>
89 #include <bus/isa/i386/isa.h>
90 #include <bus/isa/rtc.h>
91 #include <i386/isa/timerreg.h>
93 #include <i386/isa/intr_machdep.h>
96 #include <bus/mca/i386/mca_machdep.h>
100 #include <i386/isa/intr_machdep.h>
101 /* The interrupt triggered by the 8254 (timer) chip */
103 static u_long read_intr_count (int vec);
104 static void setup_8254_mixed_mode (void);
106 static void i8254_restore(void);
109 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
110 * can use a simple formula for leap years.
112 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
113 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
116 #define TIMER_FREQ 1193182
119 static uint8_t i8254_walltimer_sel;
120 static uint16_t i8254_walltimer_cntr;
122 int adjkerntz; /* local offset from GMT in seconds */
123 int disable_rtc_set; /* disable resettodr() if != 0 */
124 volatile u_int idelayed;
125 int statclock_disable = 1; /* we don't use the statclock right now */
126 u_int stat_imask = SWI_CLOCK_MASK;
129 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
131 enum tstate { RELEASED, ACQUIRED };
132 enum tstate timer0_state;
133 enum tstate timer1_state;
134 enum tstate timer2_state;
136 static int beeping = 0;
137 static u_int clk_imask = HWI_MASK | SWI_MASK;
138 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
139 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
140 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
141 static u_int tsc_present;
143 static int i8254_cputimer_div;
145 static struct callout sysbeepstop_ch;
147 static sysclock_t i8254_cputimer_count(void);
148 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
149 static void i8254_cputimer_destruct(struct cputimer *cputimer);
151 static struct cputimer i8254_cputimer = {
156 i8254_cputimer_count,
157 cputimer_default_fromhz,
158 cputimer_default_fromus,
159 i8254_cputimer_construct,
160 i8254_cputimer_destruct,
166 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
167 * counting as of this interrupt. We use timer1 in free-running mode (not
168 * generating any interrupts) as our main counter. Each cpu has timeouts
172 clkintr(struct intrframe frame)
174 static sysclock_t timer1_count;
175 struct globaldata *gd = mycpu;
176 struct globaldata *gscan;
180 * SWSTROBE mode is a one-shot, the timer is no longer running
185 * XXX the dispatcher needs work. right now we call systimer_intr()
186 * directly or via IPI for any cpu with systimers queued, which is
187 * usually *ALL* of them. We need a better way to do this.
189 timer1_count = sys_cputimer->count();
190 for (n = 0; n < ncpus; ++n) {
191 gscan = globaldata_find(n);
192 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
195 lwkt_send_ipiq(gscan, (ipifunc_t)systimer_intr, &timer1_count);
197 systimer_intr(&timer1_count, &frame);
201 /* Reset clock interrupt by asserting bit 7 of port 0x61 */
203 outb(0x61, inb(0x61) | 0x80);
212 acquire_timer2(int mode)
214 if (timer2_state != RELEASED)
216 timer2_state = ACQUIRED;
219 * This access to the timer registers is as atomic as possible
220 * because it is a single instruction. We could do better if we
223 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
230 if (timer2_state != ACQUIRED)
232 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
233 timer2_state = RELEASED;
238 * This routine receives statistical clock interrupts from the RTC.
239 * As explained above, these occur at 128 interrupts per second.
240 * When profiling, we receive interrupts at a rate of 1024 Hz.
242 * This does not actually add as much overhead as it sounds, because
243 * when the statistical clock is active, the hardclock driver no longer
244 * needs to keep (inaccurate) statistics on its own. This decouples
245 * statistics gathering from scheduling interrupts.
247 * The RTC chip requires that we read status register C (RTC_INTR)
248 * to acknowledge an interrupt, before it will generate the next one.
249 * Under high interrupt load, rtcintr() can be indefinitely delayed and
250 * the clock can tick immediately after the read from RTC_INTR. In this
251 * case, the mc146818A interrupt signal will not drop for long enough
252 * to register with the 8259 PIC. If an interrupt is missed, the stat
253 * clock will halt, considerably degrading system performance. This is
254 * why we use 'while' rather than a more straightforward 'if' below.
255 * Stat clock ticks can still be lost, causing minor loss of accuracy
256 * in the statistics, but the stat clock will no longer stop.
259 rtcintr(struct intrframe frame)
261 while (rtcin(RTC_INTR) & RTCIR_PERIOD)
263 /* statclock(&frame); no longer used */
270 DB_SHOW_COMMAND(rtc, rtc)
272 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
273 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
274 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
275 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
280 * Return the current cpu timer count as a 32 bit integer.
284 i8254_cputimer_count(void)
286 static __uint16_t cputimer_last;
291 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
292 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */
293 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
294 count = -count; /* -> countup */
295 if (count < cputimer_last) /* rollover */
296 i8254_cputimer.base += 0x00010000;
297 ret = i8254_cputimer.base | count;
298 cputimer_last = count;
304 * This function is called whenever the system timebase changes, allowing
305 * us to calculate what is needed to convert a system timebase tick
306 * into an 8254 tick for the interrupt timer. If we can convert to a
307 * simple shift, multiplication, or division, we do so. Otherwise 64
308 * bit arithmatic is required every time the interrupt timer is reloaded.
311 cputimer_intr_config(struct cputimer *timer)
317 * Will a simple divide do the trick?
319 div = (timer->freq + (i8254_cputimer.freq / 2)) / i8254_cputimer.freq;
320 freq = i8254_cputimer.freq * div;
322 if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
323 i8254_cputimer_div = div;
325 i8254_cputimer_div = 0;
329 * Reload for the next timeout. It is possible for the reload value
330 * to be 0 or negative, indicating that an immediate timer interrupt
331 * is desired. For now make the minimum 2 ticks.
333 * We may have to convert from the system timebase to the 8254 timebase.
336 cputimer_intr_reload(sysclock_t reload)
340 if (i8254_cputimer_div)
341 reload /= i8254_cputimer_div;
343 reload = (int64_t)reload * i8254_cputimer.freq / sys_cputimer->freq;
349 if (timer0_running) {
350 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
351 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
352 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
353 if (reload < count) {
354 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
355 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
356 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
361 reload = 0; /* full count */
362 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
363 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
364 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
370 * Wait "n" microseconds.
371 * Relies on timer 1 counting down from (cputimer_freq / hz)
372 * Note: timer had better have been programmed before this is first used!
377 int delta, prev_tick, tick, ticks_left;
382 static int state = 0;
386 for (n1 = 1; n1 <= 10000000; n1 *= 10)
391 printf("DELAY(%d)...", n);
394 * Guard against the timer being uninitialized if we are called
395 * early for console i/o.
397 if (timer0_state == RELEASED)
401 * Read the counter first, so that the rest of the setup overhead is
402 * counted. Then calculate the number of hardware timer ticks
403 * required, rounding up to be sure we delay at least the requested
404 * number of microseconds.
406 prev_tick = sys_cputimer->count();
407 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
413 while (ticks_left > 0) {
414 tick = sys_cputimer->count();
418 delta = tick - prev_tick;
426 printf(" %d calls to getit() at %d usec each\n",
427 getit_calls, (n + 5) / getit_calls);
432 sysbeepstop(void *chan)
434 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
440 sysbeep(int pitch, int period)
442 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
445 * Nobody else is using timer2, we do not need the clock lock
447 outb(TIMER_CNTR2, pitch);
448 outb(TIMER_CNTR2, (pitch>>8));
450 /* enable counter2 output to speaker */
451 outb(IO_PPI, inb(IO_PPI) | 3);
453 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
459 * RTC support routines
472 val = inb(IO_RTC + 1);
479 writertc(u_char reg, u_char val)
487 outb(IO_RTC + 1, val);
488 inb(0x84); /* XXX work around wrong order in rtcin() */
495 return(bcd2bin(rtcin(port)));
499 calibrate_clocks(void)
502 u_int count, prev_count, tot_count;
503 int sec, start_sec, timeout;
506 printf("Calibrating clock(s) ... ");
507 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
511 /* Read the mc146818A seconds counter. */
513 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
514 sec = rtcin(RTC_SEC);
521 /* Wait for the mC146818A seconds counter to change. */
524 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
525 sec = rtcin(RTC_SEC);
526 if (sec != start_sec)
533 /* Start keeping track of the i8254 counter. */
534 prev_count = sys_cputimer->count();
540 old_tsc = 0; /* shut up gcc */
543 * Wait for the mc146818A seconds counter to change. Read the i8254
544 * counter for each iteration since this is convenient and only
545 * costs a few usec of inaccuracy. The timing of the final reads
546 * of the counters almost matches the timing of the initial reads,
547 * so the main cause of inaccuracy is the varying latency from
548 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
549 * rtcin(RTC_SEC) that returns a changed seconds count. The
550 * maximum inaccuracy from this cause is < 10 usec on 486's.
554 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
555 sec = rtcin(RTC_SEC);
556 count = sys_cputimer->count();
557 tot_count += (int)(count - prev_count);
559 if (sec != start_sec)
566 * Read the cpu cycle counter. The timing considerations are
567 * similar to those for the i8254 clock.
570 tsc_freq = rdtsc() - old_tsc;
573 printf("TSC clock: %u Hz, ", tsc_freq);
574 printf("i8254 clock: %u Hz\n", tot_count);
578 printf("failed, using default i8254 clock of %u Hz\n",
579 i8254_cputimer.freq);
580 return (i8254_cputimer.freq);
586 timer0_state = ACQUIRED;
591 * Timer0 is our fine-grained variable clock interrupt
593 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
594 outb(TIMER_CNTR0, 2); /* lsb */
595 outb(TIMER_CNTR0, 0); /* msb */
598 * Timer1 or timer2 is our free-running clock, but only if another
599 * has not been selected.
601 cputimer_register(&i8254_cputimer);
602 cputimer_select(&i8254_cputimer, 0);
607 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
612 * Should we use timer 1 or timer 2 ?
615 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
616 if (which != 1 && which != 2)
621 timer->name = "i8254_timer1";
622 timer->type = CPUTIMER_8254_SEL1;
623 i8254_walltimer_sel = TIMER_SEL1;
624 i8254_walltimer_cntr = TIMER_CNTR1;
625 timer1_state = ACQUIRED;
628 timer->name = "i8254_timer2";
629 timer->type = CPUTIMER_8254_SEL2;
630 i8254_walltimer_sel = TIMER_SEL2;
631 i8254_walltimer_cntr = TIMER_CNTR2;
632 timer2_state = ACQUIRED;
636 timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
638 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
639 outb(i8254_walltimer_cntr, 0); /* lsb */
640 outb(i8254_walltimer_cntr, 0); /* msb */
641 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
645 i8254_cputimer_destruct(struct cputimer *timer)
647 switch(timer->type) {
648 case CPUTIMER_8254_SEL1:
649 timer1_state = RELEASED;
651 case CPUTIMER_8254_SEL2:
652 timer2_state = RELEASED;
663 /* Restore all of the RTC's "status" (actually, control) registers. */
664 writertc(RTC_STATUSB, RTCSB_24HR);
665 writertc(RTC_STATUSA, rtc_statusa);
666 writertc(RTC_STATUSB, rtc_statusb);
670 * Restore all the timers.
672 * This function is called to resynchronize our core timekeeping after a
673 * long halt, e.g. from apm_default_resume() and friends. It is also
674 * called if after a BIOS call we have detected munging of the 8254.
675 * It is necessary because cputimer_count() counter's delta may have grown
676 * too large for nanouptime() and friends to handle, or (in the case of 8254
677 * munging) might cause the SYSTIMER code to prematurely trigger.
683 i8254_restore(); /* restore timer_freq and hz */
684 rtc_restore(); /* reenable RTC interrupts */
689 * Initialize 8254 timer 0 early so that it can be used in DELAY().
697 * Can we use the TSC?
699 if (cpu_feature & CPUID_TSC)
705 * Initial RTC state, don't do anything unexpected
707 writertc(RTC_STATUSA, rtc_statusa);
708 writertc(RTC_STATUSB, RTCSB_24HR);
711 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
712 * generate an interrupt, which we will ignore for now.
714 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
715 * (so it counts a full 2^16 and repeats). We will use this timer
719 freq = calibrate_clocks();
720 #ifdef CLK_CALIBRATION_LOOP
723 "Press a key on the console to abort clock calibration\n");
724 while (cncheckc() == -1)
730 * Use the calibrated i8254 frequency if it seems reasonable.
731 * Otherwise use the default, and don't use the calibrated i586
734 delta = freq > i8254_cputimer.freq ?
735 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
736 if (delta < i8254_cputimer.freq / 100) {
737 #ifndef CLK_USE_I8254_CALIBRATION
740 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
741 freq = i8254_cputimer.freq;
743 cputimer_set_frequency(&i8254_cputimer, freq);
747 "%d Hz differs from default of %d Hz by more than 1%%\n",
748 freq, i8254_cputimer.freq);
752 #ifndef CLK_USE_TSC_CALIBRATION
756 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
760 if (tsc_present && tsc_freq == 0) {
762 * Calibration of the i586 clock relative to the mc146818A
763 * clock failed. Do a less accurate calibration relative
764 * to the i8254 clock.
766 u_int64_t old_tsc = rdtsc();
769 tsc_freq = rdtsc() - old_tsc;
770 #ifdef CLK_USE_TSC_CALIBRATION
772 printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
778 * We can not use the TSC in SMP mode, until we figure out a
779 * cheap (impossible), reliable and precise (yeah right!) way
780 * to synchronize the TSCs of all the CPUs.
781 * Curse Intel for leaving the counter out of the I/O APIC.
786 * We can not use the TSC if we support APM. Precise timekeeping
787 * on an APM'ed machine is at best a fools pursuit, since
788 * any and all of the time spent in various SMM code can't
789 * be reliably accounted for. Reading the RTC is your only
790 * source of reliable time info. The i8254 looses too of course
791 * but we need to have some kind of time...
792 * We don't know at this point whether APM is going to be used
793 * or not, nor when it might be activated. Play it safe.
796 #endif /* NAPM > 0 */
798 #endif /* !defined(SMP) */
802 * Initialize the time of day register, based on the time base which is, e.g.
806 inittodr(time_t base)
808 unsigned long sec, days;
820 /* Look if we have a RTC present and the time is valid */
821 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
824 /* wait for time update to complete */
825 /* If RTCSA_TUP is zero, we have at least 244us before next update */
827 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
833 #ifdef USE_RTC_CENTURY
834 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
836 year = readrtc(RTC_YEAR) + 1900;
844 month = readrtc(RTC_MONTH);
845 for (m = 1; m < month; m++)
846 days += daysinmonth[m-1];
847 if ((month > 2) && LEAPYEAR(year))
849 days += readrtc(RTC_DAY) - 1;
851 for (y = 1970; y < year; y++)
852 days += DAYSPERYEAR + LEAPYEAR(y);
853 sec = ((( days * 24 +
854 readrtc(RTC_HRS)) * 60 +
855 readrtc(RTC_MIN)) * 60 +
857 /* sec now contains the number of seconds, since Jan 1 1970,
858 in the local time zone */
860 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
862 y = time_second - sec;
863 if (y <= -2 || y >= 2) {
864 /* badly off, adjust it */
873 printf("Invalid time in real time clock.\n");
874 printf("Check and reset the date immediately!\n");
878 * Write system time back to RTC
895 /* Disable RTC updates and interrupts. */
896 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
898 /* Calculate local time to put in RTC */
900 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
902 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
903 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
904 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
906 /* We have now the days since 01-01-1970 in tm */
907 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
908 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
910 y++, m = DAYSPERYEAR + LEAPYEAR(y))
913 /* Now we have the years in y and the day-of-the-year in tm */
914 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
915 #ifdef USE_RTC_CENTURY
916 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
922 if (m == 1 && LEAPYEAR(y))
929 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
930 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
932 /* Reenable RTC updates and interrupts. */
933 writertc(RTC_STATUSB, rtc_statusb);
939 * Start both clocks running. DragonFly note: the stat clock is no longer
940 * used. Instead, 8254 based systimers are used for all major clock
941 * interrupts. statclock_disable is set by default.
949 struct intrec *clkdesc;
952 if (statclock_disable) {
954 * The stat interrupt mask is different without the
955 * statistics clock. Also, don't set the interrupt
956 * flag which would normally cause the RTC to generate
959 stat_imask = HWI_MASK | SWI_MASK;
960 rtc_statusb = RTCSB_24HR;
962 /* Setting stathz to nonzero early helps avoid races. */
963 stathz = RTC_NOPROFRATE;
964 profhz = RTC_PROFRATE;
967 /* Finish initializing 8253 timer 0. */
970 apic_8254_intr = isa_apic_irq(0);
972 if (apic_8254_intr >= 0 ) {
973 if (apic_int_type(0, 0) == 3)
976 /* look for ExtInt on pin 0 */
977 if (apic_int_type(0, 0) == 3) {
978 apic_8254_intr = apic_irq(0, 0);
979 setup_8254_mixed_mode();
981 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
984 clkdesc = inthand_add("clk", apic_8254_intr, (inthand2_t *)clkintr,
985 NULL, &clk_imask, INTR_EXCL | INTR_FAST, NULL);
986 INTREN(1 << apic_8254_intr);
990 inthand_add("clk", 0, (inthand2_t *)clkintr, NULL, &clk_imask,
991 INTR_EXCL | INTR_FAST, NULL);
996 /* Initialize RTC. */
997 writertc(RTC_STATUSA, rtc_statusa);
998 writertc(RTC_STATUSB, RTCSB_24HR);
1000 if (statclock_disable == 0) {
1001 diag = rtcin(RTC_DIAG);
1003 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
1006 if (isa_apic_irq(8) != 8)
1007 panic("APIC RTC != 8");
1008 #endif /* APIC_IO */
1010 inthand_add("rtc", 8, (inthand2_t *)rtcintr, NULL, &stat_imask,
1011 INTR_EXCL | INTR_FAST, NULL);
1017 #endif /* APIC_IO */
1019 writertc(RTC_STATUSB, rtc_statusb);
1023 if (apic_8254_trial) {
1025 int lastcnt = read_intr_count(apic_8254_intr);
1028 * XXX this assumes the 8254 is the cpu timer. Force an
1029 * 8254 Timer0 interrupt and wait 1/100s for it to happen,
1030 * then see if we got it.
1032 printf("APIC_IO: Testing 8254 interrupt delivery\n");
1033 cputimer_intr_reload(2); /* XXX assumes 8254 */
1034 base = sys_cputimer->count();
1035 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
1037 if (read_intr_count(apic_8254_intr) - lastcnt == 0) {
1039 * The MP table is broken.
1040 * The 8254 was not connected to the specified pin
1042 * Workaround: Limited variant of mixed mode.
1044 INTRDIS(1 << apic_8254_intr);
1045 inthand_remove(clkdesc);
1046 printf("APIC_IO: Broken MP table detected: "
1047 "8254 is not connected to "
1048 "IOAPIC #%d intpin %d\n",
1049 int_to_apicintpin[apic_8254_intr].ioapic,
1050 int_to_apicintpin[apic_8254_intr].int_pin);
1052 * Revoke current ISA IRQ 0 assignment and
1053 * configure a fallback interrupt routing from
1054 * the 8254 Timer via the 8259 PIC to the
1055 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1056 * We reuse the low level interrupt handler number.
1058 if (apic_irq(0, 0) < 0) {
1059 revoke_apic_irq(apic_8254_intr);
1060 assign_apic_irq(0, 0, apic_8254_intr);
1062 apic_8254_intr = apic_irq(0, 0);
1063 setup_8254_mixed_mode();
1064 inthand_add("clk", apic_8254_intr,
1065 (inthand2_t *)clkintr,
1067 INTR_EXCL | INTR_FAST, NULL);
1068 INTREN(1 << apic_8254_intr);
1072 if (apic_int_type(0, 0) != 3 ||
1073 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1074 int_to_apicintpin[apic_8254_intr].int_pin != 0) {
1075 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1076 int_to_apicintpin[apic_8254_intr].ioapic,
1077 int_to_apicintpin[apic_8254_intr].int_pin);
1080 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1083 callout_init(&sysbeepstop_ch);
1088 read_intr_count(int vec)
1091 up = intr_countp[vec];
1098 setup_8254_mixed_mode()
1101 * Allow 8254 timer to INTerrupt 8259:
1102 * re-initialize master 8259:
1103 * reset; prog 4 bytes, single ICU, edge triggered
1105 outb(IO_ICU1, 0x13);
1106 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */
1107 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1108 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1109 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1111 /* program IO APIC for type 3 INT on INT0 */
1112 if (ext_int_setup(0, 0) < 0)
1113 panic("8254 redirect via APIC pin0 impossible!");
1118 setstatclockrate(int newhz)
1120 if (newhz == RTC_PROFRATE)
1121 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1123 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1124 writertc(RTC_STATUSA, rtc_statusa);
1129 tsc_get_timecount(struct timecounter *tc)
1135 #ifdef KERN_TIMESTAMP
1136 #define KERN_TIMESTAMP_SIZE 16384
1137 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1138 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1139 sizeof(tsc), "LU", "Kernel timestamps");
1145 tsc[i] = (u_int32_t)rdtsc();
1148 if (i >= KERN_TIMESTAMP_SIZE)
1150 tsc[i] = 0; /* mark last entry */
1152 #endif /* KERN_TIMESTAMP */
1159 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1166 if (sys_cputimer == &i8254_cputimer)
1167 count = sys_cputimer->count();
1175 snprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1176 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1179 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1180 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1182 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1183 0, 0, hw_i8254_timestamp, "A", "");