2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
37 #include "opt_ifpoll.h"
39 #include <sys/param.h>
41 #include <sys/endian.h>
42 #include <sys/kernel.h>
43 #include <sys/interrupt.h>
45 #include <sys/malloc.h>
46 #include <sys/queue.h>
48 #include <sys/serialize.h>
49 #include <sys/socket.h>
50 #include <sys/sockio.h>
51 #include <sys/sysctl.h>
53 #include <netinet/ip.h>
54 #include <netinet/tcp.h>
57 #include <net/ethernet.h>
59 #include <net/if_arp.h>
60 #include <net/if_dl.h>
61 #include <net/if_media.h>
62 #include <net/if_poll.h>
63 #include <net/if_types.h>
64 #include <net/ifq_var.h>
65 #include <net/vlan/if_vlan_var.h>
66 #include <net/vlan/if_vlan_ether.h>
68 #include <dev/netif/mii_layer/mii.h>
69 #include <dev/netif/mii_layer/miivar.h>
70 #include <dev/netif/mii_layer/brgphyreg.h>
72 #include <bus/pci/pcidevs.h>
73 #include <bus/pci/pcireg.h>
74 #include <bus/pci/pcivar.h>
76 #include <dev/netif/bge/if_bgereg.h>
77 #include <dev/netif/bnx/if_bnxvar.h>
79 /* "device miibus" required. See GENERIC if you get errors here. */
80 #include "miibus_if.h"
82 #define BNX_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
84 #define BNX_INTR_CKINTVL ((10 * hz) / 1000) /* 10ms */
86 static const struct bnx_type {
91 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
92 "Broadcom BCM5717 Gigabit Ethernet" },
93 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717C,
94 "Broadcom BCM5717C Gigabit Ethernet" },
95 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
96 "Broadcom BCM5718 Gigabit Ethernet" },
97 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
98 "Broadcom BCM5719 Gigabit Ethernet" },
99 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
100 "Broadcom BCM5720 Gigabit Ethernet" },
102 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5725,
103 "Broadcom BCM5725 Gigabit Ethernet" },
104 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5727,
105 "Broadcom BCM5727 Gigabit Ethernet" },
106 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5762,
107 "Broadcom BCM5762 Gigabit Ethernet" },
109 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
110 "Broadcom BCM57761 Gigabit Ethernet" },
111 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762,
112 "Broadcom BCM57762 Gigabit Ethernet" },
113 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
114 "Broadcom BCM57765 Gigabit Ethernet" },
115 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766,
116 "Broadcom BCM57766 Gigabit Ethernet" },
117 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
118 "Broadcom BCM57781 Gigabit Ethernet" },
119 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782,
120 "Broadcom BCM57782 Gigabit Ethernet" },
121 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
122 "Broadcom BCM57785 Gigabit Ethernet" },
123 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786,
124 "Broadcom BCM57786 Gigabit Ethernet" },
125 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
126 "Broadcom BCM57791 Fast Ethernet" },
127 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
128 "Broadcom BCM57795 Fast Ethernet" },
133 #define BNX_IS_JUMBO_CAPABLE(sc) ((sc)->bnx_flags & BNX_FLAG_JUMBO)
134 #define BNX_IS_5717_PLUS(sc) ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
135 #define BNX_IS_57765_PLUS(sc) ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
136 #define BNX_IS_57765_FAMILY(sc) \
137 ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
139 typedef int (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
141 static int bnx_probe(device_t);
142 static int bnx_attach(device_t);
143 static int bnx_detach(device_t);
144 static void bnx_shutdown(device_t);
145 static int bnx_suspend(device_t);
146 static int bnx_resume(device_t);
147 static int bnx_miibus_readreg(device_t, int, int);
148 static int bnx_miibus_writereg(device_t, int, int, int);
149 static void bnx_miibus_statchg(device_t);
152 static void bnx_npoll(struct ifnet *, struct ifpoll_info *);
153 static void bnx_npoll_compat(struct ifnet *, void *, int);
155 static void bnx_intr_legacy(void *);
156 static void bnx_msi(void *);
157 static void bnx_msi_oneshot(void *);
158 static void bnx_intr(struct bnx_softc *);
159 static void bnx_enable_intr(struct bnx_softc *);
160 static void bnx_disable_intr(struct bnx_softc *);
161 static void bnx_txeof(struct bnx_softc *, uint16_t);
162 static void bnx_rxeof(struct bnx_softc *, uint16_t, int);
164 static void bnx_start(struct ifnet *, struct ifaltq_subque *);
165 static int bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
166 static void bnx_init(void *);
167 static void bnx_stop(struct bnx_softc *);
168 static void bnx_watchdog(struct ifnet *);
169 static int bnx_ifmedia_upd(struct ifnet *);
170 static void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
171 static void bnx_tick(void *);
173 static int bnx_alloc_jumbo_mem(struct bnx_softc *);
174 static void bnx_free_jumbo_mem(struct bnx_softc *);
175 static struct bnx_jslot
176 *bnx_jalloc(struct bnx_softc *);
177 static void bnx_jfree(void *);
178 static void bnx_jref(void *);
179 static int bnx_newbuf_std(struct bnx_softc *, int, int);
180 static int bnx_newbuf_jumbo(struct bnx_softc *, int, int);
181 static void bnx_setup_rxdesc_std(struct bnx_softc *, int);
182 static void bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
183 static int bnx_init_rx_ring_std(struct bnx_softc *);
184 static void bnx_free_rx_ring_std(struct bnx_softc *);
185 static int bnx_init_rx_ring_jumbo(struct bnx_softc *);
186 static void bnx_free_rx_ring_jumbo(struct bnx_softc *);
187 static void bnx_free_tx_ring(struct bnx_softc *);
188 static int bnx_init_tx_ring(struct bnx_softc *);
189 static int bnx_dma_alloc(struct bnx_softc *);
190 static void bnx_dma_free(struct bnx_softc *);
191 static int bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
192 bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
193 static void bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
195 bnx_defrag_shortdma(struct mbuf *);
196 static int bnx_encap(struct bnx_softc *, struct mbuf **,
198 static int bnx_setup_tso(struct bnx_softc *, struct mbuf **,
199 uint16_t *, uint16_t *);
201 static void bnx_reset(struct bnx_softc *);
202 static int bnx_chipinit(struct bnx_softc *);
203 static int bnx_blockinit(struct bnx_softc *);
204 static void bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
205 static void bnx_enable_msi(struct bnx_softc *sc);
206 static void bnx_setmulti(struct bnx_softc *);
207 static void bnx_setpromisc(struct bnx_softc *);
208 static void bnx_stats_update_regs(struct bnx_softc *);
209 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
211 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
212 static void bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
214 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
216 static void bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
217 static void bnx_writembx(struct bnx_softc *, int, int);
218 static int bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
219 static uint8_t bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
220 static int bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
222 static void bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
223 static void bnx_copper_link_upd(struct bnx_softc *, uint32_t);
224 static void bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
225 static void bnx_link_poll(struct bnx_softc *);
227 static int bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
228 static int bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
229 static int bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
230 static int bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
232 static void bnx_coal_change(struct bnx_softc *);
233 static int bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
234 static int bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
235 static int bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
236 static int bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
237 static int bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
238 static int bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
239 static int bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
242 static int bnx_msi_enable = 1;
243 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
245 static device_method_t bnx_methods[] = {
246 /* Device interface */
247 DEVMETHOD(device_probe, bnx_probe),
248 DEVMETHOD(device_attach, bnx_attach),
249 DEVMETHOD(device_detach, bnx_detach),
250 DEVMETHOD(device_shutdown, bnx_shutdown),
251 DEVMETHOD(device_suspend, bnx_suspend),
252 DEVMETHOD(device_resume, bnx_resume),
255 DEVMETHOD(bus_print_child, bus_generic_print_child),
256 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
259 DEVMETHOD(miibus_readreg, bnx_miibus_readreg),
260 DEVMETHOD(miibus_writereg, bnx_miibus_writereg),
261 DEVMETHOD(miibus_statchg, bnx_miibus_statchg),
266 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
267 static devclass_t bnx_devclass;
269 DECLARE_DUMMY_MODULE(if_bnx);
270 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
271 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
274 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
276 device_t dev = sc->bnx_dev;
279 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
280 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
281 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
286 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
288 device_t dev = sc->bnx_dev;
290 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
291 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
292 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
296 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
298 CSR_WRITE_4(sc, off, val);
302 bnx_writembx(struct bnx_softc *sc, int off, int val)
304 CSR_WRITE_4(sc, off, val);
308 * Read a sequence of bytes from NVRAM.
311 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
317 * Read a byte of data stored in the EEPROM at address 'addr.' The
318 * BCM570x supports both the traditional bitbang interface and an
319 * auto access interface for reading the EEPROM. We use the auto
323 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
329 * Enable use of auto EEPROM access so we can avoid
330 * having to use the bitbang method.
332 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
334 /* Reset the EEPROM, load the clock period. */
335 CSR_WRITE_4(sc, BGE_EE_ADDR,
336 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
339 /* Issue the read EEPROM command. */
340 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
342 /* Wait for completion */
343 for(i = 0; i < BNX_TIMEOUT * 10; i++) {
345 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
349 if (i == BNX_TIMEOUT) {
350 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
355 byte = CSR_READ_4(sc, BGE_EE_DATA);
357 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
363 * Read a sequence of bytes from the EEPROM.
366 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
372 for (byte = 0, err = 0, i = 0; i < len; i++) {
373 err = bnx_eeprom_getbyte(sc, off + i, &byte);
383 bnx_miibus_readreg(device_t dev, int phy, int reg)
385 struct bnx_softc *sc = device_get_softc(dev);
389 KASSERT(phy == sc->bnx_phyno,
390 ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
392 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
393 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
394 CSR_WRITE_4(sc, BGE_MI_MODE,
395 sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
399 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
400 BGE_MIPHY(phy) | BGE_MIREG(reg));
402 /* Poll for the PHY register access to complete. */
403 for (i = 0; i < BNX_TIMEOUT; i++) {
405 val = CSR_READ_4(sc, BGE_MI_COMM);
406 if ((val & BGE_MICOMM_BUSY) == 0) {
408 val = CSR_READ_4(sc, BGE_MI_COMM);
412 if (i == BNX_TIMEOUT) {
413 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
414 "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
418 /* Restore the autopoll bit if necessary. */
419 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
420 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
424 if (val & BGE_MICOMM_READFAIL)
427 return (val & 0xFFFF);
431 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
433 struct bnx_softc *sc = device_get_softc(dev);
436 KASSERT(phy == sc->bnx_phyno,
437 ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
439 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
440 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
441 CSR_WRITE_4(sc, BGE_MI_MODE,
442 sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
446 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
447 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
449 for (i = 0; i < BNX_TIMEOUT; i++) {
451 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
453 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
457 if (i == BNX_TIMEOUT) {
458 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
459 "(phy %d, reg %d, val %d)\n", phy, reg, val);
462 /* Restore the autopoll bit if necessary. */
463 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
464 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
472 bnx_miibus_statchg(device_t dev)
474 struct bnx_softc *sc;
475 struct mii_data *mii;
477 sc = device_get_softc(dev);
478 mii = device_get_softc(sc->bnx_miibus);
480 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
481 (IFM_ACTIVE | IFM_AVALID)) {
482 switch (IFM_SUBTYPE(mii->mii_media_active)) {
499 if (sc->bnx_link == 0)
502 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
503 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
504 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
505 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
507 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
510 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
511 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
513 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
518 * Memory management for jumbo frames.
521 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
523 struct ifnet *ifp = &sc->arpcom.ac_if;
524 struct bnx_jslot *entry;
530 * Create tag for jumbo mbufs.
531 * This is really a bit of a kludge. We allocate a special
532 * jumbo buffer pool which (thanks to the way our DMA
533 * memory allocation works) will consist of contiguous
534 * pages. This means that even though a jumbo buffer might
535 * be larger than a page size, we don't really need to
536 * map it into more than one DMA segment. However, the
537 * default mbuf tag will result in multi-segment mappings,
538 * so we have to create a special jumbo mbuf tag that
539 * lets us get away with mapping the jumbo buffers as
540 * a single segment. I think eventually the driver should
541 * be changed so that it uses ordinary mbufs and cluster
542 * buffers, i.e. jumbo frames can span multiple DMA
543 * descriptors. But that's a project for another day.
547 * Create DMA stuffs for jumbo RX ring.
549 error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
550 &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
551 &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
552 (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
553 &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
555 if_printf(ifp, "could not create jumbo RX ring\n");
560 * Create DMA stuffs for jumbo buffer block.
562 error = bnx_dma_block_alloc(sc, BNX_JMEM,
563 &sc->bnx_cdata.bnx_jumbo_tag,
564 &sc->bnx_cdata.bnx_jumbo_map,
565 (void **)&sc->bnx_ldata.bnx_jumbo_buf,
568 if_printf(ifp, "could not create jumbo buffer\n");
572 SLIST_INIT(&sc->bnx_jfree_listhead);
575 * Now divide it up into 9K pieces and save the addresses
576 * in an array. Note that we play an evil trick here by using
577 * the first few bytes in the buffer to hold the the address
578 * of the softc structure for this interface. This is because
579 * bnx_jfree() needs it, but it is called by the mbuf management
580 * code which will not pass it to us explicitly.
582 for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
583 entry = &sc->bnx_cdata.bnx_jslots[i];
585 entry->bnx_buf = ptr;
586 entry->bnx_paddr = paddr;
587 entry->bnx_inuse = 0;
589 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
598 bnx_free_jumbo_mem(struct bnx_softc *sc)
600 /* Destroy jumbo RX ring. */
601 bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
602 sc->bnx_cdata.bnx_rx_jumbo_ring_map,
603 sc->bnx_ldata.bnx_rx_jumbo_ring);
605 /* Destroy jumbo buffer block. */
606 bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
607 sc->bnx_cdata.bnx_jumbo_map,
608 sc->bnx_ldata.bnx_jumbo_buf);
612 * Allocate a jumbo buffer.
614 static struct bnx_jslot *
615 bnx_jalloc(struct bnx_softc *sc)
617 struct bnx_jslot *entry;
619 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
620 entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
622 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
623 entry->bnx_inuse = 1;
625 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
627 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
632 * Adjust usage count on a jumbo buffer.
637 struct bnx_jslot *entry = (struct bnx_jslot *)arg;
638 struct bnx_softc *sc = entry->bnx_sc;
641 panic("bnx_jref: can't find softc pointer!");
643 if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
644 panic("bnx_jref: asked to reference buffer "
645 "that we don't manage!");
646 } else if (entry->bnx_inuse == 0) {
647 panic("bnx_jref: buffer already free!");
649 atomic_add_int(&entry->bnx_inuse, 1);
654 * Release a jumbo buffer.
659 struct bnx_jslot *entry = (struct bnx_jslot *)arg;
660 struct bnx_softc *sc = entry->bnx_sc;
663 panic("bnx_jfree: can't find softc pointer!");
665 if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
666 panic("bnx_jfree: asked to free buffer that we don't manage!");
667 } else if (entry->bnx_inuse == 0) {
668 panic("bnx_jfree: buffer already free!");
671 * Possible MP race to 0, use the serializer. The atomic insn
672 * is still needed for races against bnx_jref().
674 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
675 atomic_subtract_int(&entry->bnx_inuse, 1);
676 if (entry->bnx_inuse == 0) {
677 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead,
680 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
686 * Intialize a standard receive ring descriptor.
689 bnx_newbuf_std(struct bnx_softc *sc, int i, int init)
691 struct mbuf *m_new = NULL;
692 bus_dma_segment_t seg;
696 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
699 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
700 m_adj(m_new, ETHER_ALIGN);
702 error = bus_dmamap_load_mbuf_segment(sc->bnx_cdata.bnx_rx_mtag,
703 sc->bnx_cdata.bnx_rx_tmpmap, m_new,
704 &seg, 1, &nsegs, BUS_DMA_NOWAIT);
711 bus_dmamap_sync(sc->bnx_cdata.bnx_rx_mtag,
712 sc->bnx_cdata.bnx_rx_std_dmamap[i],
713 BUS_DMASYNC_POSTREAD);
714 bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
715 sc->bnx_cdata.bnx_rx_std_dmamap[i]);
718 map = sc->bnx_cdata.bnx_rx_tmpmap;
719 sc->bnx_cdata.bnx_rx_tmpmap = sc->bnx_cdata.bnx_rx_std_dmamap[i];
720 sc->bnx_cdata.bnx_rx_std_dmamap[i] = map;
722 sc->bnx_cdata.bnx_rx_std_chain[i].bnx_mbuf = m_new;
723 sc->bnx_cdata.bnx_rx_std_chain[i].bnx_paddr = seg.ds_addr;
725 bnx_setup_rxdesc_std(sc, i);
730 bnx_setup_rxdesc_std(struct bnx_softc *sc, int i)
732 struct bnx_rxchain *rc;
735 rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
736 r = &sc->bnx_ldata.bnx_rx_std_ring[i];
738 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
739 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
740 r->bge_len = rc->bnx_mbuf->m_len;
742 r->bge_flags = BGE_RXBDFLAG_END;
746 * Initialize a jumbo receive ring descriptor. This allocates
747 * a jumbo buffer from the pool managed internally by the driver.
750 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
752 struct mbuf *m_new = NULL;
753 struct bnx_jslot *buf;
756 /* Allocate the mbuf. */
757 MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
761 /* Allocate the jumbo buffer */
762 buf = bnx_jalloc(sc);
768 /* Attach the buffer to the mbuf. */
769 m_new->m_ext.ext_arg = buf;
770 m_new->m_ext.ext_buf = buf->bnx_buf;
771 m_new->m_ext.ext_free = bnx_jfree;
772 m_new->m_ext.ext_ref = bnx_jref;
773 m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
775 m_new->m_flags |= M_EXT;
777 m_new->m_data = m_new->m_ext.ext_buf;
778 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
780 paddr = buf->bnx_paddr;
781 m_adj(m_new, ETHER_ALIGN);
782 paddr += ETHER_ALIGN;
784 /* Save necessary information */
785 sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_mbuf = m_new;
786 sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_paddr = paddr;
788 /* Set up the descriptor. */
789 bnx_setup_rxdesc_jumbo(sc, i);
794 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
797 struct bnx_rxchain *rc;
799 r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
800 rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
802 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
803 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
804 r->bge_len = rc->bnx_mbuf->m_len;
806 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
810 bnx_init_rx_ring_std(struct bnx_softc *sc)
814 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
815 error = bnx_newbuf_std(sc, i, 1);
820 sc->bnx_std = BGE_STD_RX_RING_CNT - 1;
821 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
827 bnx_free_rx_ring_std(struct bnx_softc *sc)
831 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
832 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
834 if (rc->bnx_mbuf != NULL) {
835 bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
836 sc->bnx_cdata.bnx_rx_std_dmamap[i]);
837 m_freem(rc->bnx_mbuf);
840 bzero(&sc->bnx_ldata.bnx_rx_std_ring[i],
841 sizeof(struct bge_rx_bd));
846 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
851 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
852 error = bnx_newbuf_jumbo(sc, i, 1);
857 sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
859 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
860 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
861 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
863 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
869 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
873 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
874 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
876 if (rc->bnx_mbuf != NULL) {
877 m_freem(rc->bnx_mbuf);
880 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
881 sizeof(struct bge_rx_bd));
886 bnx_free_tx_ring(struct bnx_softc *sc)
890 for (i = 0; i < BGE_TX_RING_CNT; i++) {
891 if (sc->bnx_cdata.bnx_tx_chain[i] != NULL) {
892 bus_dmamap_unload(sc->bnx_cdata.bnx_tx_mtag,
893 sc->bnx_cdata.bnx_tx_dmamap[i]);
894 m_freem(sc->bnx_cdata.bnx_tx_chain[i]);
895 sc->bnx_cdata.bnx_tx_chain[i] = NULL;
897 bzero(&sc->bnx_ldata.bnx_tx_ring[i],
898 sizeof(struct bge_tx_bd));
903 bnx_init_tx_ring(struct bnx_softc *sc)
906 sc->bnx_tx_saved_considx = 0;
907 sc->bnx_tx_prodidx = 0;
909 /* Initialize transmit producer index for host-memory send ring. */
910 bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bnx_tx_prodidx);
911 bnx_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
917 bnx_setmulti(struct bnx_softc *sc)
920 struct ifmultiaddr *ifma;
921 uint32_t hashes[4] = { 0, 0, 0, 0 };
924 ifp = &sc->arpcom.ac_if;
926 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
927 for (i = 0; i < 4; i++)
928 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
932 /* First, zot all the existing filters. */
933 for (i = 0; i < 4; i++)
934 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
936 /* Now program new ones. */
937 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
938 if (ifma->ifma_addr->sa_family != AF_LINK)
941 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
942 ETHER_ADDR_LEN) & 0x7f;
943 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
946 for (i = 0; i < 4; i++)
947 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
951 * Do endian, PCI and DMA initialization. Also check the on-board ROM
955 bnx_chipinit(struct bnx_softc *sc)
957 uint32_t dma_rw_ctl, mode_ctl;
960 /* Set endian type before we access any non-PCI registers. */
961 pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
962 BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
964 /* Clear the MAC control register */
965 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
968 * Clear the MAC statistics block in the NIC's
971 for (i = BGE_STATS_BLOCK;
972 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
973 BNX_MEMWIN_WRITE(sc, i, 0);
975 for (i = BGE_STATUS_BLOCK;
976 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
977 BNX_MEMWIN_WRITE(sc, i, 0);
979 if (BNX_IS_57765_FAMILY(sc)) {
982 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
983 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
984 val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
986 /* Access the lower 1K of PL PCI-E block registers. */
987 CSR_WRITE_4(sc, BGE_MODE_CTL,
988 val | BGE_MODECTL_PCIE_PL_SEL);
990 val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
991 val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
992 CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
994 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
996 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
997 /* Fix transmit hangs */
998 val = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);
999 val |= BGE_CPMU_PADRNG_CTL_RDIV2;
1000 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, val);
1002 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1003 val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1005 /* Access the lower 1K of DL PCI-E block registers. */
1006 CSR_WRITE_4(sc, BGE_MODE_CTL,
1007 val | BGE_MODECTL_PCIE_DL_SEL);
1009 val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
1010 val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
1011 val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
1012 CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
1014 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1017 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
1018 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
1019 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
1020 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
1024 * Set up the PCI DMA control register.
1026 dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4);
1028 * Disable 32bytes cache alignment for DMA write to host memory
1031 * 64bytes cache alignment for DMA write to host memory is still
1034 dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1035 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1036 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1038 * Enable HW workaround for controllers that misinterpret
1039 * a status tag update and leave interrupts permanently
1042 if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1043 sc->bnx_asicrev != BGE_ASICREV_BCM5762 &&
1044 !BNX_IS_57765_FAMILY(sc))
1045 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1047 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n",
1050 pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1053 * Set up general mode register.
1055 mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1056 BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1057 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1060 * Disable memory write invalidate. Apparently it is not supported
1061 * properly by these devices. Also ensure that INTx isn't disabled,
1062 * as these chips need it even when using MSI.
1064 PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1065 (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1067 /* Set the timer prescaler (always 66Mhz) */
1068 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1074 bnx_blockinit(struct bnx_softc *sc)
1076 struct bge_rcb *rcb;
1083 * Initialize the memory window pointer register so that
1084 * we can access the first 32K of internal NIC RAM. This will
1085 * allow us to set up the TX send ring RCBs and the RX return
1086 * ring RCBs, plus other things which live in NIC memory.
1088 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1090 /* Configure mbuf pool watermarks */
1091 if (BNX_IS_57765_PLUS(sc)) {
1092 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1093 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1094 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1095 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1097 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1098 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1101 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1102 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1103 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1106 /* Configure DMA resource watermarks */
1107 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1108 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1110 /* Enable buffer manager */
1111 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1113 * Change the arbitration algorithm of TXMBUF read request to
1114 * round-robin instead of priority based for BCM5719. When
1115 * TXFIFO is almost empty, RDMA will hold its request until
1116 * TXFIFO is not almost empty.
1118 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1119 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1120 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1121 sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 ||
1122 sc->bnx_chipid == BGE_CHIPID_BCM5720_A0)
1123 val |= BGE_BMANMODE_LOMBUF_ATTN;
1124 CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1126 /* Poll for buffer manager start indication */
1127 for (i = 0; i < BNX_TIMEOUT; i++) {
1128 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1133 if (i == BNX_TIMEOUT) {
1134 if_printf(&sc->arpcom.ac_if,
1135 "buffer manager failed to start\n");
1139 /* Enable flow-through queues */
1140 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1141 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1143 /* Wait until queue initialization is complete */
1144 for (i = 0; i < BNX_TIMEOUT; i++) {
1145 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1150 if (i == BNX_TIMEOUT) {
1151 if_printf(&sc->arpcom.ac_if,
1152 "flow-through queue init failed\n");
1157 * Summary of rings supported by the controller:
1159 * Standard Receive Producer Ring
1160 * - This ring is used to feed receive buffers for "standard"
1161 * sized frames (typically 1536 bytes) to the controller.
1163 * Jumbo Receive Producer Ring
1164 * - This ring is used to feed receive buffers for jumbo sized
1165 * frames (i.e. anything bigger than the "standard" frames)
1166 * to the controller.
1168 * Mini Receive Producer Ring
1169 * - This ring is used to feed receive buffers for "mini"
1170 * sized frames to the controller.
1171 * - This feature required external memory for the controller
1172 * but was never used in a production system. Should always
1175 * Receive Return Ring
1176 * - After the controller has placed an incoming frame into a
1177 * receive buffer that buffer is moved into a receive return
1178 * ring. The driver is then responsible to passing the
1179 * buffer up to the stack. Many versions of the controller
1180 * support multiple RR rings.
1183 * - This ring is used for outgoing frames. Many versions of
1184 * the controller support multiple send rings.
1187 /* Initialize the standard receive producer ring control block. */
1188 rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1189 rcb->bge_hostaddr.bge_addr_lo =
1190 BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1191 rcb->bge_hostaddr.bge_addr_hi =
1192 BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1193 if (BNX_IS_57765_PLUS(sc)) {
1195 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1196 * Bits 15-2 : Maximum RX frame size
1197 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled
1200 rcb->bge_maxlen_flags =
1201 BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1204 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1205 * Bits 15-2 : Reserved (should be 0)
1206 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1209 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1211 if (BNX_IS_5717_PLUS(sc))
1212 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1214 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1215 /* Write the standard receive producer ring control block. */
1216 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1217 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1218 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1219 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1220 /* Reset the standard receive producer ring producer index. */
1221 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1224 * Initialize the jumbo RX producer ring control
1225 * block. We set the 'ring disabled' bit in the
1226 * flags field until we're actually ready to start
1227 * using this ring (i.e. once we set the MTU
1228 * high enough to require it).
1230 if (BNX_IS_JUMBO_CAPABLE(sc)) {
1231 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1232 /* Get the jumbo receive producer ring RCB parameters. */
1233 rcb->bge_hostaddr.bge_addr_lo =
1234 BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1235 rcb->bge_hostaddr.bge_addr_hi =
1236 BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1237 rcb->bge_maxlen_flags =
1238 BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1239 BGE_RCB_FLAG_RING_DISABLED);
1240 if (BNX_IS_5717_PLUS(sc))
1241 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1243 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1244 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1245 rcb->bge_hostaddr.bge_addr_hi);
1246 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1247 rcb->bge_hostaddr.bge_addr_lo);
1248 /* Program the jumbo receive producer ring RCB parameters. */
1249 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1250 rcb->bge_maxlen_flags);
1251 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1252 /* Reset the jumbo receive producer ring producer index. */
1253 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1257 * The BD ring replenish thresholds control how often the
1258 * hardware fetches new BD's from the producer rings in host
1259 * memory. Setting the value too low on a busy system can
1260 * starve the hardware and recue the throughpout.
1262 * Set the BD ring replentish thresholds. The recommended
1263 * values are 1/8th the number of descriptors allocated to
1267 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1268 if (BNX_IS_JUMBO_CAPABLE(sc)) {
1269 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1270 BGE_JUMBO_RX_RING_CNT/8);
1272 if (BNX_IS_57765_PLUS(sc)) {
1273 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1274 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1278 * Disable all send rings by setting the 'ring disabled' bit
1279 * in the flags field of all the TX send ring control blocks,
1280 * located in NIC memory.
1282 if (BNX_IS_5717_PLUS(sc))
1284 else if (BNX_IS_57765_FAMILY(sc) ||
1285 sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1289 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1290 for (i = 0; i < limit; i++) {
1291 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1292 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1293 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1294 vrcb += sizeof(struct bge_rcb);
1297 /* Configure send ring RCB 0 (we use only the first ring) */
1298 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1299 BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_tx_ring_paddr);
1300 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1301 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1302 if (BNX_IS_5717_PLUS(sc)) {
1303 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1305 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1306 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1308 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1309 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1312 * Disable all receive return rings by setting the
1313 * 'ring disabled' bit in the flags field of all the receive
1314 * return ring control blocks, located in NIC memory.
1316 if (BNX_IS_5717_PLUS(sc)) {
1317 /* Should be 17, use 16 until we get an SRAM map. */
1319 } else if (BNX_IS_57765_FAMILY(sc) ||
1320 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1325 /* Disable all receive return rings. */
1326 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1327 for (i = 0; i < limit; i++) {
1328 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1329 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1330 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1331 BGE_RCB_FLAG_RING_DISABLED);
1332 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1333 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1334 (i * (sizeof(uint64_t))), 0);
1335 vrcb += sizeof(struct bge_rcb);
1339 * Set up receive return ring 0. Note that the NIC address
1340 * for RX return rings is 0x0. The return rings live entirely
1341 * within the host, so the nicaddr field in the RCB isn't used.
1343 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1344 BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_rx_return_ring_paddr);
1345 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1346 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1347 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1348 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1349 BGE_RCB_MAXLEN_FLAGS(sc->bnx_return_ring_cnt, 0));
1351 /* Set random backoff seed for TX */
1352 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1353 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1354 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1355 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1356 BGE_TX_BACKOFF_SEED_MASK);
1358 /* Set inter-packet gap */
1360 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1361 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1362 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1363 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1365 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1368 * Specify which ring to use for packets that don't match
1371 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1374 * Configure number of RX lists. One interrupt distribution
1375 * list, sixteen active lists, one bad frames class.
1377 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1379 /* Inialize RX list placement stats mask. */
1380 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1381 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1383 /* Disable host coalescing until we get it set up */
1384 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1386 /* Poll to make sure it's shut down. */
1387 for (i = 0; i < BNX_TIMEOUT; i++) {
1388 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1393 if (i == BNX_TIMEOUT) {
1394 if_printf(&sc->arpcom.ac_if,
1395 "host coalescing engine failed to idle\n");
1399 /* Set up host coalescing defaults */
1400 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bnx_rx_coal_ticks);
1401 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bnx_tx_coal_ticks);
1402 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bnx_rx_coal_bds);
1403 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bnx_tx_coal_bds);
1404 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bnx_rx_coal_bds_int);
1405 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bnx_tx_coal_bds_int);
1407 /* Set up address of status block */
1408 bzero(sc->bnx_ldata.bnx_status_block, BGE_STATUS_BLK_SZ);
1409 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1410 BGE_ADDR_HI(sc->bnx_ldata.bnx_status_block_paddr));
1411 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1412 BGE_ADDR_LO(sc->bnx_ldata.bnx_status_block_paddr));
1414 /* Set up status block partail update size. */
1415 val = BGE_STATBLKSZ_32BYTE;
1418 * Does not seem to have visible effect in both
1419 * bulk data (1472B UDP datagram) and tiny data
1420 * (18B UDP datagram) TX tests.
1422 val |= BGE_HCCMODE_CLRTICK_TX;
1424 /* Turn on host coalescing state machine */
1425 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1427 /* Turn on RX BD completion state machine and enable attentions */
1428 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1429 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1431 /* Turn on RX list placement state machine */
1432 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1434 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1435 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1436 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1437 BGE_MACMODE_FRMHDR_DMA_ENB;
1439 if (sc->bnx_flags & BNX_FLAG_TBI)
1440 val |= BGE_PORTMODE_TBI;
1441 else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1442 val |= BGE_PORTMODE_GMII;
1444 val |= BGE_PORTMODE_MII;
1446 /* Turn on DMA, clear stats */
1447 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1449 /* Set misc. local control, enable interrupts on attentions */
1450 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1453 /* Assert GPIO pins for PHY reset */
1454 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1455 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1456 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1457 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1460 /* Turn on write DMA state machine */
1461 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1462 /* Enable host coalescing bug fix. */
1463 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1464 if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1465 /* Request larger DMA burst size to get better performance. */
1466 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1468 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1471 if (BNX_IS_57765_PLUS(sc)) {
1472 uint32_t dmactl, dmactl_reg;
1474 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1475 dmactl_reg = BGE_RDMA_RSRVCTRL2;
1477 dmactl_reg = BGE_RDMA_RSRVCTRL;
1479 dmactl = CSR_READ_4(sc, dmactl_reg);
1481 * Adjust tx margin to prevent TX data corruption and
1482 * fix internal FIFO overflow.
1484 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1485 sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1486 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1487 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1488 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1489 BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1490 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1491 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1492 BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1495 * Enable fix for read DMA FIFO overruns.
1496 * The fix is to limit the number of RX BDs
1497 * the hardware would fetch at a fime.
1499 CSR_WRITE_4(sc, dmactl_reg,
1500 dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1503 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1504 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1505 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1506 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1507 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1508 } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1509 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1512 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1513 ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL2;
1515 ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL;
1518 * Allow 4KB burst length reads for non-LSO frames.
1519 * Enable 512B burst length reads for buffer descriptors.
1521 CSR_WRITE_4(sc, ctrl_reg,
1522 CSR_READ_4(sc, ctrl_reg) |
1523 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1524 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1527 /* Turn on read DMA state machine */
1528 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1529 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1530 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1531 if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1532 sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1533 sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1534 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1535 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1536 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1538 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1539 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1540 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1541 BGE_RDMAMODE_H2BNC_VLAN_DET;
1543 * Allow multiple outstanding read requests from
1544 * non-LSO read DMA engine.
1546 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1548 if (sc->bnx_asicrev == BGE_ASICREV_BCM57766)
1549 val |= BGE_RDMAMODE_JMB_2K_MMRR;
1550 if (sc->bnx_flags & BNX_FLAG_TSO)
1551 val |= BGE_RDMAMODE_TSO4_ENABLE;
1552 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1553 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1556 /* Turn on RX data completion state machine */
1557 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1559 /* Turn on RX BD initiator state machine */
1560 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1562 /* Turn on RX data and RX BD initiator state machine */
1563 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1565 /* Turn on send BD completion state machine */
1566 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1568 /* Turn on send data completion state machine */
1569 val = BGE_SDCMODE_ENABLE;
1570 if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1571 val |= BGE_SDCMODE_CDELAY;
1572 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1574 /* Turn on send data initiator state machine */
1575 if (sc->bnx_flags & BNX_FLAG_TSO) {
1576 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1577 BGE_SDIMODE_HW_LSO_PRE_DMA);
1579 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1582 /* Turn on send BD initiator state machine */
1583 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1585 /* Turn on send BD selector state machine */
1586 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1588 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1589 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1590 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1592 /* ack/clear link change events */
1593 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1594 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1595 BGE_MACSTAT_LINK_CHANGED);
1596 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1599 * Enable attention when the link has changed state for
1600 * devices that use auto polling.
1602 if (sc->bnx_flags & BNX_FLAG_TBI) {
1603 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1605 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1606 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1612 * Clear any pending link state attention.
1613 * Otherwise some link state change events may be lost until attention
1614 * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1615 * It's not necessary on newer BCM chips - perhaps enabling link
1616 * state change attentions implies clearing pending attention.
1618 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1619 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1620 BGE_MACSTAT_LINK_CHANGED);
1622 /* Enable link state change attentions. */
1623 BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1629 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1630 * against our list and return its name if we find a match. Note
1631 * that since the Broadcom controller contains VPD support, we
1632 * can get the device name string from the controller itself instead
1633 * of the compiled-in string. This is a little slow, but it guarantees
1634 * we'll always announce the right product name.
1637 bnx_probe(device_t dev)
1639 const struct bnx_type *t;
1640 uint16_t product, vendor;
1642 if (!pci_is_pcie(dev))
1645 product = pci_get_device(dev);
1646 vendor = pci_get_vendor(dev);
1648 for (t = bnx_devs; t->bnx_name != NULL; t++) {
1649 if (vendor == t->bnx_vid && product == t->bnx_did)
1652 if (t->bnx_name == NULL)
1655 device_set_desc(dev, t->bnx_name);
1660 bnx_attach(device_t dev)
1663 struct bnx_softc *sc;
1665 int error = 0, rid, capmask;
1666 uint8_t ether_addr[ETHER_ADDR_LEN];
1668 driver_intr_t *intr_func;
1669 uintptr_t mii_priv = 0;
1671 #ifdef BNX_TSO_DEBUG
1676 sc = device_get_softc(dev);
1678 callout_init_mp(&sc->bnx_stat_timer);
1679 callout_init_mp(&sc->bnx_intr_timer);
1680 lwkt_serialize_init(&sc->bnx_jslot_serializer);
1682 product = pci_get_device(dev);
1684 #ifndef BURN_BRIDGES
1685 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1688 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1689 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1691 device_printf(dev, "chip is in D%d power mode "
1692 "-- setting to D0\n", pci_get_powerstate(dev));
1694 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1696 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1697 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1699 #endif /* !BURN_BRIDGE */
1702 * Map control/status registers.
1704 pci_enable_busmaster(dev);
1707 sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1710 if (sc->bnx_res == NULL) {
1711 device_printf(dev, "couldn't map memory\n");
1715 sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1716 sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1718 /* Save various chip information */
1720 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1721 BGE_PCIMISCCTL_ASICREV_SHIFT;
1722 if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1723 /* All chips having dedicated ASICREV register have CPMU */
1724 sc->bnx_flags |= BNX_FLAG_CPMU;
1727 case PCI_PRODUCT_BROADCOM_BCM5717:
1728 case PCI_PRODUCT_BROADCOM_BCM5717C:
1729 case PCI_PRODUCT_BROADCOM_BCM5718:
1730 case PCI_PRODUCT_BROADCOM_BCM5719:
1731 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1732 case PCI_PRODUCT_BROADCOM_BCM5725:
1733 case PCI_PRODUCT_BROADCOM_BCM5727:
1734 case PCI_PRODUCT_BROADCOM_BCM5762:
1735 sc->bnx_chipid = pci_read_config(dev,
1736 BGE_PCI_GEN2_PRODID_ASICREV, 4);
1739 case PCI_PRODUCT_BROADCOM_BCM57761:
1740 case PCI_PRODUCT_BROADCOM_BCM57762:
1741 case PCI_PRODUCT_BROADCOM_BCM57765:
1742 case PCI_PRODUCT_BROADCOM_BCM57766:
1743 case PCI_PRODUCT_BROADCOM_BCM57781:
1744 case PCI_PRODUCT_BROADCOM_BCM57782:
1745 case PCI_PRODUCT_BROADCOM_BCM57785:
1746 case PCI_PRODUCT_BROADCOM_BCM57786:
1747 case PCI_PRODUCT_BROADCOM_BCM57791:
1748 case PCI_PRODUCT_BROADCOM_BCM57795:
1749 sc->bnx_chipid = pci_read_config(dev,
1750 BGE_PCI_GEN15_PRODID_ASICREV, 4);
1754 sc->bnx_chipid = pci_read_config(dev,
1755 BGE_PCI_PRODID_ASICREV, 4);
1759 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_C0)
1760 sc->bnx_chipid = BGE_CHIPID_BCM5720_A0;
1762 sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1763 sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1765 switch (sc->bnx_asicrev) {
1766 case BGE_ASICREV_BCM5717:
1767 case BGE_ASICREV_BCM5719:
1768 case BGE_ASICREV_BCM5720:
1769 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1772 case BGE_ASICREV_BCM5762:
1773 sc->bnx_flags |= BNX_FLAG_57765_PLUS;
1776 case BGE_ASICREV_BCM57765:
1777 case BGE_ASICREV_BCM57766:
1778 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1781 sc->bnx_flags |= BNX_FLAG_SHORTDMA;
1783 sc->bnx_flags |= BNX_FLAG_TSO;
1784 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 &&
1785 sc->bnx_chipid == BGE_CHIPID_BCM5719_A0)
1786 sc->bnx_flags &= ~BNX_FLAG_TSO;
1788 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1789 BNX_IS_57765_FAMILY(sc)) {
1791 * All BCM57785 and BCM5718 families chips have a bug that
1792 * under certain situation interrupt will not be enabled
1793 * even if status tag is written to BGE_MBX_IRQ0_LO mailbox.
1795 * While BCM5719 and BCM5720 have a hardware workaround
1796 * which could fix the above bug.
1797 * See the comment near BGE_PCIDMARWCTL_TAGGED_STATUS_WA in
1800 * For the rest of the chips in these two families, we will
1801 * have to poll the status block at high rate (10ms currently)
1802 * to check whether the interrupt is hosed or not.
1803 * See bnx_intr_check() for details.
1805 sc->bnx_flags |= BNX_FLAG_STATUSTAG_BUG;
1808 sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1809 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1810 sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1811 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1813 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1814 device_printf(dev, "CHIP ID 0x%08x; "
1815 "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1816 sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1819 * Set various PHY quirk flags.
1822 capmask = MII_CAPMASK_DEFAULT;
1823 if (product == PCI_PRODUCT_BROADCOM_BCM57791 ||
1824 product == PCI_PRODUCT_BROADCOM_BCM57795) {
1826 capmask &= ~BMSR_EXTSTAT;
1829 mii_priv |= BRGPHY_FLAG_WIRESPEED;
1830 if (sc->bnx_chipid == BGE_CHIPID_BCM5762_A0)
1831 mii_priv |= BRGPHY_FLAG_5762_A0;
1833 /* Initialize if_name earlier, so if_printf could be used */
1834 ifp = &sc->arpcom.ac_if;
1835 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1837 /* Try to reset the chip. */
1840 if (bnx_chipinit(sc)) {
1841 device_printf(dev, "chip initialization failed\n");
1847 * Get station address
1849 error = bnx_get_eaddr(sc, ether_addr);
1851 device_printf(dev, "failed to read station address\n");
1855 if (BNX_IS_57765_PLUS(sc)) {
1856 sc->bnx_return_ring_cnt = BGE_RETURN_RING_CNT;
1858 /* 5705/5750 limits RX return ring to 512 entries. */
1859 sc->bnx_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1862 error = bnx_dma_alloc(sc);
1867 * Allocate interrupt
1869 sc->bnx_irq_type = pci_alloc_1intr(dev, bnx_msi_enable, &sc->bnx_irq_rid,
1872 sc->bnx_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bnx_irq_rid,
1874 if (sc->bnx_irq == NULL) {
1875 device_printf(dev, "couldn't map interrupt\n");
1880 if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
1881 sc->bnx_flags |= BNX_FLAG_ONESHOT_MSI;
1885 /* Set default tuneable values. */
1886 sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
1887 sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
1888 sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
1889 sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
1890 sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_INT_DEF;
1891 sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_INT_DEF;
1892 sc->bnx_tx_wreg = BNX_TX_WREG_NSEGS;
1894 /* Set up ifnet structure */
1896 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1897 ifp->if_ioctl = bnx_ioctl;
1898 ifp->if_start = bnx_start;
1899 #ifdef IFPOLL_ENABLE
1900 ifp->if_npoll = bnx_npoll;
1902 ifp->if_watchdog = bnx_watchdog;
1903 ifp->if_init = bnx_init;
1904 ifp->if_mtu = ETHERMTU;
1905 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1906 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1907 ifq_set_ready(&ifp->if_snd);
1909 ifp->if_capabilities |= IFCAP_HWCSUM;
1910 ifp->if_hwassist = BNX_CSUM_FEATURES;
1911 if (sc->bnx_flags & BNX_FLAG_TSO) {
1912 ifp->if_capabilities |= IFCAP_TSO;
1913 ifp->if_hwassist |= CSUM_TSO;
1915 ifp->if_capenable = ifp->if_capabilities;
1918 * Figure out what sort of media we have by checking the
1919 * hardware config word in the first 32k of NIC internal memory,
1920 * or fall back to examining the EEPROM if necessary.
1921 * Note: on some BCM5700 cards, this value appears to be unset.
1922 * If that's the case, we have to rely on identifying the NIC
1923 * by its PCI subsystem ID, as we do below for the SysKonnect
1926 if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
1927 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1929 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1931 device_printf(dev, "failed to read EEPROM\n");
1935 hwcfg = ntohl(hwcfg);
1938 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1939 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
1940 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1941 sc->bnx_flags |= BNX_FLAG_TBI;
1944 if (sc->bnx_flags & BNX_FLAG_CPMU)
1945 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
1947 sc->bnx_mi_mode = BGE_MIMODE_BASE;
1949 /* Setup link status update stuffs */
1950 if (sc->bnx_flags & BNX_FLAG_TBI) {
1951 sc->bnx_link_upd = bnx_tbi_link_upd;
1952 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1953 } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1954 sc->bnx_link_upd = bnx_autopoll_link_upd;
1955 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1957 sc->bnx_link_upd = bnx_copper_link_upd;
1958 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1961 /* Set default PHY address */
1965 * PHY address mapping for various devices.
1967 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
1968 * ---------+-------+-------+-------+-------+
1969 * BCM57XX | 1 | X | X | X |
1970 * BCM5704 | 1 | X | 1 | X |
1971 * BCM5717 | 1 | 8 | 2 | 9 |
1972 * BCM5719 | 1 | 8 | 2 | 9 |
1973 * BCM5720 | 1 | 8 | 2 | 9 |
1975 * Other addresses may respond but they are not
1976 * IEEE compliant PHYs and should be ignored.
1978 if (BNX_IS_5717_PLUS(sc)) {
1981 f = pci_get_function(dev);
1982 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
1983 if (CSR_READ_4(sc, BGE_SGDIG_STS) &
1984 BGE_SGDIGSTS_IS_SERDES)
1985 sc->bnx_phyno = f + 8;
1987 sc->bnx_phyno = f + 1;
1989 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
1990 BGE_CPMU_PHY_STRAP_IS_SERDES)
1991 sc->bnx_phyno = f + 8;
1993 sc->bnx_phyno = f + 1;
1997 if (sc->bnx_flags & BNX_FLAG_TBI) {
1998 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
1999 bnx_ifmedia_upd, bnx_ifmedia_sts);
2000 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2001 ifmedia_add(&sc->bnx_ifmedia,
2002 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2003 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2004 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
2005 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
2007 struct mii_probe_args mii_args;
2009 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
2010 mii_args.mii_probemask = 1 << sc->bnx_phyno;
2011 mii_args.mii_capmask = capmask;
2012 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2013 mii_args.mii_priv = mii_priv;
2015 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
2017 device_printf(dev, "MII without any PHY!\n");
2023 * Create sysctl nodes.
2025 sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2026 sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2027 SYSCTL_STATIC_CHILDREN(_hw),
2029 device_get_nameunit(dev),
2031 if (sc->bnx_sysctl_tree == NULL) {
2032 device_printf(dev, "can't add sysctl node\n");
2037 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2038 SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2039 OID_AUTO, "rx_coal_ticks",
2040 CTLTYPE_INT | CTLFLAG_RW,
2041 sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2042 "Receive coalescing ticks (usec).");
2043 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2044 SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2045 OID_AUTO, "tx_coal_ticks",
2046 CTLTYPE_INT | CTLFLAG_RW,
2047 sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2048 "Transmit coalescing ticks (usec).");
2049 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2050 SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2051 OID_AUTO, "rx_coal_bds",
2052 CTLTYPE_INT | CTLFLAG_RW,
2053 sc, 0, bnx_sysctl_rx_coal_bds, "I",
2054 "Receive max coalesced BD count.");
2055 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2056 SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2057 OID_AUTO, "tx_coal_bds",
2058 CTLTYPE_INT | CTLFLAG_RW,
2059 sc, 0, bnx_sysctl_tx_coal_bds, "I",
2060 "Transmit max coalesced BD count.");
2062 * A common design characteristic for many Broadcom
2063 * client controllers is that they only support a
2064 * single outstanding DMA read operation on the PCIe
2065 * bus. This means that it will take twice as long to
2066 * fetch a TX frame that is split into header and
2067 * payload buffers as it does to fetch a single,
2068 * contiguous TX frame (2 reads vs. 1 read). For these
2069 * controllers, coalescing buffers to reduce the number
2070 * of memory reads is effective way to get maximum
2071 * performance(about 940Mbps). Without collapsing TX
2072 * buffers the maximum TCP bulk transfer performance
2073 * is about 850Mbps. However forcing coalescing mbufs
2074 * consumes a lot of CPU cycles, so leave it off by
2077 SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2078 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2079 "force_defrag", CTLFLAG_RW, &sc->bnx_force_defrag, 0,
2080 "Force defragment on TX path");
2082 SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2083 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2084 "tx_wreg", CTLFLAG_RW, &sc->bnx_tx_wreg, 0,
2085 "# of segments before writing to hardware register");
2087 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2088 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2089 "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2090 sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2091 "Receive max coalesced BD count during interrupt.");
2092 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2093 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2094 "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2095 sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2096 "Transmit max coalesced BD count during interrupt.");
2098 #ifdef BNX_TSO_DEBUG
2099 for (i = 0; i < BNX_TSO_NSTATS; ++i) {
2100 ksnprintf(desc, sizeof(desc), "tso%d", i + 1);
2101 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2102 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2103 desc, CTLFLAG_RW, &sc->bnx_tsosegs[i], "");
2108 * Call MI attach routine.
2110 ether_ifattach(ifp, ether_addr, NULL);
2112 ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2114 #ifdef IFPOLL_ENABLE
2115 ifpoll_compat_setup(&sc->bnx_npoll,
2116 &sc->bnx_sysctl_ctx, sc->bnx_sysctl_tree,
2117 device_get_unit(dev), ifp->if_serializer);
2120 if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
2121 if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
2122 intr_func = bnx_msi_oneshot;
2124 device_printf(dev, "oneshot MSI\n");
2126 intr_func = bnx_msi;
2129 intr_func = bnx_intr_legacy;
2131 error = bus_setup_intr(dev, sc->bnx_irq, INTR_MPSAFE, intr_func, sc,
2132 &sc->bnx_intrhand, ifp->if_serializer);
2134 ether_ifdetach(ifp);
2135 device_printf(dev, "couldn't set up irq\n");
2139 sc->bnx_intr_cpuid = rman_get_cpuid(sc->bnx_irq);
2140 sc->bnx_stat_cpuid = sc->bnx_intr_cpuid;
2149 bnx_detach(device_t dev)
2151 struct bnx_softc *sc = device_get_softc(dev);
2153 if (device_is_attached(dev)) {
2154 struct ifnet *ifp = &sc->arpcom.ac_if;
2156 lwkt_serialize_enter(ifp->if_serializer);
2159 bus_teardown_intr(dev, sc->bnx_irq, sc->bnx_intrhand);
2160 lwkt_serialize_exit(ifp->if_serializer);
2162 ether_ifdetach(ifp);
2165 if (sc->bnx_flags & BNX_FLAG_TBI)
2166 ifmedia_removeall(&sc->bnx_ifmedia);
2168 device_delete_child(dev, sc->bnx_miibus);
2169 bus_generic_detach(dev);
2171 if (sc->bnx_irq != NULL) {
2172 bus_release_resource(dev, SYS_RES_IRQ, sc->bnx_irq_rid,
2175 if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI)
2176 pci_release_msi(dev);
2178 if (sc->bnx_res != NULL) {
2179 bus_release_resource(dev, SYS_RES_MEMORY,
2180 BGE_PCI_BAR0, sc->bnx_res);
2183 if (sc->bnx_sysctl_tree != NULL)
2184 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2192 bnx_reset(struct bnx_softc *sc)
2195 uint32_t cachesize, command, pcistate, reset;
2196 void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2202 write_op = bnx_writemem_direct;
2204 /* Save some important PCI state. */
2205 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2206 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2207 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2209 pci_write_config(dev, BGE_PCI_MISC_CTL,
2210 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2211 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2212 BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2214 /* Disable fastboot on controllers that support it. */
2216 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2217 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2220 * Write the magic number to SRAM at offset 0xB50.
2221 * When firmware finishes its initialization it will
2222 * write ~BGE_MAGIC_NUMBER to the same location.
2224 bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2226 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2228 /* XXX: Broadcom Linux driver. */
2229 /* Force PCI-E 1.0a mode */
2230 if (!BNX_IS_57765_PLUS(sc) &&
2231 CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2232 (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2233 BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2234 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2235 BGE_PCIE_PHY_TSTCTL_PSCRAM);
2237 if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2238 /* Prevent PCIE link training during global reset */
2239 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2244 * Set GPHY Power Down Override to leave GPHY
2245 * powered up in D0 uninitialized.
2247 if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2248 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2250 /* Issue global reset */
2251 write_op(sc, BGE_MISC_CFG, reset);
2255 /* XXX: Broadcom Linux driver. */
2256 if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2259 DELAY(500000); /* wait for link training to complete */
2260 v = pci_read_config(dev, 0xc4, 4);
2261 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2264 devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2266 /* Disable no snoop and disable relaxed ordering. */
2267 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2269 /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2270 if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2271 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2272 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2275 pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2278 /* Clear error status. */
2279 pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2280 PCIEM_DEVSTS_CORR_ERR |
2281 PCIEM_DEVSTS_NFATAL_ERR |
2282 PCIEM_DEVSTS_FATAL_ERR |
2283 PCIEM_DEVSTS_UNSUPP_REQ, 2);
2285 /* Reset some of the PCI state that got zapped by reset */
2286 pci_write_config(dev, BGE_PCI_MISC_CTL,
2287 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2288 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2289 BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2290 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2291 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2292 write_op(sc, BGE_MISC_CFG, (65 << 1));
2294 /* Enable memory arbiter */
2295 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2298 * Poll until we see the 1's complement of the magic number.
2299 * This indicates that the firmware initialization is complete.
2301 for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2302 val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2303 if (val == ~BGE_MAGIC_NUMBER)
2307 if (i == BNX_FIRMWARE_TIMEOUT) {
2308 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2309 "timed out, found 0x%08x\n", val);
2312 /* BCM57765 A0 needs additional time before accessing. */
2313 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2317 * XXX Wait for the value of the PCISTATE register to
2318 * return to its original pre-reset state. This is a
2319 * fairly good indicator of reset completion. If we don't
2320 * wait for the reset to fully complete, trying to read
2321 * from the device's non-PCI registers may yield garbage
2324 for (i = 0; i < BNX_TIMEOUT; i++) {
2325 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2330 /* Fix up byte swapping */
2331 CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2333 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2336 * The 5704 in TBI mode apparently needs some special
2337 * adjustment to insure the SERDES drive level is set
2340 if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2341 (sc->bnx_flags & BNX_FLAG_TBI)) {
2344 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2345 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2346 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2349 CSR_WRITE_4(sc, BGE_MI_MODE,
2350 sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
2353 /* XXX: Broadcom Linux driver. */
2354 if (!BNX_IS_57765_PLUS(sc)) {
2357 /* Enable Data FIFO protection. */
2358 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2359 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2364 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2365 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2366 CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2371 * Frame reception handling. This is called if there's a frame
2372 * on the receive return list.
2374 * Note: we have to be able to handle two possibilities here:
2375 * 1) the frame is from the jumbo recieve ring
2376 * 2) the frame is from the standard receive ring
2380 bnx_rxeof(struct bnx_softc *sc, uint16_t rx_prod, int count)
2383 int stdcnt = 0, jumbocnt = 0;
2385 ifp = &sc->arpcom.ac_if;
2387 while (sc->bnx_rx_saved_considx != rx_prod && count != 0) {
2388 struct bge_rx_bd *cur_rx;
2390 struct mbuf *m = NULL;
2391 uint16_t vlan_tag = 0;
2397 &sc->bnx_ldata.bnx_rx_return_ring[sc->bnx_rx_saved_considx];
2399 rxidx = cur_rx->bge_idx;
2400 BNX_INC(sc->bnx_rx_saved_considx, sc->bnx_return_ring_cnt);
2402 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2404 vlan_tag = cur_rx->bge_vlan_tag;
2407 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2408 BNX_INC(sc->bnx_jumbo, BGE_JUMBO_RX_RING_CNT);
2411 if (rxidx != sc->bnx_jumbo) {
2412 IFNET_STAT_INC(ifp, ierrors, 1);
2413 if_printf(ifp, "sw jumbo index(%d) "
2414 "and hw jumbo index(%d) mismatch, drop!\n",
2415 sc->bnx_jumbo, rxidx);
2416 bnx_setup_rxdesc_jumbo(sc, rxidx);
2420 m = sc->bnx_cdata.bnx_rx_jumbo_chain[rxidx].bnx_mbuf;
2421 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2422 IFNET_STAT_INC(ifp, ierrors, 1);
2423 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2426 if (bnx_newbuf_jumbo(sc, sc->bnx_jumbo, 0)) {
2427 IFNET_STAT_INC(ifp, ierrors, 1);
2428 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2432 BNX_INC(sc->bnx_std, BGE_STD_RX_RING_CNT);
2435 if (rxidx != sc->bnx_std) {
2436 IFNET_STAT_INC(ifp, ierrors, 1);
2437 if_printf(ifp, "sw std index(%d) "
2438 "and hw std index(%d) mismatch, drop!\n",
2439 sc->bnx_std, rxidx);
2440 bnx_setup_rxdesc_std(sc, rxidx);
2444 m = sc->bnx_cdata.bnx_rx_std_chain[rxidx].bnx_mbuf;
2445 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2446 IFNET_STAT_INC(ifp, ierrors, 1);
2447 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2450 if (bnx_newbuf_std(sc, sc->bnx_std, 0)) {
2451 IFNET_STAT_INC(ifp, ierrors, 1);
2452 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2457 IFNET_STAT_INC(ifp, ipackets, 1);
2458 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2459 m->m_pkthdr.rcvif = ifp;
2461 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2462 (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2463 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2464 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2465 if ((cur_rx->bge_error_flag &
2466 BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2467 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2469 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2470 m->m_pkthdr.csum_data =
2471 cur_rx->bge_tcp_udp_csum;
2472 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2478 * If we received a packet with a vlan tag, pass it
2479 * to vlan_input() instead of ether_input().
2482 m->m_flags |= M_VLANTAG;
2483 m->m_pkthdr.ether_vlantag = vlan_tag;
2485 ifp->if_input(ifp, m);
2488 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bnx_rx_saved_considx);
2490 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
2492 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
2496 bnx_txeof(struct bnx_softc *sc, uint16_t tx_cons)
2500 ifp = &sc->arpcom.ac_if;
2503 * Go through our tx ring and free mbufs for those
2504 * frames that have been sent.
2506 while (sc->bnx_tx_saved_considx != tx_cons) {
2509 idx = sc->bnx_tx_saved_considx;
2510 if (sc->bnx_cdata.bnx_tx_chain[idx] != NULL) {
2511 IFNET_STAT_INC(ifp, opackets, 1);
2512 bus_dmamap_unload(sc->bnx_cdata.bnx_tx_mtag,
2513 sc->bnx_cdata.bnx_tx_dmamap[idx]);
2514 m_freem(sc->bnx_cdata.bnx_tx_chain[idx]);
2515 sc->bnx_cdata.bnx_tx_chain[idx] = NULL;
2518 BNX_INC(sc->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2521 if ((BGE_TX_RING_CNT - sc->bnx_txcnt) >=
2522 (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2523 ifq_clr_oactive(&ifp->if_snd);
2525 if (sc->bnx_txcnt == 0)
2528 if (!ifq_is_empty(&ifp->if_snd))
2532 #ifdef IFPOLL_ENABLE
2535 bnx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2537 struct bnx_softc *sc = ifp->if_softc;
2539 ASSERT_SERIALIZED(ifp->if_serializer);
2542 int cpuid = sc->bnx_npoll.ifpc_cpuid;
2544 info->ifpi_rx[cpuid].poll_func = bnx_npoll_compat;
2545 info->ifpi_rx[cpuid].arg = NULL;
2546 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
2548 if (ifp->if_flags & IFF_RUNNING)
2549 bnx_disable_intr(sc);
2550 ifq_set_cpuid(&ifp->if_snd, cpuid);
2552 if (ifp->if_flags & IFF_RUNNING)
2553 bnx_enable_intr(sc);
2554 ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2559 bnx_npoll_compat(struct ifnet *ifp, void *arg __unused, int cycle)
2561 struct bnx_softc *sc = ifp->if_softc;
2562 struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2563 uint16_t rx_prod, tx_cons;
2565 ASSERT_SERIALIZED(ifp->if_serializer);
2567 if (sc->bnx_npoll.ifpc_stcount-- == 0) {
2568 sc->bnx_npoll.ifpc_stcount = sc->bnx_npoll.ifpc_stfrac;
2570 * Process link state changes.
2575 sc->bnx_status_tag = sblk->bge_status_tag;
2578 * Use a load fence to ensure that status_tag is saved
2579 * before rx_prod and tx_cons.
2583 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2584 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2586 if (sc->bnx_rx_saved_considx != rx_prod)
2587 bnx_rxeof(sc, rx_prod, cycle);
2589 if (sc->bnx_tx_saved_considx != tx_cons)
2590 bnx_txeof(sc, tx_cons);
2592 if (sc->bnx_coal_chg)
2593 bnx_coal_change(sc);
2596 #endif /* IFPOLL_ENABLE */
2599 bnx_intr_legacy(void *xsc)
2601 struct bnx_softc *sc = xsc;
2602 struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2604 if (sc->bnx_status_tag == sblk->bge_status_tag) {
2607 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
2608 if (val & BGE_PCISTAT_INTR_NOTACT)
2614 * Interrupt will have to be disabled if tagged status
2615 * is used, else interrupt will always be asserted on
2616 * certain chips (at least on BCM5750 AX/BX).
2618 bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2626 struct bnx_softc *sc = xsc;
2628 /* Disable interrupt first */
2629 bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2634 bnx_msi_oneshot(void *xsc)
2640 bnx_intr(struct bnx_softc *sc)
2642 struct ifnet *ifp = &sc->arpcom.ac_if;
2643 struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2644 uint16_t rx_prod, tx_cons;
2647 sc->bnx_status_tag = sblk->bge_status_tag;
2649 * Use a load fence to ensure that status_tag is saved
2650 * before rx_prod, tx_cons and status.
2654 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2655 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2656 status = sblk->bge_status;
2658 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2661 if (ifp->if_flags & IFF_RUNNING) {
2662 if (sc->bnx_rx_saved_considx != rx_prod)
2663 bnx_rxeof(sc, rx_prod, -1);
2665 if (sc->bnx_tx_saved_considx != tx_cons)
2666 bnx_txeof(sc, tx_cons);
2669 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
2671 if (sc->bnx_coal_chg)
2672 bnx_coal_change(sc);
2678 struct bnx_softc *sc = xsc;
2679 struct ifnet *ifp = &sc->arpcom.ac_if;
2681 lwkt_serialize_enter(ifp->if_serializer);
2683 KKASSERT(mycpuid == sc->bnx_stat_cpuid);
2685 bnx_stats_update_regs(sc);
2687 if (sc->bnx_flags & BNX_FLAG_TBI) {
2689 * Since in TBI mode auto-polling can't be used we should poll
2690 * link status manually. Here we register pending link event
2691 * and trigger interrupt.
2694 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2695 } else if (!sc->bnx_link) {
2696 mii_tick(device_get_softc(sc->bnx_miibus));
2699 callout_reset(&sc->bnx_stat_timer, hz, bnx_tick, sc);
2701 lwkt_serialize_exit(ifp->if_serializer);
2705 bnx_stats_update_regs(struct bnx_softc *sc)
2707 struct ifnet *ifp = &sc->arpcom.ac_if;
2708 struct bge_mac_stats_regs stats;
2712 s = (uint32_t *)&stats;
2713 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2714 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2718 IFNET_STAT_SET(ifp, collisions,
2719 (stats.dot3StatsSingleCollisionFrames +
2720 stats.dot3StatsMultipleCollisionFrames +
2721 stats.dot3StatsExcessiveCollisions +
2722 stats.dot3StatsLateCollisions));
2726 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2727 * pointers to descriptors.
2730 bnx_encap(struct bnx_softc *sc, struct mbuf **m_head0, uint32_t *txidx,
2733 struct bge_tx_bd *d = NULL;
2734 uint16_t csum_flags = 0, vlan_tag = 0, mss = 0;
2735 bus_dma_segment_t segs[BNX_NSEG_NEW];
2737 int error, maxsegs, nsegs, idx, i;
2738 struct mbuf *m_head = *m_head0, *m_new;
2740 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
2741 #ifdef BNX_TSO_DEBUG
2745 error = bnx_setup_tso(sc, m_head0, &mss, &csum_flags);
2750 #ifdef BNX_TSO_DEBUG
2751 tso_nsegs = (m_head->m_pkthdr.len /
2752 m_head->m_pkthdr.tso_segsz) - 1;
2753 if (tso_nsegs > (BNX_TSO_NSTATS - 1))
2754 tso_nsegs = BNX_TSO_NSTATS - 1;
2755 else if (tso_nsegs < 0)
2757 sc->bnx_tsosegs[tso_nsegs]++;
2759 } else if (m_head->m_pkthdr.csum_flags & BNX_CSUM_FEATURES) {
2760 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2761 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2762 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2763 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2764 if (m_head->m_flags & M_LASTFRAG)
2765 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2766 else if (m_head->m_flags & M_FRAG)
2767 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2769 if (m_head->m_flags & M_VLANTAG) {
2770 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
2771 vlan_tag = m_head->m_pkthdr.ether_vlantag;
2775 map = sc->bnx_cdata.bnx_tx_dmamap[idx];
2777 maxsegs = (BGE_TX_RING_CNT - sc->bnx_txcnt) - BNX_NSEG_RSVD;
2778 KASSERT(maxsegs >= BNX_NSEG_SPARE,
2779 ("not enough segments %d", maxsegs));
2781 if (maxsegs > BNX_NSEG_NEW)
2782 maxsegs = BNX_NSEG_NEW;
2785 * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
2786 * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
2787 * but when such padded frames employ the bge IP/TCP checksum
2788 * offload, the hardware checksum assist gives incorrect results
2789 * (possibly from incorporating its own padding into the UDP/TCP
2790 * checksum; who knows). If we pad such runts with zeros, the
2791 * onboard checksum comes out correct.
2793 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2794 m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
2795 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
2800 if ((sc->bnx_flags & BNX_FLAG_SHORTDMA) && m_head->m_next != NULL) {
2801 m_new = bnx_defrag_shortdma(m_head);
2802 if (m_new == NULL) {
2806 *m_head0 = m_head = m_new;
2808 if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
2809 sc->bnx_force_defrag && m_head->m_next != NULL) {
2811 * Forcefully defragment mbuf chain to overcome hardware
2812 * limitation which only support a single outstanding
2813 * DMA read operation. If it fails, keep moving on using
2814 * the original mbuf chain.
2816 m_new = m_defrag(m_head, MB_DONTWAIT);
2818 *m_head0 = m_head = m_new;
2821 error = bus_dmamap_load_mbuf_defrag(sc->bnx_cdata.bnx_tx_mtag, map,
2822 m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2825 *segs_used += nsegs;
2828 bus_dmamap_sync(sc->bnx_cdata.bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2830 for (i = 0; ; i++) {
2831 d = &sc->bnx_ldata.bnx_tx_ring[idx];
2833 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2834 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2835 d->bge_len = segs[i].ds_len;
2836 d->bge_flags = csum_flags;
2837 d->bge_vlan_tag = vlan_tag;
2842 BNX_INC(idx, BGE_TX_RING_CNT);
2844 /* Mark the last segment as end of packet... */
2845 d->bge_flags |= BGE_TXBDFLAG_END;
2848 * Insure that the map for this transmission is placed at
2849 * the array index of the last descriptor in this chain.
2851 sc->bnx_cdata.bnx_tx_dmamap[*txidx] = sc->bnx_cdata.bnx_tx_dmamap[idx];
2852 sc->bnx_cdata.bnx_tx_dmamap[idx] = map;
2853 sc->bnx_cdata.bnx_tx_chain[idx] = m_head;
2854 sc->bnx_txcnt += nsegs;
2856 BNX_INC(idx, BGE_TX_RING_CNT);
2867 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2868 * to the mbuf data regions directly in the transmit descriptors.
2871 bnx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
2873 struct bnx_softc *sc = ifp->if_softc;
2874 struct mbuf *m_head = NULL;
2878 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
2880 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
2883 prodidx = sc->bnx_tx_prodidx;
2885 while (sc->bnx_cdata.bnx_tx_chain[prodidx] == NULL) {
2887 * Sanity check: avoid coming within BGE_NSEG_RSVD
2888 * descriptors of the end of the ring. Also make
2889 * sure there are BGE_NSEG_SPARE descriptors for
2890 * jumbo buffers' or TSO segments' defragmentation.
2892 if ((BGE_TX_RING_CNT - sc->bnx_txcnt) <
2893 (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
2894 ifq_set_oactive(&ifp->if_snd);
2898 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2903 * Pack the data into the transmit ring. If we
2904 * don't have room, set the OACTIVE flag and wait
2905 * for the NIC to drain the ring.
2907 if (bnx_encap(sc, &m_head, &prodidx, &nsegs)) {
2908 ifq_set_oactive(&ifp->if_snd);
2909 IFNET_STAT_INC(ifp, oerrors, 1);
2913 if (nsegs >= sc->bnx_tx_wreg) {
2915 bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2919 ETHER_BPF_MTAP(ifp, m_head);
2922 * Set a timeout in case the chip goes out to lunch.
2929 bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2931 sc->bnx_tx_prodidx = prodidx;
2937 struct bnx_softc *sc = xsc;
2938 struct ifnet *ifp = &sc->arpcom.ac_if;
2942 ASSERT_SERIALIZED(ifp->if_serializer);
2944 /* Cancel pending I/O and flush buffers. */
2950 * Init the various state machines, ring
2951 * control blocks and firmware.
2953 if (bnx_blockinit(sc)) {
2954 if_printf(ifp, "initialization failure\n");
2960 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2961 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2963 /* Load our MAC address. */
2964 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2965 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2966 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2968 /* Enable or disable promiscuous mode as needed. */
2971 /* Program multicast filter. */
2975 if (bnx_init_rx_ring_std(sc)) {
2976 if_printf(ifp, "RX ring initialization failed\n");
2981 /* Init jumbo RX ring. */
2982 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
2983 if (bnx_init_rx_ring_jumbo(sc)) {
2984 if_printf(ifp, "Jumbo RX ring initialization failed\n");
2990 /* Init our RX return ring index */
2991 sc->bnx_rx_saved_considx = 0;
2994 bnx_init_tx_ring(sc);
2996 /* Enable TX MAC state machine lockup fix. */
2997 mode = CSR_READ_4(sc, BGE_TX_MODE);
2998 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
2999 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
3000 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
3001 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3002 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
3003 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3005 /* Turn on transmitter */
3006 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3008 /* Turn on receiver */
3009 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3012 * Set the number of good frames to receive after RX MBUF
3013 * Low Watermark has been reached. After the RX MAC receives
3014 * this number of frames, it will drop subsequent incoming
3015 * frames until the MBUF High Watermark is reached.
3017 if (BNX_IS_57765_FAMILY(sc))
3018 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
3020 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3022 if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
3024 if_printf(ifp, "MSI_MODE: %#x\n",
3025 CSR_READ_4(sc, BGE_MSI_MODE));
3029 /* Tell firmware we're alive. */
3030 BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3032 /* Enable host interrupts if polling(4) is not enabled. */
3033 PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3034 #ifdef IFPOLL_ENABLE
3035 if (ifp->if_flags & IFF_NPOLLING)
3036 bnx_disable_intr(sc);
3039 bnx_enable_intr(sc);
3041 bnx_ifmedia_upd(ifp);
3043 ifp->if_flags |= IFF_RUNNING;
3044 ifq_clr_oactive(&ifp->if_snd);
3046 callout_reset_bycpu(&sc->bnx_stat_timer, hz, bnx_tick, sc,
3047 sc->bnx_stat_cpuid);
3051 * Set media options.
3054 bnx_ifmedia_upd(struct ifnet *ifp)
3056 struct bnx_softc *sc = ifp->if_softc;
3058 /* If this is a 1000baseX NIC, enable the TBI port. */
3059 if (sc->bnx_flags & BNX_FLAG_TBI) {
3060 struct ifmedia *ifm = &sc->bnx_ifmedia;
3062 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3065 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3070 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3071 BNX_CLRBIT(sc, BGE_MAC_MODE,
3072 BGE_MACMODE_HALF_DUPLEX);
3074 BNX_SETBIT(sc, BGE_MAC_MODE,
3075 BGE_MACMODE_HALF_DUPLEX);
3082 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3086 if (mii->mii_instance) {
3087 struct mii_softc *miisc;
3089 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3090 mii_phy_reset(miisc);
3095 * Force an interrupt so that we will call bnx_link_upd
3096 * if needed and clear any pending link state attention.
3097 * Without this we are not getting any further interrupts
3098 * for link state changes and thus will not UP the link and
3099 * not be able to send in bnx_start. The only way to get
3100 * things working was to receive a packet and get an RX
3103 * bnx_tick should help for fiber cards and we might not
3104 * need to do this here if BNX_FLAG_TBI is set but as
3105 * we poll for fiber anyway it should not harm.
3107 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3113 * Report current media status.
3116 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3118 struct bnx_softc *sc = ifp->if_softc;
3120 if (sc->bnx_flags & BNX_FLAG_TBI) {
3121 ifmr->ifm_status = IFM_AVALID;
3122 ifmr->ifm_active = IFM_ETHER;
3123 if (CSR_READ_4(sc, BGE_MAC_STS) &
3124 BGE_MACSTAT_TBI_PCS_SYNCHED) {
3125 ifmr->ifm_status |= IFM_ACTIVE;
3127 ifmr->ifm_active |= IFM_NONE;
3131 ifmr->ifm_active |= IFM_1000_SX;
3132 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3133 ifmr->ifm_active |= IFM_HDX;
3135 ifmr->ifm_active |= IFM_FDX;
3137 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3140 ifmr->ifm_active = mii->mii_media_active;
3141 ifmr->ifm_status = mii->mii_media_status;
3146 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3148 struct bnx_softc *sc = ifp->if_softc;
3149 struct ifreq *ifr = (struct ifreq *)data;
3150 int mask, error = 0;
3152 ASSERT_SERIALIZED(ifp->if_serializer);
3156 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3157 (BNX_IS_JUMBO_CAPABLE(sc) &&
3158 ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3160 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3161 ifp->if_mtu = ifr->ifr_mtu;
3162 if (ifp->if_flags & IFF_RUNNING)
3167 if (ifp->if_flags & IFF_UP) {
3168 if (ifp->if_flags & IFF_RUNNING) {
3169 mask = ifp->if_flags ^ sc->bnx_if_flags;
3172 * If only the state of the PROMISC flag
3173 * changed, then just use the 'set promisc
3174 * mode' command instead of reinitializing
3175 * the entire NIC. Doing a full re-init
3176 * means reloading the firmware and waiting
3177 * for it to start up, which may take a
3178 * second or two. Similarly for ALLMULTI.
3180 if (mask & IFF_PROMISC)
3182 if (mask & IFF_ALLMULTI)
3187 } else if (ifp->if_flags & IFF_RUNNING) {
3190 sc->bnx_if_flags = ifp->if_flags;
3194 if (ifp->if_flags & IFF_RUNNING)
3199 if (sc->bnx_flags & BNX_FLAG_TBI) {
3200 error = ifmedia_ioctl(ifp, ifr,
3201 &sc->bnx_ifmedia, command);
3203 struct mii_data *mii;
3205 mii = device_get_softc(sc->bnx_miibus);
3206 error = ifmedia_ioctl(ifp, ifr,
3207 &mii->mii_media, command);
3211 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3212 if (mask & IFCAP_HWCSUM) {
3213 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3214 if (ifp->if_capenable & IFCAP_TXCSUM)
3215 ifp->if_hwassist |= BNX_CSUM_FEATURES;
3217 ifp->if_hwassist &= ~BNX_CSUM_FEATURES;
3219 if (mask & IFCAP_TSO) {
3220 ifp->if_capenable ^= (mask & IFCAP_TSO);
3221 if (ifp->if_capenable & IFCAP_TSO)
3222 ifp->if_hwassist |= CSUM_TSO;
3224 ifp->if_hwassist &= ~CSUM_TSO;
3228 error = ether_ioctl(ifp, command, data);
3235 bnx_watchdog(struct ifnet *ifp)
3237 struct bnx_softc *sc = ifp->if_softc;
3239 if_printf(ifp, "watchdog timeout -- resetting\n");
3243 IFNET_STAT_INC(ifp, oerrors, 1);
3245 if (!ifq_is_empty(&ifp->if_snd))
3250 * Stop the adapter and free any mbufs allocated to the
3254 bnx_stop(struct bnx_softc *sc)
3256 struct ifnet *ifp = &sc->arpcom.ac_if;
3258 ASSERT_SERIALIZED(ifp->if_serializer);
3260 callout_stop(&sc->bnx_stat_timer);
3263 * Disable all of the receiver blocks
3265 bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3266 bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3267 bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3268 bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3269 bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3270 bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3273 * Disable all of the transmit blocks
3275 bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3276 bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3277 bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3278 bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3279 bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3280 bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3283 * Shut down all of the memory managers and related
3286 bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3287 bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3288 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3289 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3291 /* Disable host interrupts. */
3292 bnx_disable_intr(sc);
3295 * Tell firmware we're shutting down.
3297 BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3299 /* Free the RX lists. */
3300 bnx_free_rx_ring_std(sc);
3302 /* Free jumbo RX list. */
3303 if (BNX_IS_JUMBO_CAPABLE(sc))
3304 bnx_free_rx_ring_jumbo(sc);
3306 /* Free TX buffers. */
3307 bnx_free_tx_ring(sc);
3309 sc->bnx_status_tag = 0;
3311 sc->bnx_coal_chg = 0;
3313 sc->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
3315 ifp->if_flags &= ~IFF_RUNNING;
3316 ifq_clr_oactive(&ifp->if_snd);
3321 * Stop all chip I/O so that the kernel's probe routines don't
3322 * get confused by errant DMAs when rebooting.
3325 bnx_shutdown(device_t dev)
3327 struct bnx_softc *sc = device_get_softc(dev);
3328 struct ifnet *ifp = &sc->arpcom.ac_if;
3330 lwkt_serialize_enter(ifp->if_serializer);
3333 lwkt_serialize_exit(ifp->if_serializer);
3337 bnx_suspend(device_t dev)
3339 struct bnx_softc *sc = device_get_softc(dev);
3340 struct ifnet *ifp = &sc->arpcom.ac_if;
3342 lwkt_serialize_enter(ifp->if_serializer);
3344 lwkt_serialize_exit(ifp->if_serializer);
3350 bnx_resume(device_t dev)
3352 struct bnx_softc *sc = device_get_softc(dev);
3353 struct ifnet *ifp = &sc->arpcom.ac_if;
3355 lwkt_serialize_enter(ifp->if_serializer);
3357 if (ifp->if_flags & IFF_UP) {
3360 if (!ifq_is_empty(&ifp->if_snd))
3364 lwkt_serialize_exit(ifp->if_serializer);
3370 bnx_setpromisc(struct bnx_softc *sc)
3372 struct ifnet *ifp = &sc->arpcom.ac_if;
3374 if (ifp->if_flags & IFF_PROMISC)
3375 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3377 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3381 bnx_dma_free(struct bnx_softc *sc)
3385 /* Destroy RX mbuf DMA stuffs. */
3386 if (sc->bnx_cdata.bnx_rx_mtag != NULL) {
3387 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3388 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3389 sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3391 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3392 sc->bnx_cdata.bnx_rx_tmpmap);
3393 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3396 /* Destroy TX mbuf DMA stuffs. */
3397 if (sc->bnx_cdata.bnx_tx_mtag != NULL) {
3398 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3399 bus_dmamap_destroy(sc->bnx_cdata.bnx_tx_mtag,
3400 sc->bnx_cdata.bnx_tx_dmamap[i]);
3402 bus_dma_tag_destroy(sc->bnx_cdata.bnx_tx_mtag);
3405 /* Destroy standard RX ring */
3406 bnx_dma_block_free(sc->bnx_cdata.bnx_rx_std_ring_tag,
3407 sc->bnx_cdata.bnx_rx_std_ring_map,
3408 sc->bnx_ldata.bnx_rx_std_ring);
3410 if (BNX_IS_JUMBO_CAPABLE(sc))
3411 bnx_free_jumbo_mem(sc);
3413 /* Destroy RX return ring */
3414 bnx_dma_block_free(sc->bnx_cdata.bnx_rx_return_ring_tag,
3415 sc->bnx_cdata.bnx_rx_return_ring_map,
3416 sc->bnx_ldata.bnx_rx_return_ring);
3418 /* Destroy TX ring */
3419 bnx_dma_block_free(sc->bnx_cdata.bnx_tx_ring_tag,
3420 sc->bnx_cdata.bnx_tx_ring_map,
3421 sc->bnx_ldata.bnx_tx_ring);
3423 /* Destroy status block */
3424 bnx_dma_block_free(sc->bnx_cdata.bnx_status_tag,
3425 sc->bnx_cdata.bnx_status_map,
3426 sc->bnx_ldata.bnx_status_block);
3428 /* Destroy the parent tag */
3429 if (sc->bnx_cdata.bnx_parent_tag != NULL)
3430 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
3434 bnx_dma_alloc(struct bnx_softc *sc)
3436 struct ifnet *ifp = &sc->arpcom.ac_if;
3437 bus_size_t txmaxsz, txmaxsegsz;
3441 * Allocate the parent bus DMA tag appropriate for PCI.
3443 * All of the NetExtreme/NetLink controllers have 4GB boundary
3445 * Whenever an address crosses a multiple of the 4GB boundary
3446 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3447 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3448 * state machine will lockup and cause the device to hang.
3450 error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3451 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3453 BUS_SPACE_MAXSIZE_32BIT, 0,
3454 BUS_SPACE_MAXSIZE_32BIT,
3455 0, &sc->bnx_cdata.bnx_parent_tag);
3457 if_printf(ifp, "could not allocate parent dma tag\n");
3462 * Create DMA tag and maps for RX mbufs.
3464 error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3465 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3466 NULL, NULL, MCLBYTES, 1, MCLBYTES,
3467 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3468 &sc->bnx_cdata.bnx_rx_mtag);
3470 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3474 error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3475 BUS_DMA_WAITOK, &sc->bnx_cdata.bnx_rx_tmpmap);
3477 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3478 sc->bnx_cdata.bnx_rx_mtag = NULL;
3482 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3483 error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3485 &sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3489 for (j = 0; j < i; ++j) {
3490 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3491 sc->bnx_cdata.bnx_rx_std_dmamap[j]);
3493 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3494 sc->bnx_cdata.bnx_rx_mtag = NULL;
3496 if_printf(ifp, "could not create DMA map for RX\n");
3502 * Create DMA tag and maps for TX mbufs.
3504 if (sc->bnx_flags & BNX_FLAG_TSO)
3505 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header);
3507 txmaxsz = BNX_JUMBO_FRAMELEN;
3508 if (sc->bnx_asicrev == BGE_ASICREV_BCM57766)
3509 txmaxsegsz = MCLBYTES;
3511 txmaxsegsz = PAGE_SIZE;
3512 error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3513 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3515 txmaxsz, BNX_NSEG_NEW, txmaxsegsz,
3516 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3518 &sc->bnx_cdata.bnx_tx_mtag);
3520 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3524 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3525 error = bus_dmamap_create(sc->bnx_cdata.bnx_tx_mtag,
3526 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3527 &sc->bnx_cdata.bnx_tx_dmamap[i]);
3531 for (j = 0; j < i; ++j) {
3532 bus_dmamap_destroy(sc->bnx_cdata.bnx_tx_mtag,
3533 sc->bnx_cdata.bnx_tx_dmamap[j]);
3535 bus_dma_tag_destroy(sc->bnx_cdata.bnx_tx_mtag);
3536 sc->bnx_cdata.bnx_tx_mtag = NULL;
3538 if_printf(ifp, "could not create DMA map for TX\n");
3544 * Create DMA stuffs for standard RX ring.
3546 error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3547 &sc->bnx_cdata.bnx_rx_std_ring_tag,
3548 &sc->bnx_cdata.bnx_rx_std_ring_map,
3549 (void *)&sc->bnx_ldata.bnx_rx_std_ring,
3550 &sc->bnx_ldata.bnx_rx_std_ring_paddr);
3552 if_printf(ifp, "could not create std RX ring\n");
3557 * Create jumbo buffer pool.
3559 if (BNX_IS_JUMBO_CAPABLE(sc)) {
3560 error = bnx_alloc_jumbo_mem(sc);
3562 if_printf(ifp, "could not create jumbo buffer pool\n");
3568 * Create DMA stuffs for RX return ring.
3570 error = bnx_dma_block_alloc(sc,
3571 BGE_RX_RTN_RING_SZ(sc->bnx_return_ring_cnt),
3572 &sc->bnx_cdata.bnx_rx_return_ring_tag,
3573 &sc->bnx_cdata.bnx_rx_return_ring_map,
3574 (void *)&sc->bnx_ldata.bnx_rx_return_ring,
3575 &sc->bnx_ldata.bnx_rx_return_ring_paddr);
3577 if_printf(ifp, "could not create RX ret ring\n");
3582 * Create DMA stuffs for TX ring.
3584 error = bnx_dma_block_alloc(sc, BGE_TX_RING_SZ,
3585 &sc->bnx_cdata.bnx_tx_ring_tag,
3586 &sc->bnx_cdata.bnx_tx_ring_map,
3587 (void *)&sc->bnx_ldata.bnx_tx_ring,
3588 &sc->bnx_ldata.bnx_tx_ring_paddr);
3590 if_printf(ifp, "could not create TX ring\n");
3595 * Create DMA stuffs for status block.
3597 error = bnx_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3598 &sc->bnx_cdata.bnx_status_tag,
3599 &sc->bnx_cdata.bnx_status_map,
3600 (void *)&sc->bnx_ldata.bnx_status_block,
3601 &sc->bnx_ldata.bnx_status_block_paddr);
3603 if_printf(ifp, "could not create status block\n");
3611 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3612 bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3617 error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0,
3618 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3619 size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3623 *tag = dmem.dmem_tag;
3624 *map = dmem.dmem_map;
3625 *addr = dmem.dmem_addr;
3626 *paddr = dmem.dmem_busaddr;
3632 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3635 bus_dmamap_unload(tag, map);
3636 bus_dmamem_free(tag, addr, map);
3637 bus_dma_tag_destroy(tag);
3642 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status)
3644 struct ifnet *ifp = &sc->arpcom.ac_if;
3646 #define PCS_ENCODE_ERR (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3649 * Sometimes PCS encoding errors are detected in
3650 * TBI mode (on fiber NICs), and for some reason
3651 * the chip will signal them as link changes.
3652 * If we get a link change event, but the 'PCS
3653 * encoding error' bit in the MAC status register
3654 * is set, don't bother doing a link check.
3655 * This avoids spurious "gigabit link up" messages
3656 * that sometimes appear on fiber NICs during
3657 * periods of heavy traffic.
3659 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3660 if (!sc->bnx_link) {
3662 if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) {
3663 BNX_CLRBIT(sc, BGE_MAC_MODE,
3664 BGE_MACMODE_TBI_SEND_CFGS);
3666 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3669 if_printf(ifp, "link UP\n");
3671 ifp->if_link_state = LINK_STATE_UP;
3672 if_link_state_change(ifp);
3674 } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3679 if_printf(ifp, "link DOWN\n");
3681 ifp->if_link_state = LINK_STATE_DOWN;
3682 if_link_state_change(ifp);
3686 #undef PCS_ENCODE_ERR
3688 /* Clear the attention. */
3689 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3690 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3691 BGE_MACSTAT_LINK_CHANGED);
3695 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3697 struct ifnet *ifp = &sc->arpcom.ac_if;
3698 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3701 bnx_miibus_statchg(sc->bnx_dev);
3705 if_printf(ifp, "link UP\n");
3707 if_printf(ifp, "link DOWN\n");
3710 /* Clear the attention. */
3711 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3712 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3713 BGE_MACSTAT_LINK_CHANGED);
3717 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3719 struct ifnet *ifp = &sc->arpcom.ac_if;
3720 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3724 if (!sc->bnx_link &&
3725 (mii->mii_media_status & IFM_ACTIVE) &&
3726 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3729 if_printf(ifp, "link UP\n");
3730 } else if (sc->bnx_link &&
3731 (!(mii->mii_media_status & IFM_ACTIVE) ||
3732 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3735 if_printf(ifp, "link DOWN\n");
3738 /* Clear the attention. */
3739 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3740 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3741 BGE_MACSTAT_LINK_CHANGED);
3745 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3747 struct bnx_softc *sc = arg1;
3749 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3750 &sc->bnx_rx_coal_ticks,
3751 BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX,
3752 BNX_RX_COAL_TICKS_CHG);
3756 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3758 struct bnx_softc *sc = arg1;
3760 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3761 &sc->bnx_tx_coal_ticks,
3762 BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX,
3763 BNX_TX_COAL_TICKS_CHG);
3767 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
3769 struct bnx_softc *sc = arg1;
3771 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3772 &sc->bnx_rx_coal_bds,
3773 BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3774 BNX_RX_COAL_BDS_CHG);
3778 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
3780 struct bnx_softc *sc = arg1;
3782 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3783 &sc->bnx_tx_coal_bds,
3784 BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3785 BNX_TX_COAL_BDS_CHG);
3789 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3791 struct bnx_softc *sc = arg1;
3793 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3794 &sc->bnx_rx_coal_bds_int,
3795 BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3796 BNX_RX_COAL_BDS_INT_CHG);
3800 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3802 struct bnx_softc *sc = arg1;
3804 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3805 &sc->bnx_tx_coal_bds_int,
3806 BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3807 BNX_TX_COAL_BDS_INT_CHG);
3811 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3812 int coal_min, int coal_max, uint32_t coal_chg_mask)
3814 struct bnx_softc *sc = arg1;
3815 struct ifnet *ifp = &sc->arpcom.ac_if;
3818 lwkt_serialize_enter(ifp->if_serializer);
3821 error = sysctl_handle_int(oidp, &v, 0, req);
3822 if (!error && req->newptr != NULL) {
3823 if (v < coal_min || v > coal_max) {
3827 sc->bnx_coal_chg |= coal_chg_mask;
3831 lwkt_serialize_exit(ifp->if_serializer);
3836 bnx_coal_change(struct bnx_softc *sc)
3838 struct ifnet *ifp = &sc->arpcom.ac_if;
3840 ASSERT_SERIALIZED(ifp->if_serializer);
3842 if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) {
3843 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3844 sc->bnx_rx_coal_ticks);
3846 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3849 if_printf(ifp, "rx_coal_ticks -> %u\n",
3850 sc->bnx_rx_coal_ticks);
3854 if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) {
3855 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3856 sc->bnx_tx_coal_ticks);
3858 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3861 if_printf(ifp, "tx_coal_ticks -> %u\n",
3862 sc->bnx_tx_coal_ticks);
3866 if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) {
3867 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3868 sc->bnx_rx_coal_bds);
3870 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3873 if_printf(ifp, "rx_coal_bds -> %u\n",
3874 sc->bnx_rx_coal_bds);
3878 if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) {
3879 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3880 sc->bnx_tx_coal_bds);
3882 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3885 if_printf(ifp, "tx_coal_bds -> %u\n",
3886 sc->bnx_tx_coal_bds);
3890 if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) {
3891 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
3892 sc->bnx_rx_coal_bds_int);
3894 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
3897 if_printf(ifp, "rx_coal_bds_int -> %u\n",
3898 sc->bnx_rx_coal_bds_int);
3902 if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) {
3903 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
3904 sc->bnx_tx_coal_bds_int);
3906 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
3909 if_printf(ifp, "tx_coal_bds_int -> %u\n",
3910 sc->bnx_tx_coal_bds_int);
3914 sc->bnx_coal_chg = 0;
3918 bnx_intr_check(void *xsc)
3920 struct bnx_softc *sc = xsc;
3921 struct ifnet *ifp = &sc->arpcom.ac_if;
3922 struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
3924 lwkt_serialize_enter(ifp->if_serializer);
3926 KKASSERT(mycpuid == sc->bnx_intr_cpuid);
3928 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
3929 lwkt_serialize_exit(ifp->if_serializer);
3933 if (sblk->bge_idx[0].bge_rx_prod_idx != sc->bnx_rx_saved_considx ||
3934 sblk->bge_idx[0].bge_tx_cons_idx != sc->bnx_tx_saved_considx) {
3935 if (sc->bnx_rx_check_considx == sc->bnx_rx_saved_considx &&
3936 sc->bnx_tx_check_considx == sc->bnx_tx_saved_considx) {
3937 if (!sc->bnx_intr_maylose) {
3938 sc->bnx_intr_maylose = TRUE;
3942 if_printf(ifp, "lost interrupt\n");
3946 sc->bnx_intr_maylose = FALSE;
3947 sc->bnx_rx_check_considx = sc->bnx_rx_saved_considx;
3948 sc->bnx_tx_check_considx = sc->bnx_tx_saved_considx;
3951 callout_reset(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
3952 bnx_intr_check, sc);
3953 lwkt_serialize_exit(ifp->if_serializer);
3957 bnx_enable_intr(struct bnx_softc *sc)
3959 struct ifnet *ifp = &sc->arpcom.ac_if;
3961 lwkt_serialize_handler_enable(ifp->if_serializer);
3966 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3967 if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
3968 /* XXX Linux driver */
3969 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3973 * Unmask the interrupt when we stop polling.
3975 PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3976 BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3979 * Trigger another interrupt, since above writing
3980 * to interrupt mailbox0 may acknowledge pending
3983 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3985 if (sc->bnx_flags & BNX_FLAG_STATUSTAG_BUG) {
3986 sc->bnx_intr_maylose = FALSE;
3987 sc->bnx_rx_check_considx = 0;
3988 sc->bnx_tx_check_considx = 0;
3991 if_printf(ifp, "status tag bug workaround\n");
3993 /* 10ms check interval */
3994 callout_reset_bycpu(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
3995 bnx_intr_check, sc, sc->bnx_intr_cpuid);
4000 bnx_disable_intr(struct bnx_softc *sc)
4002 struct ifnet *ifp = &sc->arpcom.ac_if;
4005 * Mask the interrupt when we start polling.
4007 PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
4008 BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4011 * Acknowledge possible asserted interrupt.
4013 bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4015 callout_stop(&sc->bnx_intr_timer);
4016 sc->bnx_intr_maylose = FALSE;
4017 sc->bnx_rx_check_considx = 0;
4018 sc->bnx_tx_check_considx = 0;
4020 sc->bnx_npoll.ifpc_stcount = 0;
4022 lwkt_serialize_handler_disable(ifp->if_serializer);
4026 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[])
4031 mac_addr = bnx_readmem_ind(sc, 0x0c14);
4032 if ((mac_addr >> 16) == 0x484b) {
4033 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4034 ether_addr[1] = (uint8_t)mac_addr;
4035 mac_addr = bnx_readmem_ind(sc, 0x0c18);
4036 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4037 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4038 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4039 ether_addr[5] = (uint8_t)mac_addr;
4046 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[])
4048 int mac_offset = BGE_EE_MAC_OFFSET;
4050 if (BNX_IS_5717_PLUS(sc)) {
4053 f = pci_get_function(sc->bnx_dev);
4055 mac_offset = BGE_EE_MAC_OFFSET_5717;
4057 mac_offset += BGE_EE_MAC_OFFSET_5717_OFF;
4060 return bnx_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4064 bnx_get_eaddr_eeprom(struct bnx_softc *sc, uint8_t ether_addr[])
4066 if (sc->bnx_flags & BNX_FLAG_NO_EEPROM)
4069 return bnx_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4074 bnx_get_eaddr(struct bnx_softc *sc, uint8_t eaddr[])
4076 static const bnx_eaddr_fcn_t bnx_eaddr_funcs[] = {
4077 /* NOTE: Order is critical */
4079 bnx_get_eaddr_nvram,
4080 bnx_get_eaddr_eeprom,
4083 const bnx_eaddr_fcn_t *func;
4085 for (func = bnx_eaddr_funcs; *func != NULL; ++func) {
4086 if ((*func)(sc, eaddr) == 0)
4089 return (*func == NULL ? ENXIO : 0);
4093 * NOTE: 'm' is not freed upon failure
4096 bnx_defrag_shortdma(struct mbuf *m)
4102 * If device receive two back-to-back send BDs with less than
4103 * or equal to 8 total bytes then the device may hang. The two
4104 * back-to-back send BDs must in the same frame for this failure
4105 * to occur. Scan mbuf chains and see whether two back-to-back
4106 * send BDs are there. If this is the case, allocate new mbuf
4107 * and copy the frame to workaround the silicon bug.
4109 for (n = m, found = 0; n != NULL; n = n->m_next) {
4120 n = m_defrag(m, MB_DONTWAIT);
4127 bnx_stop_block(struct bnx_softc *sc, bus_size_t reg, uint32_t bit)
4131 BNX_CLRBIT(sc, reg, bit);
4132 for (i = 0; i < BNX_TIMEOUT; i++) {
4133 if ((CSR_READ_4(sc, reg) & bit) == 0)
4140 bnx_link_poll(struct bnx_softc *sc)
4144 status = CSR_READ_4(sc, BGE_MAC_STS);
4145 if ((status & sc->bnx_link_chg) || sc->bnx_link_evt) {
4146 sc->bnx_link_evt = 0;
4147 sc->bnx_link_upd(sc, status);
4152 bnx_enable_msi(struct bnx_softc *sc)
4156 msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
4157 msi_mode |= BGE_MSIMODE_ENABLE;
4158 if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
4161 * 5718-PG105-R says that "one shot" mode
4162 * does not work if MSI is used, however,
4163 * it obviously works.
4165 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
4167 CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
4171 bnx_dma_swap_options(struct bnx_softc *sc)
4173 uint32_t dma_options;
4175 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
4176 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
4177 #if BYTE_ORDER == BIG_ENDIAN
4178 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
4180 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
4181 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
4182 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA |
4183 BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE |
4184 BGE_MODECTL_HTX2B_ENABLE;
4190 bnx_setup_tso(struct bnx_softc *sc, struct mbuf **mp,
4191 uint16_t *mss0, uint16_t *flags0)
4196 int thoff, iphlen, hoff, hlen;
4197 uint16_t flags, mss;
4200 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4202 hoff = m->m_pkthdr.csum_lhlen;
4203 iphlen = m->m_pkthdr.csum_iphlen;
4204 thoff = m->m_pkthdr.csum_thlen;
4206 KASSERT(hoff > 0, ("invalid ether header len"));
4207 KASSERT(iphlen > 0, ("invalid ip header len"));
4208 KASSERT(thoff > 0, ("invalid tcp header len"));
4210 if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4211 m = m_pullup(m, hoff + iphlen + thoff);
4218 ip = mtodoff(m, struct ip *, hoff);
4219 th = mtodoff(m, struct tcphdr *, hoff + iphlen);
4221 mss = m->m_pkthdr.tso_segsz;
4222 flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA;
4224 ip->ip_len = htons(mss + iphlen + thoff);
4227 hlen = (iphlen + thoff) >> 2;
4228 mss |= ((hlen & 0x3) << 14);
4229 flags |= ((hlen & 0xf8) << 7) | ((hlen & 0x4) << 2);