sys/dev/netif/bnx/if_bnx.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36 #include "opt_bnx.h"
  37 #include "opt_ifpoll.h"
  38
  39 #include <sys/param.h>
  40 #include <sys/bus.h>
  41 #include <sys/endian.h>
  42 #include <sys/kernel.h>
  43 #include <sys/interrupt.h>
  44 #include <sys/mbuf.h>
  45 #include <sys/malloc.h>
  46 #include <sys/queue.h>
  47 #include <sys/rman.h>
  48 #include <sys/serialize.h>
  49 #include <sys/socket.h>
  50 #include <sys/sockio.h>
  51 #include <sys/sysctl.h>
  52
  53 #include <netinet/ip.h>
  54 #include <netinet/tcp.h>
  55
  56 #include <net/bpf.h>
  57 #include <net/ethernet.h>
  58 #include <net/if.h>
  59 #include <net/if_arp.h>
  60 #include <net/if_dl.h>
  61 #include <net/if_media.h>
  62 #include <net/if_poll.h>
  63 #include <net/if_types.h>
  64 #include <net/ifq_var.h>
  65 #include <net/vlan/if_vlan_var.h>
  66 #include <net/vlan/if_vlan_ether.h>
  67
  68 #include <dev/netif/mii_layer/mii.h>
  69 #include <dev/netif/mii_layer/miivar.h>
  70 #include <dev/netif/mii_layer/brgphyreg.h>
  71
  72 #include <bus/pci/pcidevs.h>
  73 #include <bus/pci/pcireg.h>
  74 #include <bus/pci/pcivar.h>
  75
  76 #include <dev/netif/bge/if_bgereg.h>
  77 #include <dev/netif/bnx/if_bnxvar.h>
  78
  79 /* "device miibus" required.  See GENERIC if you get errors here. */
  80 #include "miibus_if.h"
  81
  82 #define BNX_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
  83
  84 #define BNX_INTR_CKINTVL        ((10 * hz) / 1000)      /* 10ms */
  85
  86 static const struct bnx_type {
  87         uint16_t                bnx_vid;
  88         uint16_t                bnx_did;
  89         char                    *bnx_name;
  90 } bnx_devs[] = {
  91         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
  92                 "Broadcom BCM5717 Gigabit Ethernet" },
  93         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717C,
  94                 "Broadcom BCM5717C Gigabit Ethernet" },
  95         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
  96                 "Broadcom BCM5718 Gigabit Ethernet" },
  97         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
  98                 "Broadcom BCM5719 Gigabit Ethernet" },
  99         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
 100                 "Broadcom BCM5720 Gigabit Ethernet" },
 101
 102         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5725,
 103                 "Broadcom BCM5725 Gigabit Ethernet" },
 104         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5727,
 105                 "Broadcom BCM5727 Gigabit Ethernet" },
 106         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5762,
 107                 "Broadcom BCM5762 Gigabit Ethernet" },
 108
 109         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
 110                 "Broadcom BCM57761 Gigabit Ethernet" },
 111         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762,
 112                 "Broadcom BCM57762 Gigabit Ethernet" },
 113         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
 114                 "Broadcom BCM57765 Gigabit Ethernet" },
 115         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766,
 116                 "Broadcom BCM57766 Gigabit Ethernet" },
 117         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
 118                 "Broadcom BCM57781 Gigabit Ethernet" },
 119         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782,
 120                 "Broadcom BCM57782 Gigabit Ethernet" },
 121         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
 122                 "Broadcom BCM57785 Gigabit Ethernet" },
 123         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786,
 124                 "Broadcom BCM57786 Gigabit Ethernet" },
 125         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
 126                 "Broadcom BCM57791 Fast Ethernet" },
 127         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
 128                 "Broadcom BCM57795 Fast Ethernet" },
 129
 130         { 0, 0, NULL }
 131 };
 132
 133 #define BNX_IS_JUMBO_CAPABLE(sc)        ((sc)->bnx_flags & BNX_FLAG_JUMBO)
 134 #define BNX_IS_5717_PLUS(sc)            ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
 135 #define BNX_IS_57765_PLUS(sc)           ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
 136 #define BNX_IS_57765_FAMILY(sc)  \
 137         ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
 138
 139 typedef int     (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
 140
 141 static int      bnx_probe(device_t);
 142 static int      bnx_attach(device_t);
 143 static int      bnx_detach(device_t);
 144 static void     bnx_shutdown(device_t);
 145 static int      bnx_suspend(device_t);
 146 static int      bnx_resume(device_t);
 147 static int      bnx_miibus_readreg(device_t, int, int);
 148 static int      bnx_miibus_writereg(device_t, int, int, int);
 149 static void     bnx_miibus_statchg(device_t);
 150
 151 #ifdef IFPOLL_ENABLE
 152 static void     bnx_npoll(struct ifnet *, struct ifpoll_info *);
 153 static void     bnx_npoll_compat(struct ifnet *, void *, int);
 154 #endif
 155 static void     bnx_intr_legacy(void *);
 156 static void     bnx_msi(void *);
 157 static void     bnx_msi_oneshot(void *);
 158 static void     bnx_intr(struct bnx_softc *);
 159 static void     bnx_enable_intr(struct bnx_softc *);
 160 static void     bnx_disable_intr(struct bnx_softc *);
 161 static void     bnx_txeof(struct bnx_tx_ring *, uint16_t);
 162 static void     bnx_rxeof(struct bnx_softc *, uint16_t, int);
 163
 164 static void     bnx_start(struct ifnet *, struct ifaltq_subque *);
 165 static int      bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 166 static void     bnx_init(void *);
 167 static void     bnx_stop(struct bnx_softc *);
 168 static void     bnx_watchdog(struct ifnet *);
 169 static int      bnx_ifmedia_upd(struct ifnet *);
 170 static void     bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 171 static void     bnx_tick(void *);
 172
 173 static int      bnx_alloc_jumbo_mem(struct bnx_softc *);
 174 static void     bnx_free_jumbo_mem(struct bnx_softc *);
 175 static struct bnx_jslot
 176                 *bnx_jalloc(struct bnx_softc *);
 177 static void     bnx_jfree(void *);
 178 static void     bnx_jref(void *);
 179 static int      bnx_newbuf_std(struct bnx_softc *, int, int);
 180 static int      bnx_newbuf_jumbo(struct bnx_softc *, int, int);
 181 static void     bnx_setup_rxdesc_std(struct bnx_softc *, int);
 182 static void     bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
 183 static int      bnx_init_rx_ring_std(struct bnx_softc *);
 184 static void     bnx_free_rx_ring_std(struct bnx_softc *);
 185 static int      bnx_init_rx_ring_jumbo(struct bnx_softc *);
 186 static void     bnx_free_rx_ring_jumbo(struct bnx_softc *);
 187 static void     bnx_free_tx_ring(struct bnx_tx_ring *);
 188 static int      bnx_init_tx_ring(struct bnx_tx_ring *);
 189 static int      bnx_create_tx_ring(struct bnx_tx_ring *);
 190 static void     bnx_destroy_tx_ring(struct bnx_tx_ring *);
 191 static int      bnx_dma_alloc(struct bnx_softc *);
 192 static void     bnx_dma_free(struct bnx_softc *);
 193 static int      bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
 194                     bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
 195 static void     bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 196 static struct mbuf *
 197                 bnx_defrag_shortdma(struct mbuf *);
 198 static int      bnx_encap(struct bnx_tx_ring *, struct mbuf **,
 199                     uint32_t *, int *);
 200 static int      bnx_setup_tso(struct bnx_tx_ring *, struct mbuf **,
 201                     uint16_t *, uint16_t *);
 202
 203 static void     bnx_reset(struct bnx_softc *);
 204 static int      bnx_chipinit(struct bnx_softc *);
 205 static int      bnx_blockinit(struct bnx_softc *);
 206 static void     bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
 207 static void     bnx_enable_msi(struct bnx_softc *sc);
 208 static void     bnx_setmulti(struct bnx_softc *);
 209 static void     bnx_setpromisc(struct bnx_softc *);
 210 static void     bnx_stats_update_regs(struct bnx_softc *);
 211 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
 212
 213 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
 214 static void     bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
 215 #ifdef notdef
 216 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
 217 #endif
 218 static void     bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
 219 static void     bnx_writembx(struct bnx_softc *, int, int);
 220 static int      bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
 221 static uint8_t  bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
 222 static int      bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
 223
 224 static void     bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
 225 static void     bnx_copper_link_upd(struct bnx_softc *, uint32_t);
 226 static void     bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
 227 static void     bnx_link_poll(struct bnx_softc *);
 228
 229 static int      bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
 230 static int      bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
 231 static int      bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
 232 static int      bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
 233
 234 static void     bnx_coal_change(struct bnx_softc *);
 235 static int      bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 236 static int      bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 237 static int      bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
 238 static int      bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
 239 static int      bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 240 static int      bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 241 static int      bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
 242                     int, int, uint32_t);
 243
 244 static int      bnx_msi_enable = 1;
 245 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
 246
 247 static device_method_t bnx_methods[] = {
 248         /* Device interface */
 249         DEVMETHOD(device_probe,         bnx_probe),
 250         DEVMETHOD(device_attach,        bnx_attach),
 251         DEVMETHOD(device_detach,        bnx_detach),
 252         DEVMETHOD(device_shutdown,      bnx_shutdown),
 253         DEVMETHOD(device_suspend,       bnx_suspend),
 254         DEVMETHOD(device_resume,        bnx_resume),
 255
 256         /* bus interface */
 257         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 258         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 259
 260         /* MII interface */
 261         DEVMETHOD(miibus_readreg,       bnx_miibus_readreg),
 262         DEVMETHOD(miibus_writereg,      bnx_miibus_writereg),
 263         DEVMETHOD(miibus_statchg,       bnx_miibus_statchg),
 264
 265         DEVMETHOD_END
 266 };
 267
 268 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
 269 static devclass_t bnx_devclass;
 270
 271 DECLARE_DUMMY_MODULE(if_bnx);
 272 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
 273 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
 274
 275 static uint32_t
 276 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
 277 {
 278         device_t dev = sc->bnx_dev;
 279         uint32_t val;
 280
 281         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 282         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 283         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 284         return (val);
 285 }
 286
 287 static void
 288 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
 289 {
 290         device_t dev = sc->bnx_dev;
 291
 292         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 293         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 294         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 295 }
 296
 297 static void
 298 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
 299 {
 300         CSR_WRITE_4(sc, off, val);
 301 }
 302
 303 static void
 304 bnx_writembx(struct bnx_softc *sc, int off, int val)
 305 {
 306         CSR_WRITE_4(sc, off, val);
 307 }
 308
 309 /*
 310  * Read a sequence of bytes from NVRAM.
 311  */
 312 static int
 313 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
 314 {
 315         return (1);
 316 }
 317
 318 /*
 319  * Read a byte of data stored in the EEPROM at address 'addr.' The
 320  * BCM570x supports both the traditional bitbang interface and an
 321  * auto access interface for reading the EEPROM. We use the auto
 322  * access method.
 323  */
 324 static uint8_t
 325 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
 326 {
 327         int i;
 328         uint32_t byte = 0;
 329
 330         /*
 331          * Enable use of auto EEPROM access so we can avoid
 332          * having to use the bitbang method.
 333          */
 334         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 335
 336         /* Reset the EEPROM, load the clock period. */
 337         CSR_WRITE_4(sc, BGE_EE_ADDR,
 338             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 339         DELAY(20);
 340
 341         /* Issue the read EEPROM command. */
 342         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 343
 344         /* Wait for completion */
 345         for(i = 0; i < BNX_TIMEOUT * 10; i++) {
 346                 DELAY(10);
 347                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 348                         break;
 349         }
 350
 351         if (i == BNX_TIMEOUT) {
 352                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 353                 return(1);
 354         }
 355
 356         /* Get result. */
 357         byte = CSR_READ_4(sc, BGE_EE_DATA);
 358
 359         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 360
 361         return(0);
 362 }
 363
 364 /*
 365  * Read a sequence of bytes from the EEPROM.
 366  */
 367 static int
 368 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
 369 {
 370         size_t i;
 371         int err;
 372         uint8_t byte;
 373
 374         for (byte = 0, err = 0, i = 0; i < len; i++) {
 375                 err = bnx_eeprom_getbyte(sc, off + i, &byte);
 376                 if (err)
 377                         break;
 378                 *(dest + i) = byte;
 379         }
 380
 381         return(err ? 1 : 0);
 382 }
 383
 384 static int
 385 bnx_miibus_readreg(device_t dev, int phy, int reg)
 386 {
 387         struct bnx_softc *sc = device_get_softc(dev);
 388         uint32_t val;
 389         int i;
 390
 391         KASSERT(phy == sc->bnx_phyno,
 392             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 393
 394         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 395         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 396                 CSR_WRITE_4(sc, BGE_MI_MODE,
 397                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 398                 DELAY(80);
 399         }
 400
 401         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 402             BGE_MIPHY(phy) | BGE_MIREG(reg));
 403
 404         /* Poll for the PHY register access to complete. */
 405         for (i = 0; i < BNX_TIMEOUT; i++) {
 406                 DELAY(10);
 407                 val = CSR_READ_4(sc, BGE_MI_COMM);
 408                 if ((val & BGE_MICOMM_BUSY) == 0) {
 409                         DELAY(5);
 410                         val = CSR_READ_4(sc, BGE_MI_COMM);
 411                         break;
 412                 }
 413         }
 414         if (i == BNX_TIMEOUT) {
 415                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
 416                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 417                 val = 0;
 418         }
 419
 420         /* Restore the autopoll bit if necessary. */
 421         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 422                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 423                 DELAY(80);
 424         }
 425
 426         if (val & BGE_MICOMM_READFAIL)
 427                 return 0;
 428
 429         return (val & 0xFFFF);
 430 }
 431
 432 static int
 433 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
 434 {
 435         struct bnx_softc *sc = device_get_softc(dev);
 436         int i;
 437
 438         KASSERT(phy == sc->bnx_phyno,
 439             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 440
 441         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 442         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 443                 CSR_WRITE_4(sc, BGE_MI_MODE,
 444                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 445                 DELAY(80);
 446         }
 447
 448         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 449             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 450
 451         for (i = 0; i < BNX_TIMEOUT; i++) {
 452                 DELAY(10);
 453                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 454                         DELAY(5);
 455                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 456                         break;
 457                 }
 458         }
 459         if (i == BNX_TIMEOUT) {
 460                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 461                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
 462         }
 463
 464         /* Restore the autopoll bit if necessary. */
 465         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 466                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 467                 DELAY(80);
 468         }
 469
 470         return 0;
 471 }
 472
 473 static void
 474 bnx_miibus_statchg(device_t dev)
 475 {
 476         struct bnx_softc *sc;
 477         struct mii_data *mii;
 478
 479         sc = device_get_softc(dev);
 480         mii = device_get_softc(sc->bnx_miibus);
 481
 482         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 483             (IFM_ACTIVE | IFM_AVALID)) {
 484                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 485                 case IFM_10_T:
 486                 case IFM_100_TX:
 487                         sc->bnx_link = 1;
 488                         break;
 489                 case IFM_1000_T:
 490                 case IFM_1000_SX:
 491                 case IFM_2500_SX:
 492                         sc->bnx_link = 1;
 493                         break;
 494                 default:
 495                         sc->bnx_link = 0;
 496                         break;
 497                 }
 498         } else {
 499                 sc->bnx_link = 0;
 500         }
 501         if (sc->bnx_link == 0)
 502                 return;
 503
 504         BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 505         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 506             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
 507                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 508         } else {
 509                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 510         }
 511
 512         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 513                 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 514         } else {
 515                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 516         }
 517 }
 518
 519 /*
 520  * Memory management for jumbo frames.
 521  */
 522 static int
 523 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
 524 {
 525         struct ifnet *ifp = &sc->arpcom.ac_if;
 526         struct bnx_jslot *entry;
 527         uint8_t *ptr;
 528         bus_addr_t paddr;
 529         int i, error;
 530
 531         /*
 532          * Create tag for jumbo mbufs.
 533          * This is really a bit of a kludge. We allocate a special
 534          * jumbo buffer pool which (thanks to the way our DMA
 535          * memory allocation works) will consist of contiguous
 536          * pages. This means that even though a jumbo buffer might
 537          * be larger than a page size, we don't really need to
 538          * map it into more than one DMA segment. However, the
 539          * default mbuf tag will result in multi-segment mappings,
 540          * so we have to create a special jumbo mbuf tag that
 541          * lets us get away with mapping the jumbo buffers as
 542          * a single segment. I think eventually the driver should
 543          * be changed so that it uses ordinary mbufs and cluster
 544          * buffers, i.e. jumbo frames can span multiple DMA
 545          * descriptors. But that's a project for another day.
 546          */
 547
 548         /*
 549          * Create DMA stuffs for jumbo RX ring.
 550          */
 551         error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 552                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 553                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 554                                     (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
 555                                     &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
 556         if (error) {
 557                 if_printf(ifp, "could not create jumbo RX ring\n");
 558                 return error;
 559         }
 560
 561         /*
 562          * Create DMA stuffs for jumbo buffer block.
 563          */
 564         error = bnx_dma_block_alloc(sc, BNX_JMEM,
 565                                     &sc->bnx_cdata.bnx_jumbo_tag,
 566                                     &sc->bnx_cdata.bnx_jumbo_map,
 567                                     (void **)&sc->bnx_ldata.bnx_jumbo_buf,
 568                                     &paddr);
 569         if (error) {
 570                 if_printf(ifp, "could not create jumbo buffer\n");
 571                 return error;
 572         }
 573
 574         SLIST_INIT(&sc->bnx_jfree_listhead);
 575
 576         /*
 577          * Now divide it up into 9K pieces and save the addresses
 578          * in an array. Note that we play an evil trick here by using
 579          * the first few bytes in the buffer to hold the the address
 580          * of the softc structure for this interface. This is because
 581          * bnx_jfree() needs it, but it is called by the mbuf management
 582          * code which will not pass it to us explicitly.
 583          */
 584         for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
 585                 entry = &sc->bnx_cdata.bnx_jslots[i];
 586                 entry->bnx_sc = sc;
 587                 entry->bnx_buf = ptr;
 588                 entry->bnx_paddr = paddr;
 589                 entry->bnx_inuse = 0;
 590                 entry->bnx_slot = i;
 591                 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
 592
 593                 ptr += BNX_JLEN;
 594                 paddr += BNX_JLEN;
 595         }
 596         return 0;
 597 }
 598
 599 static void
 600 bnx_free_jumbo_mem(struct bnx_softc *sc)
 601 {
 602         /* Destroy jumbo RX ring. */
 603         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 604                            sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 605                            sc->bnx_ldata.bnx_rx_jumbo_ring);
 606
 607         /* Destroy jumbo buffer block. */
 608         bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
 609                            sc->bnx_cdata.bnx_jumbo_map,
 610                            sc->bnx_ldata.bnx_jumbo_buf);
 611 }
 612
 613 /*
 614  * Allocate a jumbo buffer.
 615  */
 616 static struct bnx_jslot *
 617 bnx_jalloc(struct bnx_softc *sc)
 618 {
 619         struct bnx_jslot *entry;
 620
 621         lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 622         entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
 623         if (entry) {
 624                 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
 625                 entry->bnx_inuse = 1;
 626         } else {
 627                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 628         }
 629         lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 630         return(entry);
 631 }
 632
 633 /*
 634  * Adjust usage count on a jumbo buffer.
 635  */
 636 static void
 637 bnx_jref(void *arg)
 638 {
 639         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 640         struct bnx_softc *sc = entry->bnx_sc;
 641
 642         if (sc == NULL)
 643                 panic("bnx_jref: can't find softc pointer!");
 644
 645         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 646                 panic("bnx_jref: asked to reference buffer "
 647                     "that we don't manage!");
 648         } else if (entry->bnx_inuse == 0) {
 649                 panic("bnx_jref: buffer already free!");
 650         } else {
 651                 atomic_add_int(&entry->bnx_inuse, 1);
 652         }
 653 }
 654
 655 /*
 656  * Release a jumbo buffer.
 657  */
 658 static void
 659 bnx_jfree(void *arg)
 660 {
 661         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 662         struct bnx_softc *sc = entry->bnx_sc;
 663
 664         if (sc == NULL)
 665                 panic("bnx_jfree: can't find softc pointer!");
 666
 667         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 668                 panic("bnx_jfree: asked to free buffer that we don't manage!");
 669         } else if (entry->bnx_inuse == 0) {
 670                 panic("bnx_jfree: buffer already free!");
 671         } else {
 672                 /*
 673                  * Possible MP race to 0, use the serializer.  The atomic insn
 674                  * is still needed for races against bnx_jref().
 675                  */
 676                 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 677                 atomic_subtract_int(&entry->bnx_inuse, 1);
 678                 if (entry->bnx_inuse == 0) {
 679                         SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead,
 680                                           entry, jslot_link);
 681                 }
 682                 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 683         }
 684 }
 685
 686
 687 /*
 688  * Intialize a standard receive ring descriptor.
 689  */
 690 static int
 691 bnx_newbuf_std(struct bnx_softc *sc, int i, int init)
 692 {
 693         struct mbuf *m_new = NULL;
 694         bus_dma_segment_t seg;
 695         bus_dmamap_t map;
 696         int error, nsegs;
 697
 698         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 699         if (m_new == NULL)
 700                 return ENOBUFS;
 701         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 702         m_adj(m_new, ETHER_ALIGN);
 703
 704         error = bus_dmamap_load_mbuf_segment(sc->bnx_cdata.bnx_rx_mtag,
 705                         sc->bnx_cdata.bnx_rx_tmpmap, m_new,
 706                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 707         if (error) {
 708                 m_freem(m_new);
 709                 return error;
 710         }
 711
 712         if (!init) {
 713                 bus_dmamap_sync(sc->bnx_cdata.bnx_rx_mtag,
 714                                 sc->bnx_cdata.bnx_rx_std_dmamap[i],
 715                                 BUS_DMASYNC_POSTREAD);
 716                 bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
 717                         sc->bnx_cdata.bnx_rx_std_dmamap[i]);
 718         }
 719
 720         map = sc->bnx_cdata.bnx_rx_tmpmap;
 721         sc->bnx_cdata.bnx_rx_tmpmap = sc->bnx_cdata.bnx_rx_std_dmamap[i];
 722         sc->bnx_cdata.bnx_rx_std_dmamap[i] = map;
 723
 724         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_mbuf = m_new;
 725         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_paddr = seg.ds_addr;
 726
 727         bnx_setup_rxdesc_std(sc, i);
 728         return 0;
 729 }
 730
 731 static void
 732 bnx_setup_rxdesc_std(struct bnx_softc *sc, int i)
 733 {
 734         struct bnx_rxchain *rc;
 735         struct bge_rx_bd *r;
 736
 737         rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
 738         r = &sc->bnx_ldata.bnx_rx_std_ring[i];
 739
 740         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
 741         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
 742         r->bge_len = rc->bnx_mbuf->m_len;
 743         r->bge_idx = i;
 744         r->bge_flags = BGE_RXBDFLAG_END;
 745 }
 746
 747 /*
 748  * Initialize a jumbo receive ring descriptor. This allocates
 749  * a jumbo buffer from the pool managed internally by the driver.
 750  */
 751 static int
 752 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
 753 {
 754         struct mbuf *m_new = NULL;
 755         struct bnx_jslot *buf;
 756         bus_addr_t paddr;
 757
 758         /* Allocate the mbuf. */
 759         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
 760         if (m_new == NULL)
 761                 return ENOBUFS;
 762
 763         /* Allocate the jumbo buffer */
 764         buf = bnx_jalloc(sc);
 765         if (buf == NULL) {
 766                 m_freem(m_new);
 767                 return ENOBUFS;
 768         }
 769
 770         /* Attach the buffer to the mbuf. */
 771         m_new->m_ext.ext_arg = buf;
 772         m_new->m_ext.ext_buf = buf->bnx_buf;
 773         m_new->m_ext.ext_free = bnx_jfree;
 774         m_new->m_ext.ext_ref = bnx_jref;
 775         m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
 776
 777         m_new->m_flags |= M_EXT;
 778
 779         m_new->m_data = m_new->m_ext.ext_buf;
 780         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 781
 782         paddr = buf->bnx_paddr;
 783         m_adj(m_new, ETHER_ALIGN);
 784         paddr += ETHER_ALIGN;
 785
 786         /* Save necessary information */
 787         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_mbuf = m_new;
 788         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_paddr = paddr;
 789
 790         /* Set up the descriptor. */
 791         bnx_setup_rxdesc_jumbo(sc, i);
 792         return 0;
 793 }
 794
 795 static void
 796 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
 797 {
 798         struct bge_rx_bd *r;
 799         struct bnx_rxchain *rc;
 800
 801         r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
 802         rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 803
 804         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
 805         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
 806         r->bge_len = rc->bnx_mbuf->m_len;
 807         r->bge_idx = i;
 808         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 809 }
 810
 811 static int
 812 bnx_init_rx_ring_std(struct bnx_softc *sc)
 813 {
 814         int i, error;
 815
 816         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 817                 error = bnx_newbuf_std(sc, i, 1);
 818                 if (error)
 819                         return error;
 820         }
 821
 822         sc->bnx_std = BGE_STD_RX_RING_CNT - 1;
 823         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
 824
 825         return(0);
 826 }
 827
 828 static void
 829 bnx_free_rx_ring_std(struct bnx_softc *sc)
 830 {
 831         int i;
 832
 833         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 834                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
 835
 836                 if (rc->bnx_mbuf != NULL) {
 837                         bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
 838                                           sc->bnx_cdata.bnx_rx_std_dmamap[i]);
 839                         m_freem(rc->bnx_mbuf);
 840                         rc->bnx_mbuf = NULL;
 841                 }
 842                 bzero(&sc->bnx_ldata.bnx_rx_std_ring[i],
 843                     sizeof(struct bge_rx_bd));
 844         }
 845 }
 846
 847 static int
 848 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
 849 {
 850         struct bge_rcb *rcb;
 851         int i, error;
 852
 853         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 854                 error = bnx_newbuf_jumbo(sc, i, 1);
 855                 if (error)
 856                         return error;
 857         }
 858
 859         sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
 860
 861         rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
 862         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 863         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 864
 865         bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
 866
 867         return(0);
 868 }
 869
 870 static void
 871 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
 872 {
 873         int i;
 874
 875         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 876                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 877
 878                 if (rc->bnx_mbuf != NULL) {
 879                         m_freem(rc->bnx_mbuf);
 880                         rc->bnx_mbuf = NULL;
 881                 }
 882                 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
 883                     sizeof(struct bge_rx_bd));
 884         }
 885 }
 886
 887 static void
 888 bnx_free_tx_ring(struct bnx_tx_ring *txr)
 889 {
 890         int i;
 891
 892         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 893                 if (txr->bnx_tx_chain[i] != NULL) {
 894                         bus_dmamap_unload(txr->bnx_tx_mtag,
 895                             txr->bnx_tx_dmamap[i]);
 896                         m_freem(txr->bnx_tx_chain[i]);
 897                         txr->bnx_tx_chain[i] = NULL;
 898                 }
 899                 bzero(&txr->bnx_tx_ring[i], sizeof(struct bge_tx_bd));
 900         }
 901         txr->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
 902 }
 903
 904 static int
 905 bnx_init_tx_ring(struct bnx_tx_ring *txr)
 906 {
 907         txr->bnx_txcnt = 0;
 908         txr->bnx_tx_saved_considx = 0;
 909         txr->bnx_tx_prodidx = 0;
 910
 911         /* Initialize transmit producer index for host-memory send ring. */
 912         bnx_writembx(txr->bnx_sc, BGE_MBX_TX_HOST_PROD0_LO,
 913             txr->bnx_tx_prodidx);
 914
 915         return(0);
 916 }
 917
 918 static void
 919 bnx_setmulti(struct bnx_softc *sc)
 920 {
 921         struct ifnet *ifp;
 922         struct ifmultiaddr *ifma;
 923         uint32_t hashes[4] = { 0, 0, 0, 0 };
 924         int h, i;
 925
 926         ifp = &sc->arpcom.ac_if;
 927
 928         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 929                 for (i = 0; i < 4; i++)
 930                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
 931                 return;
 932         }
 933
 934         /* First, zot all the existing filters. */
 935         for (i = 0; i < 4; i++)
 936                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
 937
 938         /* Now program new ones. */
 939         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 940                 if (ifma->ifma_addr->sa_family != AF_LINK)
 941                         continue;
 942                 h = ether_crc32_le(
 943                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 944                     ETHER_ADDR_LEN) & 0x7f;
 945                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
 946         }
 947
 948         for (i = 0; i < 4; i++)
 949                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
 950 }
 951
 952 /*
 953  * Do endian, PCI and DMA initialization. Also check the on-board ROM
 954  * self-test results.
 955  */
 956 static int
 957 bnx_chipinit(struct bnx_softc *sc)
 958 {
 959         uint32_t dma_rw_ctl, mode_ctl;
 960         int i;
 961
 962         /* Set endian type before we access any non-PCI registers. */
 963         pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
 964             BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
 965
 966         /* Clear the MAC control register */
 967         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
 968
 969         /*
 970          * Clear the MAC statistics block in the NIC's
 971          * internal memory.
 972          */
 973         for (i = BGE_STATS_BLOCK;
 974             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
 975                 BNX_MEMWIN_WRITE(sc, i, 0);
 976
 977         for (i = BGE_STATUS_BLOCK;
 978             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
 979                 BNX_MEMWIN_WRITE(sc, i, 0);
 980
 981         if (BNX_IS_57765_FAMILY(sc)) {
 982                 uint32_t val;
 983
 984                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
 985                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
 986                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
 987
 988                         /* Access the lower 1K of PL PCI-E block registers. */
 989                         CSR_WRITE_4(sc, BGE_MODE_CTL,
 990                             val | BGE_MODECTL_PCIE_PL_SEL);
 991
 992                         val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
 993                         val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
 994                         CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
 995
 996                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
 997                 }
 998                 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
 999                         /* Fix transmit hangs */
1000                         val = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);
1001                         val |= BGE_CPMU_PADRNG_CTL_RDIV2;
1002                         CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, val);
1003
1004                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1005                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1006
1007                         /* Access the lower 1K of DL PCI-E block registers. */
1008                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1009                             val | BGE_MODECTL_PCIE_DL_SEL);
1010
1011                         val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
1012                         val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
1013                         val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
1014                         CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
1015
1016                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1017                 }
1018
1019                 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
1020                 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
1021                 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
1022                 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
1023         }
1024
1025         /*
1026          * Set up the PCI DMA control register.
1027          */
1028         dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4);
1029         /*
1030          * Disable 32bytes cache alignment for DMA write to host memory
1031          *
1032          * NOTE:
1033          * 64bytes cache alignment for DMA write to host memory is still
1034          * enabled.
1035          */
1036         dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1037         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1038                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1039         /*
1040          * Enable HW workaround for controllers that misinterpret
1041          * a status tag update and leave interrupts permanently
1042          * disabled.
1043          */
1044         if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1045             sc->bnx_asicrev != BGE_ASICREV_BCM5762 &&
1046             !BNX_IS_57765_FAMILY(sc))
1047                 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1048         if (bootverbose) {
1049                 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n",
1050                     dma_rw_ctl);
1051         }
1052         pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1053
1054         /*
1055          * Set up general mode register.
1056          */
1057         mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1058             BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1059         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1060
1061         /*
1062          * Disable memory write invalidate.  Apparently it is not supported
1063          * properly by these devices.  Also ensure that INTx isn't disabled,
1064          * as these chips need it even when using MSI.
1065          */
1066         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1067             (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1068
1069         /* Set the timer prescaler (always 66Mhz) */
1070         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1071
1072         return(0);
1073 }
1074
1075 static int
1076 bnx_blockinit(struct bnx_softc *sc)
1077 {
1078         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
1079         struct bge_rcb *rcb;
1080         bus_size_t vrcb;
1081         bge_hostaddr taddr;
1082         uint32_t val;
1083         int i, limit;
1084
1085         /*
1086          * Initialize the memory window pointer register so that
1087          * we can access the first 32K of internal NIC RAM. This will
1088          * allow us to set up the TX send ring RCBs and the RX return
1089          * ring RCBs, plus other things which live in NIC memory.
1090          */
1091         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1092
1093         /* Configure mbuf pool watermarks */
1094         if (BNX_IS_57765_PLUS(sc)) {
1095                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1096                 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1097                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1098                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1099                 } else {
1100                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1101                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1102                 }
1103         } else {
1104                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1105                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1106                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1107         }
1108
1109         /* Configure DMA resource watermarks */
1110         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1111         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1112
1113         /* Enable buffer manager */
1114         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1115         /*
1116          * Change the arbitration algorithm of TXMBUF read request to
1117          * round-robin instead of priority based for BCM5719.  When
1118          * TXFIFO is almost empty, RDMA will hold its request until
1119          * TXFIFO is not almost empty.
1120          */
1121         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1122                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1123         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1124             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 ||
1125             sc->bnx_chipid == BGE_CHIPID_BCM5720_A0)
1126                 val |= BGE_BMANMODE_LOMBUF_ATTN;
1127         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1128
1129         /* Poll for buffer manager start indication */
1130         for (i = 0; i < BNX_TIMEOUT; i++) {
1131                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1132                         break;
1133                 DELAY(10);
1134         }
1135
1136         if (i == BNX_TIMEOUT) {
1137                 if_printf(&sc->arpcom.ac_if,
1138                           "buffer manager failed to start\n");
1139                 return(ENXIO);
1140         }
1141
1142         /* Enable flow-through queues */
1143         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1144         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1145
1146         /* Wait until queue initialization is complete */
1147         for (i = 0; i < BNX_TIMEOUT; i++) {
1148                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1149                         break;
1150                 DELAY(10);
1151         }
1152
1153         if (i == BNX_TIMEOUT) {
1154                 if_printf(&sc->arpcom.ac_if,
1155                           "flow-through queue init failed\n");
1156                 return(ENXIO);
1157         }
1158
1159         /*
1160          * Summary of rings supported by the controller:
1161          *
1162          * Standard Receive Producer Ring
1163          * - This ring is used to feed receive buffers for "standard"
1164          *   sized frames (typically 1536 bytes) to the controller.
1165          *
1166          * Jumbo Receive Producer Ring
1167          * - This ring is used to feed receive buffers for jumbo sized
1168          *   frames (i.e. anything bigger than the "standard" frames)
1169          *   to the controller.
1170          *
1171          * Mini Receive Producer Ring
1172          * - This ring is used to feed receive buffers for "mini"
1173          *   sized frames to the controller.
1174          * - This feature required external memory for the controller
1175          *   but was never used in a production system.  Should always
1176          *   be disabled.
1177          *
1178          * Receive Return Ring
1179          * - After the controller has placed an incoming frame into a
1180          *   receive buffer that buffer is moved into a receive return
1181          *   ring.  The driver is then responsible to passing the
1182          *   buffer up to the stack.  Many versions of the controller
1183          *   support multiple RR rings.
1184          *
1185          * Send Ring
1186          * - This ring is used for outgoing frames.  Many versions of
1187          *   the controller support multiple send rings.
1188          */
1189
1190         /* Initialize the standard receive producer ring control block. */
1191         rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1192         rcb->bge_hostaddr.bge_addr_lo =
1193             BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1194         rcb->bge_hostaddr.bge_addr_hi =
1195             BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1196         if (BNX_IS_57765_PLUS(sc)) {
1197                 /*
1198                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1199                  * Bits 15-2 : Maximum RX frame size
1200                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
1201                  * Bit 0     : Reserved
1202                  */
1203                 rcb->bge_maxlen_flags =
1204                     BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1205         } else {
1206                 /*
1207                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1208                  * Bits 15-2 : Reserved (should be 0)
1209                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1210                  * Bit 0     : Reserved
1211                  */
1212                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1213         }
1214         if (BNX_IS_5717_PLUS(sc))
1215                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1216         else
1217                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1218         /* Write the standard receive producer ring control block. */
1219         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1220         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1221         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1222         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1223         /* Reset the standard receive producer ring producer index. */
1224         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1225
1226         /*
1227          * Initialize the jumbo RX producer ring control
1228          * block.  We set the 'ring disabled' bit in the
1229          * flags field until we're actually ready to start
1230          * using this ring (i.e. once we set the MTU
1231          * high enough to require it).
1232          */
1233         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1234                 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1235                 /* Get the jumbo receive producer ring RCB parameters. */
1236                 rcb->bge_hostaddr.bge_addr_lo =
1237                     BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1238                 rcb->bge_hostaddr.bge_addr_hi =
1239                     BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1240                 rcb->bge_maxlen_flags =
1241                     BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1242                     BGE_RCB_FLAG_RING_DISABLED);
1243                 if (BNX_IS_5717_PLUS(sc))
1244                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1245                 else
1246                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1247                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1248                     rcb->bge_hostaddr.bge_addr_hi);
1249                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1250                     rcb->bge_hostaddr.bge_addr_lo);
1251                 /* Program the jumbo receive producer ring RCB parameters. */
1252                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1253                     rcb->bge_maxlen_flags);
1254                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1255                 /* Reset the jumbo receive producer ring producer index. */
1256                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1257         }
1258
1259         /*
1260          * The BD ring replenish thresholds control how often the
1261          * hardware fetches new BD's from the producer rings in host
1262          * memory.  Setting the value too low on a busy system can
1263          * starve the hardware and recue the throughpout.
1264          *
1265          * Set the BD ring replentish thresholds. The recommended
1266          * values are 1/8th the number of descriptors allocated to
1267          * each ring.
1268          */
1269         val = 8;
1270         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1271         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1272                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1273                     BGE_JUMBO_RX_RING_CNT/8);
1274         }
1275         if (BNX_IS_57765_PLUS(sc)) {
1276                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1277                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1278         }
1279
1280         /*
1281          * Disable all send rings by setting the 'ring disabled' bit
1282          * in the flags field of all the TX send ring control blocks,
1283          * located in NIC memory.
1284          */
1285         if (BNX_IS_5717_PLUS(sc))
1286                 limit = 4;
1287         else if (BNX_IS_57765_FAMILY(sc) ||
1288             sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1289                 limit = 2;
1290         else
1291                 limit = 1;
1292         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1293         for (i = 0; i < limit; i++) {
1294                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1295                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1296                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1297                 vrcb += sizeof(struct bge_rcb);
1298         }
1299
1300         /* Configure send ring RCB 0 (we use only the first ring) */
1301         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1302         BGE_HOSTADDR(taddr, txr->bnx_tx_ring_paddr);
1303         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1304         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1305         if (BNX_IS_5717_PLUS(sc)) {
1306                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1307         } else {
1308                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1309                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1310         }
1311         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1312             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1313
1314         /*
1315          * Disable all receive return rings by setting the
1316          * 'ring disabled' bit in the flags field of all the receive
1317          * return ring control blocks, located in NIC memory.
1318          */
1319         if (BNX_IS_5717_PLUS(sc)) {
1320                 /* Should be 17, use 16 until we get an SRAM map. */
1321                 limit = 16;
1322         } else if (BNX_IS_57765_FAMILY(sc) ||
1323             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1324                 limit = 4;
1325         } else {
1326                 limit = 1;
1327         }
1328         /* Disable all receive return rings. */
1329         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1330         for (i = 0; i < limit; i++) {
1331                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1332                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1333                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1334                     BGE_RCB_FLAG_RING_DISABLED);
1335                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1336                 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1337                     (i * (sizeof(uint64_t))), 0);
1338                 vrcb += sizeof(struct bge_rcb);
1339         }
1340
1341         /*
1342          * Set up receive return ring 0.  Note that the NIC address
1343          * for RX return rings is 0x0.  The return rings live entirely
1344          * within the host, so the nicaddr field in the RCB isn't used.
1345          */
1346         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1347         BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_rx_return_ring_paddr);
1348         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1349         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1350         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1351         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1352             BGE_RCB_MAXLEN_FLAGS(BNX_RETURN_RING_CNT, 0));
1353
1354         /* Set random backoff seed for TX */
1355         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1356             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1357             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1358             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1359             BGE_TX_BACKOFF_SEED_MASK);
1360
1361         /* Set inter-packet gap */
1362         val = 0x2620;
1363         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1364             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1365                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1366                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1367         }
1368         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1369
1370         /*
1371          * Specify which ring to use for packets that don't match
1372          * any RX rules.
1373          */
1374         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1375
1376         /*
1377          * Configure number of RX lists. One interrupt distribution
1378          * list, sixteen active lists, one bad frames class.
1379          */
1380         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1381
1382         /* Inialize RX list placement stats mask. */
1383         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1384         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1385
1386         /* Disable host coalescing until we get it set up */
1387         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1388
1389         /* Poll to make sure it's shut down. */
1390         for (i = 0; i < BNX_TIMEOUT; i++) {
1391                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1392                         break;
1393                 DELAY(10);
1394         }
1395
1396         if (i == BNX_TIMEOUT) {
1397                 if_printf(&sc->arpcom.ac_if,
1398                           "host coalescing engine failed to idle\n");
1399                 return(ENXIO);
1400         }
1401
1402         /* Set up host coalescing defaults */
1403         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bnx_rx_coal_ticks);
1404         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bnx_tx_coal_ticks);
1405         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bnx_rx_coal_bds);
1406         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bnx_tx_coal_bds);
1407         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bnx_rx_coal_bds_int);
1408         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bnx_tx_coal_bds_int);
1409
1410         /* Set up address of status block */
1411         bzero(sc->bnx_ldata.bnx_status_block, BGE_STATUS_BLK_SZ);
1412         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1413             BGE_ADDR_HI(sc->bnx_ldata.bnx_status_block_paddr));
1414         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1415             BGE_ADDR_LO(sc->bnx_ldata.bnx_status_block_paddr));
1416
1417         /* Set up status block partail update size. */
1418         val = BGE_STATBLKSZ_32BYTE;
1419 #if 0
1420         /*
1421          * Does not seem to have visible effect in both
1422          * bulk data (1472B UDP datagram) and tiny data
1423          * (18B UDP datagram) TX tests.
1424          */
1425         val |= BGE_HCCMODE_CLRTICK_TX;
1426 #endif
1427         /* Turn on host coalescing state machine */
1428         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1429
1430         /* Turn on RX BD completion state machine and enable attentions */
1431         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1432             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1433
1434         /* Turn on RX list placement state machine */
1435         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1436
1437         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1438             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1439             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1440             BGE_MACMODE_FRMHDR_DMA_ENB;
1441
1442         if (sc->bnx_flags & BNX_FLAG_TBI)
1443                 val |= BGE_PORTMODE_TBI;
1444         else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1445                 val |= BGE_PORTMODE_GMII;
1446         else
1447                 val |= BGE_PORTMODE_MII;
1448
1449         /* Turn on DMA, clear stats */
1450         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1451
1452         /* Set misc. local control, enable interrupts on attentions */
1453         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1454
1455 #ifdef notdef
1456         /* Assert GPIO pins for PHY reset */
1457         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1458             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1459         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1460             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1461 #endif
1462
1463         /* Turn on write DMA state machine */
1464         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1465         /* Enable host coalescing bug fix. */
1466         val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1467         if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1468                 /* Request larger DMA burst size to get better performance. */
1469                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1470         }
1471         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1472         DELAY(40);
1473
1474         if (BNX_IS_57765_PLUS(sc)) {
1475                 uint32_t dmactl, dmactl_reg;
1476
1477                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1478                         dmactl_reg = BGE_RDMA_RSRVCTRL2;
1479                 else
1480                         dmactl_reg = BGE_RDMA_RSRVCTRL;
1481
1482                 dmactl = CSR_READ_4(sc, dmactl_reg);
1483                 /*
1484                  * Adjust tx margin to prevent TX data corruption and
1485                  * fix internal FIFO overflow.
1486                  */
1487                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1488                     sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1489                     sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1490                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1491                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1492                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1493                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1494                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1495                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1496                 }
1497                 /*
1498                  * Enable fix for read DMA FIFO overruns.
1499                  * The fix is to limit the number of RX BDs
1500                  * the hardware would fetch at a fime.
1501                  */
1502                 CSR_WRITE_4(sc, dmactl_reg,
1503                     dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1504         }
1505
1506         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1507                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1508                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1509                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1510                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1511         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1512             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1513                 uint32_t ctrl_reg;
1514
1515                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1516                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL2;
1517                 else
1518                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL;
1519
1520                 /*
1521                  * Allow 4KB burst length reads for non-LSO frames.
1522                  * Enable 512B burst length reads for buffer descriptors.
1523                  */
1524                 CSR_WRITE_4(sc, ctrl_reg,
1525                     CSR_READ_4(sc, ctrl_reg) |
1526                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1527                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1528         }
1529
1530         /* Turn on read DMA state machine */
1531         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1532         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1533                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1534         if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1535             sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1536             sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1537                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1538                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1539                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1540         }
1541         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1542             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1543                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1544                     BGE_RDMAMODE_H2BNC_VLAN_DET;
1545                 /*
1546                  * Allow multiple outstanding read requests from
1547                  * non-LSO read DMA engine.
1548                  */
1549                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1550         }
1551         if (sc->bnx_asicrev == BGE_ASICREV_BCM57766)
1552                 val |= BGE_RDMAMODE_JMB_2K_MMRR;
1553         if (sc->bnx_flags & BNX_FLAG_TSO)
1554                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1555         val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1556         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1557         DELAY(40);
1558
1559         /* Turn on RX data completion state machine */
1560         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1561
1562         /* Turn on RX BD initiator state machine */
1563         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1564
1565         /* Turn on RX data and RX BD initiator state machine */
1566         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1567
1568         /* Turn on send BD completion state machine */
1569         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1570
1571         /* Turn on send data completion state machine */
1572         val = BGE_SDCMODE_ENABLE;
1573         if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1574                 val |= BGE_SDCMODE_CDELAY;
1575         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1576
1577         /* Turn on send data initiator state machine */
1578         if (sc->bnx_flags & BNX_FLAG_TSO) {
1579                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1580                     BGE_SDIMODE_HW_LSO_PRE_DMA);
1581         } else {
1582                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1583         }
1584
1585         /* Turn on send BD initiator state machine */
1586         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1587
1588         /* Turn on send BD selector state machine */
1589         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1590
1591         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1592         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1593             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1594
1595         /* ack/clear link change events */
1596         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1597             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1598             BGE_MACSTAT_LINK_CHANGED);
1599         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1600
1601         /*
1602          * Enable attention when the link has changed state for
1603          * devices that use auto polling.
1604          */
1605         if (sc->bnx_flags & BNX_FLAG_TBI) {
1606                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1607         } else {
1608                 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1609                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1610                         DELAY(80);
1611                 }
1612         }
1613
1614         /*
1615          * Clear any pending link state attention.
1616          * Otherwise some link state change events may be lost until attention
1617          * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1618          * It's not necessary on newer BCM chips - perhaps enabling link
1619          * state change attentions implies clearing pending attention.
1620          */
1621         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1622             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1623             BGE_MACSTAT_LINK_CHANGED);
1624
1625         /* Enable link state change attentions. */
1626         BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1627
1628         return(0);
1629 }
1630
1631 /*
1632  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1633  * against our list and return its name if we find a match. Note
1634  * that since the Broadcom controller contains VPD support, we
1635  * can get the device name string from the controller itself instead
1636  * of the compiled-in string. This is a little slow, but it guarantees
1637  * we'll always announce the right product name.
1638  */
1639 static int
1640 bnx_probe(device_t dev)
1641 {
1642         const struct bnx_type *t;
1643         uint16_t product, vendor;
1644
1645         if (!pci_is_pcie(dev))
1646                 return ENXIO;
1647
1648         product = pci_get_device(dev);
1649         vendor = pci_get_vendor(dev);
1650
1651         for (t = bnx_devs; t->bnx_name != NULL; t++) {
1652                 if (vendor == t->bnx_vid && product == t->bnx_did)
1653                         break;
1654         }
1655         if (t->bnx_name == NULL)
1656                 return ENXIO;
1657
1658         device_set_desc(dev, t->bnx_name);
1659         return 0;
1660 }
1661
1662 static int
1663 bnx_attach(device_t dev)
1664 {
1665         struct ifnet *ifp;
1666         struct bnx_softc *sc;
1667         uint32_t hwcfg = 0;
1668         int error = 0, rid, capmask;
1669         uint8_t ether_addr[ETHER_ADDR_LEN];
1670         uint16_t product;
1671         driver_intr_t *intr_func;
1672         uintptr_t mii_priv = 0;
1673         u_int intr_flags;
1674 #ifdef BNX_TSO_DEBUG
1675         char desc[32];
1676         int i;
1677 #endif
1678
1679         sc = device_get_softc(dev);
1680         sc->bnx_dev = dev;
1681         callout_init_mp(&sc->bnx_stat_timer);
1682         callout_init_mp(&sc->bnx_intr_timer);
1683         lwkt_serialize_init(&sc->bnx_jslot_serializer);
1684
1685         product = pci_get_device(dev);
1686
1687 #ifndef BURN_BRIDGES
1688         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1689                 uint32_t irq, mem;
1690
1691                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1692                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1693
1694                 device_printf(dev, "chip is in D%d power mode "
1695                     "-- setting to D0\n", pci_get_powerstate(dev));
1696
1697                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1698
1699                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1700                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1701         }
1702 #endif  /* !BURN_BRIDGE */
1703
1704         /*
1705          * Map control/status registers.
1706          */
1707         pci_enable_busmaster(dev);
1708
1709         rid = BGE_PCI_BAR0;
1710         sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1711             RF_ACTIVE);
1712
1713         if (sc->bnx_res == NULL) {
1714                 device_printf(dev, "couldn't map memory\n");
1715                 return ENXIO;
1716         }
1717
1718         sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1719         sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1720
1721         /* Save various chip information */
1722         sc->bnx_chipid =
1723             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1724             BGE_PCIMISCCTL_ASICREV_SHIFT;
1725         if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1726                 /* All chips having dedicated ASICREV register have CPMU */
1727                 sc->bnx_flags |= BNX_FLAG_CPMU;
1728
1729                 switch (product) {
1730                 case PCI_PRODUCT_BROADCOM_BCM5717:
1731                 case PCI_PRODUCT_BROADCOM_BCM5717C:
1732                 case PCI_PRODUCT_BROADCOM_BCM5718:
1733                 case PCI_PRODUCT_BROADCOM_BCM5719:
1734                 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1735                 case PCI_PRODUCT_BROADCOM_BCM5725:
1736                 case PCI_PRODUCT_BROADCOM_BCM5727:
1737                 case PCI_PRODUCT_BROADCOM_BCM5762:
1738                         sc->bnx_chipid = pci_read_config(dev,
1739                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
1740                         break;
1741
1742                 case PCI_PRODUCT_BROADCOM_BCM57761:
1743                 case PCI_PRODUCT_BROADCOM_BCM57762:
1744                 case PCI_PRODUCT_BROADCOM_BCM57765:
1745                 case PCI_PRODUCT_BROADCOM_BCM57766:
1746                 case PCI_PRODUCT_BROADCOM_BCM57781:
1747                 case PCI_PRODUCT_BROADCOM_BCM57782:
1748                 case PCI_PRODUCT_BROADCOM_BCM57785:
1749                 case PCI_PRODUCT_BROADCOM_BCM57786:
1750                 case PCI_PRODUCT_BROADCOM_BCM57791:
1751                 case PCI_PRODUCT_BROADCOM_BCM57795:
1752                         sc->bnx_chipid = pci_read_config(dev,
1753                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
1754                         break;
1755
1756                 default:
1757                         sc->bnx_chipid = pci_read_config(dev,
1758                             BGE_PCI_PRODID_ASICREV, 4);
1759                         break;
1760                 }
1761         }
1762         if (sc->bnx_chipid == BGE_CHIPID_BCM5717_C0)
1763                 sc->bnx_chipid = BGE_CHIPID_BCM5720_A0;
1764
1765         sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1766         sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1767
1768         switch (sc->bnx_asicrev) {
1769         case BGE_ASICREV_BCM5717:
1770         case BGE_ASICREV_BCM5719:
1771         case BGE_ASICREV_BCM5720:
1772                 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1773                 break;
1774
1775         case BGE_ASICREV_BCM5762:
1776                 sc->bnx_flags |= BNX_FLAG_57765_PLUS;
1777                 break;
1778
1779         case BGE_ASICREV_BCM57765:
1780         case BGE_ASICREV_BCM57766:
1781                 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1782                 break;
1783         }
1784         sc->bnx_flags |= BNX_FLAG_SHORTDMA;
1785
1786         sc->bnx_flags |= BNX_FLAG_TSO;
1787         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 &&
1788             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0)
1789                 sc->bnx_flags &= ~BNX_FLAG_TSO;
1790
1791         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1792             BNX_IS_57765_FAMILY(sc)) {
1793                 /*
1794                  * All BCM57785 and BCM5718 families chips have a bug that
1795                  * under certain situation interrupt will not be enabled
1796                  * even if status tag is written to BGE_MBX_IRQ0_LO mailbox.
1797                  *
1798                  * While BCM5719 and BCM5720 have a hardware workaround
1799                  * which could fix the above bug.
1800                  * See the comment near BGE_PCIDMARWCTL_TAGGED_STATUS_WA in
1801                  * bnx_chipinit().
1802                  *
1803                  * For the rest of the chips in these two families, we will
1804                  * have to poll the status block at high rate (10ms currently)
1805                  * to check whether the interrupt is hosed or not.
1806                  * See bnx_intr_check() for details.
1807                  */
1808                 sc->bnx_flags |= BNX_FLAG_STATUSTAG_BUG;
1809         }
1810
1811         sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1812         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1813             sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1814                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1815         else
1816                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1817         device_printf(dev, "CHIP ID 0x%08x; "
1818                       "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1819                       sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1820
1821         /*
1822          * Set various PHY quirk flags.
1823          */
1824
1825         capmask = MII_CAPMASK_DEFAULT;
1826         if (product == PCI_PRODUCT_BROADCOM_BCM57791 ||
1827             product == PCI_PRODUCT_BROADCOM_BCM57795) {
1828                 /* 10/100 only */
1829                 capmask &= ~BMSR_EXTSTAT;
1830         }
1831
1832         mii_priv |= BRGPHY_FLAG_WIRESPEED;
1833         if (sc->bnx_chipid == BGE_CHIPID_BCM5762_A0)
1834                 mii_priv |= BRGPHY_FLAG_5762_A0;
1835
1836         /* Initialize if_name earlier, so if_printf could be used */
1837         ifp = &sc->arpcom.ac_if;
1838         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1839
1840         /* Try to reset the chip. */
1841         bnx_reset(sc);
1842
1843         if (bnx_chipinit(sc)) {
1844                 device_printf(dev, "chip initialization failed\n");
1845                 error = ENXIO;
1846                 goto fail;
1847         }
1848
1849         /*
1850          * Get station address
1851          */
1852         error = bnx_get_eaddr(sc, ether_addr);
1853         if (error) {
1854                 device_printf(dev, "failed to read station address\n");
1855                 goto fail;
1856         }
1857
1858         /* XXX */
1859         sc->bnx_tx_ringcnt = 1;
1860
1861         error = bnx_dma_alloc(sc);
1862         if (error)
1863                 goto fail;
1864
1865         /*
1866          * Allocate interrupt
1867          */
1868         sc->bnx_irq_type = pci_alloc_1intr(dev, bnx_msi_enable, &sc->bnx_irq_rid,
1869             &intr_flags);
1870
1871         sc->bnx_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bnx_irq_rid,
1872             intr_flags);
1873         if (sc->bnx_irq == NULL) {
1874                 device_printf(dev, "couldn't map interrupt\n");
1875                 error = ENXIO;
1876                 goto fail;
1877         }
1878
1879         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
1880                 sc->bnx_flags |= BNX_FLAG_ONESHOT_MSI;
1881                 bnx_enable_msi(sc);
1882         }
1883
1884         /* Set default tuneable values. */
1885         sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
1886         sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
1887         sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
1888         sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
1889         sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_INT_DEF;
1890         sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_INT_DEF;
1891
1892         /* Set up ifnet structure */
1893         ifp->if_softc = sc;
1894         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1895         ifp->if_ioctl = bnx_ioctl;
1896         ifp->if_start = bnx_start;
1897 #ifdef IFPOLL_ENABLE
1898         ifp->if_npoll = bnx_npoll;
1899 #endif
1900         ifp->if_watchdog = bnx_watchdog;
1901         ifp->if_init = bnx_init;
1902         ifp->if_mtu = ETHERMTU;
1903         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1904         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1905         ifq_set_ready(&ifp->if_snd);
1906
1907         ifp->if_capabilities |= IFCAP_HWCSUM;
1908         ifp->if_hwassist = BNX_CSUM_FEATURES;
1909         if (sc->bnx_flags & BNX_FLAG_TSO) {
1910                 ifp->if_capabilities |= IFCAP_TSO;
1911                 ifp->if_hwassist |= CSUM_TSO;
1912         }
1913         ifp->if_capenable = ifp->if_capabilities;
1914
1915         /*
1916          * Figure out what sort of media we have by checking the
1917          * hardware config word in the first 32k of NIC internal memory,
1918          * or fall back to examining the EEPROM if necessary.
1919          * Note: on some BCM5700 cards, this value appears to be unset.
1920          * If that's the case, we have to rely on identifying the NIC
1921          * by its PCI subsystem ID, as we do below for the SysKonnect
1922          * SK-9D41.
1923          */
1924         if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
1925                 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1926         } else {
1927                 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1928                                     sizeof(hwcfg))) {
1929                         device_printf(dev, "failed to read EEPROM\n");
1930                         error = ENXIO;
1931                         goto fail;
1932                 }
1933                 hwcfg = ntohl(hwcfg);
1934         }
1935
1936         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1937         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
1938             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1939                 sc->bnx_flags |= BNX_FLAG_TBI;
1940
1941         /* Setup MI MODE */
1942         if (sc->bnx_flags & BNX_FLAG_CPMU)
1943                 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
1944         else
1945                 sc->bnx_mi_mode = BGE_MIMODE_BASE;
1946
1947         /* Setup link status update stuffs */
1948         if (sc->bnx_flags & BNX_FLAG_TBI) {
1949                 sc->bnx_link_upd = bnx_tbi_link_upd;
1950                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1951         } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1952                 sc->bnx_link_upd = bnx_autopoll_link_upd;
1953                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1954         } else {
1955                 sc->bnx_link_upd = bnx_copper_link_upd;
1956                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1957         }
1958
1959         /* Set default PHY address */
1960         sc->bnx_phyno = 1;
1961
1962         /*
1963          * PHY address mapping for various devices.
1964          *
1965          *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
1966          * ---------+-------+-------+-------+-------+
1967          * BCM57XX  |   1   |   X   |   X   |   X   |
1968          * BCM5704  |   1   |   X   |   1   |   X   |
1969          * BCM5717  |   1   |   8   |   2   |   9   |
1970          * BCM5719  |   1   |   8   |   2   |   9   |
1971          * BCM5720  |   1   |   8   |   2   |   9   |
1972          *
1973          * Other addresses may respond but they are not
1974          * IEEE compliant PHYs and should be ignored.
1975          */
1976         if (BNX_IS_5717_PLUS(sc)) {
1977                 int f;
1978
1979                 f = pci_get_function(dev);
1980                 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
1981                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
1982                             BGE_SGDIGSTS_IS_SERDES)
1983                                 sc->bnx_phyno = f + 8;
1984                         else
1985                                 sc->bnx_phyno = f + 1;
1986                 } else {
1987                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
1988                             BGE_CPMU_PHY_STRAP_IS_SERDES)
1989                                 sc->bnx_phyno = f + 8;
1990                         else
1991                                 sc->bnx_phyno = f + 1;
1992                 }
1993         }
1994
1995         if (sc->bnx_flags & BNX_FLAG_TBI) {
1996                 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
1997                     bnx_ifmedia_upd, bnx_ifmedia_sts);
1998                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1999                 ifmedia_add(&sc->bnx_ifmedia,
2000                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2001                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2002                 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
2003                 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
2004         } else {
2005                 struct mii_probe_args mii_args;
2006
2007                 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
2008                 mii_args.mii_probemask = 1 << sc->bnx_phyno;
2009                 mii_args.mii_capmask = capmask;
2010                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2011                 mii_args.mii_priv = mii_priv;
2012
2013                 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
2014                 if (error) {
2015                         device_printf(dev, "MII without any PHY!\n");
2016                         goto fail;
2017                 }
2018         }
2019
2020         /*
2021          * Create sysctl nodes.
2022          */
2023         sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2024         sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2025                                               SYSCTL_STATIC_CHILDREN(_hw),
2026                                               OID_AUTO,
2027                                               device_get_nameunit(dev),
2028                                               CTLFLAG_RD, 0, "");
2029         if (sc->bnx_sysctl_tree == NULL) {
2030                 device_printf(dev, "can't add sysctl node\n");
2031                 error = ENXIO;
2032                 goto fail;
2033         }
2034
2035         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2036                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2037                         OID_AUTO, "rx_coal_ticks",
2038                         CTLTYPE_INT | CTLFLAG_RW,
2039                         sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2040                         "Receive coalescing ticks (usec).");
2041         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2042                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2043                         OID_AUTO, "tx_coal_ticks",
2044                         CTLTYPE_INT | CTLFLAG_RW,
2045                         sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2046                         "Transmit coalescing ticks (usec).");
2047         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2048                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2049                         OID_AUTO, "rx_coal_bds",
2050                         CTLTYPE_INT | CTLFLAG_RW,
2051                         sc, 0, bnx_sysctl_rx_coal_bds, "I",
2052                         "Receive max coalesced BD count.");
2053         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2054                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2055                         OID_AUTO, "tx_coal_bds",
2056                         CTLTYPE_INT | CTLFLAG_RW,
2057                         sc, 0, bnx_sysctl_tx_coal_bds, "I",
2058                         "Transmit max coalesced BD count.");
2059         /*
2060          * A common design characteristic for many Broadcom
2061          * client controllers is that they only support a
2062          * single outstanding DMA read operation on the PCIe
2063          * bus. This means that it will take twice as long to
2064          * fetch a TX frame that is split into header and
2065          * payload buffers as it does to fetch a single,
2066          * contiguous TX frame (2 reads vs. 1 read). For these
2067          * controllers, coalescing buffers to reduce the number
2068          * of memory reads is effective way to get maximum
2069          * performance(about 940Mbps).  Without collapsing TX
2070          * buffers the maximum TCP bulk transfer performance
2071          * is about 850Mbps. However forcing coalescing mbufs
2072          * consumes a lot of CPU cycles, so leave it off by
2073          * default.
2074          */
2075         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2076             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2077             "force_defrag", CTLFLAG_RW, &sc->bnx_force_defrag, 0,
2078             "Force defragment on TX path");
2079
2080         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2081             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2082             "tx_wreg", CTLFLAG_RW, &sc->bnx_tx_ring[0].bnx_tx_wreg, 0,
2083             "# of segments before writing to hardware register");
2084
2085         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2086             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2087             "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2088             sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2089             "Receive max coalesced BD count during interrupt.");
2090         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2091             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2092             "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2093             sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2094             "Transmit max coalesced BD count during interrupt.");
2095
2096 #ifdef BNX_TSO_DEBUG
2097         for (i = 0; i < BNX_TSO_NSTATS; ++i) {
2098                 ksnprintf(desc, sizeof(desc), "tso%d", i + 1);
2099                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2100                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2101                     desc, CTLFLAG_RW, &sc->bnx_tsosegs[i], "");
2102         }
2103 #endif
2104
2105         /*
2106          * Call MI attach routine.
2107          */
2108         ether_ifattach(ifp, ether_addr, NULL);
2109
2110         ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2111
2112 #ifdef IFPOLL_ENABLE
2113         ifpoll_compat_setup(&sc->bnx_npoll,
2114             &sc->bnx_sysctl_ctx, sc->bnx_sysctl_tree,
2115             device_get_unit(dev), ifp->if_serializer);
2116 #endif
2117
2118         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
2119                 if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
2120                         intr_func = bnx_msi_oneshot;
2121                         if (bootverbose)
2122                                 device_printf(dev, "oneshot MSI\n");
2123                 } else {
2124                         intr_func = bnx_msi;
2125                 }
2126         } else {
2127                 intr_func = bnx_intr_legacy;
2128         }
2129         error = bus_setup_intr(dev, sc->bnx_irq, INTR_MPSAFE, intr_func, sc,
2130             &sc->bnx_intrhand, ifp->if_serializer);
2131         if (error) {
2132                 ether_ifdetach(ifp);
2133                 device_printf(dev, "couldn't set up irq\n");
2134                 goto fail;
2135         }
2136
2137         sc->bnx_intr_cpuid = rman_get_cpuid(sc->bnx_irq);
2138         sc->bnx_stat_cpuid = sc->bnx_intr_cpuid;
2139
2140         return(0);
2141 fail:
2142         bnx_detach(dev);
2143         return(error);
2144 }
2145
2146 static int
2147 bnx_detach(device_t dev)
2148 {
2149         struct bnx_softc *sc = device_get_softc(dev);
2150
2151         if (device_is_attached(dev)) {
2152                 struct ifnet *ifp = &sc->arpcom.ac_if;
2153
2154                 lwkt_serialize_enter(ifp->if_serializer);
2155                 bnx_stop(sc);
2156                 bnx_reset(sc);
2157                 bus_teardown_intr(dev, sc->bnx_irq, sc->bnx_intrhand);
2158                 lwkt_serialize_exit(ifp->if_serializer);
2159
2160                 ether_ifdetach(ifp);
2161         }
2162
2163         if (sc->bnx_flags & BNX_FLAG_TBI)
2164                 ifmedia_removeall(&sc->bnx_ifmedia);
2165         if (sc->bnx_miibus)
2166                 device_delete_child(dev, sc->bnx_miibus);
2167         bus_generic_detach(dev);
2168
2169         if (sc->bnx_irq != NULL) {
2170                 bus_release_resource(dev, SYS_RES_IRQ, sc->bnx_irq_rid,
2171                     sc->bnx_irq);
2172         }
2173         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI)
2174                 pci_release_msi(dev);
2175
2176         if (sc->bnx_res != NULL) {
2177                 bus_release_resource(dev, SYS_RES_MEMORY,
2178                     BGE_PCI_BAR0, sc->bnx_res);
2179         }
2180
2181         if (sc->bnx_sysctl_tree != NULL)
2182                 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2183
2184         bnx_dma_free(sc);
2185
2186         return 0;
2187 }
2188
2189 static void
2190 bnx_reset(struct bnx_softc *sc)
2191 {
2192         device_t dev;
2193         uint32_t cachesize, command, pcistate, reset;
2194         void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2195         int i, val = 0;
2196         uint16_t devctl;
2197
2198         dev = sc->bnx_dev;
2199
2200         write_op = bnx_writemem_direct;
2201
2202         /* Save some important PCI state. */
2203         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2204         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2205         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2206
2207         pci_write_config(dev, BGE_PCI_MISC_CTL,
2208             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2209             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2210             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2211
2212         /* Disable fastboot on controllers that support it. */
2213         if (bootverbose)
2214                 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2215         CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2216
2217         /*
2218          * Write the magic number to SRAM at offset 0xB50.
2219          * When firmware finishes its initialization it will
2220          * write ~BGE_MAGIC_NUMBER to the same location.
2221          */
2222         bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2223
2224         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2225
2226         /* XXX: Broadcom Linux driver. */
2227         /* Force PCI-E 1.0a mode */
2228         if (!BNX_IS_57765_PLUS(sc) &&
2229             CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2230             (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2231              BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2232                 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2233                     BGE_PCIE_PHY_TSTCTL_PSCRAM);
2234         }
2235         if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2236                 /* Prevent PCIE link training during global reset */
2237                 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2238                 reset |= (1<<29);
2239         }
2240
2241         /*
2242          * Set GPHY Power Down Override to leave GPHY
2243          * powered up in D0 uninitialized.
2244          */
2245         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2246                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2247
2248         /* Issue global reset */
2249         write_op(sc, BGE_MISC_CFG, reset);
2250
2251         DELAY(1000);
2252
2253         /* XXX: Broadcom Linux driver. */
2254         if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2255                 uint32_t v;
2256
2257                 DELAY(500000); /* wait for link training to complete */
2258                 v = pci_read_config(dev, 0xc4, 4);
2259                 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2260         }
2261
2262         devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2263
2264         /* Disable no snoop and disable relaxed ordering. */
2265         devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2266
2267         /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2268         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2269                 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2270                 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2271         }
2272
2273         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2274             devctl, 2);
2275
2276         /* Clear error status. */
2277         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2278             PCIEM_DEVSTS_CORR_ERR |
2279             PCIEM_DEVSTS_NFATAL_ERR |
2280             PCIEM_DEVSTS_FATAL_ERR |
2281             PCIEM_DEVSTS_UNSUPP_REQ, 2);
2282
2283         /* Reset some of the PCI state that got zapped by reset */
2284         pci_write_config(dev, BGE_PCI_MISC_CTL,
2285             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2286             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2287             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2288         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2289         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2290         write_op(sc, BGE_MISC_CFG, (65 << 1));
2291
2292         /* Enable memory arbiter */
2293         CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2294
2295         /*
2296          * Poll until we see the 1's complement of the magic number.
2297          * This indicates that the firmware initialization is complete.
2298          */
2299         for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2300                 val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2301                 if (val == ~BGE_MAGIC_NUMBER)
2302                         break;
2303                 DELAY(10);
2304         }
2305         if (i == BNX_FIRMWARE_TIMEOUT) {
2306                 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2307                           "timed out, found 0x%08x\n", val);
2308         }
2309
2310         /* BCM57765 A0 needs additional time before accessing. */
2311         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2312                 DELAY(10 * 1000);
2313
2314         /*
2315          * XXX Wait for the value of the PCISTATE register to
2316          * return to its original pre-reset state. This is a
2317          * fairly good indicator of reset completion. If we don't
2318          * wait for the reset to fully complete, trying to read
2319          * from the device's non-PCI registers may yield garbage
2320          * results.
2321          */
2322         for (i = 0; i < BNX_TIMEOUT; i++) {
2323                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2324                         break;
2325                 DELAY(10);
2326         }
2327
2328         /* Fix up byte swapping */
2329         CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2330
2331         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2332
2333         /*
2334          * The 5704 in TBI mode apparently needs some special
2335          * adjustment to insure the SERDES drive level is set
2336          * to 1.2V.
2337          */
2338         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2339             (sc->bnx_flags & BNX_FLAG_TBI)) {
2340                 uint32_t serdescfg;
2341
2342                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2343                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2344                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2345         }
2346
2347         CSR_WRITE_4(sc, BGE_MI_MODE,
2348             sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
2349         DELAY(80);
2350
2351         /* XXX: Broadcom Linux driver. */
2352         if (!BNX_IS_57765_PLUS(sc)) {
2353                 uint32_t v;
2354
2355                 /* Enable Data FIFO protection. */
2356                 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2357                 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2358         }
2359
2360         DELAY(10000);
2361
2362         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2363                 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2364                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2365         }
2366 }
2367
2368 /*
2369  * Frame reception handling. This is called if there's a frame
2370  * on the receive return list.
2371  *
2372  * Note: we have to be able to handle two possibilities here:
2373  * 1) the frame is from the jumbo recieve ring
2374  * 2) the frame is from the standard receive ring
2375  */
2376
2377 static void
2378 bnx_rxeof(struct bnx_softc *sc, uint16_t rx_prod, int count)
2379 {
2380         struct ifnet *ifp;
2381         int stdcnt = 0, jumbocnt = 0;
2382
2383         ifp = &sc->arpcom.ac_if;
2384
2385         while (sc->bnx_rx_saved_considx != rx_prod && count != 0) {
2386                 struct bge_rx_bd        *cur_rx;
2387                 uint32_t                rxidx;
2388                 struct mbuf             *m = NULL;
2389                 uint16_t                vlan_tag = 0;
2390                 int                     have_tag = 0;
2391
2392                 --count;
2393
2394                 cur_rx =
2395             &sc->bnx_ldata.bnx_rx_return_ring[sc->bnx_rx_saved_considx];
2396
2397                 rxidx = cur_rx->bge_idx;
2398                 BNX_INC(sc->bnx_rx_saved_considx, BNX_RETURN_RING_CNT);
2399
2400                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2401                         have_tag = 1;
2402                         vlan_tag = cur_rx->bge_vlan_tag;
2403                 }
2404
2405                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2406                         BNX_INC(sc->bnx_jumbo, BGE_JUMBO_RX_RING_CNT);
2407                         jumbocnt++;
2408
2409                         if (rxidx != sc->bnx_jumbo) {
2410                                 IFNET_STAT_INC(ifp, ierrors, 1);
2411                                 if_printf(ifp, "sw jumbo index(%d) "
2412                                     "and hw jumbo index(%d) mismatch, drop!\n",
2413                                     sc->bnx_jumbo, rxidx);
2414                                 bnx_setup_rxdesc_jumbo(sc, rxidx);
2415                                 continue;
2416                         }
2417
2418                         m = sc->bnx_cdata.bnx_rx_jumbo_chain[rxidx].bnx_mbuf;
2419                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2420                                 IFNET_STAT_INC(ifp, ierrors, 1);
2421                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2422                                 continue;
2423                         }
2424                         if (bnx_newbuf_jumbo(sc, sc->bnx_jumbo, 0)) {
2425                                 IFNET_STAT_INC(ifp, ierrors, 1);
2426                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2427                                 continue;
2428                         }
2429                 } else {
2430                         BNX_INC(sc->bnx_std, BGE_STD_RX_RING_CNT);
2431                         stdcnt++;
2432
2433                         if (rxidx != sc->bnx_std) {
2434                                 IFNET_STAT_INC(ifp, ierrors, 1);
2435                                 if_printf(ifp, "sw std index(%d) "
2436                                     "and hw std index(%d) mismatch, drop!\n",
2437                                     sc->bnx_std, rxidx);
2438                                 bnx_setup_rxdesc_std(sc, rxidx);
2439                                 continue;
2440                         }
2441
2442                         m = sc->bnx_cdata.bnx_rx_std_chain[rxidx].bnx_mbuf;
2443                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2444                                 IFNET_STAT_INC(ifp, ierrors, 1);
2445                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2446                                 continue;
2447                         }
2448                         if (bnx_newbuf_std(sc, sc->bnx_std, 0)) {
2449                                 IFNET_STAT_INC(ifp, ierrors, 1);
2450                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2451                                 continue;
2452                         }
2453                 }
2454
2455                 IFNET_STAT_INC(ifp, ipackets, 1);
2456                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2457                 m->m_pkthdr.rcvif = ifp;
2458
2459                 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2460                     (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2461                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2462                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2463                                 if ((cur_rx->bge_error_flag &
2464                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2465                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2466                         }
2467                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2468                                 m->m_pkthdr.csum_data =
2469                                     cur_rx->bge_tcp_udp_csum;
2470                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2471                                     CSUM_PSEUDO_HDR;
2472                         }
2473                 }
2474
2475                 /*
2476                  * If we received a packet with a vlan tag, pass it
2477                  * to vlan_input() instead of ether_input().
2478                  */
2479                 if (have_tag) {
2480                         m->m_flags |= M_VLANTAG;
2481                         m->m_pkthdr.ether_vlantag = vlan_tag;
2482                 }
2483                 ifp->if_input(ifp, m);
2484         }
2485
2486         bnx_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bnx_rx_saved_considx);
2487         if (stdcnt)
2488                 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
2489         if (jumbocnt)
2490                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
2491 }
2492
2493 static void
2494 bnx_txeof(struct bnx_tx_ring *txr, uint16_t tx_cons)
2495 {
2496         struct ifnet *ifp = &txr->bnx_sc->arpcom.ac_if;
2497
2498         /*
2499          * Go through our tx ring and free mbufs for those
2500          * frames that have been sent.
2501          */
2502         while (txr->bnx_tx_saved_considx != tx_cons) {
2503                 uint32_t idx = 0;
2504
2505                 idx = txr->bnx_tx_saved_considx;
2506                 if (txr->bnx_tx_chain[idx] != NULL) {
2507                         IFNET_STAT_INC(ifp, opackets, 1);
2508                         bus_dmamap_unload(txr->bnx_tx_mtag,
2509                             txr->bnx_tx_dmamap[idx]);
2510                         m_freem(txr->bnx_tx_chain[idx]);
2511                         txr->bnx_tx_chain[idx] = NULL;
2512                 }
2513                 txr->bnx_txcnt--;
2514                 BNX_INC(txr->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2515         }
2516
2517         if ((BGE_TX_RING_CNT - txr->bnx_txcnt) >=
2518             (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2519                 ifq_clr_oactive(&ifp->if_snd);
2520
2521         if (txr->bnx_txcnt == 0)
2522                 ifp->if_timer = 0;
2523
2524         if (!ifq_is_empty(&ifp->if_snd))
2525                 if_devstart(ifp);
2526 }
2527
2528 #ifdef IFPOLL_ENABLE
2529
2530 static void
2531 bnx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2532 {
2533         struct bnx_softc *sc = ifp->if_softc;
2534
2535         ASSERT_SERIALIZED(ifp->if_serializer);
2536
2537         if (info != NULL) {
2538                 int cpuid = sc->bnx_npoll.ifpc_cpuid;
2539
2540                 info->ifpi_rx[cpuid].poll_func = bnx_npoll_compat;
2541                 info->ifpi_rx[cpuid].arg = NULL;
2542                 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
2543
2544                 if (ifp->if_flags & IFF_RUNNING)
2545                         bnx_disable_intr(sc);
2546                 ifq_set_cpuid(&ifp->if_snd, cpuid);
2547         } else {
2548                 if (ifp->if_flags & IFF_RUNNING)
2549                         bnx_enable_intr(sc);
2550                 ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2551         }
2552 }
2553
2554 static void
2555 bnx_npoll_compat(struct ifnet *ifp, void *arg __unused, int cycle)
2556 {
2557         struct bnx_softc *sc = ifp->if_softc;
2558         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
2559         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2560         uint16_t rx_prod, tx_cons;
2561
2562         ASSERT_SERIALIZED(ifp->if_serializer);
2563
2564         if (sc->bnx_npoll.ifpc_stcount-- == 0) {
2565                 sc->bnx_npoll.ifpc_stcount = sc->bnx_npoll.ifpc_stfrac;
2566                 /*
2567                  * Process link state changes.
2568                  */
2569                 bnx_link_poll(sc);
2570         }
2571
2572         sc->bnx_status_tag = sblk->bge_status_tag;
2573
2574         /*
2575          * Use a load fence to ensure that status_tag is saved
2576          * before rx_prod and tx_cons.
2577          */
2578         cpu_lfence();
2579
2580         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2581         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2582
2583         if (sc->bnx_rx_saved_considx != rx_prod)
2584                 bnx_rxeof(sc, rx_prod, cycle);
2585
2586         if (txr->bnx_tx_saved_considx != tx_cons)
2587                 bnx_txeof(txr, tx_cons);
2588
2589         if (sc->bnx_coal_chg)
2590                 bnx_coal_change(sc);
2591 }
2592
2593 #endif  /* IFPOLL_ENABLE */
2594
2595 static void
2596 bnx_intr_legacy(void *xsc)
2597 {
2598         struct bnx_softc *sc = xsc;
2599         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2600
2601         if (sc->bnx_status_tag == sblk->bge_status_tag) {
2602                 uint32_t val;
2603
2604                 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
2605                 if (val & BGE_PCISTAT_INTR_NOTACT)
2606                         return;
2607         }
2608
2609         /*
2610          * NOTE:
2611          * Interrupt will have to be disabled if tagged status
2612          * is used, else interrupt will always be asserted on
2613          * certain chips (at least on BCM5750 AX/BX).
2614          */
2615         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2616
2617         bnx_intr(sc);
2618 }
2619
2620 static void
2621 bnx_msi(void *xsc)
2622 {
2623         struct bnx_softc *sc = xsc;
2624
2625         /* Disable interrupt first */
2626         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2627         bnx_intr(sc);
2628 }
2629
2630 static void
2631 bnx_msi_oneshot(void *xsc)
2632 {
2633         bnx_intr(xsc);
2634 }
2635
2636 static void
2637 bnx_intr(struct bnx_softc *sc)
2638 {
2639         struct ifnet *ifp = &sc->arpcom.ac_if;
2640         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2641         uint16_t rx_prod, tx_cons;
2642         uint32_t status;
2643
2644         sc->bnx_status_tag = sblk->bge_status_tag;
2645         /*
2646          * Use a load fence to ensure that status_tag is saved
2647          * before rx_prod, tx_cons and status.
2648          */
2649         cpu_lfence();
2650
2651         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2652         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2653         status = sblk->bge_status;
2654
2655         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2656                 bnx_link_poll(sc);
2657
2658         if (ifp->if_flags & IFF_RUNNING) {
2659                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
2660
2661                 if (sc->bnx_rx_saved_considx != rx_prod)
2662                         bnx_rxeof(sc, rx_prod, -1);
2663
2664                 if (txr->bnx_tx_saved_considx != tx_cons)
2665                         bnx_txeof(txr, tx_cons);
2666         }
2667
2668         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
2669
2670         if (sc->bnx_coal_chg)
2671                 bnx_coal_change(sc);
2672 }
2673
2674 static void
2675 bnx_tick(void *xsc)
2676 {
2677         struct bnx_softc *sc = xsc;
2678         struct ifnet *ifp = &sc->arpcom.ac_if;
2679
2680         lwkt_serialize_enter(ifp->if_serializer);
2681
2682         KKASSERT(mycpuid == sc->bnx_stat_cpuid);
2683
2684         bnx_stats_update_regs(sc);
2685
2686         if (sc->bnx_flags & BNX_FLAG_TBI) {
2687                 /*
2688                  * Since in TBI mode auto-polling can't be used we should poll
2689                  * link status manually. Here we register pending link event
2690                  * and trigger interrupt.
2691                  */
2692                 sc->bnx_link_evt++;
2693                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2694         } else if (!sc->bnx_link) {
2695                 mii_tick(device_get_softc(sc->bnx_miibus));
2696         }
2697
2698         callout_reset(&sc->bnx_stat_timer, hz, bnx_tick, sc);
2699
2700         lwkt_serialize_exit(ifp->if_serializer);
2701 }
2702
2703 static void
2704 bnx_stats_update_regs(struct bnx_softc *sc)
2705 {
2706         struct ifnet *ifp = &sc->arpcom.ac_if;
2707         struct bge_mac_stats_regs stats;
2708         uint32_t *s;
2709         int i;
2710
2711         s = (uint32_t *)&stats;
2712         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2713                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2714                 s++;
2715         }
2716
2717         IFNET_STAT_SET(ifp, collisions,
2718            (stats.dot3StatsSingleCollisionFrames +
2719            stats.dot3StatsMultipleCollisionFrames +
2720            stats.dot3StatsExcessiveCollisions +
2721            stats.dot3StatsLateCollisions));
2722 }
2723
2724 /*
2725  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2726  * pointers to descriptors.
2727  */
2728 static int
2729 bnx_encap(struct bnx_tx_ring *txr, struct mbuf **m_head0, uint32_t *txidx,
2730     int *segs_used)
2731 {
2732         struct bge_tx_bd *d = NULL;
2733         uint16_t csum_flags = 0, vlan_tag = 0, mss = 0;
2734         bus_dma_segment_t segs[BNX_NSEG_NEW];
2735         bus_dmamap_t map;
2736         int error, maxsegs, nsegs, idx, i;
2737         struct mbuf *m_head = *m_head0, *m_new;
2738
2739         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
2740 #ifdef BNX_TSO_DEBUG
2741                 int tso_nsegs;
2742 #endif
2743
2744                 error = bnx_setup_tso(txr, m_head0, &mss, &csum_flags);
2745                 if (error)
2746                         return error;
2747                 m_head = *m_head0;
2748
2749 #ifdef BNX_TSO_DEBUG
2750                 tso_nsegs = (m_head->m_pkthdr.len /
2751                     m_head->m_pkthdr.tso_segsz) - 1;
2752                 if (tso_nsegs > (BNX_TSO_NSTATS - 1))
2753                         tso_nsegs = BNX_TSO_NSTATS - 1;
2754                 else if (tso_nsegs < 0)
2755                         tso_nsegs = 0;
2756                 txr->sc->bnx_tsosegs[tso_nsegs]++;
2757 #endif
2758         } else if (m_head->m_pkthdr.csum_flags & BNX_CSUM_FEATURES) {
2759                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2760                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2761                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2762                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2763                 if (m_head->m_flags & M_LASTFRAG)
2764                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2765                 else if (m_head->m_flags & M_FRAG)
2766                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2767         }
2768         if (m_head->m_flags & M_VLANTAG) {
2769                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
2770                 vlan_tag = m_head->m_pkthdr.ether_vlantag;
2771         }
2772
2773         idx = *txidx;
2774         map = txr->bnx_tx_dmamap[idx];
2775
2776         maxsegs = (BGE_TX_RING_CNT - txr->bnx_txcnt) - BNX_NSEG_RSVD;
2777         KASSERT(maxsegs >= BNX_NSEG_SPARE,
2778                 ("not enough segments %d", maxsegs));
2779
2780         if (maxsegs > BNX_NSEG_NEW)
2781                 maxsegs = BNX_NSEG_NEW;
2782
2783         /*
2784          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
2785          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
2786          * but when such padded frames employ the bge IP/TCP checksum
2787          * offload, the hardware checksum assist gives incorrect results
2788          * (possibly from incorporating its own padding into the UDP/TCP
2789          * checksum; who knows).  If we pad such runts with zeros, the
2790          * onboard checksum comes out correct.
2791          */
2792         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2793             m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
2794                 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
2795                 if (error)
2796                         goto back;
2797         }
2798
2799         if ((txr->bnx_sc->bnx_flags & BNX_FLAG_SHORTDMA) &&
2800             m_head->m_next != NULL) {
2801                 m_new = bnx_defrag_shortdma(m_head);
2802                 if (m_new == NULL) {
2803                         error = ENOBUFS;
2804                         goto back;
2805                 }
2806                 *m_head0 = m_head = m_new;
2807         }
2808         if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
2809             txr->bnx_sc->bnx_force_defrag && m_head->m_next != NULL) {
2810                 /*
2811                  * Forcefully defragment mbuf chain to overcome hardware
2812                  * limitation which only support a single outstanding
2813                  * DMA read operation.  If it fails, keep moving on using
2814                  * the original mbuf chain.
2815                  */
2816                 m_new = m_defrag(m_head, MB_DONTWAIT);
2817                 if (m_new != NULL)
2818                         *m_head0 = m_head = m_new;
2819         }
2820
2821         error = bus_dmamap_load_mbuf_defrag(txr->bnx_tx_mtag, map,
2822             m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2823         if (error)
2824                 goto back;
2825         *segs_used += nsegs;
2826
2827         m_head = *m_head0;
2828         bus_dmamap_sync(txr->bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2829
2830         for (i = 0; ; i++) {
2831                 d = &txr->bnx_tx_ring[idx];
2832
2833                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2834                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2835                 d->bge_len = segs[i].ds_len;
2836                 d->bge_flags = csum_flags;
2837                 d->bge_vlan_tag = vlan_tag;
2838                 d->bge_mss = mss;
2839
2840                 if (i == nsegs - 1)
2841                         break;
2842                 BNX_INC(idx, BGE_TX_RING_CNT);
2843         }
2844         /* Mark the last segment as end of packet... */
2845         d->bge_flags |= BGE_TXBDFLAG_END;
2846
2847         /*
2848          * Insure that the map for this transmission is placed at
2849          * the array index of the last descriptor in this chain.
2850          */
2851         txr->bnx_tx_dmamap[*txidx] = txr->bnx_tx_dmamap[idx];
2852         txr->bnx_tx_dmamap[idx] = map;
2853         txr->bnx_tx_chain[idx] = m_head;
2854         txr->bnx_txcnt += nsegs;
2855
2856         BNX_INC(idx, BGE_TX_RING_CNT);
2857         *txidx = idx;
2858 back:
2859         if (error) {
2860                 m_freem(*m_head0);
2861                 *m_head0 = NULL;
2862         }
2863         return error;
2864 }
2865
2866 /*
2867  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2868  * to the mbuf data regions directly in the transmit descriptors.
2869  */
2870 static void
2871 bnx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
2872 {
2873         struct bnx_softc *sc = ifp->if_softc;
2874         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
2875         struct mbuf *m_head = NULL;
2876         uint32_t prodidx;
2877         int nsegs = 0;
2878
2879         ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
2880
2881         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
2882                 return;
2883
2884         prodidx = txr->bnx_tx_prodidx;
2885
2886         while (txr->bnx_tx_chain[prodidx] == NULL) {
2887                 /*
2888                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2889                  * descriptors of the end of the ring.  Also make
2890                  * sure there are BGE_NSEG_SPARE descriptors for
2891                  * jumbo buffers' or TSO segments' defragmentation.
2892                  */
2893                 if ((BGE_TX_RING_CNT - txr->bnx_txcnt) <
2894                     (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
2895                         ifq_set_oactive(&ifp->if_snd);
2896                         break;
2897                 }
2898
2899                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2900                 if (m_head == NULL)
2901                         break;
2902
2903                 /*
2904                  * Pack the data into the transmit ring. If we
2905                  * don't have room, set the OACTIVE flag and wait
2906                  * for the NIC to drain the ring.
2907                  */
2908                 if (bnx_encap(txr, &m_head, &prodidx, &nsegs)) {
2909                         ifq_set_oactive(&ifp->if_snd);
2910                         IFNET_STAT_INC(ifp, oerrors, 1);
2911                         break;
2912                 }
2913
2914                 if (nsegs >= txr->bnx_tx_wreg) {
2915                         /* Transmit */
2916                         bnx_writembx(txr->bnx_sc, BGE_MBX_TX_HOST_PROD0_LO,
2917                             prodidx);
2918                         nsegs = 0;
2919                 }
2920
2921                 ETHER_BPF_MTAP(ifp, m_head);
2922
2923                 /*
2924                  * Set a timeout in case the chip goes out to lunch.
2925                  */
2926                 ifp->if_timer = 5;
2927         }
2928
2929         if (nsegs > 0) {
2930                 /* Transmit */
2931                 bnx_writembx(txr->bnx_sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2932         }
2933         txr->bnx_tx_prodidx = prodidx;
2934 }
2935
2936 static void
2937 bnx_init(void *xsc)
2938 {
2939         struct bnx_softc *sc = xsc;
2940         struct ifnet *ifp = &sc->arpcom.ac_if;
2941         uint16_t *m;
2942         uint32_t mode;
2943         int i;
2944
2945         ASSERT_SERIALIZED(ifp->if_serializer);
2946
2947         /* Cancel pending I/O and flush buffers. */
2948         bnx_stop(sc);
2949         bnx_reset(sc);
2950         bnx_chipinit(sc);
2951
2952         /*
2953          * Init the various state machines, ring
2954          * control blocks and firmware.
2955          */
2956         if (bnx_blockinit(sc)) {
2957                 if_printf(ifp, "initialization failure\n");
2958                 bnx_stop(sc);
2959                 return;
2960         }
2961
2962         /* Specify MTU. */
2963         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2964             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2965
2966         /* Load our MAC address. */
2967         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2968         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2969         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2970
2971         /* Enable or disable promiscuous mode as needed. */
2972         bnx_setpromisc(sc);
2973
2974         /* Program multicast filter. */
2975         bnx_setmulti(sc);
2976
2977         /* Init RX ring. */
2978         if (bnx_init_rx_ring_std(sc)) {
2979                 if_printf(ifp, "RX ring initialization failed\n");
2980                 bnx_stop(sc);
2981                 return;
2982         }
2983
2984         /* Init jumbo RX ring. */
2985         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
2986                 if (bnx_init_rx_ring_jumbo(sc)) {
2987                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
2988                         bnx_stop(sc);
2989                         return;
2990                 }
2991         }
2992
2993         /* Init our RX return ring index */
2994         sc->bnx_rx_saved_considx = 0;
2995
2996         /* Init TX ring. */
2997         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
2998                 bnx_init_tx_ring(&sc->bnx_tx_ring[i]);
2999
3000         /* Enable TX MAC state machine lockup fix. */
3001         mode = CSR_READ_4(sc, BGE_TX_MODE);
3002         mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3003         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
3004             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
3005                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3006                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
3007                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3008         }
3009         /* Turn on transmitter */
3010         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3011
3012         /* Turn on receiver */
3013         BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3014
3015         /*
3016          * Set the number of good frames to receive after RX MBUF
3017          * Low Watermark has been reached.  After the RX MAC receives
3018          * this number of frames, it will drop subsequent incoming
3019          * frames until the MBUF High Watermark is reached.
3020          */
3021         if (BNX_IS_57765_FAMILY(sc))
3022                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
3023         else
3024                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3025
3026         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
3027                 if (bootverbose) {
3028                         if_printf(ifp, "MSI_MODE: %#x\n",
3029                             CSR_READ_4(sc, BGE_MSI_MODE));
3030                 }
3031         }
3032
3033         /* Tell firmware we're alive. */
3034         BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3035
3036         /* Enable host interrupts if polling(4) is not enabled. */
3037         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3038 #ifdef IFPOLL_ENABLE
3039         if (ifp->if_flags & IFF_NPOLLING)
3040                 bnx_disable_intr(sc);
3041         else
3042 #endif
3043         bnx_enable_intr(sc);
3044
3045         bnx_ifmedia_upd(ifp);
3046
3047         ifp->if_flags |= IFF_RUNNING;
3048         ifq_clr_oactive(&ifp->if_snd);
3049
3050         callout_reset_bycpu(&sc->bnx_stat_timer, hz, bnx_tick, sc,
3051             sc->bnx_stat_cpuid);
3052 }
3053
3054 /*
3055  * Set media options.
3056  */
3057 static int
3058 bnx_ifmedia_upd(struct ifnet *ifp)
3059 {
3060         struct bnx_softc *sc = ifp->if_softc;
3061
3062         /* If this is a 1000baseX NIC, enable the TBI port. */
3063         if (sc->bnx_flags & BNX_FLAG_TBI) {
3064                 struct ifmedia *ifm = &sc->bnx_ifmedia;
3065
3066                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3067                         return(EINVAL);
3068
3069                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3070                 case IFM_AUTO:
3071                         break;
3072
3073                 case IFM_1000_SX:
3074                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3075                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3076                                     BGE_MACMODE_HALF_DUPLEX);
3077                         } else {
3078                                 BNX_SETBIT(sc, BGE_MAC_MODE,
3079                                     BGE_MACMODE_HALF_DUPLEX);
3080                         }
3081                         break;
3082                 default:
3083                         return(EINVAL);
3084                 }
3085         } else {
3086                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3087
3088                 sc->bnx_link_evt++;
3089                 sc->bnx_link = 0;
3090                 if (mii->mii_instance) {
3091                         struct mii_softc *miisc;
3092
3093                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3094                                 mii_phy_reset(miisc);
3095                 }
3096                 mii_mediachg(mii);
3097
3098                 /*
3099                  * Force an interrupt so that we will call bnx_link_upd
3100                  * if needed and clear any pending link state attention.
3101                  * Without this we are not getting any further interrupts
3102                  * for link state changes and thus will not UP the link and
3103                  * not be able to send in bnx_start.  The only way to get
3104                  * things working was to receive a packet and get an RX
3105                  * intr.
3106                  *
3107                  * bnx_tick should help for fiber cards and we might not
3108                  * need to do this here if BNX_FLAG_TBI is set but as
3109                  * we poll for fiber anyway it should not harm.
3110                  */
3111                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3112         }
3113         return(0);
3114 }
3115
3116 /*
3117  * Report current media status.
3118  */
3119 static void
3120 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3121 {
3122         struct bnx_softc *sc = ifp->if_softc;
3123
3124         if (sc->bnx_flags & BNX_FLAG_TBI) {
3125                 ifmr->ifm_status = IFM_AVALID;
3126                 ifmr->ifm_active = IFM_ETHER;
3127                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3128                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3129                         ifmr->ifm_status |= IFM_ACTIVE;
3130                 } else {
3131                         ifmr->ifm_active |= IFM_NONE;
3132                         return;
3133                 }
3134
3135                 ifmr->ifm_active |= IFM_1000_SX;
3136                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3137                         ifmr->ifm_active |= IFM_HDX;
3138                 else
3139                         ifmr->ifm_active |= IFM_FDX;
3140         } else {
3141                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3142
3143                 mii_pollstat(mii);
3144                 ifmr->ifm_active = mii->mii_media_active;
3145                 ifmr->ifm_status = mii->mii_media_status;
3146         }
3147 }
3148
3149 static int
3150 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3151 {
3152         struct bnx_softc *sc = ifp->if_softc;
3153         struct ifreq *ifr = (struct ifreq *)data;
3154         int mask, error = 0;
3155
3156         ASSERT_SERIALIZED(ifp->if_serializer);
3157
3158         switch (command) {
3159         case SIOCSIFMTU:
3160                 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3161                     (BNX_IS_JUMBO_CAPABLE(sc) &&
3162                      ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3163                         error = EINVAL;
3164                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3165                         ifp->if_mtu = ifr->ifr_mtu;
3166                         if (ifp->if_flags & IFF_RUNNING)
3167                                 bnx_init(sc);
3168                 }
3169                 break;
3170         case SIOCSIFFLAGS:
3171                 if (ifp->if_flags & IFF_UP) {
3172                         if (ifp->if_flags & IFF_RUNNING) {
3173                                 mask = ifp->if_flags ^ sc->bnx_if_flags;
3174
3175                                 /*
3176                                  * If only the state of the PROMISC flag
3177                                  * changed, then just use the 'set promisc
3178                                  * mode' command instead of reinitializing
3179                                  * the entire NIC. Doing a full re-init
3180                                  * means reloading the firmware and waiting
3181                                  * for it to start up, which may take a
3182                                  * second or two.  Similarly for ALLMULTI.
3183                                  */
3184                                 if (mask & IFF_PROMISC)
3185                                         bnx_setpromisc(sc);
3186                                 if (mask & IFF_ALLMULTI)
3187                                         bnx_setmulti(sc);
3188                         } else {
3189                                 bnx_init(sc);
3190                         }
3191                 } else if (ifp->if_flags & IFF_RUNNING) {
3192                         bnx_stop(sc);
3193                 }
3194                 sc->bnx_if_flags = ifp->if_flags;
3195                 break;
3196         case SIOCADDMULTI:
3197         case SIOCDELMULTI:
3198                 if (ifp->if_flags & IFF_RUNNING)
3199                         bnx_setmulti(sc);
3200                 break;
3201         case SIOCSIFMEDIA:
3202         case SIOCGIFMEDIA:
3203                 if (sc->bnx_flags & BNX_FLAG_TBI) {
3204                         error = ifmedia_ioctl(ifp, ifr,
3205                             &sc->bnx_ifmedia, command);
3206                 } else {
3207                         struct mii_data *mii;
3208
3209                         mii = device_get_softc(sc->bnx_miibus);
3210                         error = ifmedia_ioctl(ifp, ifr,
3211                                               &mii->mii_media, command);
3212                 }
3213                 break;
3214         case SIOCSIFCAP:
3215                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3216                 if (mask & IFCAP_HWCSUM) {
3217                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3218                         if (ifp->if_capenable & IFCAP_TXCSUM)
3219                                 ifp->if_hwassist |= BNX_CSUM_FEATURES;
3220                         else
3221                                 ifp->if_hwassist &= ~BNX_CSUM_FEATURES;
3222                 }
3223                 if (mask & IFCAP_TSO) {
3224                         ifp->if_capenable ^= (mask & IFCAP_TSO);
3225                         if (ifp->if_capenable & IFCAP_TSO)
3226                                 ifp->if_hwassist |= CSUM_TSO;
3227                         else
3228                                 ifp->if_hwassist &= ~CSUM_TSO;
3229                 }
3230                 break;
3231         default:
3232                 error = ether_ioctl(ifp, command, data);
3233                 break;
3234         }
3235         return error;
3236 }
3237
3238 static void
3239 bnx_watchdog(struct ifnet *ifp)
3240 {
3241         struct bnx_softc *sc = ifp->if_softc;
3242
3243         if_printf(ifp, "watchdog timeout -- resetting\n");
3244
3245         bnx_init(sc);
3246
3247         IFNET_STAT_INC(ifp, oerrors, 1);
3248
3249         if (!ifq_is_empty(&ifp->if_snd))
3250                 if_devstart(ifp);
3251 }
3252
3253 /*
3254  * Stop the adapter and free any mbufs allocated to the
3255  * RX and TX lists.
3256  */
3257 static void
3258 bnx_stop(struct bnx_softc *sc)
3259 {
3260         struct ifnet *ifp = &sc->arpcom.ac_if;
3261         int i;
3262
3263         ASSERT_SERIALIZED(ifp->if_serializer);
3264
3265         callout_stop(&sc->bnx_stat_timer);
3266
3267         /*
3268          * Disable all of the receiver blocks
3269          */
3270         bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3271         bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3272         bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3273         bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3274         bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3275         bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3276
3277         /*
3278          * Disable all of the transmit blocks
3279          */
3280         bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3281         bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3282         bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3283         bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3284         bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3285         bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3286
3287         /*
3288          * Shut down all of the memory managers and related
3289          * state machines.
3290          */
3291         bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3292         bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3293         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3294         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3295
3296         /* Disable host interrupts. */
3297         bnx_disable_intr(sc);
3298
3299         /*
3300          * Tell firmware we're shutting down.
3301          */
3302         BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3303
3304         /* Free the RX lists. */
3305         bnx_free_rx_ring_std(sc);
3306
3307         /* Free jumbo RX list. */
3308         if (BNX_IS_JUMBO_CAPABLE(sc))
3309                 bnx_free_rx_ring_jumbo(sc);
3310
3311         /* Free TX buffers. */
3312         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3313                 bnx_free_tx_ring(&sc->bnx_tx_ring[i]);
3314
3315         sc->bnx_status_tag = 0;
3316         sc->bnx_link = 0;
3317         sc->bnx_coal_chg = 0;
3318
3319         ifp->if_flags &= ~IFF_RUNNING;
3320         ifq_clr_oactive(&ifp->if_snd);
3321         ifp->if_timer = 0;
3322 }
3323
3324 /*
3325  * Stop all chip I/O so that the kernel's probe routines don't
3326  * get confused by errant DMAs when rebooting.
3327  */
3328 static void
3329 bnx_shutdown(device_t dev)
3330 {
3331         struct bnx_softc *sc = device_get_softc(dev);
3332         struct ifnet *ifp = &sc->arpcom.ac_if;
3333
3334         lwkt_serialize_enter(ifp->if_serializer);
3335         bnx_stop(sc);
3336         bnx_reset(sc);
3337         lwkt_serialize_exit(ifp->if_serializer);
3338 }
3339
3340 static int
3341 bnx_suspend(device_t dev)
3342 {
3343         struct bnx_softc *sc = device_get_softc(dev);
3344         struct ifnet *ifp = &sc->arpcom.ac_if;
3345
3346         lwkt_serialize_enter(ifp->if_serializer);
3347         bnx_stop(sc);
3348         lwkt_serialize_exit(ifp->if_serializer);
3349
3350         return 0;
3351 }
3352
3353 static int
3354 bnx_resume(device_t dev)
3355 {
3356         struct bnx_softc *sc = device_get_softc(dev);
3357         struct ifnet *ifp = &sc->arpcom.ac_if;
3358
3359         lwkt_serialize_enter(ifp->if_serializer);
3360
3361         if (ifp->if_flags & IFF_UP) {
3362                 bnx_init(sc);
3363
3364                 if (!ifq_is_empty(&ifp->if_snd))
3365                         if_devstart(ifp);
3366         }
3367
3368         lwkt_serialize_exit(ifp->if_serializer);
3369
3370         return 0;
3371 }
3372
3373 static void
3374 bnx_setpromisc(struct bnx_softc *sc)
3375 {
3376         struct ifnet *ifp = &sc->arpcom.ac_if;
3377
3378         if (ifp->if_flags & IFF_PROMISC)
3379                 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3380         else
3381                 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3382 }
3383
3384 static void
3385 bnx_dma_free(struct bnx_softc *sc)
3386 {
3387         int i;
3388
3389         /* Destroy RX mbuf DMA stuffs. */
3390         if (sc->bnx_cdata.bnx_rx_mtag != NULL) {
3391                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3392                         bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3393                             sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3394                 }
3395                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3396                                    sc->bnx_cdata.bnx_rx_tmpmap);
3397                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3398         }
3399
3400         /* Destroy TX rings */
3401         if (sc->bnx_tx_ring != NULL) {
3402                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3403                         bnx_destroy_tx_ring(&sc->bnx_tx_ring[i]);
3404                 kfree(sc->bnx_tx_ring, M_DEVBUF);
3405         }
3406
3407         /* Destroy standard RX ring */
3408         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_std_ring_tag,
3409                            sc->bnx_cdata.bnx_rx_std_ring_map,
3410                            sc->bnx_ldata.bnx_rx_std_ring);
3411
3412         if (BNX_IS_JUMBO_CAPABLE(sc))
3413                 bnx_free_jumbo_mem(sc);
3414
3415         /* Destroy RX return ring */
3416         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_return_ring_tag,
3417                            sc->bnx_cdata.bnx_rx_return_ring_map,
3418                            sc->bnx_ldata.bnx_rx_return_ring);
3419
3420         /* Destroy status block */
3421         bnx_dma_block_free(sc->bnx_cdata.bnx_status_tag,
3422                            sc->bnx_cdata.bnx_status_map,
3423                            sc->bnx_ldata.bnx_status_block);
3424
3425         /* Destroy the parent tag */
3426         if (sc->bnx_cdata.bnx_parent_tag != NULL)
3427                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
3428 }
3429
3430 static int
3431 bnx_dma_alloc(struct bnx_softc *sc)
3432 {
3433         struct ifnet *ifp = &sc->arpcom.ac_if;
3434         int i, error;
3435
3436         /*
3437          * Allocate the parent bus DMA tag appropriate for PCI.
3438          *
3439          * All of the NetExtreme/NetLink controllers have 4GB boundary
3440          * DMA bug.
3441          * Whenever an address crosses a multiple of the 4GB boundary
3442          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3443          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3444          * state machine will lockup and cause the device to hang.
3445          */
3446         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3447                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3448                                    NULL, NULL,
3449                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3450                                    BUS_SPACE_MAXSIZE_32BIT,
3451                                    0, &sc->bnx_cdata.bnx_parent_tag);
3452         if (error) {
3453                 if_printf(ifp, "could not allocate parent dma tag\n");
3454                 return error;
3455         }
3456
3457         /*
3458          * Create DMA tag and maps for RX mbufs.
3459          */
3460         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3461                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3462                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3463                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3464                                    &sc->bnx_cdata.bnx_rx_mtag);
3465         if (error) {
3466                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3467                 return error;
3468         }
3469
3470         error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3471                                   BUS_DMA_WAITOK, &sc->bnx_cdata.bnx_rx_tmpmap);
3472         if (error) {
3473                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3474                 sc->bnx_cdata.bnx_rx_mtag = NULL;
3475                 return error;
3476         }
3477
3478         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3479                 error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3480                                           BUS_DMA_WAITOK,
3481                                           &sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3482                 if (error) {
3483                         int j;
3484
3485                         for (j = 0; j < i; ++j) {
3486                                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3487                                         sc->bnx_cdata.bnx_rx_std_dmamap[j]);
3488                         }
3489                         bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3490                         sc->bnx_cdata.bnx_rx_mtag = NULL;
3491
3492                         if_printf(ifp, "could not create DMA map for RX\n");
3493                         return error;
3494                 }
3495         }
3496
3497         /*
3498          * Create DMA stuffs for standard RX ring.
3499          */
3500         error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3501                                     &sc->bnx_cdata.bnx_rx_std_ring_tag,
3502                                     &sc->bnx_cdata.bnx_rx_std_ring_map,
3503                                     (void *)&sc->bnx_ldata.bnx_rx_std_ring,
3504                                     &sc->bnx_ldata.bnx_rx_std_ring_paddr);
3505         if (error) {
3506                 if_printf(ifp, "could not create std RX ring\n");
3507                 return error;
3508         }
3509
3510         /*
3511          * Create jumbo buffer pool.
3512          */
3513         if (BNX_IS_JUMBO_CAPABLE(sc)) {
3514                 error = bnx_alloc_jumbo_mem(sc);
3515                 if (error) {
3516                         if_printf(ifp, "could not create jumbo buffer pool\n");
3517                         return error;
3518                 }
3519         }
3520
3521         /*
3522          * Create DMA stuffs for RX return ring.
3523          */
3524         error = bnx_dma_block_alloc(sc,
3525             BGE_RX_RTN_RING_SZ(BNX_RETURN_RING_CNT),
3526             &sc->bnx_cdata.bnx_rx_return_ring_tag,
3527             &sc->bnx_cdata.bnx_rx_return_ring_map,
3528             (void *)&sc->bnx_ldata.bnx_rx_return_ring,
3529             &sc->bnx_ldata.bnx_rx_return_ring_paddr);
3530         if (error) {
3531                 if_printf(ifp, "could not create RX ret ring\n");
3532                 return error;
3533         }
3534
3535         /*
3536          * Create DMA stuffs for status block.
3537          */
3538         error = bnx_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3539                                     &sc->bnx_cdata.bnx_status_tag,
3540                                     &sc->bnx_cdata.bnx_status_map,
3541                                     (void *)&sc->bnx_ldata.bnx_status_block,
3542                                     &sc->bnx_ldata.bnx_status_block_paddr);
3543         if (error) {
3544                 if_printf(ifp, "could not create status block\n");
3545                 return error;
3546         }
3547
3548         sc->bnx_tx_ring = kmalloc_cachealign(
3549             sizeof(struct bnx_tx_ring) * sc->bnx_tx_ringcnt, M_DEVBUF,
3550             M_WAITOK | M_ZERO);
3551         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3552                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3553
3554                 txr->bnx_sc = sc;
3555                 error = bnx_create_tx_ring(txr);
3556                 if (error) {
3557                         device_printf(sc->bnx_dev,
3558                             "can't create %dth tx ring\n", i);
3559                         return error;
3560                 }
3561         }
3562
3563         return 0;
3564 }
3565
3566 static int
3567 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3568                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3569 {
3570         bus_dmamem_t dmem;
3571         int error;
3572
3573         error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0,
3574                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3575                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3576         if (error)
3577                 return error;
3578
3579         *tag = dmem.dmem_tag;
3580         *map = dmem.dmem_map;
3581         *addr = dmem.dmem_addr;
3582         *paddr = dmem.dmem_busaddr;
3583
3584         return 0;
3585 }
3586
3587 static void
3588 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3589 {
3590         if (tag != NULL) {
3591                 bus_dmamap_unload(tag, map);
3592                 bus_dmamem_free(tag, addr, map);
3593                 bus_dma_tag_destroy(tag);
3594         }
3595 }
3596
3597 static void
3598 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status)
3599 {
3600         struct ifnet *ifp = &sc->arpcom.ac_if;
3601
3602 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3603
3604         /*
3605          * Sometimes PCS encoding errors are detected in
3606          * TBI mode (on fiber NICs), and for some reason
3607          * the chip will signal them as link changes.
3608          * If we get a link change event, but the 'PCS
3609          * encoding error' bit in the MAC status register
3610          * is set, don't bother doing a link check.
3611          * This avoids spurious "gigabit link up" messages
3612          * that sometimes appear on fiber NICs during
3613          * periods of heavy traffic.
3614          */
3615         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3616                 if (!sc->bnx_link) {
3617                         sc->bnx_link++;
3618                         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) {
3619                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3620                                     BGE_MACMODE_TBI_SEND_CFGS);
3621                         }
3622                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3623
3624                         if (bootverbose)
3625                                 if_printf(ifp, "link UP\n");
3626
3627                         ifp->if_link_state = LINK_STATE_UP;
3628                         if_link_state_change(ifp);
3629                 }
3630         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3631                 if (sc->bnx_link) {
3632                         sc->bnx_link = 0;
3633
3634                         if (bootverbose)
3635                                 if_printf(ifp, "link DOWN\n");
3636
3637                         ifp->if_link_state = LINK_STATE_DOWN;
3638                         if_link_state_change(ifp);
3639                 }
3640         }
3641
3642 #undef PCS_ENCODE_ERR
3643
3644         /* Clear the attention. */
3645         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3646             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3647             BGE_MACSTAT_LINK_CHANGED);
3648 }
3649
3650 static void
3651 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3652 {
3653         struct ifnet *ifp = &sc->arpcom.ac_if;
3654         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3655
3656         mii_pollstat(mii);
3657         bnx_miibus_statchg(sc->bnx_dev);
3658
3659         if (bootverbose) {
3660                 if (sc->bnx_link)
3661                         if_printf(ifp, "link UP\n");
3662                 else
3663                         if_printf(ifp, "link DOWN\n");
3664         }
3665
3666         /* Clear the attention. */
3667         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3668             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3669             BGE_MACSTAT_LINK_CHANGED);
3670 }
3671
3672 static void
3673 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3674 {
3675         struct ifnet *ifp = &sc->arpcom.ac_if;
3676         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3677
3678         mii_pollstat(mii);
3679
3680         if (!sc->bnx_link &&
3681             (mii->mii_media_status & IFM_ACTIVE) &&
3682             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3683                 sc->bnx_link++;
3684                 if (bootverbose)
3685                         if_printf(ifp, "link UP\n");
3686         } else if (sc->bnx_link &&
3687             (!(mii->mii_media_status & IFM_ACTIVE) ||
3688             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3689                 sc->bnx_link = 0;
3690                 if (bootverbose)
3691                         if_printf(ifp, "link DOWN\n");
3692         }
3693
3694         /* Clear the attention. */
3695         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3696             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3697             BGE_MACSTAT_LINK_CHANGED);
3698 }
3699
3700 static int
3701 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3702 {
3703         struct bnx_softc *sc = arg1;
3704
3705         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3706             &sc->bnx_rx_coal_ticks,
3707             BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX,
3708             BNX_RX_COAL_TICKS_CHG);
3709 }
3710
3711 static int
3712 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3713 {
3714         struct bnx_softc *sc = arg1;
3715
3716         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3717             &sc->bnx_tx_coal_ticks,
3718             BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX,
3719             BNX_TX_COAL_TICKS_CHG);
3720 }
3721
3722 static int
3723 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
3724 {
3725         struct bnx_softc *sc = arg1;
3726
3727         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3728             &sc->bnx_rx_coal_bds,
3729             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3730             BNX_RX_COAL_BDS_CHG);
3731 }
3732
3733 static int
3734 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
3735 {
3736         struct bnx_softc *sc = arg1;
3737
3738         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3739             &sc->bnx_tx_coal_bds,
3740             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3741             BNX_TX_COAL_BDS_CHG);
3742 }
3743
3744 static int
3745 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3746 {
3747         struct bnx_softc *sc = arg1;
3748
3749         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3750             &sc->bnx_rx_coal_bds_int,
3751             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3752             BNX_RX_COAL_BDS_INT_CHG);
3753 }
3754
3755 static int
3756 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3757 {
3758         struct bnx_softc *sc = arg1;
3759
3760         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3761             &sc->bnx_tx_coal_bds_int,
3762             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3763             BNX_TX_COAL_BDS_INT_CHG);
3764 }
3765
3766 static int
3767 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3768     int coal_min, int coal_max, uint32_t coal_chg_mask)
3769 {
3770         struct bnx_softc *sc = arg1;
3771         struct ifnet *ifp = &sc->arpcom.ac_if;
3772         int error = 0, v;
3773
3774         lwkt_serialize_enter(ifp->if_serializer);
3775
3776         v = *coal;
3777         error = sysctl_handle_int(oidp, &v, 0, req);
3778         if (!error && req->newptr != NULL) {
3779                 if (v < coal_min || v > coal_max) {
3780                         error = EINVAL;
3781                 } else {
3782                         *coal = v;
3783                         sc->bnx_coal_chg |= coal_chg_mask;
3784                 }
3785         }
3786
3787         lwkt_serialize_exit(ifp->if_serializer);
3788         return error;
3789 }
3790
3791 static void
3792 bnx_coal_change(struct bnx_softc *sc)
3793 {
3794         struct ifnet *ifp = &sc->arpcom.ac_if;
3795
3796         ASSERT_SERIALIZED(ifp->if_serializer);
3797
3798         if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) {
3799                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3800                             sc->bnx_rx_coal_ticks);
3801                 DELAY(10);
3802                 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3803
3804                 if (bootverbose) {
3805                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3806                                   sc->bnx_rx_coal_ticks);
3807                 }
3808         }
3809
3810         if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) {
3811                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3812                             sc->bnx_tx_coal_ticks);
3813                 DELAY(10);
3814                 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3815
3816                 if (bootverbose) {
3817                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3818                                   sc->bnx_tx_coal_ticks);
3819                 }
3820         }
3821
3822         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) {
3823                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3824                             sc->bnx_rx_coal_bds);
3825                 DELAY(10);
3826                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3827
3828                 if (bootverbose) {
3829                         if_printf(ifp, "rx_coal_bds -> %u\n",
3830                                   sc->bnx_rx_coal_bds);
3831                 }
3832         }
3833
3834         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) {
3835                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3836                             sc->bnx_tx_coal_bds);
3837                 DELAY(10);
3838                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3839
3840                 if (bootverbose) {
3841                         if_printf(ifp, "tx_coal_bds -> %u\n",
3842                                   sc->bnx_tx_coal_bds);
3843                 }
3844         }
3845
3846         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) {
3847                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
3848                     sc->bnx_rx_coal_bds_int);
3849                 DELAY(10);
3850                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
3851
3852                 if (bootverbose) {
3853                         if_printf(ifp, "rx_coal_bds_int -> %u\n",
3854                             sc->bnx_rx_coal_bds_int);
3855                 }
3856         }
3857
3858         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) {
3859                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
3860                     sc->bnx_tx_coal_bds_int);
3861                 DELAY(10);
3862                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
3863
3864                 if (bootverbose) {
3865                         if_printf(ifp, "tx_coal_bds_int -> %u\n",
3866                             sc->bnx_tx_coal_bds_int);
3867                 }
3868         }
3869
3870         sc->bnx_coal_chg = 0;
3871 }
3872
3873 static void
3874 bnx_intr_check(void *xsc)
3875 {
3876         struct bnx_softc *sc = xsc;
3877         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
3878         struct ifnet *ifp = &sc->arpcom.ac_if;
3879         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
3880
3881         lwkt_serialize_enter(ifp->if_serializer);
3882
3883         KKASSERT(mycpuid == sc->bnx_intr_cpuid);
3884
3885         if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
3886                 lwkt_serialize_exit(ifp->if_serializer);
3887                 return;
3888         }
3889
3890         if (sblk->bge_idx[0].bge_rx_prod_idx != sc->bnx_rx_saved_considx ||
3891             sblk->bge_idx[0].bge_tx_cons_idx != txr->bnx_tx_saved_considx) {
3892                 if (sc->bnx_rx_check_considx == sc->bnx_rx_saved_considx &&
3893                     sc->bnx_tx_check_considx == txr->bnx_tx_saved_considx) {
3894                         if (!sc->bnx_intr_maylose) {
3895                                 sc->bnx_intr_maylose = TRUE;
3896                                 goto done;
3897                         }
3898                         if (bootverbose)
3899                                 if_printf(ifp, "lost interrupt\n");
3900                         bnx_msi(sc);
3901                 }
3902         }
3903         sc->bnx_intr_maylose = FALSE;
3904         sc->bnx_rx_check_considx = sc->bnx_rx_saved_considx;
3905         sc->bnx_tx_check_considx = txr->bnx_tx_saved_considx;
3906
3907 done:
3908         callout_reset(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
3909             bnx_intr_check, sc);
3910         lwkt_serialize_exit(ifp->if_serializer);
3911 }
3912
3913 static void
3914 bnx_enable_intr(struct bnx_softc *sc)
3915 {
3916         struct ifnet *ifp = &sc->arpcom.ac_if;
3917
3918         lwkt_serialize_handler_enable(ifp->if_serializer);
3919
3920         /*
3921          * Enable interrupt.
3922          */
3923         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3924         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
3925                 /* XXX Linux driver */
3926                 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3927         }
3928
3929         /*
3930          * Unmask the interrupt when we stop polling.
3931          */
3932         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3933             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3934
3935         /*
3936          * Trigger another interrupt, since above writing
3937          * to interrupt mailbox0 may acknowledge pending
3938          * interrupt.
3939          */
3940         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3941
3942         if (sc->bnx_flags & BNX_FLAG_STATUSTAG_BUG) {
3943                 sc->bnx_intr_maylose = FALSE;
3944                 sc->bnx_rx_check_considx = 0;
3945                 sc->bnx_tx_check_considx = 0;
3946
3947                 if (bootverbose)
3948                         if_printf(ifp, "status tag bug workaround\n");
3949
3950                 /* 10ms check interval */
3951                 callout_reset_bycpu(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
3952                     bnx_intr_check, sc, sc->bnx_intr_cpuid);
3953         }
3954 }
3955
3956 static void
3957 bnx_disable_intr(struct bnx_softc *sc)
3958 {
3959         struct ifnet *ifp = &sc->arpcom.ac_if;
3960
3961         /*
3962          * Mask the interrupt when we start polling.
3963          */
3964         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3965             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3966
3967         /*
3968          * Acknowledge possible asserted interrupt.
3969          */
3970         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3971
3972         callout_stop(&sc->bnx_intr_timer);
3973         sc->bnx_intr_maylose = FALSE;
3974         sc->bnx_rx_check_considx = 0;
3975         sc->bnx_tx_check_considx = 0;
3976
3977         sc->bnx_npoll.ifpc_stcount = 0;
3978
3979         lwkt_serialize_handler_disable(ifp->if_serializer);
3980 }
3981
3982 static int
3983 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[])
3984 {
3985         uint32_t mac_addr;
3986         int ret = 1;
3987
3988         mac_addr = bnx_readmem_ind(sc, 0x0c14);
3989         if ((mac_addr >> 16) == 0x484b) {
3990                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
3991                 ether_addr[1] = (uint8_t)mac_addr;
3992                 mac_addr = bnx_readmem_ind(sc, 0x0c18);
3993                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
3994                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
3995                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
3996                 ether_addr[5] = (uint8_t)mac_addr;
3997                 ret = 0;
3998         }
3999         return ret;
4000 }
4001
4002 static int
4003 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[])
4004 {
4005         int mac_offset = BGE_EE_MAC_OFFSET;
4006
4007         if (BNX_IS_5717_PLUS(sc)) {
4008                 int f;
4009
4010                 f = pci_get_function(sc->bnx_dev);
4011                 if (f & 1)
4012                         mac_offset = BGE_EE_MAC_OFFSET_5717;
4013                 if (f > 1)
4014                         mac_offset += BGE_EE_MAC_OFFSET_5717_OFF;
4015         }
4016
4017         return bnx_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4018 }
4019
4020 static int
4021 bnx_get_eaddr_eeprom(struct bnx_softc *sc, uint8_t ether_addr[])
4022 {
4023         if (sc->bnx_flags & BNX_FLAG_NO_EEPROM)
4024                 return 1;
4025
4026         return bnx_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4027                                ETHER_ADDR_LEN);
4028 }
4029
4030 static int
4031 bnx_get_eaddr(struct bnx_softc *sc, uint8_t eaddr[])
4032 {
4033         static const bnx_eaddr_fcn_t bnx_eaddr_funcs[] = {
4034                 /* NOTE: Order is critical */
4035                 bnx_get_eaddr_mem,
4036                 bnx_get_eaddr_nvram,
4037                 bnx_get_eaddr_eeprom,
4038                 NULL
4039         };
4040         const bnx_eaddr_fcn_t *func;
4041
4042         for (func = bnx_eaddr_funcs; *func != NULL; ++func) {
4043                 if ((*func)(sc, eaddr) == 0)
4044                         break;
4045         }
4046         return (*func == NULL ? ENXIO : 0);
4047 }
4048
4049 /*
4050  * NOTE: 'm' is not freed upon failure
4051  */
4052 struct mbuf *
4053 bnx_defrag_shortdma(struct mbuf *m)
4054 {
4055         struct mbuf *n;
4056         int found;
4057
4058         /*
4059          * If device receive two back-to-back send BDs with less than
4060          * or equal to 8 total bytes then the device may hang.  The two
4061          * back-to-back send BDs must in the same frame for this failure
4062          * to occur.  Scan mbuf chains and see whether two back-to-back
4063          * send BDs are there.  If this is the case, allocate new mbuf
4064          * and copy the frame to workaround the silicon bug.
4065          */
4066         for (n = m, found = 0; n != NULL; n = n->m_next) {
4067                 if (n->m_len < 8) {
4068                         found++;
4069                         if (found > 1)
4070                                 break;
4071                         continue;
4072                 }
4073                 found = 0;
4074         }
4075
4076         if (found > 1)
4077                 n = m_defrag(m, MB_DONTWAIT);
4078         else
4079                 n = m;
4080         return n;
4081 }
4082
4083 static void
4084 bnx_stop_block(struct bnx_softc *sc, bus_size_t reg, uint32_t bit)
4085 {
4086         int i;
4087
4088         BNX_CLRBIT(sc, reg, bit);
4089         for (i = 0; i < BNX_TIMEOUT; i++) {
4090                 if ((CSR_READ_4(sc, reg) & bit) == 0)
4091                         return;
4092                 DELAY(100);
4093         }
4094 }
4095
4096 static void
4097 bnx_link_poll(struct bnx_softc *sc)
4098 {
4099         uint32_t status;
4100
4101         status = CSR_READ_4(sc, BGE_MAC_STS);
4102         if ((status & sc->bnx_link_chg) || sc->bnx_link_evt) {
4103                 sc->bnx_link_evt = 0;
4104                 sc->bnx_link_upd(sc, status);
4105         }
4106 }
4107
4108 static void
4109 bnx_enable_msi(struct bnx_softc *sc)
4110 {
4111         uint32_t msi_mode;
4112
4113         msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
4114         msi_mode |= BGE_MSIMODE_ENABLE;
4115         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
4116                 /*
4117                  * NOTE:
4118                  * 5718-PG105-R says that "one shot" mode
4119                  * does not work if MSI is used, however,
4120                  * it obviously works.
4121                  */
4122                 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
4123         }
4124         CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
4125 }
4126
4127 static uint32_t
4128 bnx_dma_swap_options(struct bnx_softc *sc)
4129 {
4130         uint32_t dma_options;
4131
4132         dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
4133             BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
4134 #if BYTE_ORDER == BIG_ENDIAN
4135         dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
4136 #endif
4137         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
4138             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
4139                 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA |
4140                     BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE |
4141                     BGE_MODECTL_HTX2B_ENABLE;
4142         }
4143         return dma_options;
4144 }
4145
4146 static int
4147 bnx_setup_tso(struct bnx_tx_ring *txr, struct mbuf **mp,
4148     uint16_t *mss0, uint16_t *flags0)
4149 {
4150         struct mbuf *m;
4151         struct ip *ip;
4152         struct tcphdr *th;
4153         int thoff, iphlen, hoff, hlen;
4154         uint16_t flags, mss;
4155
4156         m = *mp;
4157         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4158
4159         hoff = m->m_pkthdr.csum_lhlen;
4160         iphlen = m->m_pkthdr.csum_iphlen;
4161         thoff = m->m_pkthdr.csum_thlen;
4162
4163         KASSERT(hoff > 0, ("invalid ether header len"));
4164         KASSERT(iphlen > 0, ("invalid ip header len"));
4165         KASSERT(thoff > 0, ("invalid tcp header len"));
4166
4167         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4168                 m = m_pullup(m, hoff + iphlen + thoff);
4169                 if (m == NULL) {
4170                         *mp = NULL;
4171                         return ENOBUFS;
4172                 }
4173                 *mp = m;
4174         }
4175         ip = mtodoff(m, struct ip *, hoff);
4176         th = mtodoff(m, struct tcphdr *, hoff + iphlen);
4177
4178         mss = m->m_pkthdr.tso_segsz;
4179         flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA;
4180
4181         ip->ip_len = htons(mss + iphlen + thoff);
4182         th->th_sum = 0;
4183
4184         hlen = (iphlen + thoff) >> 2;
4185         mss |= ((hlen & 0x3) << 14);
4186         flags |= ((hlen & 0xf8) << 7) | ((hlen & 0x4) << 2);
4187
4188         *mss0 = mss;
4189         *flags0 = flags;
4190
4191         return 0;
4192 }
4193
4194 static int
4195 bnx_create_tx_ring(struct bnx_tx_ring *txr)
4196 {
4197         bus_size_t txmaxsz, txmaxsegsz;
4198         int i, error;
4199
4200         /*
4201          * Create DMA tag and maps for TX mbufs.
4202          */
4203         if (txr->bnx_sc->bnx_flags & BNX_FLAG_TSO)
4204                 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header);
4205         else
4206                 txmaxsz = BNX_JUMBO_FRAMELEN;
4207         if (txr->bnx_sc->bnx_asicrev == BGE_ASICREV_BCM57766)
4208                 txmaxsegsz = MCLBYTES;
4209         else
4210                 txmaxsegsz = PAGE_SIZE;
4211         error = bus_dma_tag_create(txr->bnx_sc->bnx_cdata.bnx_parent_tag,
4212             1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
4213             txmaxsz, BNX_NSEG_NEW, txmaxsegsz,
4214             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
4215             &txr->bnx_tx_mtag);
4216         if (error) {
4217                 device_printf(txr->bnx_sc->bnx_dev,
4218                     "could not allocate TX mbuf dma tag\n");
4219                 return error;
4220         }
4221
4222         for (i = 0; i < BGE_TX_RING_CNT; i++) {
4223                 error = bus_dmamap_create(txr->bnx_tx_mtag,
4224                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
4225                     &txr->bnx_tx_dmamap[i]);
4226                 if (error) {
4227                         int j;
4228
4229                         for (j = 0; j < i; ++j) {
4230                                 bus_dmamap_destroy(txr->bnx_tx_mtag,
4231                                         txr->bnx_tx_dmamap[j]);
4232                         }
4233                         bus_dma_tag_destroy(txr->bnx_tx_mtag);
4234                         txr->bnx_tx_mtag = NULL;
4235
4236                         device_printf(txr->bnx_sc->bnx_dev,
4237                             "could not create DMA map for TX\n");
4238                         return error;
4239                 }
4240         }
4241
4242         /*
4243          * Create DMA stuffs for TX ring.
4244          */
4245         error = bnx_dma_block_alloc(txr->bnx_sc, BGE_TX_RING_SZ,
4246             &txr->bnx_tx_ring_tag, &txr->bnx_tx_ring_map,
4247             (void *)&txr->bnx_tx_ring, &txr->bnx_tx_ring_paddr);
4248         if (error) {
4249                 device_printf(txr->bnx_sc->bnx_dev,
4250                     "could not create TX ring\n");
4251                 return error;
4252         }
4253
4254         txr->bnx_tx_wreg = BNX_TX_WREG_NSEGS;
4255
4256         return 0;
4257 }
4258
4259 static void
4260 bnx_destroy_tx_ring(struct bnx_tx_ring *txr)
4261 {
4262         /* Destroy TX mbuf DMA stuffs. */
4263         if (txr->bnx_tx_mtag != NULL) {
4264                 int i;
4265
4266                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
4267                         bus_dmamap_destroy(txr->bnx_tx_mtag,
4268                             txr->bnx_tx_dmamap[i]);
4269                 }
4270                 bus_dma_tag_destroy(txr->bnx_tx_mtag);
4271         }
4272
4273         /* Destroy TX ring */
4274         bnx_dma_block_free(txr->bnx_tx_ring_tag,
4275             txr->bnx_tx_ring_map, txr->bnx_tx_ring);
4276 }