2 * Copyright (C) 1993, David Greenman. This software may be used, modified,
3 * copied, distributed, and sold, in both source and binary form provided
4 * that the above copyright and these terms are retained. Under no
5 * circumstances is the author responsible for the proper functioning
6 * of this software, nor does the author assume any responsibility
7 * for damages incurred with its use.
9 * $FreeBSD: src/sys/dev/ed/if_edreg.h,v 1.32 2003/10/15 17:22:15 shiba Exp $
10 * $DragonFly: src/sys/dev/netif/ed/if_edreg.h,v 1.4 2004/02/13 21:15:12 joerg Exp $
13 * National Semiconductor DS8390 NIC register definitions
16 * Modification history
18 * Revision 2.2 1993/11/29 16:33:39 davidg
19 * From Thomas Sandford <t.d.g.sandford@comp.brad.ac.uk>
20 * Add support for the 8013W board type
22 * Revision 2.1 1993/11/22 10:52:33 davidg
23 * patch to add support for SMC8216 (Elite-Ultra) boards
26 * Revision 2.0 93/09/29 00:37:15 davidg
27 * changed double buffering flag to multi buffering
28 * made changes/additions for 3c503 multi-buffering
29 * ...companion to Rev. 2.0 of 'ed' driver.
31 * Revision 1.1 93/06/23 03:01:07 davidg
37 * Page 0 register offsets
39 #define ED_P0_CR 0x00 /* Command Register */
41 #define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */
42 #define ED_P0_PSTART 0x01 /* Page Start register (write) */
44 #define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */
45 #define ED_P0_PSTOP 0x02 /* Page Stop register (write) */
47 #define ED_P0_BNRY 0x03 /* Boundary Pointer */
49 #define ED_P0_TSR 0x04 /* Transmit Status Register (read) */
50 #define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */
52 #define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */
53 #define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */
55 #define ED_P0_FIFO 0x06 /* FIFO register (read) */
56 #define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */
58 #define ED_P0_ISR 0x07 /* Interrupt Status Register */
60 #define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */
61 #define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */
63 #define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */
64 #define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */
66 #define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */
68 #define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */
70 #define ED_P0_RSR 0x0c /* Receive Status (read) */
71 #define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */
73 #define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */
74 #define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */
76 #define ED_P0_CNTR1 0x0e /* CRC error counter (read) */
77 #define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */
79 #define ED_P0_CNTR2 0x0f /* missed packet counter (read) */
80 #define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */
83 * Page 1 register offsets
85 #define ED_P1_CR 0x00 /* Command Register */
86 #define ED_P1_PAR0 0x01 /* Physical Address Register 0 */
87 #define ED_P1_PAR1 0x02 /* Physical Address Register 1 */
88 #define ED_P1_PAR2 0x03 /* Physical Address Register 2 */
89 #define ED_P1_PAR3 0x04 /* Physical Address Register 3 */
90 #define ED_P1_PAR4 0x05 /* Physical Address Register 4 */
91 #define ED_P1_PAR5 0x06 /* Physical Address Register 5 */
92 #define ED_P1_PAR(i) (ED_P1_PAR0 + i)
93 #define ED_P1_CURR 0x07 /* Current RX ring-buffer page */
94 #define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */
95 #define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */
96 #define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */
97 #define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */
98 #define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */
99 #define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */
100 #define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */
101 #define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */
102 #define ED_P1_MAR(i) (ED_P1_MAR0 + i)
105 * Page 2 register offsets
107 #define ED_P2_CR 0x00 /* Command Register */
108 #define ED_P2_PSTART 0x01 /* Page Start (read) */
109 #define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */
110 #define ED_P2_PSTOP 0x02 /* Page Stop (read) */
111 #define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */
112 #define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */
113 #define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */
114 #define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */
115 #define ED_P2_ACU 0x06 /* Address Counter Upper */
116 #define ED_P2_ACL 0x07 /* Address Counter Lower */
117 #define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */
118 #define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */
119 #define ED_P2_DCR 0x0e /* Data Configuration Register (read) */
120 #define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */
123 * Command Register (CR) definitions
127 * STP: SToP. Software reset command. Takes the controller offline. No
128 * packets will be received or transmitted. Any reception or
129 * transmission in progress will continue to completion before
130 * entering reset state. To exit this state, the STP bit must
131 * reset and the STA bit must be set. The software reset has
132 * executed only when indicated by the RST bit in the ISR being
135 #define ED_CR_STP 0x01
138 * STA: STArt. This bit is used to activate the NIC after either power-up,
139 * or when the NIC has been put in reset mode by software command
142 #define ED_CR_STA 0x02
145 * TXP: Transmit Packet. This bit must be set to indicate transmission of
146 * a packet. TXP is internally reset either after the transmission is
147 * completed or aborted. This bit should be set only after the Transmit
148 * Byte Count and Transmit Page Start register have been programmed.
150 #define ED_CR_TXP 0x04
153 * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation
154 * of the remote DMA channel. RD2 can be set to abort any remote DMA
155 * command in progress. The Remote Byte Count registers should be cleared
156 * when a remote DMA has been aborted. The Remote Start Addresses are not
157 * restored to the starting address if the remote DMA is aborted.
159 * RD2 RD1 RD0 function
166 #define ED_CR_RD0 0x08
167 #define ED_CR_RD1 0x10
168 #define ED_CR_RD2 0x20
171 * PS0, PS1: Page Select. The two bits select which register set or 'page' to
180 #define ED_CR_PS0 0x40
181 #define ED_CR_PS1 0x80
182 /* bit encoded aliases */
183 #define ED_CR_PAGE_0 0x00 /* (for consistency) */
184 #define ED_CR_PAGE_1 0x40
185 #define ED_CR_PAGE_2 0x80
188 * Interrupt Status Register (ISR) definitions
192 * PRX: Packet Received. Indicates packet received with no errors.
194 #define ED_ISR_PRX 0x01
197 * PTX: Packet Transmitted. Indicates packet transmitted with no errors.
199 #define ED_ISR_PTX 0x02
202 * RXE: Receive Error. Indicates that a packet was received with one or more
203 * the following errors: CRC error, frame alignment error, FIFO overrun,
206 #define ED_ISR_RXE 0x04
209 * TXE: Transmission Error. Indicates that an attempt to transmit a packet
210 * resulted in one or more of the following errors: excessive
211 * collisions, FIFO underrun.
213 #define ED_ISR_TXE 0x08
216 * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network
217 * would exceed (has exceeded?) the boundary pointer, resulting in data
218 * that was previously received and not yet read from the buffer to be
221 #define ED_ISR_OVW 0x10
224 * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley
225 * Counters has been set.
227 #define ED_ISR_CNT 0x20
230 * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed.
232 #define ED_ISR_RDC 0x40
235 * RST: Reset status. Set when the NIC enters the reset state and cleared when a
236 * Start Command is issued to the CR. This bit is also set when a receive
237 * ring-buffer overrun (OverWrite) occurs and is cleared when one or more
238 * packets have been removed from the ring. This is a read-only bit.
240 #define ED_ISR_RST 0x80
243 * Interrupt Mask Register (IMR) definitions
247 * PRXE: Packet Received interrupt Enable. If set, a received packet will cause
250 #define ED_IMR_PRXE 0x01
253 * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when
254 * a packet transmission completes.
256 #define ED_IMR_PTXE 0x02
259 * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a
260 * packet is received with an error.
262 #define ED_IMR_RXEE 0x04
265 * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever
266 * a transmission results in an error.
268 #define ED_IMR_TXEE 0x08
271 * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever
272 * the receive ring-buffer is overrun. i.e. when the boundary pointer is exceeded.
274 #define ED_IMR_OVWE 0x10
277 * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever
278 * the MSB of one or more of the Network Statistics counters has been set.
280 #define ED_IMR_CNTE 0x20
283 * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated
284 * when a remote DMA transfer has completed.
286 #define ED_IMR_RDCE 0x40
289 * bit 7 is unused/reserved
293 * Data Configuration Register (DCR) definitions
297 * WTS: Word Transfer Select. WTS establishes byte or word transfers for
298 * both remote and local DMA transfers
300 #define ED_DCR_WTS 0x01
303 * BOS: Byte Order Select. BOS sets the byte order for the host.
304 * Should be 0 for 80x86, and 1 for 68000 series processors
306 #define ED_DCR_BOS 0x02
309 * LAS: Long Address Select. When LAS is 1, the contents of the remote
310 * DMA registers RSAR0 and RSAR1 are used to provide A16-A31
312 #define ED_DCR_LAS 0x04
315 * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2
316 * of the TCR must also be programmed for loopback operation.
317 * When 1, normal operation is selected.
319 #define ED_DCR_LS 0x08
322 * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer
323 * under program control. When 1, remote DMA is automatically initiated
324 * and the boundary pointer is automatically updated
326 #define ED_DCR_AR 0x10
329 * FT0, FT1: Fifo Threshold select.
330 * FT1 FT0 Word-width Byte-width
332 * 0 1 2 words 4 bytes
333 * 1 0 4 words 8 bytes
334 * 1 1 8 words 12 bytes
336 * During transmission, the FIFO threshold indicates the number of bytes
337 * or words that the FIFO has filled from the local DMA before BREQ is
338 * asserted. The transmission threshold is 16 bytes minus the receiver
341 #define ED_DCR_FT0 0x20
342 #define ED_DCR_FT1 0x40
345 * bit 7 (0x80) is unused/reserved
349 * Transmit Configuration Register (TCR) definitions
353 * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC
354 * is not appended by the transmitter.
356 #define ED_TCR_CRC 0x01
359 * LB0, LB1: Loopback control. These two bits set the type of loopback that is
363 * 0 0 0 - normal operation (DCR_LS = 0)
364 * 0 1 1 - internal loopback (DCR_LS = 0)
365 * 1 0 2 - external loopback (DCR_LS = 1)
366 * 1 1 3 - external loopback (DCR_LS = 0)
368 #define ED_TCR_LB0 0x02
369 #define ED_TCR_LB1 0x04
372 * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows
373 * another station to disable the NIC's transmitter by transmitting to
374 * a multicast address hashing to bit 62. Reception of a multicast address
375 * hashing to bit 63 enables the transmitter.
377 #define ED_TCR_ATD 0x08
380 * OFST: Collision Offset enable. This bit when set modifies the backoff
381 * algorithm to allow prioritization of nodes.
383 #define ED_TCR_OFST 0x10
386 * bits 5, 6, and 7 are unused/reserved
390 * Transmit Status Register (TSR) definitions
394 * PTX: Packet Transmitted. Indicates successful transmission of packet.
396 #define ED_TSR_PTX 0x01
399 * bit 1 (0x02) is unused/reserved
403 * COL: Transmit Collided. Indicates that the transmission collided at least
404 * once with another station on the network.
406 #define ED_TSR_COL 0x04
409 * ABT: Transmit aborted. Indicates that the transmission was aborted due to
410 * excessive collisions.
412 #define ED_TSR_ABT 0x08
415 * CRS: Carrier Sense Lost. Indicates that carrier was lost during the
416 * transmission of the packet. (Transmission is not aborted because
417 * of a loss of carrier)
419 #define ED_TSR_CRS 0x10
422 * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/
423 * transmission memory before the FIFO emptied. Transmission of the
424 * packet was aborted.
426 #define ED_TSR_FU 0x20
429 * CDH: CD Heartbeat. Indicates that the collision detection circuitry
430 * isn't working correctly during a collision heartbeat test.
432 #define ED_TSR_CDH 0x40
435 * OWC: Out of Window Collision: Indicates that a collision occurred after
436 * a slot time (51.2us). The transmission is rescheduled just as in
439 #define ED_TSR_OWC 0x80
442 * Receiver Configuration Register (RCR) definitions
446 * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1,
447 * packets with CRC and frame errors are not discarded.
449 #define ED_RCR_SEP 0x01
452 * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded.
453 * If set to 1, packets with less than 64 byte are not discarded.
455 #define ED_RCR_AR 0x02
458 * AB: Accept Broadcast. If set, packets sent to the broadcast address will be
461 #define ED_RCR_AB 0x04
464 * AM: Accept Multicast. If set, packets sent to a multicast address are checked
465 * for a match in the hashing array. If clear, multicast packets are ignored.
467 #define ED_RCR_AM 0x08
470 * PRO: Promiscuous Physical. If set, all packets with a physical addresses are
471 * accepted. If clear, a physical destination address must match this
472 * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM
473 * must also be set. In addition, the multicast hashing array must be set
474 * to all 1's so that all multicast addresses are accepted.
476 #define ED_RCR_PRO 0x10
479 * MON: Monitor Mode. If set, packets will be checked for good CRC and framing,
480 * but are not stored in the ring-buffer. If clear, packets are stored (normal
483 #define ED_RCR_MON 0x20
486 * INTT: Interrupt Trigger Mode for AX88190.
488 #define ED_RCR_INTT 0x40
491 * bit 7 is unused/reserved.
495 * Receiver Status Register (RSR) definitions
499 * PRX: Packet Received without error.
501 #define ED_RSR_PRX 0x01
504 * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame
507 #define ED_RSR_CRC 0x02
510 * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on
511 * a byte boundary and the CRC did not match at the last byte boundary.
513 #define ED_RSR_FAE 0x04
516 * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA)
517 * causing it to overrun. Reception of the packet is aborted.
519 #define ED_RSR_FO 0x08
522 * MPA: Missed Packet. Indicates that the received packet couldn't be stored in
523 * the ring-buffer because of insufficient buffer space (exceeding the
524 * boundary pointer), or because the transfer to the ring-buffer was inhibited
525 * by RCR_MON - monitor mode.
527 #define ED_RSR_MPA 0x10
530 * PHY: Physical address. If 0, the packet received was sent to a physical address.
531 * If 1, the packet was accepted because of a multicast/broadcast address
534 #define ED_RSR_PHY 0x20
537 * DIS: Receiver Disabled. Set to indicate that the receiver has entered monitor
538 * mode. Cleared when the receiver exits monitor mode.
540 #define ED_RSR_DIS 0x40
543 * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs
544 * are active, and the transceiver has set the CD line as a result of the
547 #define ED_RSR_DFR 0x80
550 * receive ring descriptor
552 * The National Semiconductor DS8390 Network interface controller uses
553 * the following receive ring headers. The way this works is that the
554 * memory on the interface card is chopped up into 256 bytes blocks.
555 * A contiguous portion of those blocks are marked for receive packets
556 * by setting start and end block #'s in the NIC. For each packet that
557 * is put into the receive ring, one of these headers (4 bytes each) is
558 * tacked onto the front. The first byte is a copy of the receiver status
559 * register at the time the packet was received.
562 u_char rsr; /* receiver status */
563 u_char next_packet; /* pointer to next packet */
564 u_short count; /* bytes in packet (length + 4) */
570 #define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */
571 #define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */
576 #define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */
577 #define ED_VENDOR_3COM 0x01 /* 3Com */
578 #define ED_VENDOR_NOVELL 0x02 /* Novell */
579 #define ED_VENDOR_PCCARD 0x03 /* PCMCIA/PCCARD */
580 #define ED_VENDOR_HP 0x04 /* Hewlett Packard */
581 #define ED_VENDOR_LINKSYS 0x05 /* Linksys (Dlink) */
582 #define ED_VENDOR_SIC 0x06 /* Allied-Telesis SIC */
585 * Compile-time config flags
588 * this sets the default for enabling/disabling the transceiver
590 #define ED_FLAGS_DISABLE_TRANCEIVER 0x0001
593 * This forces the board to be used in 8/16bit mode even if it
594 * autoconfigs differently
596 #define ED_FLAGS_FORCE_8BIT_MODE 0x0002
597 #define ED_FLAGS_FORCE_16BIT_MODE 0x0004
600 * This disables the use of double transmit buffers.
602 #define ED_FLAGS_NO_MULTI_BUFFERING 0x0008
605 * This forces all operations with the NIC memory to use Programmed
606 * I/O (i.e. not via shared memory)
608 #define ED_FLAGS_FORCE_PIO 0x0010
611 * These are flags describing the chip type.
613 #define ED_FLAGS_TOSH_ETHER 0x10000
614 #define ED_FLAGS_GWETHER 0x20000
615 #define ED_FLAGS_AX88190 0x30000
616 #define ED_FLAGS_LINKSYS 0x80000
618 #define ED_FLAGS_GETTYPE(flg) ((flg) & 0xff0000)
621 * Definitions for Western digital/SMC WD80x3 series ASIC
624 * Memory Select Register (MSR)
628 /* next three definitions for Toshiba */
629 #define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */
630 #define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */
631 #define ED_WD_MSR_LEN 0x20 /* data bus width, 0 = 16 bits,
633 #define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
634 #define ED_WD_MSR_MENB 0x40 /* Memory enable */
635 #define ED_WD_MSR_RST 0x80 /* Reset board */
638 * Interface Configuration Register (ICR)
642 #define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */
643 #define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */
644 #define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */
645 #define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */
646 #define ED_WD_ICR_RLA 0x10 /* recall LAN address */
647 #define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */
648 #define ED_WD_ICR_RIO 0x40 /* recall i/o address */
649 #define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */
650 #define ED_WD_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */
651 #define ED_WD_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K,
652 0x02 = 16K, 0x01 = 8K */
653 /* 64K can only be used if mem address
655 /* IAR holds address A23-A16 (R/W) */
658 * IO Address Register (IAR)
663 * EEROM Address Register
668 * Interrupt Request Register (IRR)
672 #define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */
673 #define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */
674 #define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */
675 #define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */
676 #define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */
679 * The three bits of the encoded IRQ are decoded as follows:
691 #define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */
692 #define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */
693 #define ED_WD_IRR_IEN 0x80 /* Interrupt enable */
696 * LA Address Register (LAAR)
700 #define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */
701 #define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */
702 #define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */
703 #define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */
705 /* i/o base offset to station address/card-ID PROM */
709 * 83C790 specific registers
712 * Hardware Support Register (HWR) ('790)
714 #define ED_WD790_HWR 4
716 #define WD_WD790_HWR_NUKE 0x10 /* hardware reset */
717 #define ED_WD790_HWR_LPRM 0x40 /* LAN PROM select */
718 #define ED_WD790_HWR_SWH 0x80 /* switch register set */
721 * ICR790 Interrupt Control Register for the 83C790
723 #define ED_WD790_ICR 6
725 #define ED_WD790_ICR_EIL 0x01 /* enable interrupts */
728 * REV/IOPA Revision / I/O Pipe register for the 83C79X
730 #define ED_WD790_REV 7
732 #define ED_WD790 0x20
733 #define ED_WD795 0x40
736 * 79X RAM Address Register (RAR)
737 * Enabled with SWH bit=1 in HWR register
739 #define ED_WD790_RAR 0x0b
741 #define ED_WD790_RAR_SZ8 0x00 /* 8k memory buffer */
742 #define ED_WD790_RAR_SZ16 0x10 /* 16k memory buffer */
743 #define ED_WD790_RAR_SZ32 0x20 /* 32k memory buffer */
744 #define ED_WD790_RAR_SZ64 0x30 /* 64k memory buffer */
747 * General Control Register (GCR)
748 * Enabled with SWH bit=1 in HWR register
750 #define ED_WD790_GCR 0x0d
752 #define ED_WD790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */
753 #define ED_WD790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */
754 #define ED_WD790_GCR_ZWSEN 0x20 /* zero wait state enable */
755 #define ED_WD790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */
756 #define ED_WD790_GCR_LIT 0x01 /* Link Integrity Test Enable */
758 * The three bits of the encoded IRQ are decoded as follows:
771 /* i/o base offset to CARD ID */
772 #define ED_WD_CARD_ID ED_WD_PROM+6
774 /* Board type codes in card ID */
775 #define ED_TYPE_WD8003S 0x02
776 #define ED_TYPE_WD8003E 0x03
777 #define ED_TYPE_WD8013EBT 0x05
778 #define ED_TYPE_TOSHIBA1 0x11 /* named PCETA1 */
779 #define ED_TYPE_TOSHIBA2 0x12 /* named PCETA2 */
780 #define ED_TYPE_TOSHIBA3 0x13 /* named PCETB */
781 #define ED_TYPE_TOSHIBA4 0x14 /* named PCETC */
782 #define ED_TYPE_WD8003W 0x24
783 #define ED_TYPE_WD8003EB 0x25
784 #define ED_TYPE_WD8013W 0x26
785 #define ED_TYPE_WD8013EP 0x27
786 #define ED_TYPE_WD8013WC 0x28
787 #define ED_TYPE_WD8013EPC 0x29
788 #define ED_TYPE_SMC8216T 0x2a
789 #define ED_TYPE_SMC8216C 0x2b
790 #define ED_TYPE_WD8013EBP 0x2c
792 /* Bit definitions in card ID */
793 #define ED_WD_REV_MASK 0x1f /* Revision mask */
794 #define ED_WD_SOFTCONFIG 0x20 /* Soft config */
795 #define ED_WD_LARGERAM 0x40 /* Large RAM */
796 #define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */
799 * Checksum total. All 8 bytes in station address PROM will add up to this
801 #define ED_WD_ROM_CHECKSUM_TOTAL 0xFF
802 #define ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER 0xA5
804 #define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */
805 #define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */
806 #define ED_WD_IO_PORTS 32 /* # of i/o addresses used */
808 #define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */
811 * Definitions for 3Com 3c503
813 #define ED_3COM_NIC_OFFSET 0
814 #define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */
817 * XXX - The I/O address range is fragmented in the 3c503; this is the
818 * number of regs at iobase.
820 #define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */
822 /* tx memory starts in second bank on 8bit cards */
823 #define ED_3COM_TX_PAGE_OFFSET_8BIT 0x20
825 /* tx memory starts in first bank on 16bit cards */
826 #define ED_3COM_TX_PAGE_OFFSET_16BIT 0x0
828 /* ...and rx memory starts in second bank */
829 #define ED_3COM_RX_PAGE_OFFSET_16BIT 0x20
833 * Page Start Register. Must match PSTART in NIC
835 #define ED_3COM_PSTR 0
838 * Page Stop Register. Must match PSTOP in NIC
840 #define ED_3COM_PSPR 1
843 * Drq Timer Register. Determines number of bytes to be transfered during
846 #define ED_3COM_DQTR 2
849 * Base Configuration Register. Read-only register which contains the
850 * board-configured I/O base address of the adapter. Bit encoded.
852 #define ED_3COM_BCFR 3
854 #define ED_3COM_BCFR_2E0 0x01
855 #define ED_3COM_BCFR_2A0 0x02
856 #define ED_3COM_BCFR_280 0x04
857 #define ED_3COM_BCFR_250 0x08
858 #define ED_3COM_BCFR_350 0x10
859 #define ED_3COM_BCFR_330 0x20
860 #define ED_3COM_BCFR_310 0x40
861 #define ED_3COM_BCFR_300 0x80
864 * EPROM Configuration Register. Read-only register which contains the
865 * board-configured memory base address. Bit encoded.
867 #define ED_3COM_PCFR 4
869 #define ED_3COM_PCFR_C8000 0x10
870 #define ED_3COM_PCFR_CC000 0x20
871 #define ED_3COM_PCFR_D8000 0x40
872 #define ED_3COM_PCFR_DC000 0x80
875 * GA Configuration Register. Gate-Array Configuration Register.
877 #define ED_3COM_GACFR 5
880 * mbs2 mbs1 mbs0 start address
886 * Note that with adapters with only 8K, the setting for 0x2000 must
889 #define ED_3COM_GACFR_MBS0 0x01
890 #define ED_3COM_GACFR_MBS1 0x02
891 #define ED_3COM_GACFR_MBS2 0x04
893 #define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */
894 #define ED_3COM_GACFR_TEST 0x10 /* for GA testing */
895 #define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */
896 #define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */
897 #define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */
900 * Control Register. Miscellaneous control functions.
904 #define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */
905 #define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */
906 #define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */
907 #define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */
908 #define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */
909 #define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */
910 #define ED_3COM_CR_DDIR 0x40 /* DMA direction select */
911 #define ED_3COM_CR_START 0x80 /* Start DMA controller */
914 * Status Register. Miscellaneous status information.
916 #define ED_3COM_STREG 7
918 #define ED_3COM_STREG_REV 0x07 /* GA revision */
919 #define ED_3COM_STREG_DIP 0x08 /* DMA in progress */
920 #define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */
921 #define ED_3COM_STREG_OFLW 0x20 /* Overflow */
922 #define ED_3COM_STREG_UFLW 0x40 /* Underflow */
923 #define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */
926 * Interrupt/DMA Configuration Register
928 #define ED_3COM_IDCFR 8
930 #define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */
931 #define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */
932 #define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */
933 #define ED_3COM_IDCFR_UNUSED 0x08 /* not used */
934 #define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */
935 #define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */
936 #define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */
937 #define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */
940 * DMA Address Register MSB
942 #define ED_3COM_DAMSB 9
945 * DMA Address Register LSB
947 #define ED_3COM_DALSB 0x0a
950 * Vector Pointer Register 2
952 #define ED_3COM_VPTR2 0x0b
955 * Vector Pointer Register 1
957 #define ED_3COM_VPTR1 0x0c
960 * Vector Pointer Register 0
962 #define ED_3COM_VPTR0 0x0d
965 * Register File Access MSB
967 #define ED_3COM_RFMSB 0x0e
970 * Register File Access LSB
972 #define ED_3COM_RFLSB 0x0f
975 * Definitions for Novell NE1000/2000 boards
981 #define ED_TYPE_NE1000 0x01
982 #define ED_TYPE_NE2000 0x02
985 * Register offsets/total
987 #define ED_NOVELL_NIC_OFFSET 0x00
988 #define ED_NOVELL_ASIC_OFFSET 0x10
989 #define ED_NOVELL_IO_PORTS 32
992 * Remote DMA data register; for reading or writing to the NIC mem
993 * via programmed I/O (offset from ASIC base)
995 #define ED_NOVELL_DATA 0x00
998 * Reset register; reading from this register causes a board reset
1000 #define ED_NOVELL_RESET 0x0f
1003 * Definitions for PCCARD
1005 #define ED_PC_PAGE_OFFSET 0x40 /* page offset for NIC access to mem */
1006 #define ED_PC_IO_PORTS 32
1007 #define ED_PC_ASIC_OFFSET 0x10
1008 #define ED_PC_RESET 0x0f /* Reset(offset from ASIC base) */
1009 #define ED_PC_MISC 0x08 /* Misc (offset from ASIC base) */
1015 #define ZE_PAGE_OFFSET 0x40 /* mem buffer starts at 0x4000 */
1017 #define ZE_DATA_IO 0x10
1018 #define ZE_MISC 0x18
1019 #define ZE_RESET 0x1F
1022 * Definitions for HP PC LAN Adapter Plus; based on the CRYNWR packet
1023 * driver for the card.
1026 #define ED_HPP_ASIC_OFFSET 0x00 /* Offset to ASIC registers */
1027 #define ED_HPP_NIC_OFFSET 0x10 /* Offset to 8390 registers */
1029 #define ED_HPP_ID 0x00 /* ID register, always 0x4850 */
1030 #define ED_HPP_PAGING 0x02 /* Page select register */
1031 #define ED_HPP_OPTION 0x04 /* Bitmask of supported options */
1032 #define ED_HPP_PAGE_0 0x08 /* Page 0 */
1033 #define ED_HPP_PAGE_2 0x0A /* Page 2 */
1034 #define ED_HPP_PAGE_4 0x0C /* Page 4 */
1035 #define ED_HPP_PAGE_6 0x0E /* Page 6 */
1038 #define ED_HPP_OUT_ADDR ED_HPP_PAGE_0 /* I/O output location */
1039 #define ED_HPP_IN_ADDR ED_HPP_PAGE_2 /* I/O input location */
1040 #define ED_HPP_DATAPORT ED_HPP_PAGE_4 /* I/O data transfer */
1042 #define ED_HPP_MAC_ADDR 0x08 /* Offset of MAC address in MAC page */
1044 #define ED_HPP_IO_PORTS 32 /* Number of IO ports */
1046 #define ED_HPP_TX_PAGE_OFFSET 0x00 /* first page of TX buffer */
1047 #define ED_HPP_RX_PAGE_START 0x06 /* start at page 6 */
1048 #define ED_HPP_RX_PAGE_STOP 0x80 /* end at page 128 */
1051 * Register pages supported.
1054 #define ED_HPP_PAGE_PERF 0 /* Normal operation */
1055 #define ED_HPP_PAGE_MAC 1 /* The ethernet address and checksum */
1056 #define ED_HPP_PAGE_HW 2 /* Hardware parameters in EEPROM */
1057 #define ED_HPP_PAGE_LAN 4 /* Transciever selection etc */
1058 #define ED_HPP_PAGE_ID 6 /* ID */
1061 * Options supported.
1064 #define ED_HPP_OPTION_NIC_RESET 0x0001 /* active low */
1065 #define ED_HPP_OPTION_CHIP_RESET 0x0002 /* active low */
1066 #define ED_HPP_OPTION_ENABLE_IRQ 0x0004
1067 #define ED_HPP_OPTION_FAKE_INTR 0x0008
1068 #define ED_HPP_OPTION_BOOT_ROM_ENB 0x0010
1069 #define ED_HPP_OPTION_IO_ENB 0x0020
1070 #define ED_HPP_OPTION_MEM_ENABLE 0x0040
1071 #define ED_HPP_OPTION_ZERO_WAIT 0x0080
1072 #define ED_HPP_OPTION_MEM_DISABLE 0x1000
1075 * Page ID configuration.
1078 #define ED_HPP_ID_REVISION_MASK 0x0300 /* revision id */
1079 #define ED_HPP_ID_SOFT_MODEL_MASK 0xFC00 /* soft model number */
1080 #define ED_HPP_ID_16_BIT_ACCESS 0x0010 /* if set use 16 bit accesses */
1081 #define ED_HPP_ID_TWISTED_PAIR 0x0040
1084 * Hardware configuration.
1087 #define ED_HPP_HW_MEM_MAP 0x09 /* low mem map location in HW page */
1088 #define ED_HPP_HW_ID 0x0C /* revision number, capabilities */
1089 #define ED_HPP_HW_IRQ 0x0D /* IRQ channel register in HW page */
1090 #define ED_HPP_HW_WRAP 0x0E /* mem wrap page for rcv */
1096 #define ED_HPP_LAN_AUI 0x01 /* Use AUI */
1097 #define ED_HPP_LAN_TL 0x40 /* Don't use AUI */
1103 #define ED_TYPE_HP_PCLANPLUS 0x00
1106 * Definitions for Allied-Telesis SIC
1108 #define ED_SIC_NIC_OFFSET 0
1109 #define ED_SIC_ASIC_OFFSET 0x10 /* offset to nic i/o regs */
1111 #define ED_SIC_IO_PORTS 17 /* # of i/o addresses used */
1117 #define ED_CHIP_TYPE_DP8390 0x00
1118 #define ED_CHIP_TYPE_WD790 0x01
1119 #define ED_CHIP_TYPE_AX88190 0x02
1122 * AX88190 IOBASE registers.
1125 #define ED_AX88190_IOBASE0 0x3ca
1126 #define ED_AX88190_IOBASE1 0x3cc
1129 * MII bus definitions.
1131 #define ED_MII_STARTDELIM 0x01
1132 #define ED_MII_WRITEOP 0x01
1133 #define ED_MII_READOP 0x02
1134 #define ED_MII_TURNAROUND 0x02
1135 #define ED_MII_IDLE 0x01
1137 #define ED_MII_STARTDELIM_BITS 2
1138 #define ED_MII_OP_BITS 2
1139 #define ED_MII_PHY_BITS 5
1140 #define ED_MII_REG_BITS 5
1141 #define ED_MII_TURNAROUND_BITS 2
1142 #define ED_MII_DATA_BITS 16
1143 #define ED_MII_ACK_BITS 1
1144 #define ED_MII_IDLE_BITS 1
1146 /* Dlink chipset used on some Netgear and Dlink PCMCIA cards */
1147 #define ED_DLINK_MIIBUS 0x0c /* MII bus register on ASIC */
1149 #define ED_DLINK_MII_RESET1 0x04
1150 #define ED_DLINK_MII_RESET2 0x08
1152 #define ED_DLINK_MII_DATATIN 0x10
1153 #define ED_DLINK_MII_DIROUT 0x20
1154 #define ED_DLINK_MII_DATAOUT 0x40
1155 #define ED_DLINK_MII_CLK 0x80