2 * Copyright 1996 Massachusetts Institute of Technology
4 * Permission to use, copy, modify, and distribute this software and
5 * its documentation for any purpose and without fee is hereby
6 * granted, provided that both the above copyright notice and this
7 * permission notice appear in all copies, that both the above
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9 * supporting documentation, and that the name of M.I.T. not be used
10 * in advertising or publicity pertaining to distribution of the
11 * software without specific, written prior permission. M.I.T. makes
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13 * purpose. It is provided "as is" without express or implied
16 * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
17 * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
18 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
20 * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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29 * $FreeBSD: src/sys/i386/include/perfmon.h,v 1.7 1999/12/29 04:33:04 peter Exp $
30 * $DragonFly: src/sys/cpu/i386/include/perfmon.h,v 1.3 2003/08/26 21:42:18 rob Exp $
34 * Interface to performance-monitoring counters for Intel Pentium and
38 #ifndef _MACHINE_PERFMON_H_
39 #define _MACHINE_PERFMON_H_
42 #include <sys/types.h>
44 #include <sys/ioccom.h>
48 #define PMIOSETUP _IOW('5', 1, struct pmc)
49 #define PMIOGET _IOWR('5', 7, struct pmc)
50 #define PMIOSTART _IOW('5', 2, int)
51 #define PMIOSTOP _IOW('5', 3, int)
52 #define PMIOREAD _IOWR('5', 4, struct pmc_data)
53 #define PMIORESET _IOW('5', 5, int)
54 #define PMIOTSTAMP _IOR('5', 6, struct pmc_tstamp)
60 unsigned char pmcus_event;
61 unsigned char pmcus_unit;
62 unsigned char pmcus_flags;
63 unsigned char pmcus_mask;
65 unsigned int pmcu_val;
71 #define pmc_event pmc_pmcu.pmcu_s.pmcus_event
72 #define pmc_unit pmc_pmcu.pmcu_s.pmcus_unit
73 #define pmc_flags pmc_pmcu.pmcu_s.pmcus_flags
74 #define pmc_mask pmc_pmcu.pmcu_s.pmcus_mask
75 #define pmc_val pmc_pmcu.pmcu_val
77 #define PMCF_USR 0x01 /* count events in user mode */
78 #define PMCF_OS 0x02 /* count events in kernel mode */
79 #define PMCF_E 0x04 /* use edge-detection mode */
80 #define PMCF_PC 0x08 /* PMx output pin control */
81 #define PMCF_INT 0x10 /* APIC interrupt enable (do not use) */
82 #define PMCF_EN 0x40 /* enable counters */
83 #define PMCF_INV 0x80 /* invert counter mask comparison */
85 #define PMCF_SYS_FLAGS (PMCF_INT | PMCF_EN) /* user cannot set */
99 #define _PATH_PERFMON "/dev/perfmon"
104 * Intra-kernel interface to performance monitoring counters
106 void perfmon_init (void);
107 int perfmon_avail (void);
108 int perfmon_setup (int, unsigned int);
109 int perfmon_get (int, unsigned int *);
110 int perfmon_fini (int);
111 int perfmon_start (int);
112 int perfmon_stop (int);
113 int perfmon_read (int, quad_t *);
114 int perfmon_reset (int);
119 * Pentium Pro performance counters, from Appendix B.
121 /* Data Cache Unit */
122 #define PMC6_DATA_MEM_REFS 0x43
123 #define PMC6_DCU_LINES_IN 0x45
124 #define PMC6_DCU_M_LINES_IN 0x46
125 #define PMC6_DCU_M_LINES_OUT 0x47
126 #define PMC6_DCU_MISS_OUTSTANDING 0x48
128 /* Instruction Fetch Unit */
129 #define PMC6_IFU_IFETCH 0x80
130 #define PMC6_IFU_IFETCH_MISS 0x81
131 #define PMC6_ITLB_MISS 0x85
132 #define PMC6_IFU_MEM_STALL 0x86
133 #define PMC6_ILD_STALL 0x87
136 #define PMC6_L2_IFETCH 0x28 /* MESI */
137 #define PMC6_L2_LD 0x29 /* MESI */
138 #define PMC6_L2_ST 0x2a /* MESI */
139 #define PMC6_L2_LINES_IN 0x24
140 #define PMC6_L2_LINES_OUT 0x26
141 #define PMC6_L2_M_LINES_INM 0x25
142 #define PMC6_L2_M_LINES_OUTM 0x27
143 #define PMC6_L2_RQSTS 0x2e /* MESI */
144 #define PMC6_L2_ADS 0x21
145 #define PMC6_L2_DBUS_BUSY 0x22
146 #define PMC6_L2_DBUS_BUSY_RD 0x23
148 /* External Bus Logic */
149 #define PMC6_BUS_DRDY_CLOCKS 0x62
150 #define PMC6_BUS_LOCK_CLOCKS 0x63
151 #define PMC6_BUS_REQ_OUTSTANDING 0x60
152 #define PMC6_BUS_TRAN_BRD 0x65
153 #define PMC6_BUS_TRAN_RFO 0x66
154 #define PMC6_BUS_TRAN_WB 0x67
155 #define PMC6_BUS_TRAN_IFETCH 0x68
156 #define PMC6_BUS_TRAN_INVAL 0x69
157 #define PMC6_BUS_TRAN_PWR 0x6a
158 #define PMC6_BUS_TRAN_P 0x6b
159 #define PMC6_BUS_TRAN_IO 0x6c
160 #define PMC6_BUS_TRAN_DEF 0x6d
161 #define PMC6_BUS_TRAN_BURST 0x6e
162 #define PMC6_BUS_TRAN_ANY 0x70
163 #define PMC6_BUS_TRAN_MEM 0x6f
164 #define PMC6_BUS_DATA_RCV 0x64
165 #define PMC6_BUS_BNR_DRV 0x61
166 #define PMC6_BUS_HIT_DRV 0x7a
167 #define PMC6_BUS_HITM_DRV 0x7b
168 #define PMC6_BUS_SNOOP_STALL 0x7e
170 /* Floating Point Unit */
171 #define PMC6_FLOPS 0xc1 /* counter 0 only */
172 #define PMC6_FP_COMP_OPS_EXE 0x10 /* counter 0 only */
173 #define PMC6_FP_ASSIST 0x11 /* counter 1 only */
174 #define PMC6_MUL 0x12 /* counter 1 only */
175 #define PMC6_DIV 0x13 /* counter 1 only */
176 #define PMC6_CYCLES_DIV_BUSY 0x14 /* counter 0 only */
178 /* Memory Ordering */
179 #define PMC6_LD_BLOCKS 0x03
180 #define PMC6_SB_DRAINS 0x04
181 #define PMC6_MISALIGN_MEM_REF 0x05
183 /* Instruction Decoding and Retirement */
184 #define PMC6_INST_RETIRED 0xc0
185 #define PMC6_UOPS_RETIRED 0xc2
186 #define PMC6_INST_DECODER 0xd0 /* (sic) */
189 #define PMC6_HW_INT_RX 0xc8
190 #define PMC6_CYCLES_INT_MASKED 0xc6
191 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
194 #define PMC6_BR_INST_RETIRED 0xc4
195 #define PMC6_BR_MISS_PRED_RETIRED 0xc5
196 #define PMC6_BR_TAKEN_RETIRED 0xc9
197 #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca
198 #define PMC6_BR_INST_DECODED 0xe0
199 #define PMC6_BTB_MISSES 0xe2
200 #define PMC6_BR_BOGUS 0xe4
201 #define PMC6_BACLEARS 0xe6
204 #define PMC6_RESOURCE_STALLS 0xa2
205 #define PMC6_PARTIAL_RAT_STALLS 0xd2
207 /* Segment Register Loads */
208 #define PMC6_SEGMENT_REG_LOADS 0x06
211 #define PMC6_CPU_CLK_UNHALTED 0x79
214 * Pentium Performance Counters
215 * This list comes from the Harvard people, not Intel.
217 #define PMC5_DATA_READ 0
218 #define PMC5_DATA_WRITE 1
219 #define PMC5_DATA_TLB_MISS 2
220 #define PMC5_DATA_READ_MISS 3
221 #define PMC5_DATA_WRITE_MISS 4
222 #define PMC5_WRITE_M_E 5
223 #define PMC5_DATA_LINES_WBACK 6
224 #define PMC5_DATA_CACHE_SNOOP 7
225 #define PMC5_DATA_CACHE_SNOOP_HIT 8
226 #define PMC5_MEM_ACCESS_BOTH 9
227 #define PMC5_BANK_CONFLICTS 10
228 #define PMC5_MISALIGNED_DATA 11
229 #define PMC5_INST_READ 12
230 #define PMC5_INST_TLB_MISS 13
231 #define PMC5_INST_CACHE_MISS 14
232 #define PMC5_SEGMENT_REG_LOAD 15
233 #define PMC5_BRANCHES 18
234 #define PMC5_BTB_HITS 19
235 #define PMC5_BRANCH_TAKEN 20
236 #define PMC5_PIPELINE_FLUSH 21
237 #define PMC5_INST_EXECUTED 22
238 #define PMC5_INST_EXECUTED_V 23
239 #define PMC5_BUS_UTILIZATION 24
240 #define PMC5_WRITE_BACKUP_STALL 25
241 #define PMC5_DATA_READ_STALL 26
242 #define PMC5_WRITE_E_M_STALL 27
243 #define PMC5_LOCKED_BUS 28
244 #define PMC5_IO_CYCLE 29
245 #define PMC5_NONCACHE_MEMORY 30
246 #define PMC5_ADDR_GEN_INTERLOCK 31
247 #define PMC5_FLOPS 34
248 #define PMC5_BP0_MATCH 35
249 #define PMC5_BP1_MATCH 36
250 #define PMC5_BP2_MATCH 37
251 #define PMC5_BP3_MATCH 38
252 #define PMC5_HW_INTR 39
253 #define PMC5_DATA_RW 40
254 #define PMC5_DATA_RW_MISS 41
256 #endif /* !_MACHINE_PERFMON_H_ */