2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $
34 * $DragonFly: src/sys/dev/netif/nge/if_nge.c,v 1.27 2005/05/31 14:11:42 joerg Exp $
38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver
39 * for FreeBSD. Datasheets are available from:
41 * http://www.national.com/ds/DP/DP83820.pdf
42 * http://www.national.com/ds/DP/DP83821.pdf
44 * These chips are used on several low cost gigabit ethernet NICs
45 * sold by D-Link, Addtron, SMC and Asante. Both parts are
46 * virtually the same, except the 83820 is a 64-bit/32-bit part,
47 * while the 83821 is 32-bit only.
49 * Many cards also use National gigE transceivers, such as the
50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
51 * contains a full register description that applies to all of these
54 * http://www.national.com/ds/DP/DP83861.pdf
56 * Written by Bill Paul <wpaul@bsdi.com>
57 * BSDi Open Source Solutions
61 * The NatSemi DP83820 and 83821 controllers are enhanced versions
62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
67 * matching buffers, one perfect address filter buffer and interrupt
68 * moderation. The 83820 supports both 64-bit and 32-bit addressing
69 * and data transfers: the 64-bit support can be toggled on or off
70 * via software. This affects the size of certain fields in the DMA
73 * There are two bugs/misfeatures in the 83820/83821 that I have
76 * - Receive buffers must be aligned on 64-bit boundaries, which means
77 * you must resort to copying data in order to fix up the payload
80 * - In order to transmit jumbo frames larger than 8170 bytes, you have
81 * to turn off transmit checksum offloading, because the chip can't
82 * compute the checksum on an outgoing frame unless it fits entirely
83 * within the TX FIFO, which is only 8192 bytes in size. If you have
84 * TX checksum offload enabled and you transmit attempt to transmit a
85 * frame larger than 8170 bytes, the transmitter will wedge.
87 * To work around the latter problem, TX checksum offload is disabled
88 * if the user selects an MTU larger than 8152 (8170 - 18).
91 #include <sys/param.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/socket.h>
100 #include <net/ifq_var.h>
101 #include <net/if_arp.h>
102 #include <net/ethernet.h>
103 #include <net/if_dl.h>
104 #include <net/if_media.h>
105 #include <net/if_types.h>
106 #include <net/vlan/if_vlan_var.h>
110 #include <vm/vm.h> /* for vtophys */
111 #include <vm/pmap.h> /* for vtophys */
112 #include <machine/bus.h>
113 #include <machine/resource.h>
115 #include <sys/rman.h>
117 #include <dev/netif/mii_layer/mii.h>
118 #include <dev/netif/mii_layer/miivar.h>
120 #include <bus/pci/pcireg.h>
121 #include <bus/pci/pcivar.h>
123 #define NGE_USEIOSPACE
125 #include "if_ngereg.h"
128 /* "controller miibus0" required. See GENERIC if you get errors here. */
129 #include "miibus_if.h"
131 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
134 * Various supported device vendors/types and their names.
136 static struct nge_type nge_devs[] = {
137 { NGE_VENDORID, NGE_DEVICEID,
138 "National Semiconductor Gigabit Ethernet" },
142 static int nge_probe(device_t);
143 static int nge_attach(device_t);
144 static int nge_detach(device_t);
146 static int nge_alloc_jumbo_mem(struct nge_softc *);
147 static void nge_free_jumbo_mem(struct nge_softc *);
148 static struct nge_jslot
149 *nge_jalloc(struct nge_softc *);
150 static void nge_jfree(void *);
151 static void nge_jref(void *);
153 static int nge_newbuf(struct nge_softc *, struct nge_desc *,
155 static int nge_encap(struct nge_softc *, struct mbuf *, uint32_t *);
156 static void nge_rxeof(struct nge_softc *);
157 static void nge_txeof(struct nge_softc *);
158 static void nge_intr(void *);
159 static void nge_tick(void *);
160 static void nge_start(struct ifnet *);
161 static int nge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
162 static void nge_init(void *);
163 static void nge_stop(struct nge_softc *);
164 static void nge_watchdog(struct ifnet *);
165 static void nge_shutdown(device_t);
166 static int nge_ifmedia_upd(struct ifnet *);
167 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
169 static void nge_delay(struct nge_softc *);
170 static void nge_eeprom_idle(struct nge_softc *);
171 static void nge_eeprom_putbyte(struct nge_softc *, int);
172 static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *);
173 static void nge_read_eeprom(struct nge_softc *, void *, int, int);
175 static void nge_mii_sync(struct nge_softc *);
176 static void nge_mii_send(struct nge_softc *, uint32_t, int);
177 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *);
178 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *);
180 static int nge_miibus_readreg(device_t, int, int);
181 static int nge_miibus_writereg(device_t, int, int, int);
182 static void nge_miibus_statchg(device_t);
184 static void nge_setmulti(struct nge_softc *);
185 static void nge_reset(struct nge_softc *);
186 static int nge_list_rx_init(struct nge_softc *);
187 static int nge_list_tx_init(struct nge_softc *);
188 #ifdef DEVICE_POLLING
189 static void nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
192 #ifdef NGE_USEIOSPACE
193 #define NGE_RES SYS_RES_IOPORT
194 #define NGE_RID NGE_PCI_LOIO
196 #define NGE_RES SYS_RES_MEMORY
197 #define NGE_RID NGE_PCI_LOMEM
200 static device_method_t nge_methods[] = {
201 /* Device interface */
202 DEVMETHOD(device_probe, nge_probe),
203 DEVMETHOD(device_attach, nge_attach),
204 DEVMETHOD(device_detach, nge_detach),
205 DEVMETHOD(device_shutdown, nge_shutdown),
208 DEVMETHOD(bus_print_child, bus_generic_print_child),
209 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
212 DEVMETHOD(miibus_readreg, nge_miibus_readreg),
213 DEVMETHOD(miibus_writereg, nge_miibus_writereg),
214 DEVMETHOD(miibus_statchg, nge_miibus_statchg),
219 static DEFINE_CLASS_0(nge, nge_driver, nge_methods, sizeof(struct nge_softc));
220 static devclass_t nge_devclass;
222 DECLARE_DUMMY_MODULE(if_nge);
223 MODULE_DEPEND(if_nge, miibus, 1, 1, 1);
224 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0);
225 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0);
227 #define NGE_SETBIT(sc, reg, x) \
228 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
230 #define NGE_CLRBIT(sc, reg, x) \
231 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
234 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
237 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
240 nge_delay(struct nge_softc *sc)
244 for (idx = (300 / 33) + 1; idx > 0; idx--)
245 CSR_READ_4(sc, NGE_CSR);
249 nge_eeprom_idle(struct nge_softc *sc)
253 SIO_SET(NGE_MEAR_EE_CSEL);
255 SIO_SET(NGE_MEAR_EE_CLK);
258 for (i = 0; i < 25; i++) {
259 SIO_CLR(NGE_MEAR_EE_CLK);
261 SIO_SET(NGE_MEAR_EE_CLK);
265 SIO_CLR(NGE_MEAR_EE_CLK);
267 SIO_CLR(NGE_MEAR_EE_CSEL);
269 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
273 * Send a read command and address to the EEPROM, check for ACK.
276 nge_eeprom_putbyte(struct nge_softc *sc, int addr)
280 d = addr | NGE_EECMD_READ;
283 * Feed in each bit and stobe the clock.
285 for (i = 0x400; i; i >>= 1) {
287 SIO_SET(NGE_MEAR_EE_DIN);
289 SIO_CLR(NGE_MEAR_EE_DIN);
291 SIO_SET(NGE_MEAR_EE_CLK);
293 SIO_CLR(NGE_MEAR_EE_CLK);
299 * Read a word of data stored in the EEPROM at address 'addr.'
302 nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest)
307 /* Force EEPROM to idle state. */
310 /* Enter EEPROM access mode. */
312 SIO_CLR(NGE_MEAR_EE_CLK);
314 SIO_SET(NGE_MEAR_EE_CSEL);
318 * Send address of word we want to read.
320 nge_eeprom_putbyte(sc, addr);
323 * Start reading bits from EEPROM.
325 for (i = 0x8000; i; i >>= 1) {
326 SIO_SET(NGE_MEAR_EE_CLK);
328 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
331 SIO_CLR(NGE_MEAR_EE_CLK);
335 /* Turn off EEPROM access mode. */
342 * Read a sequence of words from the EEPROM.
345 nge_read_eeprom(struct nge_softc *sc, void *dest, int off, int cnt)
348 uint16_t word = 0, *ptr;
350 for (i = 0; i < cnt; i++) {
351 nge_eeprom_getword(sc, off + i, &word);
352 ptr = (uint16_t *)((uint8_t *)dest + (i * 2));
358 * Sync the PHYs by setting data bit and strobing the clock 32 times.
361 nge_mii_sync(struct nge_softc *sc)
365 SIO_SET(NGE_MEAR_MII_DIR | NGE_MEAR_MII_DATA);
367 for (i = 0; i < 32; i++) {
368 SIO_SET(NGE_MEAR_MII_CLK);
370 SIO_CLR(NGE_MEAR_MII_CLK);
376 * Clock a series of bits through the MII.
379 nge_mii_send(struct nge_softc *sc, uint32_t bits, int cnt)
383 SIO_CLR(NGE_MEAR_MII_CLK);
385 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
387 SIO_SET(NGE_MEAR_MII_DATA);
389 SIO_CLR(NGE_MEAR_MII_DATA);
391 SIO_CLR(NGE_MEAR_MII_CLK);
393 SIO_SET(NGE_MEAR_MII_CLK);
398 * Read an PHY register through the MII.
401 nge_mii_readreg(struct nge_softc *sc, struct nge_mii_frame *frame)
408 * Set up frame for RX.
410 frame->mii_stdelim = NGE_MII_STARTDELIM;
411 frame->mii_opcode = NGE_MII_READOP;
412 frame->mii_turnaround = 0;
415 CSR_WRITE_4(sc, NGE_MEAR, 0);
420 SIO_SET(NGE_MEAR_MII_DIR);
425 * Send command/address info.
427 nge_mii_send(sc, frame->mii_stdelim, 2);
428 nge_mii_send(sc, frame->mii_opcode, 2);
429 nge_mii_send(sc, frame->mii_phyaddr, 5);
430 nge_mii_send(sc, frame->mii_regaddr, 5);
433 SIO_CLR((NGE_MEAR_MII_CLK | NGE_MEAR_MII_DATA));
435 SIO_SET(NGE_MEAR_MII_CLK);
439 SIO_CLR(NGE_MEAR_MII_DIR);
441 SIO_CLR(NGE_MEAR_MII_CLK);
443 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
444 SIO_SET(NGE_MEAR_MII_CLK);
448 * Now try reading data bits. If the ack failed, we still
449 * need to clock through 16 cycles to keep the PHY(s) in sync.
452 for(i = 0; i < 16; i++) {
453 SIO_CLR(NGE_MEAR_MII_CLK);
455 SIO_SET(NGE_MEAR_MII_CLK);
461 for (i = 0x8000; i; i >>= 1) {
462 SIO_CLR(NGE_MEAR_MII_CLK);
465 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
466 frame->mii_data |= i;
469 SIO_SET(NGE_MEAR_MII_CLK);
474 SIO_CLR(NGE_MEAR_MII_CLK);
476 SIO_SET(NGE_MEAR_MII_CLK);
487 * Write to a PHY register through the MII.
490 nge_mii_writereg(struct nge_softc *sc, struct nge_mii_frame *frame)
496 * Set up frame for TX.
499 frame->mii_stdelim = NGE_MII_STARTDELIM;
500 frame->mii_opcode = NGE_MII_WRITEOP;
501 frame->mii_turnaround = NGE_MII_TURNAROUND;
504 * Turn on data output.
506 SIO_SET(NGE_MEAR_MII_DIR);
510 nge_mii_send(sc, frame->mii_stdelim, 2);
511 nge_mii_send(sc, frame->mii_opcode, 2);
512 nge_mii_send(sc, frame->mii_phyaddr, 5);
513 nge_mii_send(sc, frame->mii_regaddr, 5);
514 nge_mii_send(sc, frame->mii_turnaround, 2);
515 nge_mii_send(sc, frame->mii_data, 16);
518 SIO_SET(NGE_MEAR_MII_CLK);
520 SIO_CLR(NGE_MEAR_MII_CLK);
526 SIO_CLR(NGE_MEAR_MII_DIR);
534 nge_miibus_readreg(device_t dev, int phy, int reg)
536 struct nge_softc *sc = device_get_softc(dev);
537 struct nge_mii_frame frame;
539 bzero((char *)&frame, sizeof(frame));
541 frame.mii_phyaddr = phy;
542 frame.mii_regaddr = reg;
543 nge_mii_readreg(sc, &frame);
545 return(frame.mii_data);
549 nge_miibus_writereg(device_t dev, int phy, int reg, int data)
551 struct nge_softc *sc = device_get_softc(dev);
552 struct nge_mii_frame frame;
554 bzero((char *)&frame, sizeof(frame));
556 frame.mii_phyaddr = phy;
557 frame.mii_regaddr = reg;
558 frame.mii_data = data;
559 nge_mii_writereg(sc, &frame);
565 nge_miibus_statchg(device_t dev)
567 struct nge_softc *sc = device_get_softc(dev);
568 struct mii_data *mii;
572 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
574 status = CSR_READ_4(sc, NGE_TBI_ANLPAR);
575 if (status == 0 || status & NGE_TBIANAR_FDX) {
576 NGE_SETBIT(sc, NGE_TX_CFG,
577 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
578 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
580 NGE_CLRBIT(sc, NGE_TX_CFG,
581 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
582 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
584 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
586 NGE_CLRBIT(sc, NGE_TX_CFG,
587 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
588 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
590 NGE_SETBIT(sc, NGE_TX_CFG,
591 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
592 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
595 mii = device_get_softc(sc->nge_miibus);
597 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
598 NGE_SETBIT(sc, NGE_TX_CFG,
599 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
600 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
602 NGE_CLRBIT(sc, NGE_TX_CFG,
603 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
604 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
607 /* If we have a 1000Mbps link, set the mode_1000 bit. */
608 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
609 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
610 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
612 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
618 nge_setmulti(struct nge_softc *sc)
620 struct ifnet *ifp = &sc->arpcom.ac_if;
621 struct ifmultiaddr *ifma;
622 uint32_t filtsave, h = 0, i;
625 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
626 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
627 NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH);
628 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
633 * We have to explicitly enable the multicast hash table
634 * on the NatSemi chip if we want to use it, which we do.
635 * We also have to tell it that we don't want to use the
636 * hash table for matching unicast addresses.
638 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
639 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
640 NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_UCHASH);
642 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
644 /* first, zot all the existing hash bits */
645 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
646 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
647 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
651 * From the 11 bits returned by the crc routine, the top 7
652 * bits represent the 16-bit word in the mcast hash table
653 * that needs to be updated, and the lower 4 bits represent
654 * which bit within that byte needs to be set.
656 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
657 if (ifma->ifma_addr->sa_family != AF_LINK)
659 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
660 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21;
661 index = (h >> 4) & 0x7F;
663 CSR_WRITE_4(sc, NGE_RXFILT_CTL,
664 NGE_FILTADDR_MCAST_LO + (index * 2));
665 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
668 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
672 nge_reset(struct nge_softc *sc)
676 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
678 for (i = 0; i < NGE_TIMEOUT; i++) {
679 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET) == 0)
683 if (i == NGE_TIMEOUT)
684 printf("nge%d: reset never completed\n", sc->nge_unit);
686 /* Wait a little while for the chip to get its brains in order. */
690 * If this is a NetSemi chip, make sure to clear
693 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
694 CSR_WRITE_4(sc, NGE_CLKRUN, 0);
698 * Probe for an NatSemi chip. Check the PCI vendor and device
699 * IDs against our list and return a device name if we find a match.
702 nge_probe(device_t dev)
705 uint16_t vendor, product;
707 vendor = pci_get_vendor(dev);
708 product = pci_get_device(dev);
710 for (t = nge_devs; t->nge_name != NULL; t++) {
711 if (vendor == t->nge_vid && product == t->nge_did) {
712 device_set_desc(dev, t->nge_name);
721 * Attach the interface. Allocate softc structures, do ifmedia
722 * setup and ethernet/BPF attach.
725 nge_attach(device_t dev)
727 struct nge_softc *sc;
729 uint8_t eaddr[ETHER_ADDR_LEN];
731 int error = 0, rid, s, unit;
732 const char *sep = "";
736 sc = device_get_softc(dev);
737 unit = device_get_unit(dev);
738 callout_init(&sc->nge_stat_timer);
741 * Handle power management nonsense.
743 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF;
744 if (command == 0x01) {
745 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4);
746 if (command & NGE_PSTATE_MASK) {
747 uint32_t iobase, membase, irq;
749 /* Save important PCI config data. */
750 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4);
751 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4);
752 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4);
754 /* Reset the power state. */
755 printf("nge%d: chip is in D%d power mode "
756 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK);
757 command &= 0xFFFFFFFC;
758 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4);
760 /* Restore PCI config data. */
761 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4);
762 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4);
763 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4);
768 * Map control/status registers.
770 command = pci_read_config(dev, PCIR_COMMAND, 4);
771 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
772 pci_write_config(dev, PCIR_COMMAND, command, 4);
773 command = pci_read_config(dev, PCIR_COMMAND, 4);
775 #ifdef NGE_USEIOSPACE
776 if (!(command & PCIM_CMD_PORTEN)) {
777 printf("nge%d: failed to enable I/O ports!\n", unit);
782 if (!(command & PCIM_CMD_MEMEN)) {
783 printf("nge%d: failed to enable memory mapping!\n", unit);
790 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE);
792 if (sc->nge_res == NULL) {
793 printf("nge%d: couldn't map ports/memory\n", unit);
798 sc->nge_btag = rman_get_bustag(sc->nge_res);
799 sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
801 /* Allocate interrupt */
803 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
804 RF_SHAREABLE | RF_ACTIVE);
806 if (sc->nge_irq == NULL) {
807 printf("nge%d: couldn't map interrupt\n", unit);
808 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
813 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET,
814 nge_intr, sc, &sc->nge_intrhand, NULL);
817 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
818 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
819 printf("nge%d: couldn't set up irq\n", unit);
823 /* Reset the adapter. */
827 * Get station address from the EEPROM.
829 nge_read_eeprom(sc, &eaddr[4], NGE_EE_NODEADDR, 1);
830 nge_read_eeprom(sc, &eaddr[2], NGE_EE_NODEADDR + 1, 1);
831 nge_read_eeprom(sc, &eaddr[0], NGE_EE_NODEADDR + 2, 1);
835 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
836 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
838 if (sc->nge_ldata == NULL) {
839 printf("nge%d: no memory for list buffers!\n", unit);
840 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
841 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
842 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
846 bzero(sc->nge_ldata, sizeof(struct nge_list_data));
848 /* Try to allocate memory for jumbo buffers. */
849 if (nge_alloc_jumbo_mem(sc)) {
850 printf("nge%d: jumbo buffer allocation failed\n",
852 contigfree(sc->nge_ldata,
853 sizeof(struct nge_list_data), M_DEVBUF);
854 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
855 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
856 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
861 ifp = &sc->arpcom.ac_if;
863 if_initname(ifp, "nge", unit);
864 ifp->if_mtu = ETHERMTU;
865 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
866 ifp->if_ioctl = nge_ioctl;
867 ifp->if_start = nge_start;
868 #ifdef DEVICE_POLLING
869 ifp->if_poll = nge_poll;
871 ifp->if_watchdog = nge_watchdog;
872 ifp->if_init = nge_init;
873 ifp->if_baudrate = 1000000000;
874 ifq_set_maxlen(&ifp->if_snd, NGE_TX_LIST_CNT - 1);
875 ifq_set_ready(&ifp->if_snd);
876 ifp->if_hwassist = NGE_CSUM_FEATURES;
877 ifp->if_capabilities = IFCAP_HWCSUM;
878 ifp->if_capenable = ifp->if_capabilities;
883 if (mii_phy_probe(dev, &sc->nge_miibus,
884 nge_ifmedia_upd, nge_ifmedia_sts)) {
885 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
887 device_printf(dev, "Using TBI\n");
889 sc->nge_miibus = dev;
891 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd,
893 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
894 #define PRINT(s) printf("%s%s", sep, s); sep = ", "
895 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
896 device_printf(dev, " ");
897 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
899 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
900 PRINT("1000baseSX-FDX");
901 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
907 ifmedia_set(&sc->nge_ifmedia,
908 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
910 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
912 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
913 | NGE_GPIO_GP3_OUTENB
914 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
917 printf("nge%d: MII without any PHY!\n", sc->nge_unit);
918 nge_free_jumbo_mem(sc);
919 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
920 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
921 bus_release_resource(dev, NGE_RES, NGE_RID,
929 * Call MI attach routine.
931 ether_ifattach(ifp, eaddr);
940 nge_detach(device_t dev)
942 struct nge_softc *sc;
948 sc = device_get_softc(dev);
949 ifp = &sc->arpcom.ac_if;
955 bus_generic_detach(dev);
957 device_delete_child(dev, sc->nge_miibus);
959 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
960 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
961 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
963 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF);
964 nge_free_jumbo_mem(sc);
972 * Initialize the transmit descriptors.
975 nge_list_tx_init(struct nge_softc *sc)
977 struct nge_list_data *ld;
978 struct nge_ring_data *cd;
984 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
985 if (i == (NGE_TX_LIST_CNT - 1)) {
986 ld->nge_tx_list[i].nge_nextdesc =
988 ld->nge_tx_list[i].nge_next =
989 vtophys(&ld->nge_tx_list[0]);
991 ld->nge_tx_list[i].nge_nextdesc =
992 &ld->nge_tx_list[i + 1];
993 ld->nge_tx_list[i].nge_next =
994 vtophys(&ld->nge_tx_list[i + 1]);
996 ld->nge_tx_list[i].nge_mbuf = NULL;
997 ld->nge_tx_list[i].nge_ptr = 0;
998 ld->nge_tx_list[i].nge_ctl = 0;
1001 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
1008 * Initialize the RX descriptors and allocate mbufs for them. Note that
1009 * we arrange the descriptors in a closed ring, so that the last descriptor
1010 * points back to the first.
1013 nge_list_rx_init(struct nge_softc *sc)
1015 struct nge_list_data *ld;
1016 struct nge_ring_data *cd;
1020 cd = &sc->nge_cdata;
1022 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
1023 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
1025 if (i == (NGE_RX_LIST_CNT - 1)) {
1026 ld->nge_rx_list[i].nge_nextdesc =
1027 &ld->nge_rx_list[0];
1028 ld->nge_rx_list[i].nge_next =
1029 vtophys(&ld->nge_rx_list[0]);
1031 ld->nge_rx_list[i].nge_nextdesc =
1032 &ld->nge_rx_list[i + 1];
1033 ld->nge_rx_list[i].nge_next =
1034 vtophys(&ld->nge_rx_list[i + 1]);
1038 cd->nge_rx_prod = 0;
1044 * Initialize an RX descriptor and attach an MBUF cluster.
1047 nge_newbuf(struct nge_softc *sc, struct nge_desc *c, struct mbuf *m)
1049 struct mbuf *m_new = NULL;
1050 struct nge_jslot *buf;
1053 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1054 if (m_new == NULL) {
1055 printf("nge%d: no memory for rx list "
1056 "-- packet dropped!\n", sc->nge_unit);
1060 /* Allocate the jumbo buffer */
1061 buf = nge_jalloc(sc);
1064 printf("nge%d: jumbo allocation failed "
1065 "-- packet dropped!\n", sc->nge_unit);
1070 /* Attach the buffer to the mbuf */
1071 m_new->m_ext.ext_arg = buf;
1072 m_new->m_ext.ext_buf = buf->nge_buf;
1073 m_new->m_ext.ext_free = nge_jfree;
1074 m_new->m_ext.ext_ref = nge_jref;
1075 m_new->m_ext.ext_size = NGE_JUMBO_FRAMELEN;
1077 m_new->m_data = m_new->m_ext.ext_buf;
1078 m_new->m_flags |= M_EXT;
1079 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1082 m_new->m_len = m_new->m_pkthdr.len = NGE_JLEN;
1083 m_new->m_data = m_new->m_ext.ext_buf;
1086 m_adj(m_new, sizeof(uint64_t));
1088 c->nge_mbuf = m_new;
1089 c->nge_ptr = vtophys(mtod(m_new, caddr_t));
1090 c->nge_ctl = m_new->m_len;
1097 nge_alloc_jumbo_mem(struct nge_softc *sc)
1101 struct nge_jslot *entry;
1103 /* Grab a big chunk o' storage. */
1104 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF,
1105 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1107 if (sc->nge_cdata.nge_jumbo_buf == NULL) {
1108 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit);
1112 SLIST_INIT(&sc->nge_jfree_listhead);
1115 * Now divide it up into 9K pieces and save the addresses
1118 ptr = sc->nge_cdata.nge_jumbo_buf;
1119 for (i = 0; i < NGE_JSLOTS; i++) {
1120 entry = &sc->nge_cdata.nge_jslots[i];
1122 entry->nge_buf = ptr;
1123 entry->nge_inuse = 0;
1124 entry->nge_slot = i;
1125 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jslot_link);
1133 nge_free_jumbo_mem(struct nge_softc *sc)
1135 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF);
1139 * Allocate a jumbo buffer.
1141 static struct nge_jslot *
1142 nge_jalloc(struct nge_softc *sc)
1144 struct nge_jslot *entry;
1146 entry = SLIST_FIRST(&sc->nge_jfree_listhead);
1148 if (entry == NULL) {
1150 printf("nge%d: no free jumbo buffers\n", sc->nge_unit);
1155 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jslot_link);
1156 entry->nge_inuse = 1;
1162 * Adjust usage count on a jumbo buffer. In general this doesn't
1163 * get used much because our jumbo buffers don't get passed around
1164 * a lot, but it's implemented for correctness.
1169 struct nge_jslot *entry = (struct nge_jslot *)arg;
1170 struct nge_softc *sc = entry->nge_sc;
1173 panic("nge_jref: can't find softc pointer!");
1175 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry)
1176 panic("nge_jref: asked to reference buffer "
1177 "that we don't manage!");
1178 else if (entry->nge_inuse == 0)
1179 panic("nge_jref: buffer already free!");
1185 * Release a jumbo buffer.
1188 nge_jfree(void *arg)
1190 struct nge_jslot *entry = (struct nge_jslot *)arg;
1191 struct nge_softc *sc = entry->nge_sc;
1194 panic("nge_jref: can't find softc pointer!");
1196 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry)
1197 panic("nge_jref: asked to reference buffer "
1198 "that we don't manage!");
1199 else if (entry->nge_inuse == 0)
1200 panic("nge_jref: buffer already free!");
1201 else if (--entry->nge_inuse == 0)
1202 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jslot_link);
1205 * A frame has been uploaded: pass the resulting mbuf chain up to
1206 * the higher level protocols.
1209 nge_rxeof(struct nge_softc *sc)
1212 struct ifnet *ifp = &sc->arpcom.ac_if;
1213 struct nge_desc *cur_rx;
1214 int i, total_len = 0;
1217 i = sc->nge_cdata.nge_rx_prod;
1219 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
1220 struct mbuf *m0 = NULL;
1223 #ifdef DEVICE_POLLING
1224 if (ifp->if_flags & IFF_POLLING) {
1225 if (sc->rxcycles <= 0)
1229 #endif /* DEVICE_POLLING */
1231 cur_rx = &sc->nge_ldata->nge_rx_list[i];
1232 rxstat = cur_rx->nge_rxstat;
1233 extsts = cur_rx->nge_extsts;
1234 m = cur_rx->nge_mbuf;
1235 cur_rx->nge_mbuf = NULL;
1236 total_len = NGE_RXBYTES(cur_rx);
1237 NGE_INC(i, NGE_RX_LIST_CNT);
1239 * If an error occurs, update stats, clear the
1240 * status word and leave the mbuf cluster in place:
1241 * it should simply get re-used next time this descriptor
1242 * comes up in the ring.
1244 if ((rxstat & NGE_CMDSTS_PKT_OK) == 0) {
1246 nge_newbuf(sc, cur_rx, m);
1251 * Ok. NatSemi really screwed up here. This is the
1252 * only gigE chip I know of with alignment constraints
1253 * on receive buffers. RX buffers must be 64-bit aligned.
1257 * By popular demand, ignore the alignment problems
1258 * on the Intel x86 platform. The performance hit
1259 * incurred due to unaligned accesses is much smaller
1260 * than the hit produced by forcing buffer copies all
1261 * the time, especially with jumbo frames. We still
1262 * need to fix up the alignment everywhere else though.
1264 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
1266 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1267 total_len + ETHER_ALIGN, 0, ifp, NULL);
1268 nge_newbuf(sc, cur_rx, m);
1270 printf("nge%d: no receive buffers "
1271 "available -- packet dropped!\n",
1276 m_adj(m0, ETHER_ALIGN);
1280 m->m_pkthdr.rcvif = ifp;
1281 m->m_pkthdr.len = m->m_len = total_len;
1287 /* Do IP checksum checking. */
1288 if (extsts & NGE_RXEXTSTS_IPPKT)
1289 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1290 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
1291 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1292 if ((extsts & NGE_RXEXTSTS_TCPPKT &&
1293 (extsts & NGE_RXEXTSTS_TCPCSUMERR) == 0) ||
1294 (extsts & NGE_RXEXTSTS_UDPPKT &&
1295 (extsts & NGE_RXEXTSTS_UDPCSUMERR) == 0)) {
1296 m->m_pkthdr.csum_flags |=
1297 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1298 m->m_pkthdr.csum_data = 0xffff;
1302 * If we received a packet with a vlan tag, pass it
1303 * to vlan_input() instead of ether_input().
1305 if (extsts & NGE_RXEXTSTS_VLANPKT)
1306 VLAN_INPUT_TAG(m, extsts & NGE_RXEXTSTS_VTCI);
1308 (*ifp->if_input)(ifp, m);
1311 sc->nge_cdata.nge_rx_prod = i;
1315 * A frame was downloaded to the chip. It's safe for us to clean up
1319 nge_txeof(struct nge_softc *sc)
1321 struct ifnet *ifp = &sc->arpcom.ac_if;
1322 struct nge_desc *cur_tx = NULL;
1325 /* Clear the timeout timer. */
1329 * Go through our tx list and free mbufs for those
1330 * frames that have been transmitted.
1332 idx = sc->nge_cdata.nge_tx_cons;
1333 while (idx != sc->nge_cdata.nge_tx_prod) {
1334 cur_tx = &sc->nge_ldata->nge_tx_list[idx];
1336 if (NGE_OWNDESC(cur_tx))
1339 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
1340 sc->nge_cdata.nge_tx_cnt--;
1341 NGE_INC(idx, NGE_TX_LIST_CNT);
1345 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
1347 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
1348 ifp->if_collisions++;
1349 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
1350 ifp->if_collisions++;
1353 ifp->if_collisions +=
1354 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16;
1357 if (cur_tx->nge_mbuf != NULL) {
1358 m_freem(cur_tx->nge_mbuf);
1359 cur_tx->nge_mbuf = NULL;
1362 sc->nge_cdata.nge_tx_cnt--;
1363 NGE_INC(idx, NGE_TX_LIST_CNT);
1367 sc->nge_cdata.nge_tx_cons = idx;
1370 ifp->if_flags &= ~IFF_OACTIVE;
1376 struct nge_softc *sc = xsc;
1377 struct ifnet *ifp = &sc->arpcom.ac_if;
1378 struct mii_data *mii;
1384 if (sc->nge_link == 0) {
1385 if (CSR_READ_4(sc, NGE_TBI_BMSR)
1386 & NGE_TBIBMSR_ANEG_DONE) {
1387 printf("nge%d: gigabit link up\n",
1389 nge_miibus_statchg(sc->nge_miibus);
1391 if (!ifq_is_empty(&ifp->if_snd))
1396 mii = device_get_softc(sc->nge_miibus);
1399 if (sc->nge_link == 0) {
1400 if (mii->mii_media_status & IFM_ACTIVE &&
1401 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1403 if (IFM_SUBTYPE(mii->mii_media_active)
1405 printf("nge%d: gigabit link up\n",
1407 if (!ifq_is_empty(&ifp->if_snd))
1412 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
1417 #ifdef DEVICE_POLLING
1420 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1422 struct nge_softc *sc = ifp->if_softc;
1426 /* disable interrupts */
1427 CSR_WRITE_4(sc, NGE_IER, 0);
1429 case POLL_DEREGISTER:
1430 /* enable interrupts */
1431 CSR_WRITE_4(sc, NGE_IER, 1);
1435 * On the nge, reading the status register also clears it.
1436 * So before returning to intr mode we must make sure that all
1437 * possible pending sources of interrupts have been served.
1438 * In practice this means run to completion the *eof routines,
1439 * and then call the interrupt routine
1441 sc->rxcycles = count;
1444 if (!ifq_is_empty(&ifp->if_snd))
1447 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1450 /* Reading the ISR register clears all interrupts. */
1451 status = CSR_READ_4(sc, NGE_ISR);
1453 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW))
1456 if (status & (NGE_ISR_RX_IDLE))
1457 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1459 if (status & NGE_ISR_SYSERR) {
1468 #endif /* DEVICE_POLLING */
1473 struct nge_softc *sc = arg;
1474 struct ifnet *ifp = &sc->arpcom.ac_if;
1477 /* Supress unwanted interrupts */
1478 if (!(ifp->if_flags & IFF_UP)) {
1483 /* Disable interrupts. */
1484 CSR_WRITE_4(sc, NGE_IER, 0);
1486 /* Data LED on for TBI mode */
1488 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1489 | NGE_GPIO_GP3_OUT);
1492 /* Reading the ISR register clears all interrupts. */
1493 status = CSR_READ_4(sc, NGE_ISR);
1495 if ((status & NGE_INTRS) == 0)
1498 if ((status & NGE_ISR_TX_DESC_OK) ||
1499 (status & NGE_ISR_TX_ERR) ||
1500 (status & NGE_ISR_TX_OK) ||
1501 (status & NGE_ISR_TX_IDLE))
1504 if ((status & NGE_ISR_RX_DESC_OK) ||
1505 (status & NGE_ISR_RX_ERR) ||
1506 (status & NGE_ISR_RX_OFLOW) ||
1507 (status & NGE_ISR_RX_FIFO_OFLOW) ||
1508 (status & NGE_ISR_RX_IDLE) ||
1509 (status & NGE_ISR_RX_OK))
1512 if ((status & NGE_ISR_RX_IDLE))
1513 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1515 if (status & NGE_ISR_SYSERR) {
1517 ifp->if_flags &= ~IFF_RUNNING;
1522 /* mii_tick should only be called once per second */
1523 if (status & NGE_ISR_PHY_INTR) {
1530 /* Re-enable interrupts. */
1531 CSR_WRITE_4(sc, NGE_IER, 1);
1533 if (!ifq_is_empty(&ifp->if_snd))
1536 /* Data LED off for TBI mode */
1539 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1540 & ~NGE_GPIO_GP3_OUT);
1544 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1545 * pointers to the fragment pointers.
1548 nge_encap(struct nge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1550 struct nge_desc *f = NULL;
1552 int frag, cur, cnt = 0;
1553 struct ifvlan *ifv = NULL;
1555 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1556 m_head->m_pkthdr.rcvif != NULL &&
1557 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1558 ifv = m_head->m_pkthdr.rcvif->if_softc;
1561 * Start packing the mbufs in this chain into
1562 * the fragment pointers. Stop when we run out
1563 * of fragments or hit the end of the mbuf chain.
1566 cur = frag = *txidx;
1568 for (m = m_head; m != NULL; m = m->m_next) {
1569 if (m->m_len != 0) {
1570 if ((NGE_TX_LIST_CNT -
1571 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2)
1573 f = &sc->nge_ldata->nge_tx_list[frag];
1574 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len;
1575 f->nge_ptr = vtophys(mtod(m, vm_offset_t));
1577 f->nge_ctl |= NGE_CMDSTS_OWN;
1579 NGE_INC(frag, NGE_TX_LIST_CNT);
1587 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0;
1588 if (m_head->m_pkthdr.csum_flags) {
1589 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1590 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1591 NGE_TXEXTSTS_IPCSUM;
1592 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1593 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1594 NGE_TXEXTSTS_TCPCSUM;
1595 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1596 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1597 NGE_TXEXTSTS_UDPCSUM;
1601 sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
1602 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag);
1605 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head;
1606 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE;
1607 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN;
1608 sc->nge_cdata.nge_tx_cnt += cnt;
1615 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1616 * to the mbuf data regions directly in the transmit lists. We also save a
1617 * copy of the pointers since the transmit list fragment pointers are
1618 * physical addresses.
1622 nge_start(struct ifnet *ifp)
1624 struct nge_softc *sc = ifp->if_softc;
1625 struct mbuf *m_head = NULL;
1631 idx = sc->nge_cdata.nge_tx_prod;
1633 if (ifp->if_flags & IFF_OACTIVE)
1636 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) {
1637 m_head = ifq_poll(&ifp->if_snd);
1641 if (nge_encap(sc, m_head, &idx)) {
1642 ifp->if_flags |= IFF_OACTIVE;
1645 m_head = ifq_dequeue(&ifp->if_snd);
1647 BPF_MTAP(ifp, m_head);
1651 sc->nge_cdata.nge_tx_prod = idx;
1652 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
1655 * Set a timeout in case the chip goes out to lunch.
1663 struct nge_softc *sc = xsc;
1664 struct ifnet *ifp = &sc->arpcom.ac_if;
1665 struct mii_data *mii;
1668 if (ifp->if_flags & IFF_RUNNING)
1674 * Cancel pending I/O and free all RX/TX buffers.
1677 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
1682 mii = device_get_softc(sc->nge_miibus);
1684 /* Set MAC address */
1685 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
1686 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1687 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1688 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
1689 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1690 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1691 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
1692 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1693 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1695 /* Init circular RX list. */
1696 if (nge_list_rx_init(sc) == ENOBUFS) {
1697 printf("nge%d: initialization failed: no "
1698 "memory for rx buffers\n", sc->nge_unit);
1705 * Init tx descriptors.
1707 nge_list_tx_init(sc);
1710 * For the NatSemi chip, we have to explicitly enable the
1711 * reception of ARP frames, as well as turn on the 'perfect
1712 * match' filter where we store the station address, otherwise
1713 * we won't receive unicasts meant for this host.
1715 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
1716 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
1718 /* If we want promiscuous mode, set the allframes bit. */
1719 if (ifp->if_flags & IFF_PROMISC)
1720 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1722 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1725 * Set the capture broadcast bit to capture broadcast frames.
1727 if (ifp->if_flags & IFF_BROADCAST)
1728 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1730 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1733 * Load the multicast filter.
1737 /* Turn the receive filter on */
1738 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
1741 * Load the address of the RX and TX lists.
1743 CSR_WRITE_4(sc, NGE_RX_LISTPTR,
1744 vtophys(&sc->nge_ldata->nge_rx_list[0]));
1745 CSR_WRITE_4(sc, NGE_TX_LISTPTR,
1746 vtophys(&sc->nge_ldata->nge_tx_list[0]));
1748 /* Set RX configuration */
1749 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
1751 * Enable hardware checksum validation for all IPv4
1752 * packets, do not reject packets with bad checksums.
1754 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
1757 * Tell the chip to detect and strip VLAN tag info from
1758 * received frames. The tag will be provided in the extsts
1759 * field in the RX descriptors.
1761 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
1762 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
1764 /* Set TX configuration */
1765 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
1768 * Enable TX IPv4 checksumming on a per-packet basis.
1770 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
1773 * Tell the chip to insert VLAN tags on a per-packet basis as
1774 * dictated by the code in the frame encapsulation routine.
1776 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
1778 /* Set full/half duplex mode. */
1780 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1782 NGE_SETBIT(sc, NGE_TX_CFG,
1783 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1784 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1786 NGE_CLRBIT(sc, NGE_TX_CFG,
1787 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1788 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1791 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1792 NGE_SETBIT(sc, NGE_TX_CFG,
1793 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1794 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1796 NGE_CLRBIT(sc, NGE_TX_CFG,
1797 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1798 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1803 * Enable the delivery of PHY interrupts based on
1804 * link/speed/duplex status changes. Also enable the
1805 * extsts field in the DMA descriptors (needed for
1806 * TCP/IP checksum offload on transmit).
1808 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD |
1809 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB);
1812 * Configure interrupt holdoff (moderation). We can
1813 * have the chip delay interrupt delivery for a certain
1814 * period. Units are in 100us, and the max setting
1815 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
1817 CSR_WRITE_4(sc, NGE_IHR, 0x01);
1820 * Enable interrupts.
1822 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
1823 #ifdef DEVICE_POLLING
1825 * ... only enable interrupts if we are not polling, make sure
1826 * they are off otherwise.
1828 if (ifp->if_flags & IFF_POLLING)
1829 CSR_WRITE_4(sc, NGE_IER, 0);
1831 #endif /* DEVICE_POLLING */
1832 CSR_WRITE_4(sc, NGE_IER, 1);
1834 /* Enable receiver and transmitter. */
1835 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE);
1836 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1838 nge_ifmedia_upd(ifp);
1840 ifp->if_flags |= IFF_RUNNING;
1841 ifp->if_flags &= ~IFF_OACTIVE;
1847 * Set media options.
1850 nge_ifmedia_upd(struct ifnet *ifp)
1852 struct nge_softc *sc = ifp->if_softc;
1853 struct mii_data *mii;
1856 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1858 CSR_WRITE_4(sc, NGE_TBI_ANAR,
1859 CSR_READ_4(sc, NGE_TBI_ANAR)
1860 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX
1861 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2);
1862 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG
1863 | NGE_TBIBMCR_RESTART_ANEG);
1864 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG);
1865 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media
1866 & IFM_GMASK) == IFM_FDX) {
1867 NGE_SETBIT(sc, NGE_TX_CFG,
1868 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1869 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1871 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1872 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1874 NGE_CLRBIT(sc, NGE_TX_CFG,
1875 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1876 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1878 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1879 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1882 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1883 & ~NGE_GPIO_GP3_OUT);
1885 mii = device_get_softc(sc->nge_miibus);
1887 if (mii->mii_instance) {
1888 struct mii_softc *miisc;
1889 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1890 miisc = LIST_NEXT(miisc, mii_list))
1891 mii_phy_reset(miisc);
1900 * Report current media status.
1903 nge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1905 struct nge_softc *sc = ifp->if_softc;
1906 struct mii_data *mii;
1909 ifmr->ifm_status = IFM_AVALID;
1910 ifmr->ifm_active = IFM_ETHER;
1912 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE)
1913 ifmr->ifm_status |= IFM_ACTIVE;
1914 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK)
1915 ifmr->ifm_active |= IFM_LOOP;
1916 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) {
1917 ifmr->ifm_active |= IFM_NONE;
1918 ifmr->ifm_status = 0;
1921 ifmr->ifm_active |= IFM_1000_SX;
1922 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1924 ifmr->ifm_active |= IFM_AUTO;
1925 if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1926 & NGE_TBIANAR_FDX) {
1927 ifmr->ifm_active |= IFM_FDX;
1928 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1929 & NGE_TBIANAR_HDX) {
1930 ifmr->ifm_active |= IFM_HDX;
1932 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1934 ifmr->ifm_active |= IFM_FDX;
1936 ifmr->ifm_active |= IFM_HDX;
1939 mii = device_get_softc(sc->nge_miibus);
1941 ifmr->ifm_active = mii->mii_media_active;
1942 ifmr->ifm_status = mii->mii_media_status;
1947 nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1949 struct nge_softc *sc = ifp->if_softc;
1950 struct ifreq *ifr = (struct ifreq *) data;
1951 struct mii_data *mii;
1958 if (ifr->ifr_mtu > NGE_JUMBO_MTU) {
1961 ifp->if_mtu = ifr->ifr_mtu;
1963 * Workaround: if the MTU is larger than
1964 * 8152 (TX FIFO size minus 64 minus 18), turn off
1965 * TX checksum offloading.
1967 if (ifr->ifr_mtu >= 8152)
1968 ifp->if_hwassist = 0;
1970 ifp->if_hwassist = NGE_CSUM_FEATURES;
1974 if (ifp->if_flags & IFF_UP) {
1975 if (ifp->if_flags & IFF_RUNNING &&
1976 ifp->if_flags & IFF_PROMISC &&
1977 !(sc->nge_if_flags & IFF_PROMISC)) {
1978 NGE_SETBIT(sc, NGE_RXFILT_CTL,
1979 NGE_RXFILTCTL_ALLPHYS|
1980 NGE_RXFILTCTL_ALLMULTI);
1981 } else if (ifp->if_flags & IFF_RUNNING &&
1982 !(ifp->if_flags & IFF_PROMISC) &&
1983 sc->nge_if_flags & IFF_PROMISC) {
1984 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
1985 NGE_RXFILTCTL_ALLPHYS);
1986 if (!(ifp->if_flags & IFF_ALLMULTI))
1987 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
1988 NGE_RXFILTCTL_ALLMULTI);
1990 ifp->if_flags &= ~IFF_RUNNING;
1994 if (ifp->if_flags & IFF_RUNNING)
1997 sc->nge_if_flags = ifp->if_flags;
2008 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia,
2011 mii = device_get_softc(sc->nge_miibus);
2012 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
2017 error = ether_ioctl(ifp, command, data);
2027 nge_watchdog(struct ifnet *ifp)
2029 struct nge_softc *sc = ifp->if_softc;
2032 printf("nge%d: watchdog timeout\n", sc->nge_unit);
2036 ifp->if_flags &= ~IFF_RUNNING;
2039 if (!ifq_is_empty(&ifp->if_snd))
2044 * Stop the adapter and free any mbufs allocated to the
2048 nge_stop(struct nge_softc *sc)
2050 struct ifnet *ifp = &sc->arpcom.ac_if;
2051 struct ifmedia_entry *ifm;
2052 struct mii_data *mii;
2059 mii = device_get_softc(sc->nge_miibus);
2061 callout_stop(&sc->nge_stat_timer);
2062 CSR_WRITE_4(sc, NGE_IER, 0);
2063 CSR_WRITE_4(sc, NGE_IMR, 0);
2064 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
2066 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0);
2067 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0);
2070 * Isolate/power down the PHY, but leave the media selection
2071 * unchanged so that things will be put back to normal when
2072 * we bring the interface back up.
2074 itmp = ifp->if_flags;
2075 ifp->if_flags |= IFF_UP;
2078 ifm = sc->nge_ifmedia.ifm_cur;
2080 ifm = mii->mii_media.ifm_cur;
2082 mtmp = ifm->ifm_media;
2083 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2087 ifm->ifm_media = mtmp;
2088 ifp->if_flags = itmp;
2093 * Free data in the RX lists.
2095 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
2096 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) {
2097 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf);
2098 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL;
2101 bzero(&sc->nge_ldata->nge_rx_list,
2102 sizeof(sc->nge_ldata->nge_rx_list));
2105 * Free the TX list buffers.
2107 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
2108 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) {
2109 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf);
2110 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL;
2114 bzero(&sc->nge_ldata->nge_tx_list,
2115 sizeof(sc->nge_ldata->nge_tx_list));
2117 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2121 * Stop all chip I/O so that the kernel's probe routines don't
2122 * get confused by errant DMAs when rebooting.
2125 nge_shutdown(device_t dev)
2127 struct nge_softc *sc = device_get_softc(dev);