3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.12 2005/05/25 01:44:27 dillon Exp $
40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
64 * o TCP/IP checksum offload for both RX and TX
66 * o High and normal priority transmit DMA rings
68 * o VLAN tag insertion and extraction
70 * o TCP large send (segmentation offload)
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
85 * o GMII and TBI ports/registers for interfacing with copper
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
91 * o Slight differences in register layout from the 8139C+
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7.5K, so the max MTU possible with this
111 * driver is 7500 bytes.
114 #include <sys/param.h>
115 #include <sys/endian.h>
116 #include <sys/systm.h>
117 #include <sys/sockio.h>
118 #include <sys/mbuf.h>
119 #include <sys/malloc.h>
120 #include <sys/module.h>
121 #include <sys/kernel.h>
122 #include <sys/socket.h>
125 #include <net/ifq_var.h>
126 #include <net/if_arp.h>
127 #include <net/ethernet.h>
128 #include <net/if_dl.h>
129 #include <net/if_media.h>
130 #include <net/if_types.h>
131 #include <net/vlan/if_vlan_var.h>
135 #include <machine/bus_pio.h>
136 #include <machine/bus_memio.h>
137 #include <machine/bus.h>
138 #include <machine/resource.h>
140 #include <sys/rman.h>
142 #include <dev/netif/mii_layer/mii.h>
143 #include <dev/netif/mii_layer/miivar.h>
145 #include <bus/pci/pcireg.h>
146 #include <bus/pci/pcivar.h>
148 /* "controller miibus0" required. See GENERIC if you get errors here. */
149 #include "miibus_if.h"
151 #include <dev/netif/re/if_rereg.h>
154 * The hardware supports checksumming but, as usual, some chipsets screw it
155 * all up and produce bogus packets, so we disable it by default.
157 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
158 #define RE_DISABLE_HWCSUM
161 * Various supported device vendors/types and their names.
163 static struct re_type re_devs[] = {
164 { RT_VENDORID, RT_DEVICEID_8139, RE_HWREV_8139CPLUS,
165 "RealTek 8139C+ 10/100BaseTX" },
166 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8169,
167 "RealTek 8169 Gigabit Ethernet" },
168 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8169S,
169 "RealTek 8169S Single-chip Gigabit Ethernet" },
170 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8110S,
171 "RealTek 8110S Single-chip Gigabit Ethernet" },
175 static struct re_hwrev re_hwrevs[] = {
176 { RE_HWREV_8139CPLUS, RE_8139CPLUS, "C+"},
177 { RE_HWREV_8169, RE_8169, "8169"},
178 { RE_HWREV_8169S, RE_8169, "8169S"},
179 { RE_HWREV_8110S, RE_8169, "8110S"},
183 static int re_probe(device_t);
184 static int re_attach(device_t);
185 static int re_detach(device_t);
187 static int re_encap(struct re_softc *, struct mbuf **, int *, int *);
189 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int);
190 static void re_dma_map_desc(void *, bus_dma_segment_t *, int,
192 static int re_allocmem(device_t, struct re_softc *);
193 static int re_newbuf(struct re_softc *, int, struct mbuf *);
194 static int re_rx_list_init(struct re_softc *);
195 static int re_tx_list_init(struct re_softc *);
196 static void re_rxeof(struct re_softc *);
197 static void re_txeof(struct re_softc *);
198 static void re_intr(void *);
199 static void re_tick(void *);
200 static void re_start(struct ifnet *);
201 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
202 static void re_init(void *);
203 static void re_stop(struct re_softc *);
204 static void re_watchdog(struct ifnet *);
205 static int re_suspend(device_t);
206 static int re_resume(device_t);
207 static void re_shutdown(device_t);
208 static int re_ifmedia_upd(struct ifnet *);
209 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
211 static void re_eeprom_putbyte(struct re_softc *, int);
212 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
213 static void re_read_eeprom(struct re_softc *, caddr_t, int, int, int);
214 static int re_gmii_readreg(device_t, int, int);
215 static int re_gmii_writereg(device_t, int, int, int);
217 static int re_miibus_readreg(device_t, int, int);
218 static int re_miibus_writereg(device_t, int, int, int);
219 static void re_miibus_statchg(device_t);
221 static void re_setmulti(struct re_softc *);
222 static void re_reset(struct re_softc *);
224 static int re_diag(struct re_softc *);
225 #ifdef DEVICE_POLLING
226 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
229 static device_method_t re_methods[] = {
230 /* Device interface */
231 DEVMETHOD(device_probe, re_probe),
232 DEVMETHOD(device_attach, re_attach),
233 DEVMETHOD(device_detach, re_detach),
234 DEVMETHOD(device_suspend, re_suspend),
235 DEVMETHOD(device_resume, re_resume),
236 DEVMETHOD(device_shutdown, re_shutdown),
239 DEVMETHOD(bus_print_child, bus_generic_print_child),
240 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
243 DEVMETHOD(miibus_readreg, re_miibus_readreg),
244 DEVMETHOD(miibus_writereg, re_miibus_writereg),
245 DEVMETHOD(miibus_statchg, re_miibus_statchg),
250 static driver_t re_driver = {
253 sizeof(struct re_softc)
256 static devclass_t re_devclass;
258 DECLARE_DUMMY_MODULE(if_re);
259 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
260 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
261 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
264 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
267 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
270 * Send a read command and address to the EEPROM, check for ACK.
273 re_eeprom_putbyte(struct re_softc *sc, int addr)
277 d = addr | sc->re_eecmd_read;
280 * Feed in each bit and strobe the clock.
282 for (i = 0x400; i != 0; i >>= 1) {
284 EE_SET(RE_EE_DATAIN);
286 EE_CLR(RE_EE_DATAIN);
296 * Read a word of data stored in the EEPROM at address 'addr.'
299 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
304 /* Enter EEPROM access mode. */
305 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL);
308 * Send address of word we want to read.
310 re_eeprom_putbyte(sc, addr);
312 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL);
315 * Start reading bits from EEPROM.
317 for (i = 0x8000; i != 0; i >>= 1) {
320 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
326 /* Turn off EEPROM access mode. */
327 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
333 * Read a sequence of words from the EEPROM.
336 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt, int swap)
339 uint16_t word = 0, *ptr;
341 for (i = 0; i < cnt; i++) {
342 re_eeprom_getword(sc, off + i, &word);
343 ptr = (u_int16_t *)(dest + (i * 2));
345 *ptr = be16toh(word);
352 re_gmii_readreg(device_t dev, int phy, int reg)
354 struct re_softc *sc = device_get_softc(dev);
361 /* Let the rgephy driver read the GMEDIASTAT register */
363 if (reg == RE_GMEDIASTAT)
364 return(CSR_READ_1(sc, RE_GMEDIASTAT));
366 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
369 for (i = 0; i < RE_TIMEOUT; i++) {
370 rval = CSR_READ_4(sc, RE_PHYAR);
371 if (rval & RE_PHYAR_BUSY)
376 if (i == RE_TIMEOUT) {
377 device_printf(dev, "PHY read failed\n");
381 return(rval & RE_PHYAR_PHYDATA);
385 re_gmii_writereg(device_t dev, int phy, int reg, int data)
387 struct re_softc *sc = device_get_softc(dev);
391 CSR_WRITE_4(sc, RE_PHYAR,
392 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
395 for (i = 0; i < RE_TIMEOUT; i++) {
396 rval = CSR_READ_4(sc, RE_PHYAR);
397 if ((rval & RE_PHYAR_BUSY) == 0)
403 device_printf(dev, "PHY write failed\n");
409 re_miibus_readreg(device_t dev, int phy, int reg)
411 struct re_softc *sc = device_get_softc(dev);
413 uint16_t re8139_reg = 0;
415 if (sc->re_type == RE_8169) {
416 rval = re_gmii_readreg(dev, phy, reg);
420 /* Pretend the internal PHY is only at address 0 */
426 re8139_reg = RE_BMCR;
429 re8139_reg = RE_BMSR;
432 re8139_reg = RE_ANAR;
435 re8139_reg = RE_ANER;
438 re8139_reg = RE_LPAR;
444 * Allow the rlphy driver to read the media status
445 * register. If we have a link partner which does not
446 * support NWAY, this is the register which will tell
447 * us the results of parallel detection.
450 return(CSR_READ_1(sc, RE_MEDIASTAT));
452 device_printf(dev, "bad phy register\n");
455 rval = CSR_READ_2(sc, re8139_reg);
460 re_miibus_writereg(device_t dev, int phy, int reg, int data)
462 struct re_softc *sc= device_get_softc(dev);
463 u_int16_t re8139_reg = 0;
465 if (sc->re_type == RE_8169)
466 return(re_gmii_writereg(dev, phy, reg, data));
468 /* Pretend the internal PHY is only at address 0 */
474 re8139_reg = RE_BMCR;
477 re8139_reg = RE_BMSR;
480 re8139_reg = RE_ANAR;
483 re8139_reg = RE_ANER;
486 re8139_reg = RE_LPAR;
492 device_printf(dev, "bad phy register\n");
495 CSR_WRITE_2(sc, re8139_reg, data);
500 re_miibus_statchg(device_t dev)
505 * Program the 64-bit multicast hash filter.
508 re_setmulti(struct re_softc *sc)
510 struct ifnet *ifp = &sc->arpcom.ac_if;
512 uint32_t hashes[2] = { 0, 0 };
513 struct ifmultiaddr *ifma;
517 rxfilt = CSR_READ_4(sc, RE_RXCFG);
519 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
520 rxfilt |= RE_RXCFG_RX_MULTI;
521 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
522 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
523 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
527 /* first, zot all the existing hash bits */
528 CSR_WRITE_4(sc, RE_MAR0, 0);
529 CSR_WRITE_4(sc, RE_MAR4, 0);
531 /* now program new ones */
532 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
533 if (ifma->ifma_addr->sa_family != AF_LINK)
535 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
536 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
538 hashes[0] |= (1 << h);
540 hashes[1] |= (1 << (h - 32));
545 rxfilt |= RE_RXCFG_RX_MULTI;
547 rxfilt &= ~RE_RXCFG_RX_MULTI;
549 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
550 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
551 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
555 re_reset(struct re_softc *sc)
559 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
561 for (i = 0; i < RE_TIMEOUT; i++) {
563 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
567 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
569 CSR_WRITE_1(sc, 0x82, 1);
573 * The following routine is designed to test for a defect on some
574 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
575 * lines connected to the bus, however for a 32-bit only card, they
576 * should be pulled high. The result of this defect is that the
577 * NIC will not work right if you plug it into a 64-bit slot: DMA
578 * operations will be done with 64-bit transfers, which will fail
579 * because the 64-bit data lines aren't connected.
581 * There's no way to work around this (short of talking a soldering
582 * iron to the board), however we can detect it. The method we use
583 * here is to put the NIC into digital loopback mode, set the receiver
584 * to promiscuous mode, and then try to send a frame. We then compare
585 * the frame data we sent to what was received. If the data matches,
586 * then the NIC is working correctly, otherwise we know the user has
587 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
588 * slot. In the latter case, there's no way the NIC can work correctly,
589 * so we print out a message on the console and abort the device attach.
593 re_diag(struct re_softc *sc)
595 struct ifnet *ifp = &sc->arpcom.ac_if;
597 struct ether_header *eh;
598 struct re_desc *cur_rx;
601 int total_len, i, error = 0;
602 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
603 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
605 /* Allocate a single mbuf */
607 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
612 * Initialize the NIC in test mode. This sets the chip up
613 * so that it can send and receive frames, but performs the
614 * following special functions:
615 * - Puts receiver in promiscuous mode
616 * - Enables digital loopback mode
617 * - Leaves interrupts turned off
620 ifp->if_flags |= IFF_PROMISC;
627 /* Put some data in the mbuf */
629 eh = mtod(m0, struct ether_header *);
630 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
631 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
632 eh->ether_type = htons(ETHERTYPE_IP);
633 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
636 * Queue the packet, start transmission.
637 * Note: ifq_handoff() ultimately calls re_start() for us.
640 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
641 error = ifq_handoff(ifp, m0, NULL);
648 /* Wait for it to propagate through the chip */
651 for (i = 0; i < RE_TIMEOUT; i++) {
652 status = CSR_READ_2(sc, RE_ISR);
653 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
654 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
659 if (i == RE_TIMEOUT) {
660 if_printf(ifp, "diagnostic failed to receive packet "
661 "in loopback mode\n");
667 * The packet should have been dumped into the first
668 * entry in the RX DMA ring. Grab it from there.
671 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
672 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
673 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0],
674 BUS_DMASYNC_POSTWRITE);
675 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]);
677 m0 = sc->re_ldata.re_rx_mbuf[0];
678 sc->re_ldata.re_rx_mbuf[0] = NULL;
679 eh = mtod(m0, struct ether_header *);
681 cur_rx = &sc->re_ldata.re_rx_list[0];
682 total_len = RE_RXBYTES(cur_rx);
683 rxstat = le32toh(cur_rx->re_cmdstat);
685 if (total_len != ETHER_MIN_LEN) {
686 if_printf(ifp, "diagnostic failed, received short packet\n");
691 /* Test that the received packet data matches what we sent. */
693 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
694 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
695 be16toh(eh->ether_type) != ETHERTYPE_IP) {
696 if_printf(ifp, "WARNING, DMA FAILURE!\n");
697 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
698 dst, ":", src, ":", ETHERTYPE_IP);
699 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
700 eh->ether_dhost, ":", eh->ether_shost, ":",
701 ntohs(eh->ether_type));
702 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
703 "into a 64-bit PCI slot.\n");
704 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
705 "for proper operation.\n");
706 if_printf(ifp, "Read the re(4) man page for more details.\n");
711 /* Turn interface off, release resources */
714 ifp->if_flags &= ~IFF_PROMISC;
723 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
724 * IDs against our list and return a device name if we find a match.
727 re_probe(device_t dev)
733 uint16_t vendor, product;
737 vendor = pci_get_vendor(dev);
738 product = pci_get_device(dev);
740 for (t = re_devs; t->re_name != NULL; t++) {
741 if (product == t->re_did && vendor == t->re_vid)
746 * Check if we found a RealTek device.
748 if (t->re_name == NULL)
752 * Temporarily map the I/O space so we can read the chip ID register.
754 sc = malloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
756 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
758 if (sc->re_res == NULL) {
759 device_printf(dev, "couldn't map ports/memory\n");
764 sc->re_btag = rman_get_bustag(sc->re_res);
765 sc->re_bhandle = rman_get_bushandle(sc->re_res);
767 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
768 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
772 * and continue matching for the specific chip...
774 for (; t->re_name != NULL; t++) {
775 if (product == t->re_did && vendor == t->re_vid &&
776 t->re_basetype == hwrev) {
777 device_set_desc(dev, t->re_name);
785 * This routine takes the segment list provided as the result of
786 * a bus_dma_map_load() operation and assigns the addresses/lengths
787 * to RealTek DMA descriptors. This can be called either by the RX
788 * code or the TX code. In the RX case, we'll probably wind up mapping
789 * at most one segment. For the TX case, there could be any number of
790 * segments since TX packets may span multiple mbufs. In either case,
791 * if the number of segments is larger than the re_maxsegs limit
792 * specified by the caller, we abort the mapping operation. Sadly,
793 * whoever designed the buffer mapping API did not provide a way to
794 * return an error from here, so we have to fake it a bit.
798 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg,
799 bus_size_t mapsize, int error)
801 struct re_dmaload_arg *ctx;
802 struct re_desc *d = NULL;
811 /* Signal error to caller if there's too many segments */
812 if (nseg > ctx->re_maxsegs) {
818 * Map the segment array into descriptors. Note that we set the
819 * start-of-frame and end-of-frame markers for either TX or RX, but
820 * they really only have meaning in the TX case. (In the RX case,
821 * it's the chip that tells us where packets begin and end.)
822 * We also keep track of the end of the ring and set the
823 * end-of-ring bits as needed, and we set the ownership bits
824 * in all except the very first descriptor. (The caller will
825 * set this descriptor later when it start transmission or
830 d = &ctx->re_ring[idx];
831 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) {
835 cmdstat = segs[i].ds_len;
836 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
837 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
839 cmdstat |= RE_TDESC_CMD_SOF;
841 cmdstat |= RE_TDESC_CMD_OWN;
842 if (idx == (RE_RX_DESC_CNT - 1))
843 cmdstat |= RE_TDESC_CMD_EOR;
844 d->re_cmdstat = htole32(cmdstat | ctx->re_flags);
851 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
852 ctx->re_maxsegs = nseg;
857 * Map a single buffer address.
861 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
868 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
870 *addr = segs->ds_addr;
874 re_allocmem(device_t dev, struct re_softc *sc)
879 * Allocate map for RX mbufs.
882 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0,
883 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
884 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
885 &sc->re_ldata.re_mtag);
887 device_printf(dev, "could not allocate dma tag\n");
892 * Allocate map for TX descriptor list.
894 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
895 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
896 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
897 &sc->re_ldata.re_tx_list_tag);
899 device_printf(dev, "could not allocate dma tag\n");
903 /* Allocate DMA'able memory for the TX ring */
905 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag,
906 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
907 &sc->re_ldata.re_tx_list_map);
909 device_printf(dev, "could not allocate TX ring\n");
913 /* Load the map for the TX ring. */
915 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag,
916 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
917 RE_TX_LIST_SZ, re_dma_map_addr,
918 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT);
920 device_printf(dev, "could not get addres of TX ring\n");
924 /* Create DMA maps for TX buffers */
926 for (i = 0; i < RE_TX_DESC_CNT; i++) {
927 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
928 &sc->re_ldata.re_tx_dmamap[i]);
930 device_printf(dev, "can't create DMA map for TX\n");
936 * Allocate map for RX descriptor list.
938 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
939 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
940 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
941 &sc->re_ldata.re_rx_list_tag);
943 device_printf(dev, "could not allocate dma tag\n");
947 /* Allocate DMA'able memory for the RX ring */
949 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag,
950 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
951 &sc->re_ldata.re_rx_list_map);
953 device_printf(dev, "could not allocate RX ring\n");
957 /* Load the map for the RX ring. */
959 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag,
960 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
961 RE_TX_LIST_SZ, re_dma_map_addr,
962 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT);
964 device_printf(dev, "could not get address of RX ring\n");
968 /* Create DMA maps for RX buffers */
970 for (i = 0; i < RE_RX_DESC_CNT; i++) {
971 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
972 &sc->re_ldata.re_rx_dmamap[i]);
974 device_printf(dev, "can't create DMA map for RX\n");
983 * Attach the interface. Allocate softc structures, do ifmedia
984 * setup and ethernet/BPF attach.
987 re_attach(device_t dev)
989 struct re_softc *sc = device_get_softc(dev);
991 struct re_hwrev *hw_rev;
992 uint8_t eaddr[ETHER_ADDR_LEN];
994 u_int16_t re_did = 0;
995 int error = 0, rid, i;
997 callout_init(&sc->re_timer);
1001 * Handle power management nonsense.
1004 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1005 uint32_t membase, irq;
1007 /* Save important PCI config data. */
1008 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1009 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1011 /* Reset the power state. */
1012 device_printf(dev, "chip is is in D%d power mode "
1013 "-- setting to D0\n", pci_get_powerstate(dev));
1015 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1017 /* Restore PCI config data. */
1018 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1019 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1023 * Map control/status registers.
1025 pci_enable_busmaster(dev);
1028 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1031 if (sc->re_res == NULL) {
1032 device_printf(dev, "couldn't map ports/memory\n");
1037 sc->re_btag = rman_get_bustag(sc->re_res);
1038 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1040 /* Allocate interrupt */
1042 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1043 RF_SHAREABLE | RF_ACTIVE);
1045 if (sc->re_irq == NULL) {
1046 device_printf(dev, "couldn't map interrupt\n");
1051 /* Reset the adapter. */
1054 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
1055 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) {
1056 if (hw_rev->re_rev == hwrev) {
1057 sc->re_type = hw_rev->re_type;
1062 if (sc->re_type == RE_8169) {
1063 /* Set RX length mask */
1064 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1066 /* Force station address autoload from the EEPROM */
1067 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_AUTOLOAD);
1068 for (i = 0; i < RE_TIMEOUT; i++) {
1069 if ((CSR_READ_1(sc, RE_EECMD) & RE_EEMODE_AUTOLOAD) == 0)
1073 if (i == RE_TIMEOUT)
1074 device_printf(dev, "eeprom autoload timed out\n");
1076 for (i = 0; i < ETHER_ADDR_LEN; i++)
1077 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i);
1081 /* Set RX length mask */
1082 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1084 sc->re_eecmd_read = RE_EECMD_READ_6BIT;
1085 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0);
1086 if (re_did != 0x8129)
1087 sc->re_eecmd_read = RE_EECMD_READ_8BIT;
1090 * Get station address from the EEPROM.
1092 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3, 0);
1093 for (i = 0; i < 3; i++) {
1094 eaddr[(i * 2) + 0] = as[i] & 0xff;
1095 eaddr[(i * 2) + 1] = as[i] >> 8;
1100 * Allocate the parent bus DMA tag appropriate for PCI.
1102 #define RE_NSEG_NEW 32
1103 error = bus_dma_tag_create(NULL, /* parent */
1104 1, 0, /* alignment, boundary */
1105 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1106 BUS_SPACE_MAXADDR, /* highaddr */
1107 NULL, NULL, /* filter, filterarg */
1108 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */
1109 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1110 BUS_DMA_ALLOCNOW, /* flags */
1111 &sc->re_parent_tag);
1115 error = re_allocmem(dev, sc);
1121 if (mii_phy_probe(dev, &sc->re_miibus,
1122 re_ifmedia_upd, re_ifmedia_sts)) {
1123 device_printf(dev, "MII without any phy!\n");
1128 ifp = &sc->arpcom.ac_if;
1130 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1131 ifp->if_mtu = ETHERMTU;
1132 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1133 ifp->if_ioctl = re_ioctl;
1134 ifp->if_capabilities = IFCAP_VLAN_MTU;
1135 ifp->if_start = re_start;
1136 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1137 #ifdef DEVICE_POLLING
1138 ifp->if_poll = re_poll;
1140 ifp->if_watchdog = re_watchdog;
1141 ifp->if_init = re_init;
1142 if (sc->re_type == RE_8169)
1143 ifp->if_baudrate = 1000000000;
1145 ifp->if_baudrate = 100000000;
1146 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN);
1147 ifq_set_ready(&ifp->if_snd);
1148 #ifdef RE_DISABLE_HWCSUM
1149 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1150 ifp->if_hwassist = 0;
1152 ifp->if_capenable = ifp->if_capabilities;
1153 ifp->if_hwassist = RE_CSUM_FEATURES;
1157 * Call MI attach routine.
1159 ether_ifattach(ifp, eaddr);
1161 /* Perform hardware diagnostic. */
1162 error = re_diag(sc);
1165 device_printf(dev, "hardware diagnostic failure\n");
1166 ether_ifdetach(ifp);
1170 /* Hook interrupt last to avoid having to lock softc */
1171 error = bus_setup_intr(dev, sc->re_irq, INTR_TYPE_NET, re_intr, sc,
1172 &sc->re_intrhand, NULL);
1175 device_printf(dev, "couldn't set up irq\n");
1176 ether_ifdetach(ifp);
1188 * Shutdown hardware and free up resources. This can be called any
1189 * time after the mutex has been initialized. It is called in both
1190 * the error case in attach and the normal detach case so it needs
1191 * to be careful about only freeing resources that have actually been
1195 re_detach(device_t dev)
1197 struct re_softc *sc = device_get_softc(dev);
1198 struct ifnet *ifp = &sc->arpcom.ac_if;
1203 /* These should only be active if attach succeeded */
1204 if (device_is_attached(dev)) {
1206 ether_ifdetach(ifp);
1209 device_delete_child(dev, sc->re_miibus);
1210 bus_generic_detach(dev);
1212 if (sc->re_intrhand)
1213 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1215 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1217 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1220 /* Unload and free the RX DMA ring memory and map */
1222 if (sc->re_ldata.re_rx_list_tag) {
1223 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1224 sc->re_ldata.re_rx_list_map);
1225 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1226 sc->re_ldata.re_rx_list,
1227 sc->re_ldata.re_rx_list_map);
1228 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1231 /* Unload and free the TX DMA ring memory and map */
1233 if (sc->re_ldata.re_tx_list_tag) {
1234 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1235 sc->re_ldata.re_tx_list_map);
1236 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1237 sc->re_ldata.re_tx_list,
1238 sc->re_ldata.re_tx_list_map);
1239 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1242 /* Destroy all the RX and TX buffer maps */
1244 if (sc->re_ldata.re_mtag) {
1245 for (i = 0; i < RE_TX_DESC_CNT; i++)
1246 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1247 sc->re_ldata.re_tx_dmamap[i]);
1248 for (i = 0; i < RE_RX_DESC_CNT; i++)
1249 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1250 sc->re_ldata.re_rx_dmamap[i]);
1251 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1254 /* Unload and free the stats buffer and map */
1256 if (sc->re_ldata.re_stag) {
1257 bus_dmamap_unload(sc->re_ldata.re_stag,
1258 sc->re_ldata.re_rx_list_map);
1259 bus_dmamem_free(sc->re_ldata.re_stag,
1260 sc->re_ldata.re_stats,
1261 sc->re_ldata.re_smap);
1262 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1265 if (sc->re_parent_tag)
1266 bus_dma_tag_destroy(sc->re_parent_tag);
1274 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m)
1276 struct re_dmaload_arg arg;
1277 struct mbuf *n = NULL;
1281 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1286 m->m_data = m->m_ext.ext_buf;
1289 * Initialize mbuf length fields and fixup
1290 * alignment so that the frame payload is
1293 m->m_len = m->m_pkthdr.len = MCLBYTES;
1294 m_adj(m, ETHER_ALIGN);
1300 arg.re_ring = sc->re_ldata.re_rx_list;
1302 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag,
1303 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc,
1304 &arg, BUS_DMA_NOWAIT);
1305 if (error || arg.re_maxsegs != 1) {
1311 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN);
1312 sc->re_ldata.re_rx_mbuf[idx] = m;
1314 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx],
1315 BUS_DMASYNC_PREREAD);
1321 re_tx_list_init(struct re_softc *sc)
1323 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ);
1324 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *));
1326 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1327 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1328 sc->re_ldata.re_tx_prodidx = 0;
1329 sc->re_ldata.re_tx_considx = 0;
1330 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT;
1336 re_rx_list_init(struct re_softc *sc)
1340 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ);
1341 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *));
1343 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1344 error = re_newbuf(sc, i, NULL);
1349 /* Flush the RX descriptors */
1351 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1352 sc->re_ldata.re_rx_list_map,
1353 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1355 sc->re_ldata.re_rx_prodidx = 0;
1356 sc->re_head = sc->re_tail = NULL;
1362 * RX handler for C+ and 8169. For the gigE chips, we support
1363 * the reception of jumbo frames that have been fragmented
1364 * across multiple 2K mbuf cluster buffers.
1367 re_rxeof(struct re_softc *sc)
1369 struct ifnet *ifp = &sc->arpcom.ac_if;
1371 struct re_desc *cur_rx;
1372 uint32_t rxstat, rxvlan;
1375 /* Invalidate the descriptor memory */
1377 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1378 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
1380 for (i = sc->re_ldata.re_rx_prodidx;
1381 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) {
1382 cur_rx = &sc->re_ldata.re_rx_list[i];
1383 m = sc->re_ldata.re_rx_mbuf[i];
1384 total_len = RE_RXBYTES(cur_rx);
1385 rxstat = le32toh(cur_rx->re_cmdstat);
1386 rxvlan = le32toh(cur_rx->re_vlanctl);
1388 /* Invalidate the RX mbuf and unload its map */
1390 bus_dmamap_sync(sc->re_ldata.re_mtag,
1391 sc->re_ldata.re_rx_dmamap[i],
1392 BUS_DMASYNC_POSTWRITE);
1393 bus_dmamap_unload(sc->re_ldata.re_mtag,
1394 sc->re_ldata.re_rx_dmamap[i]);
1396 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1397 m->m_len = MCLBYTES - ETHER_ALIGN;
1398 if (sc->re_head == NULL) {
1399 sc->re_head = sc->re_tail = m;
1401 m->m_flags &= ~M_PKTHDR;
1402 sc->re_tail->m_next = m;
1405 re_newbuf(sc, i, NULL);
1410 * NOTE: for the 8139C+, the frame length field
1411 * is always 12 bits in size, but for the gigE chips,
1412 * it is 13 bits (since the max RX frame length is 16K).
1413 * Unfortunately, all 32 bits in the status word
1414 * were already used, so to make room for the extra
1415 * length bit, RealTek took out the 'frame alignment
1416 * error' bit and shifted the other status bits
1417 * over one slot. The OWN, EOR, FS and LS bits are
1418 * still in the same places. We have already extracted
1419 * the frame length and checked the OWN bit, so rather
1420 * than using an alternate bit mapping, we shift the
1421 * status bits one space to the right so we can evaluate
1422 * them using the 8169 status as though it was in the
1423 * same format as that of the 8139C+.
1425 if (sc->re_type == RE_8169)
1428 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1431 * If this is part of a multi-fragment packet,
1432 * discard all the pieces.
1434 if (sc->re_head != NULL) {
1435 m_freem(sc->re_head);
1436 sc->re_head = sc->re_tail = NULL;
1438 re_newbuf(sc, i, m);
1443 * If allocating a replacement mbuf fails,
1444 * reload the current one.
1447 if (re_newbuf(sc, i, NULL)) {
1449 if (sc->re_head != NULL) {
1450 m_freem(sc->re_head);
1451 sc->re_head = sc->re_tail = NULL;
1453 re_newbuf(sc, i, m);
1457 if (sc->re_head != NULL) {
1458 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN);
1460 * Special case: if there's 4 bytes or less
1461 * in this buffer, the mbuf can be discarded:
1462 * the last 4 bytes is the CRC, which we don't
1463 * care about anyway.
1465 if (m->m_len <= ETHER_CRC_LEN) {
1466 sc->re_tail->m_len -=
1467 (ETHER_CRC_LEN - m->m_len);
1470 m->m_len -= ETHER_CRC_LEN;
1471 m->m_flags &= ~M_PKTHDR;
1472 sc->re_tail->m_next = m;
1475 sc->re_head = sc->re_tail = NULL;
1476 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1478 m->m_pkthdr.len = m->m_len =
1479 (total_len - ETHER_CRC_LEN);
1482 m->m_pkthdr.rcvif = ifp;
1484 /* Do RX checksumming if enabled */
1486 if (ifp->if_capenable & IFCAP_RXCSUM) {
1488 /* Check IP header checksum */
1489 if (rxstat & RE_RDESC_STAT_PROTOID)
1490 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1491 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1492 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1494 /* Check TCP/UDP checksum */
1495 if ((RE_TCPPKT(rxstat) &&
1496 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
1497 (RE_UDPPKT(rxstat) &&
1498 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) {
1499 m->m_pkthdr.csum_flags |=
1500 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1501 m->m_pkthdr.csum_data = 0xffff;
1505 if (rxvlan & RE_RDESC_VLANCTL_TAG)
1507 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA)));
1509 (*ifp->if_input)(ifp, m);
1512 /* Flush the RX DMA ring */
1514 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1515 sc->re_ldata.re_rx_list_map,
1516 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1518 sc->re_ldata.re_rx_prodidx = i;
1522 re_txeof(struct re_softc *sc)
1524 struct ifnet *ifp = &sc->arpcom.ac_if;
1528 /* Invalidate the TX descriptor list */
1530 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1531 sc->re_ldata.re_tx_list_map,
1532 BUS_DMASYNC_POSTREAD);
1534 for (idx = sc->re_ldata.re_tx_considx;
1535 idx != sc->re_ldata.re_tx_prodidx; RE_DESC_INC(idx)) {
1536 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
1537 if (txstat & RE_TDESC_CMD_OWN)
1541 * We only stash mbufs in the last descriptor
1542 * in a fragment chain, which also happens to
1543 * be the only place where the TX status bits
1546 if (txstat & RE_TDESC_CMD_EOF) {
1547 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
1548 sc->re_ldata.re_tx_mbuf[idx] = NULL;
1549 bus_dmamap_unload(sc->re_ldata.re_mtag,
1550 sc->re_ldata.re_tx_dmamap[idx]);
1551 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
1552 RE_TDESC_STAT_COLCNT))
1553 ifp->if_collisions++;
1554 if (txstat & RE_TDESC_STAT_TXERRSUM)
1559 sc->re_ldata.re_tx_free++;
1562 /* No changes made to the TX ring, so no flush needed */
1563 if (idx != sc->re_ldata.re_tx_considx) {
1564 sc->re_ldata.re_tx_considx = idx;
1565 ifp->if_flags &= ~IFF_OACTIVE;
1570 * If not all descriptors have been released reaped yet,
1571 * reload the timer so that we will eventually get another
1572 * interrupt that will cause us to re-enter this routine.
1573 * This is done in case the transmitter has gone idle.
1575 if (sc->re_ldata.re_tx_free != RE_TX_DESC_CNT)
1576 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1582 struct re_softc *sc = xsc;
1583 struct mii_data *mii;
1588 mii = device_get_softc(sc->re_miibus);
1591 callout_reset(&sc->re_timer, hz, re_tick, sc);
1595 #ifdef DEVICE_POLLING
1598 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1600 struct re_softc *sc = ifp->if_softc;
1604 /* disable interrupts */
1605 CSR_WRITE_2(sc, RE_IMR, 0x0000);
1607 case POLL_DEREGISTER:
1608 /* enable interrupts */
1609 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS);
1612 sc->rxcycles = count;
1616 if (!ifq_is_empty(&ifp->if_snd))
1617 (*ifp->if_start)(ifp);
1619 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1622 status = CSR_READ_2(sc, RE_ISR);
1623 if (status == 0xffff)
1626 CSR_WRITE_2(sc, RE_ISR, status);
1629 * XXX check behaviour on receiver stalls.
1632 if (status & RE_ISR_SYSTEM_ERR) {
1640 #endif /* DEVICE_POLLING */
1645 struct re_softc *sc = arg;
1646 struct ifnet *ifp = &sc->arpcom.ac_if;
1650 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0)
1656 status = CSR_READ_2(sc, RE_ISR);
1657 /* If the card has gone away the read returns 0xffff. */
1658 if (status == 0xffff)
1661 CSR_WRITE_2(sc, RE_ISR, status);
1663 if ((status & RE_INTRS_CPLUS) == 0)
1666 if (status & RE_ISR_RX_OK)
1669 if (status & RE_ISR_RX_ERR)
1672 if ((status & RE_ISR_TIMEOUT_EXPIRED) ||
1673 (status & RE_ISR_TX_ERR) ||
1674 (status & RE_ISR_TX_DESC_UNAVAIL))
1677 if (status & RE_ISR_SYSTEM_ERR) {
1682 if (status & RE_ISR_LINKCHG)
1686 if (!ifq_is_empty(&ifp->if_snd))
1687 (*ifp->if_start)(ifp);
1693 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag)
1695 struct ifnet *ifp = &sc->arpcom.ac_if;
1696 struct mbuf *m, *m_new = NULL;
1697 struct re_dmaload_arg arg;
1702 if (sc->re_ldata.re_tx_free <= 4)
1708 * Set up checksum offload. Note: checksum offload bits must
1709 * appear in all descriptors of a multi-descriptor transmit
1710 * attempt. (This is according to testing done with an 8169
1711 * chip. I'm not sure if this is a requirement or a bug.)
1716 if (m->m_pkthdr.csum_flags & CSUM_IP)
1717 arg.re_flags |= RE_TDESC_CMD_IPCSUM;
1718 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1719 arg.re_flags |= RE_TDESC_CMD_TCPCSUM;
1720 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1721 arg.re_flags |= RE_TDESC_CMD_UDPCSUM;
1725 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1726 if (arg.re_maxsegs > 4)
1727 arg.re_maxsegs -= 4;
1728 arg.re_ring = sc->re_ldata.re_tx_list;
1730 map = sc->re_ldata.re_tx_dmamap[*idx];
1731 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1732 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1734 if (error && error != EFBIG) {
1735 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1739 /* Too many segments to map, coalesce into a single mbuf */
1741 if (error || arg.re_maxsegs == 0) {
1742 m_new = m_defrag_nofree(m, MB_DONTWAIT);
1753 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1754 arg.re_ring = sc->re_ldata.re_tx_list;
1756 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1757 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1760 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1766 * Insure that the map for this transmission
1767 * is placed at the array index of the last descriptor
1770 sc->re_ldata.re_tx_dmamap[*idx] =
1771 sc->re_ldata.re_tx_dmamap[arg.re_idx];
1772 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map;
1774 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m;
1775 sc->re_ldata.re_tx_free -= arg.re_maxsegs;
1778 * Set up hardware VLAN tagging. Note: vlan tag info must
1779 * appear in the first descriptor of a multi-descriptor
1780 * transmission attempt.
1783 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1784 m->m_pkthdr.rcvif != NULL &&
1785 m->m_pkthdr.rcvif->if_type == IFT_L2VLAN) {
1787 ifv = m->m_pkthdr.rcvif->if_softc;
1789 sc->re_ldata.re_tx_list[*idx].re_vlanctl =
1790 htole32(htobe16(ifv->ifv_tag) | RE_TDESC_VLANCTL_TAG);
1793 /* Transfer ownership of packet to the chip. */
1795 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |=
1796 htole32(RE_TDESC_CMD_OWN);
1797 if (*idx != arg.re_idx)
1798 sc->re_ldata.re_tx_list[*idx].re_cmdstat |=
1799 htole32(RE_TDESC_CMD_OWN);
1801 RE_DESC_INC(arg.re_idx);
1808 * Main transmit routine for C+ and gigE NICs.
1812 re_start(struct ifnet *ifp)
1814 struct re_softc *sc = ifp->if_softc;
1815 struct mbuf *m_head = NULL, *m_head2;
1816 int called_defrag, idx, s;
1820 idx = sc->re_ldata.re_tx_prodidx;
1822 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
1823 m_head = ifq_poll(&ifp->if_snd);
1827 if (re_encap(sc, &m_head, &idx, &called_defrag)) {
1828 if (called_defrag) {
1829 m_head2 = ifq_dequeue(&ifp->if_snd);
1832 ifp->if_flags |= IFF_OACTIVE;
1836 m_head2 = ifq_dequeue(&ifp->if_snd);
1841 * If there's a BPF listener, bounce a copy of this frame
1844 BPF_MTAP(ifp, m_head);
1847 /* Flush the TX descriptors */
1848 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1849 sc->re_ldata.re_tx_list_map,
1850 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1852 sc->re_ldata.re_tx_prodidx = idx;
1855 * RealTek put the TX poll request register in a different
1856 * location on the 8169 gigE chip. I don't know why.
1858 if (sc->re_type == RE_8169)
1859 CSR_WRITE_2(sc, RE_GTXSTART, RE_TXSTART_START);
1861 CSR_WRITE_2(sc, RE_TXSTART, RE_TXSTART_START);
1864 * Use the countdown timer for interrupt moderation.
1865 * 'TX done' interrupts are disabled. Instead, we reset the
1866 * countdown timer, which will begin counting until it hits
1867 * the value in the TIMERINT register, and then trigger an
1868 * interrupt. Each time we write to the TIMERCNT register,
1869 * the timer count is reset to 0.
1871 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1876 * Set a timeout in case the chip goes out to lunch.
1884 struct re_softc *sc = xsc;
1885 struct ifnet *ifp = &sc->arpcom.ac_if;
1886 struct mii_data *mii;
1891 mii = device_get_softc(sc->re_miibus);
1894 * Cancel pending I/O and free all RX/TX buffers.
1899 * Enable C+ RX and TX mode, as well as VLAN stripping and
1900 * RX checksum offload. We must configure the C+ register
1901 * before all others.
1903 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
1904 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP |
1905 (ifp->if_capenable & IFCAP_RXCSUM ?
1906 RE_CPLUSCMD_RXCSUM_ENB : 0));
1909 * Init our MAC address. Even though the chipset
1910 * documentation doesn't mention it, we need to enter "Config
1911 * register write enable" mode to modify the ID registers.
1913 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
1914 CSR_WRITE_STREAM_4(sc, RE_IDR0,
1915 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1916 CSR_WRITE_STREAM_4(sc, RE_IDR4,
1917 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1918 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
1921 * For C+ mode, initialize the RX descriptors and mbufs.
1923 re_rx_list_init(sc);
1924 re_tx_list_init(sc);
1927 * Enable transmit and receive.
1929 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
1932 * Set the initial TX and RX configuration.
1934 if (sc->re_testmode) {
1935 if (sc->re_type == RE_8169)
1936 CSR_WRITE_4(sc, RE_TXCFG,
1937 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
1939 CSR_WRITE_4(sc, RE_TXCFG,
1940 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
1942 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
1943 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
1945 /* Set the individual bit to receive frames for this host only. */
1946 rxcfg = CSR_READ_4(sc, RE_RXCFG);
1947 rxcfg |= RE_RXCFG_RX_INDIV;
1949 /* If we want promiscuous mode, set the allframes bit. */
1950 if (ifp->if_flags & IFF_PROMISC) {
1951 rxcfg |= RE_RXCFG_RX_ALLPHYS;
1952 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1954 rxcfg &= ~RE_RXCFG_RX_ALLPHYS;
1955 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1959 * Set capture broadcast bit to capture broadcast frames.
1961 if (ifp->if_flags & IFF_BROADCAST) {
1962 rxcfg |= RE_RXCFG_RX_BROAD;
1963 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1965 rxcfg &= ~RE_RXCFG_RX_BROAD;
1966 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1970 * Program the multicast filter, if necessary.
1974 #ifdef DEVICE_POLLING
1976 * Disable interrupts if we are polling.
1978 if (ifp->if_flags & IFF_POLLING)
1979 CSR_WRITE_2(sc, RE_IMR, 0);
1980 else /* otherwise ... */
1981 #endif /* DEVICE_POLLING */
1983 * Enable interrupts.
1985 if (sc->re_testmode)
1986 CSR_WRITE_2(sc, RE_IMR, 0);
1988 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS);
1990 /* Set initial TX threshold */
1991 sc->re_txthresh = RE_TX_THRESH_INIT;
1993 /* Start RX/TX process. */
1994 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
1996 /* Enable receiver and transmitter. */
1997 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2000 * Load the addresses of the RX and TX lists into the chip.
2003 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2004 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2005 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2006 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2008 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2009 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2010 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2011 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2013 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16);
2016 * Initialize the timer interrupt register so that
2017 * a timer interrupt will be generated once the timer
2018 * reaches a certain number of ticks. The timer is
2019 * reloaded on each transmit. This gives us TX interrupt
2020 * moderation, which dramatically improves TX frame rate.
2023 if (sc->re_type == RE_8169)
2024 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800);
2026 CSR_WRITE_4(sc, RE_TIMERINT, 0x400);
2029 * For 8169 gigE NICs, set the max allowed RX packet
2030 * size so we can receive jumbo frames.
2032 if (sc->re_type == RE_8169)
2033 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2035 if (sc->re_testmode) {
2042 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2044 ifp->if_flags |= IFF_RUNNING;
2045 ifp->if_flags &= ~IFF_OACTIVE;
2047 callout_reset(&sc->re_timer, hz, re_tick, sc);
2052 * Set media options.
2055 re_ifmedia_upd(struct ifnet *ifp)
2057 struct re_softc *sc = ifp->if_softc;
2058 struct mii_data *mii;
2060 mii = device_get_softc(sc->re_miibus);
2067 * Report current media status.
2070 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2072 struct re_softc *sc = ifp->if_softc;
2073 struct mii_data *mii;
2075 mii = device_get_softc(sc->re_miibus);
2078 ifmr->ifm_active = mii->mii_media_active;
2079 ifmr->ifm_status = mii->mii_media_status;
2083 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2085 struct re_softc *sc = ifp->if_softc;
2086 struct ifreq *ifr = (struct ifreq *) data;
2087 struct mii_data *mii;
2094 if (ifr->ifr_mtu > RE_JUMBO_MTU)
2096 ifp->if_mtu = ifr->ifr_mtu;
2099 if (ifp->if_flags & IFF_UP)
2101 else if (ifp->if_flags & IFF_RUNNING)
2112 mii = device_get_softc(sc->re_miibus);
2113 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2116 ifp->if_capenable &= ~(IFCAP_HWCSUM);
2117 ifp->if_capenable |=
2118 ifr->ifr_reqcap & (IFCAP_HWCSUM);
2119 if (ifp->if_capenable & IFCAP_TXCSUM)
2120 ifp->if_hwassist = RE_CSUM_FEATURES;
2122 ifp->if_hwassist = 0;
2123 if (ifp->if_flags & IFF_RUNNING)
2127 error = ether_ioctl(ifp, command, data);
2137 re_watchdog(struct ifnet *ifp)
2139 struct re_softc *sc = ifp->if_softc;
2143 if_printf(ifp, "watchdog timeout\n");
2155 * Stop the adapter and free any mbufs allocated to the
2159 re_stop(struct re_softc *sc)
2161 struct ifnet *ifp = &sc->arpcom.ac_if;
2166 callout_stop(&sc->re_timer);
2168 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2170 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2171 CSR_WRITE_2(sc, RE_IMR, 0x0000);
2173 if (sc->re_head != NULL) {
2174 m_freem(sc->re_head);
2175 sc->re_head = sc->re_tail = NULL;
2178 /* Free the TX list buffers. */
2179 for (i = 0; i < RE_TX_DESC_CNT; i++) {
2180 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2181 bus_dmamap_unload(sc->re_ldata.re_mtag,
2182 sc->re_ldata.re_tx_dmamap[i]);
2183 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2184 sc->re_ldata.re_tx_mbuf[i] = NULL;
2188 /* Free the RX list buffers. */
2189 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2190 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2191 bus_dmamap_unload(sc->re_ldata.re_mtag,
2192 sc->re_ldata.re_rx_dmamap[i]);
2193 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2194 sc->re_ldata.re_rx_mbuf[i] = NULL;
2202 * Device suspend routine. Stop the interface and save some PCI
2203 * settings in case the BIOS doesn't restore them properly on
2207 re_suspend(device_t dev)
2209 #ifndef BURN_BRIDGES
2212 struct re_softc *sc = device_get_softc(dev);
2216 #ifndef BURN_BRIDGES
2217 for (i = 0; i < 5; i++)
2218 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2219 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2220 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2221 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2222 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2231 * Device resume routine. Restore some PCI settings in case the BIOS
2232 * doesn't, re-enable busmastering, and restart the interface if
2236 re_resume(device_t dev)
2238 struct re_softc *sc = device_get_softc(dev);
2239 struct ifnet *ifp = &sc->arpcom.ac_if;
2240 #ifndef BURN_BRIDGES
2244 #ifndef BURN_BRIDGES
2245 /* better way to do this? */
2246 for (i = 0; i < 5; i++)
2247 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2248 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2249 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2250 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2251 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2253 /* reenable busmastering */
2254 pci_enable_busmaster(dev);
2255 pci_enable_io(dev, SYS_RES_IOPORT);
2258 /* reinitialize interface if necessary */
2259 if (ifp->if_flags & IFF_UP)
2268 * Stop all chip I/O so that the kernel's probe routines don't
2269 * get confused by errant DMAs when rebooting.
2272 re_shutdown(device_t dev)
2274 struct re_softc *sc = device_get_softc(dev);