2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $
33 * $DragonFly: src/sys/dev/netif/vr/if_vr.c,v 1.24 2005/05/27 15:36:10 joerg Exp $
37 * VIA Rhine fast ethernet PCI NIC driver
39 * Supports various network adapters based on the VIA Rhine
40 * and Rhine II PCI controllers, including the D-Link DFE530TX.
41 * Datasheets are available at http://www.via.com.tw.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The VIA Rhine controllers are similar in some respects to the
50 * the DEC tulip chips, except less complicated. The controller
51 * uses an MII bus and an external physical layer interface. The
52 * receiver has a one entry perfect filter and a 64-bit hash table
53 * multicast filter. Transmit and receive descriptors are similar
56 * The Rhine has a serious flaw in its transmit DMA mechanism:
57 * transmit buffers must be longword aligned. Unfortunately,
58 * FreeBSD doesn't guarantee that mbufs will be filled in starting
59 * at longword boundaries, so we have to do a buffer copy before
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 #include <sys/sockio.h>
67 #include <sys/malloc.h>
68 #include <sys/kernel.h>
69 #include <sys/socket.h>
72 #include <net/ifq_var.h>
73 #include <net/if_arp.h>
74 #include <net/ethernet.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
80 #include <vm/vm.h> /* for vtophys */
81 #include <vm/pmap.h> /* for vtophys */
82 #include <machine/bus_pio.h>
83 #include <machine/bus_memio.h>
84 #include <machine/bus.h>
85 #include <machine/resource.h>
89 #include <dev/netif/mii_layer/mii.h>
90 #include <dev/netif/mii_layer/miivar.h>
92 #include <bus/pci/pcireg.h>
93 #include <bus/pci/pcivar.h>
97 #include <dev/netif/vr/if_vrreg.h>
99 /* "controller miibus0" required. See GENERIC if you get errors here. */
100 #include "miibus_if.h"
105 * Various supported device vendors/types and their names.
107 static struct vr_type vr_devs[] = {
108 { VIA_VENDORID, VIA_DEVICEID_RHINE,
109 "VIA VT3043 Rhine I 10/100BaseTX" },
110 { VIA_VENDORID, VIA_DEVICEID_RHINE_II,
111 "VIA VT86C100A Rhine II 10/100BaseTX" },
112 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2,
113 "VIA VT6102 Rhine II 10/100BaseTX" },
114 { VIA_VENDORID, VIA_DEVICEID_RHINE_III,
115 "VIA VT6105 Rhine III 10/100BaseTX" },
116 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M,
117 "VIA VT6105M Rhine III 10/100BaseTX" },
118 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II,
119 "Delta Electronics Rhine II 10/100BaseTX" },
120 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II,
121 "Addtron Technology Rhine II 10/100BaseTX" },
125 static int vr_probe(device_t);
126 static int vr_attach(device_t);
127 static int vr_detach(device_t);
129 static int vr_newbuf(struct vr_softc *, struct vr_chain_onefrag *,
131 static int vr_encap(struct vr_softc *, struct vr_chain *, struct mbuf * );
133 static void vr_rxeof(struct vr_softc *);
134 static void vr_rxeoc(struct vr_softc *);
135 static void vr_txeof(struct vr_softc *);
136 static void vr_txeoc(struct vr_softc *);
137 static void vr_tick(void *);
138 static void vr_intr(void *);
139 static void vr_start(struct ifnet *);
140 static int vr_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
141 static void vr_init(void *);
142 static void vr_stop(struct vr_softc *);
143 static void vr_watchdog(struct ifnet *);
144 static void vr_shutdown(device_t);
145 static int vr_ifmedia_upd(struct ifnet *);
146 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *);
149 static void vr_mii_sync(struct vr_softc *);
150 static void vr_mii_send(struct vr_softc *, uint32_t, int);
152 static int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *);
153 static int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *);
154 static int vr_miibus_readreg(device_t, int, int);
155 static int vr_miibus_writereg(device_t, int, int, int);
156 static void vr_miibus_statchg(device_t);
158 static void vr_setcfg(struct vr_softc *, int);
159 static uint8_t vr_calchash(uint8_t *);
160 static void vr_setmulti(struct vr_softc *);
161 static void vr_reset(struct vr_softc *);
162 static int vr_list_rx_init(struct vr_softc *);
163 static int vr_list_tx_init(struct vr_softc *);
164 #ifdef DEVICE_POLLING
165 static void vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
169 #define VR_RES SYS_RES_IOPORT
170 #define VR_RID VR_PCI_LOIO
172 #define VR_RES SYS_RES_MEMORY
173 #define VR_RID VR_PCI_LOMEM
176 static device_method_t vr_methods[] = {
177 /* Device interface */
178 DEVMETHOD(device_probe, vr_probe),
179 DEVMETHOD(device_attach, vr_attach),
180 DEVMETHOD(device_detach, vr_detach),
181 DEVMETHOD(device_shutdown, vr_shutdown),
184 DEVMETHOD(bus_print_child, bus_generic_print_child),
185 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
188 DEVMETHOD(miibus_readreg, vr_miibus_readreg),
189 DEVMETHOD(miibus_writereg, vr_miibus_writereg),
190 DEVMETHOD(miibus_statchg, vr_miibus_statchg),
195 static driver_t vr_driver = {
198 sizeof(struct vr_softc)
201 static devclass_t vr_devclass;
203 DECLARE_DUMMY_MODULE(if_vr);
204 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0);
205 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
207 #define VR_SETBIT(sc, reg, x) \
208 CSR_WRITE_1(sc, reg, \
209 CSR_READ_1(sc, reg) | (x))
211 #define VR_CLRBIT(sc, reg, x) \
212 CSR_WRITE_1(sc, reg, \
213 CSR_READ_1(sc, reg) & ~(x))
215 #define VR_SETBIT16(sc, reg, x) \
216 CSR_WRITE_2(sc, reg, \
217 CSR_READ_2(sc, reg) | (x))
219 #define VR_CLRBIT16(sc, reg, x) \
220 CSR_WRITE_2(sc, reg, \
221 CSR_READ_2(sc, reg) & ~(x))
223 #define VR_SETBIT32(sc, reg, x) \
224 CSR_WRITE_4(sc, reg, \
225 CSR_READ_4(sc, reg) | (x))
227 #define VR_CLRBIT32(sc, reg, x) \
228 CSR_WRITE_4(sc, reg, \
229 CSR_READ_4(sc, reg) & ~(x))
232 CSR_WRITE_1(sc, VR_MIICMD, \
233 CSR_READ_1(sc, VR_MIICMD) | (x))
236 CSR_WRITE_1(sc, VR_MIICMD, \
237 CSR_READ_1(sc, VR_MIICMD) & ~(x))
241 * Sync the PHYs by setting data bit and strobing the clock 32 times.
244 vr_mii_sync(struct vr_softc *sc)
248 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN);
250 for (i = 0; i < 32; i++) {
251 SIO_SET(VR_MIICMD_CLK);
253 SIO_CLR(VR_MIICMD_CLK);
259 * Clock a series of bits through the MII.
262 vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt)
266 SIO_CLR(VR_MIICMD_CLK);
268 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
270 SIO_SET(VR_MIICMD_DATAIN);
272 SIO_CLR(VR_MIICMD_DATAIN);
274 SIO_CLR(VR_MIICMD_CLK);
276 SIO_SET(VR_MIICMD_CLK);
282 * Read an PHY register through the MII.
285 vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame)
292 /* Set up frame for RX. */
293 frame->mii_stdelim = VR_MII_STARTDELIM;
294 frame->mii_opcode = VR_MII_READOP;
295 frame->mii_turnaround = 0;
298 CSR_WRITE_1(sc, VR_MIICMD, 0);
299 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
301 /* Turn on data xmit. */
302 SIO_SET(VR_MIICMD_DIR);
306 /* Send command/address info. */
307 vr_mii_send(sc, frame->mii_stdelim, 2);
308 vr_mii_send(sc, frame->mii_opcode, 2);
309 vr_mii_send(sc, frame->mii_phyaddr, 5);
310 vr_mii_send(sc, frame->mii_regaddr, 5);
313 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN));
315 SIO_SET(VR_MIICMD_CLK);
319 SIO_CLR(VR_MIICMD_DIR);
322 SIO_CLR(VR_MIICMD_CLK);
324 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
325 SIO_SET(VR_MIICMD_CLK);
329 * Now try reading data bits. If the ack failed, we still
330 * need to clock through 16 cycles to keep the PHY(s) in sync.
333 for(i = 0; i < 16; i++) {
334 SIO_CLR(VR_MIICMD_CLK);
336 SIO_SET(VR_MIICMD_CLK);
342 for (i = 0x8000; i; i >>= 1) {
343 SIO_CLR(VR_MIICMD_CLK);
346 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT)
347 frame->mii_data |= i;
350 SIO_SET(VR_MIICMD_CLK);
355 SIO_CLR(VR_MIICMD_CLK);
357 SIO_SET(VR_MIICMD_CLK);
372 /* Set the PHY address. */
373 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
376 /* Set the register address. */
377 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
378 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB);
380 for (i = 0; i < 10000; i++) {
381 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
385 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA);
395 * Write to a PHY register through the MII.
398 vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame)
405 CSR_WRITE_1(sc, VR_MIICMD, 0);
406 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
408 /* Set up frame for TX. */
409 frame->mii_stdelim = VR_MII_STARTDELIM;
410 frame->mii_opcode = VR_MII_WRITEOP;
411 frame->mii_turnaround = VR_MII_TURNAROUND;
413 /* Turn on data output. */
414 SIO_SET(VR_MIICMD_DIR);
418 vr_mii_send(sc, frame->mii_stdelim, 2);
419 vr_mii_send(sc, frame->mii_opcode, 2);
420 vr_mii_send(sc, frame->mii_phyaddr, 5);
421 vr_mii_send(sc, frame->mii_regaddr, 5);
422 vr_mii_send(sc, frame->mii_turnaround, 2);
423 vr_mii_send(sc, frame->mii_data, 16);
426 SIO_SET(VR_MIICMD_CLK);
428 SIO_CLR(VR_MIICMD_CLK);
432 SIO_CLR(VR_MIICMD_DIR);
444 /* Set the PHY-adress */
445 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
448 /* Set the register address and data to write. */
449 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
450 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data);
452 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB);
454 for (i = 0; i < 10000; i++) {
455 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
467 vr_miibus_readreg(device_t dev, int phy, int reg)
469 struct vr_mii_frame frame;
472 sc = device_get_softc(dev);
474 switch (sc->vr_revid) {
475 case REV_ID_VT6102_APOLLO:
483 bzero(&frame, sizeof(frame));
485 frame.mii_phyaddr = phy;
486 frame.mii_regaddr = reg;
487 vr_mii_readreg(sc, &frame);
489 return(frame.mii_data);
493 vr_miibus_writereg(device_t dev, int phy, int reg, int data)
495 struct vr_mii_frame frame;
498 sc = device_get_softc(dev);
500 switch (sc->vr_revid) {
501 case REV_ID_VT6102_APOLLO:
509 bzero(&frame, sizeof(frame));
511 frame.mii_phyaddr = phy;
512 frame.mii_regaddr = reg;
513 frame.mii_data = data;
515 vr_mii_writereg(sc, &frame);
521 vr_miibus_statchg(device_t dev)
523 struct mii_data *mii;
526 sc = device_get_softc(dev);
527 mii = device_get_softc(sc->vr_miibus);
528 vr_setcfg(sc, mii->mii_media_active);
532 * Calculate CRC of a multicast group address, return the lower 6 bits.
535 vr_calchash(uint8_t *addr)
541 /* Compute CRC for the address value. */
542 crc = 0xFFFFFFFF; /* initial value */
544 for (i = 0; i < 6; i++) {
546 for (j = 0; j < 8; j++) {
547 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
551 crc = (crc ^ 0x04c11db6) | carry;
555 /* return the filter bit position */
556 return((crc >> 26) & 0x0000003F);
560 * Program the 64-bit multicast hash filter.
563 vr_setmulti(struct vr_softc *sc)
567 uint32_t hashes[2] = { 0, 0 };
568 struct ifmultiaddr *ifma;
572 ifp = &sc->arpcom.ac_if;
574 rxfilt = CSR_READ_1(sc, VR_RXCFG);
576 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
577 rxfilt |= VR_RXCFG_RX_MULTI;
578 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
579 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
580 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
584 /* First, zero out all the existing hash bits. */
585 CSR_WRITE_4(sc, VR_MAR0, 0);
586 CSR_WRITE_4(sc, VR_MAR1, 0);
588 /* Now program new ones. */
589 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
590 ifma = ifma->ifma_link.le_next) {
591 if (ifma->ifma_addr->sa_family != AF_LINK)
593 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
595 hashes[0] |= (1 << h);
597 hashes[1] |= (1 << (h - 32));
602 rxfilt |= VR_RXCFG_RX_MULTI;
604 rxfilt &= ~VR_RXCFG_RX_MULTI;
606 CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
607 CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
608 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
612 * In order to fiddle with the
613 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
614 * first have to put the transmit and/or receive logic in the idle state.
617 vr_setcfg(struct vr_softc *sc, int media)
621 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) {
623 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON));
626 if ((media & IFM_GMASK) == IFM_FDX)
627 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
629 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
632 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON);
636 vr_reset(struct vr_softc *sc)
640 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET);
642 for (i = 0; i < VR_TIMEOUT; i++) {
644 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET))
647 if (i == VR_TIMEOUT) {
648 struct ifnet *ifp = &sc->arpcom.ac_if;
650 if (sc->vr_revid < REV_ID_VT3065_A) {
651 if_printf(ifp, "reset never completed!\n");
653 /* Use newer force reset command */
654 if_printf(ifp, "Using force reset command.\n");
655 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST);
659 /* Wait a little while for the chip to get its brains in order. */
664 * Probe for a VIA Rhine chip. Check the PCI vendor and device
665 * IDs against our list and return a device name if we find a match.
668 vr_probe(device_t dev)
674 while(t->vr_name != NULL) {
675 if ((pci_get_vendor(dev) == t->vr_vid) &&
676 (pci_get_device(dev) == t->vr_did)) {
677 device_set_desc(dev, t->vr_name);
687 * Attach the interface. Allocate softc structures, do ifmedia
688 * setup and ethernet/BPF attach.
691 vr_attach(device_t dev)
694 uint8_t eaddr[ETHER_ADDR_LEN];
702 sc = device_get_softc(dev);
703 callout_init(&sc->vr_stat_timer);
706 * Handle power management nonsense.
709 command = pci_read_config(dev, VR_PCI_CAPID, 4) & 0x000000FF;
710 if (command == 0x01) {
711 command = pci_read_config(dev, VR_PCI_PWRMGMTCTRL, 4);
712 if (command & VR_PSTATE_MASK) {
713 uint32_t iobase, membase, irq;
715 /* Save important PCI config data. */
716 iobase = pci_read_config(dev, VR_PCI_LOIO, 4);
717 membase = pci_read_config(dev, VR_PCI_LOMEM, 4);
718 irq = pci_read_config(dev, VR_PCI_INTLINE, 4);
720 /* Reset the power state. */
721 device_printf(dev, "chip is in D%d power mode "
722 "-- setting to D0\n", command & VR_PSTATE_MASK);
723 command &= 0xFFFFFFFC;
724 pci_write_config(dev, VR_PCI_PWRMGMTCTRL, command, 4);
726 /* Restore PCI config data. */
727 pci_write_config(dev, VR_PCI_LOIO, iobase, 4);
728 pci_write_config(dev, VR_PCI_LOMEM, membase, 4);
729 pci_write_config(dev, VR_PCI_INTLINE, irq, 4);
734 * Map control/status registers.
736 command = pci_read_config(dev, PCIR_COMMAND, 4);
737 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
738 pci_write_config(dev, PCIR_COMMAND, command, 4);
739 command = pci_read_config(dev, PCIR_COMMAND, 4);
740 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF;
743 if (!(command & PCIM_CMD_PORTEN)) {
744 device_printf(dev, "failed to enable I/O ports!\n");
749 if (!(command & PCIM_CMD_MEMEN)) {
750 device_printf(dev, "failed to enable memory mapping!\n");
756 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE);
758 if (sc->vr_res == NULL) {
759 device_printf(dev, "couldn't map ports/memory\n");
764 sc->vr_btag = rman_get_bustag(sc->vr_res);
765 sc->vr_bhandle = rman_get_bushandle(sc->vr_res);
767 /* Allocate interrupt */
769 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
770 RF_SHAREABLE | RF_ACTIVE);
772 if (sc->vr_irq == NULL) {
773 device_printf(dev, "couldn't map interrupt\n");
774 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
779 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET,
780 vr_intr, sc, &sc->vr_intrhand, NULL);
783 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
784 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
785 device_printf(dev, "couldn't set up irq\n");
790 * Windows may put the chip in suspend mode when it
791 * shuts down. Be sure to kick it in the head to wake it
794 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1));
796 /* Reset the adapter. */
800 * Turn on bit2 (MIION) in PCI configuration register 0x53 during
801 * initialization and disable AUTOPOLL.
803 pci_write_config(dev, VR_PCI_MODE,
804 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4);
805 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL);
807 ifp = &sc->arpcom.ac_if;
808 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
811 * Get station address. The way the Rhine chips work,
812 * you're not allowed to directly access the EEPROM once
813 * they've been programmed a special way. Consequently,
814 * we need to read the node address from the PAR0 and PAR1
817 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
819 for (i = 0; i < ETHER_ADDR_LEN; i++)
820 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
822 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF,
823 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
825 if (sc->vr_ldata == NULL) {
826 device_printf(dev, "no memory for list buffers!\n");
827 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
828 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
829 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
834 bzero(sc->vr_ldata, sizeof(struct vr_list_data));
837 ifp->if_mtu = ETHERMTU;
838 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
839 ifp->if_ioctl = vr_ioctl;
840 ifp->if_start = vr_start;
841 #ifdef DEVICE_POLLING
842 ifp->if_poll = vr_poll;
844 ifp->if_watchdog = vr_watchdog;
845 ifp->if_init = vr_init;
846 ifp->if_baudrate = 10000000;
847 ifq_set_maxlen(&ifp->if_snd, VR_TX_LIST_CNT - 1);
848 ifq_set_ready(&ifp->if_snd);
853 if (mii_phy_probe(dev, &sc->vr_miibus,
854 vr_ifmedia_upd, vr_ifmedia_sts)) {
855 if_printf(ifp, "MII without any phy!\n");
856 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
857 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
858 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
859 contigfree(sc->vr_ldata,
860 sizeof(struct vr_list_data), M_DEVBUF);
865 /* Call MI attach routine. */
866 ether_ifattach(ifp, eaddr);
874 vr_detach(device_t dev)
882 sc = device_get_softc(dev);
883 ifp = &sc->arpcom.ac_if;
888 bus_generic_detach(dev);
889 device_delete_child(dev, sc->vr_miibus);
891 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
892 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
893 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
895 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF);
903 * Initialize the transmit descriptors.
906 vr_list_tx_init(struct vr_softc *sc)
908 struct vr_chain_data *cd;
909 struct vr_list_data *ld;
914 for (i = 0; i < VR_TX_LIST_CNT; i++) {
915 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i];
916 if (i == (VR_TX_LIST_CNT - 1))
920 cd->vr_tx_chain[i].vr_nextdesc = &cd->vr_tx_chain[nexti];
923 cd->vr_tx_free = &cd->vr_tx_chain[0];
924 cd->vr_tx_tail = cd->vr_tx_head = NULL;
931 * Initialize the RX descriptors and allocate mbufs for them. Note that
932 * we arrange the descriptors in a closed ring, so that the last descriptor
933 * points back to the first.
936 vr_list_rx_init(struct vr_softc *sc)
938 struct vr_chain_data *cd;
939 struct vr_list_data *ld;
945 for (i = 0; i < VR_RX_LIST_CNT; i++) {
946 cd->vr_rx_chain[i].vr_ptr = (struct vr_desc *)&ld->vr_rx_list[i];
947 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS)
949 if (i == (VR_RX_LIST_CNT - 1))
953 cd->vr_rx_chain[i].vr_nextdesc = &cd->vr_rx_chain[nexti];
954 ld->vr_rx_list[i].vr_next = vtophys(&ld->vr_rx_list[nexti]);
957 cd->vr_rx_head = &cd->vr_rx_chain[0];
963 * Initialize an RX descriptor and attach an MBUF cluster.
964 * Note: the length fields are only 11 bits wide, which means the
965 * largest size we can specify is 2047. This is important because
966 * MCLBYTES is 2048, so we have to subtract one otherwise we'll
967 * overflow the field and make a mess.
970 vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m)
972 struct mbuf *m_new = NULL;
975 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
979 MCLGET(m_new, MB_DONTWAIT);
980 if (!(m_new->m_flags & M_EXT)) {
984 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
987 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
988 m_new->m_data = m_new->m_ext.ext_buf;
991 m_adj(m_new, sizeof(uint64_t));
994 c->vr_ptr->vr_status = VR_RXSTAT;
995 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t));
996 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN;
1002 * A frame has been uploaded: pass the resulting mbuf chain up to
1003 * the higher level protocols.
1006 vr_rxeof(struct vr_softc *sc)
1010 struct vr_chain_onefrag *cur_rx;
1014 ifp = &sc->arpcom.ac_if;
1016 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) &
1018 struct mbuf *m0 = NULL;
1020 cur_rx = sc->vr_cdata.vr_rx_head;
1021 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc;
1022 m = cur_rx->vr_mbuf;
1025 * If an error occurs, update stats, clear the
1026 * status word and leave the mbuf cluster in place:
1027 * it should simply get re-used next time this descriptor
1028 * comes up in the ring.
1030 if (rxstat & VR_RXSTAT_RXERR) {
1032 if_printf(ifp, "rx error (%02x):", rxstat & 0x000000ff);
1033 if (rxstat & VR_RXSTAT_CRCERR)
1034 printf(" crc error");
1035 if (rxstat & VR_RXSTAT_FRAMEALIGNERR)
1036 printf(" frame alignment error\n");
1037 if (rxstat & VR_RXSTAT_FIFOOFLOW)
1038 printf(" FIFO overflow");
1039 if (rxstat & VR_RXSTAT_GIANT)
1040 printf(" received giant packet");
1041 if (rxstat & VR_RXSTAT_RUNT)
1042 printf(" received runt packet");
1043 if (rxstat & VR_RXSTAT_BUSERR)
1044 printf(" system bus error");
1045 if (rxstat & VR_RXSTAT_BUFFERR)
1046 printf("rx buffer error");
1048 vr_newbuf(sc, cur_rx, m);
1052 /* No errors; receive the packet. */
1053 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status);
1056 * XXX The VIA Rhine chip includes the CRC with every
1057 * received frame, and there's no way to turn this
1058 * behavior off (at least, I can't find anything in
1059 * the manual that explains how to do it) so we have
1060 * to trim off the CRC manually.
1062 total_len -= ETHER_CRC_LEN;
1064 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1065 total_len + ETHER_ALIGN, 0, ifp, NULL);
1066 vr_newbuf(sc, cur_rx, m);
1071 m_adj(m0, ETHER_ALIGN);
1075 (*ifp->if_input)(ifp, m);
1080 vr_rxeoc(struct vr_softc *sc)
1085 ifp = &sc->arpcom.ac_if;
1089 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1092 /* Wait for receiver to stop */
1094 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON);
1096 ; /* Wait for receiver to stop */
1099 if_printf(ifp, "rx shutdown error!\n");
1100 sc->vr_flags |= VR_F_RESTART;
1106 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1107 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1108 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO);
1112 * A frame was downloaded to the chip. It's safe for us to clean up
1116 vr_txeof(struct vr_softc *sc)
1118 struct vr_chain *cur_tx;
1121 ifp = &sc->arpcom.ac_if;
1123 /* Reset the timeout timer; if_txeoc will clear it. */
1127 if (sc->vr_cdata.vr_tx_head == NULL)
1131 * Go through our tx list and free mbufs for those
1132 * frames that have been transmitted.
1134 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) {
1138 cur_tx = sc->vr_cdata.vr_tx_head;
1139 txstat = cur_tx->vr_ptr->vr_status;
1141 if ((txstat & VR_TXSTAT_ABRT) ||
1142 (txstat & VR_TXSTAT_UDF)) {
1144 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON);
1146 ; /* Wait for chip to shutdown */
1148 if_printf(ifp, "tx shutdown timeout\n");
1149 sc->vr_flags |= VR_F_RESTART;
1152 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1153 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr));
1157 if (txstat & VR_TXSTAT_OWN)
1160 if (txstat & VR_TXSTAT_ERRSUM) {
1162 if (txstat & VR_TXSTAT_DEFER)
1163 ifp->if_collisions++;
1164 if (txstat & VR_TXSTAT_LATECOLL)
1165 ifp->if_collisions++;
1168 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3;
1171 if (cur_tx->vr_mbuf != NULL) {
1172 m_freem(cur_tx->vr_mbuf);
1173 cur_tx->vr_mbuf = NULL;
1176 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) {
1177 sc->vr_cdata.vr_tx_head = NULL;
1178 sc->vr_cdata.vr_tx_tail = NULL;
1182 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc;
1187 * TX 'end of channel' interrupt handler.
1190 vr_txeoc(struct vr_softc *sc)
1194 ifp = &sc->arpcom.ac_if;
1196 if (sc->vr_cdata.vr_tx_head == NULL) {
1197 ifp->if_flags &= ~IFF_OACTIVE;
1198 sc->vr_cdata.vr_tx_tail = NULL;
1206 struct vr_softc *sc;
1207 struct mii_data *mii;
1213 if (sc->vr_flags & VR_F_RESTART) {
1214 if_printf(&sc->arpcom.ac_if, "restarting\n");
1218 sc->vr_flags &= ~VR_F_RESTART;
1221 mii = device_get_softc(sc->vr_miibus);
1224 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc);
1232 struct vr_softc *sc;
1237 ifp = &sc->arpcom.ac_if;
1239 /* Supress unwanted interrupts. */
1240 if (!(ifp->if_flags & IFF_UP)) {
1245 /* Disable interrupts. */
1246 if ((ifp->if_flags & IFF_POLLING) == 0)
1247 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1250 status = CSR_READ_2(sc, VR_ISR);
1252 CSR_WRITE_2(sc, VR_ISR, status);
1254 if ((status & VR_INTRS) == 0)
1257 if (status & VR_ISR_RX_OK)
1260 if (status & VR_ISR_RX_DROPPED) {
1261 if_printf(ifp, "rx packet lost\n");
1265 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) ||
1266 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) {
1267 if_printf(ifp, "receive error (%04x)", status);
1268 if (status & VR_ISR_RX_NOBUF)
1269 printf(" no buffers");
1270 if (status & VR_ISR_RX_OFLOW)
1271 printf(" overflow");
1272 if (status & VR_ISR_RX_DROPPED)
1273 printf(" packet lost");
1278 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) {
1284 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) ||
1285 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) {
1287 if ((status & VR_ISR_UDFI) ||
1288 (status & VR_ISR_TX_ABRT2) ||
1289 (status & VR_ISR_TX_ABRT)) {
1291 if (sc->vr_cdata.vr_tx_head != NULL) {
1292 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON);
1293 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO);
1302 /* Re-enable interrupts. */
1303 if ((ifp->if_flags & IFF_POLLING) == 0)
1304 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1306 if (!ifq_is_empty(&ifp->if_snd))
1311 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1312 * pointers to the fragment pointers.
1315 vr_encap(struct vr_softc *sc, struct vr_chain *c, struct mbuf *m_head)
1318 struct vr_desc *f = NULL;
1325 * The VIA Rhine wants packet buffers to be longword
1326 * aligned, but very often our mbufs aren't. Rather than
1327 * waste time trying to decide when to copy and when not
1328 * to copy, just do it all the time.
1330 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1331 if (m_new == NULL) {
1332 if_printf(&sc->arpcom.ac_if, "no memory for tx list\n");
1335 if (m_head->m_pkthdr.len > MHLEN) {
1336 MCLGET(m_new, MB_DONTWAIT);
1337 if (!(m_new->m_flags & M_EXT)) {
1339 if_printf(&sc->arpcom.ac_if,
1340 "no memory for tx list\n");
1344 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1345 mtod(m_new, caddr_t));
1346 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1348 * The Rhine chip doesn't auto-pad, so we have to make
1349 * sure to pad short frames out to the minimum frame length
1352 if (m_new->m_len < VR_MIN_FRAMELEN) {
1353 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len;
1354 m_new->m_len = m_new->m_pkthdr.len;
1357 f->vr_data = vtophys(mtod(m_new, caddr_t));
1358 f->vr_ctl = total_len = m_new->m_len;
1359 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG;
1364 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT;
1365 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr);
1371 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1372 * to the mbuf data regions directly in the transmit lists. We also save a
1373 * copy of the pointers since the transmit list fragment pointers are
1374 * physical addresses.
1377 vr_start(struct ifnet *ifp)
1379 struct vr_softc *sc;
1380 struct mbuf *m_head = NULL;
1381 struct vr_chain *cur_tx = NULL, *start_tx;
1385 if (ifp->if_flags & IFF_OACTIVE)
1388 /* Check for an available queue slot. If there are none, punt. */
1389 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) {
1390 ifp->if_flags |= IFF_OACTIVE;
1394 start_tx = sc->vr_cdata.vr_tx_free;
1396 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) {
1397 m_head = ifq_poll(&ifp->if_snd);
1401 /* Pick a descriptor off the free list. */
1402 cur_tx = sc->vr_cdata.vr_tx_free;
1403 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc;
1405 /* Pack the data into the descriptor. */
1406 if (vr_encap(sc, cur_tx, m_head)) {
1407 ifp->if_flags |= IFF_OACTIVE;
1412 m_head = ifq_dequeue(&ifp->if_snd);
1413 if (cur_tx != start_tx)
1414 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1416 BPF_MTAP(ifp, m_head);
1419 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1420 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO);
1423 /* If there are no frames queued, bail. */
1427 sc->vr_cdata.vr_tx_tail = cur_tx;
1429 if (sc->vr_cdata.vr_tx_head == NULL)
1430 sc->vr_cdata.vr_tx_head = start_tx;
1433 * Set a timeout in case the chip goes out to lunch.
1441 struct vr_softc *sc = xsc;
1442 struct ifnet *ifp = &sc->arpcom.ac_if;
1443 struct mii_data *mii;
1448 mii = device_get_softc(sc->vr_miibus);
1450 /* Cancel pending I/O and free all RX/TX buffers. */
1454 /* Set our station address. */
1455 for (i = 0; i < ETHER_ADDR_LEN; i++)
1456 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1459 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH);
1460 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD);
1463 * BCR0 and BCR1 can override the RXCFG and TXCFG registers,
1464 * so we must set both.
1466 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);
1467 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES);
1469 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);
1470 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD);
1472 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
1473 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES);
1475 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);
1476 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD);
1478 /* Init circular RX list. */
1479 if (vr_list_rx_init(sc) == ENOBUFS) {
1480 if_printf(ifp, "initialization failed: no memory for rx buffers\n");
1486 /* Init tx descriptors. */
1487 vr_list_tx_init(sc);
1489 /* If we want promiscuous mode, set the allframes bit. */
1490 if (ifp->if_flags & IFF_PROMISC)
1491 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1493 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1495 /* Set capture broadcast bit to capture broadcast frames. */
1496 if (ifp->if_flags & IFF_BROADCAST)
1497 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1499 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1502 * Program the multicast filter, if necessary.
1507 * Load the address of the RX list.
1509 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1511 /* Enable receiver and transmitter. */
1512 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START|
1513 VR_CMD_TX_ON|VR_CMD_RX_ON|
1516 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0]));
1519 * Enable interrupts, unless we are polling.
1521 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
1522 if ((ifp->if_flags & IFF_POLLING) == 0)
1523 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1527 ifp->if_flags |= IFF_RUNNING;
1528 ifp->if_flags &= ~IFF_OACTIVE;
1532 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc);
1536 * Set media options.
1539 vr_ifmedia_upd(struct ifnet *ifp)
1541 struct vr_softc *sc;
1545 if (ifp->if_flags & IFF_UP)
1552 * Report current media status.
1555 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1557 struct vr_softc *sc;
1558 struct mii_data *mii;
1561 mii = device_get_softc(sc->vr_miibus);
1563 ifmr->ifm_active = mii->mii_media_active;
1564 ifmr->ifm_status = mii->mii_media_status;
1568 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1570 struct vr_softc *sc = ifp->if_softc;
1571 struct ifreq *ifr = (struct ifreq *) data;
1572 struct mii_data *mii;
1579 if (ifp->if_flags & IFF_UP) {
1582 if (ifp->if_flags & IFF_RUNNING)
1594 mii = device_get_softc(sc->vr_miibus);
1595 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1598 error = ether_ioctl(ifp, command, data);
1607 #ifdef DEVICE_POLLING
1610 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1612 struct vr_softc *sc = ifp->if_softc;
1616 /* disable interrupts */
1617 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1619 case POLL_DEREGISTER:
1620 /* enable interrupts */
1621 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1631 vr_watchdog(struct ifnet *ifp)
1633 struct vr_softc *sc;
1638 if_printf(ifp, "watchdog timeout\n");
1640 #ifdef DEVICE_POLLING
1641 if (++sc->vr_wdogerrors == 1 && (ifp->if_flags & IFF_POLLING) == 0) {
1642 if_printf(ifp, "ints don't seem to be working, "
1643 "emergency switch to polling\n");
1644 emergency_poll_enable("if_vr");
1645 ether_poll_register(ifp); /* XXX illegal */
1654 if (!ifq_is_empty(&ifp->if_snd))
1659 * Stop the adapter and free any mbufs allocated to the
1663 vr_stop(struct vr_softc *sc)
1668 ifp = &sc->arpcom.ac_if;
1671 callout_stop(&sc->vr_stat_timer);
1673 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP);
1674 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON));
1675 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1676 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000);
1677 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000);
1680 * Free data in the RX lists.
1682 for (i = 0; i < VR_RX_LIST_CNT; i++) {
1683 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) {
1684 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf);
1685 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL;
1688 bzero((char *)&sc->vr_ldata->vr_rx_list,
1689 sizeof(sc->vr_ldata->vr_rx_list));
1692 * Free the TX list buffers.
1694 for (i = 0; i < VR_TX_LIST_CNT; i++) {
1695 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) {
1696 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf);
1697 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL;
1701 bzero((char *)&sc->vr_ldata->vr_tx_list,
1702 sizeof(sc->vr_ldata->vr_tx_list));
1704 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1708 * Stop all chip I/O so that the kernel's probe routines don't
1709 * get confused by errant DMAs when rebooting.
1712 vr_shutdown(device_t dev)
1714 struct vr_softc *sc;
1716 sc = device_get_softc(dev);