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32 ******************************************************************************/
36 * 82543GC Gigabit Ethernet Controller (Fiber)
37 * 82543GC Gigabit Ethernet Controller (Copper)
38 * 82544EI Gigabit Ethernet Controller (Copper)
39 * 82544EI Gigabit Ethernet Controller (Fiber)
40 * 82544GC Gigabit Ethernet Controller (Copper)
41 * 82544GC Gigabit Ethernet Controller (LOM)
44 #include "e1000_api.h"
46 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw);
47 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw);
48 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw);
49 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset,
51 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset,
53 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw);
54 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw);
55 static s32 e1000_reset_hw_82543(struct e1000_hw *hw);
56 static s32 e1000_init_hw_82543(struct e1000_hw *hw);
57 static s32 e1000_setup_link_82543(struct e1000_hw *hw);
58 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw);
59 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw);
60 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw);
61 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw);
62 static s32 e1000_led_on_82543(struct e1000_hw *hw);
63 static s32 e1000_led_off_82543(struct e1000_hw *hw);
64 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset,
66 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw);
67 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw);
68 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw);
69 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
70 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw);
71 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
72 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw);
73 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
75 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw);
76 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state);
77 static s32 e1000_read_mac_addr_82543(struct e1000_hw *hw);
81 * e1000_init_phy_params_82543 - Init PHY func ptrs.
82 * @hw: pointer to the HW structure
84 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw)
86 struct e1000_phy_info *phy = &hw->phy;
87 s32 ret_val = E1000_SUCCESS;
89 DEBUGFUNC("e1000_init_phy_params_82543");
91 if (hw->phy.media_type != e1000_media_type_copper) {
92 phy->type = e1000_phy_none;
95 phy->ops.power_up = e1000_power_up_phy_copper;
96 phy->ops.power_down = e1000_power_down_phy_copper;
100 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
101 phy->reset_delay_us = 10000;
102 phy->type = e1000_phy_m88;
104 /* Function Pointers */
105 phy->ops.check_polarity = e1000_check_polarity_m88;
106 phy->ops.commit = e1000_phy_sw_reset_generic;
107 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543;
108 phy->ops.get_cable_length = e1000_get_cable_length_m88;
109 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
110 phy->ops.read_reg = (hw->mac.type == e1000_82543)
111 ? e1000_read_phy_reg_82543
112 : e1000_read_phy_reg_m88;
113 phy->ops.reset = (hw->mac.type == e1000_82543)
114 ? e1000_phy_hw_reset_82543
115 : e1000_phy_hw_reset_generic;
116 phy->ops.write_reg = (hw->mac.type == e1000_82543)
117 ? e1000_write_phy_reg_82543
118 : e1000_write_phy_reg_m88;
119 phy->ops.get_info = e1000_get_phy_info_m88;
122 * The external PHY of the 82543 can be in a funky state.
123 * Resetting helps us read the PHY registers for acquiring
126 if (!e1000_init_phy_disabled_82543(hw)) {
127 ret_val = phy->ops.reset(hw);
129 DEBUGOUT("Resetting PHY during init failed.\n");
135 ret_val = e1000_get_phy_id(hw);
140 switch (hw->mac.type) {
142 if (phy->id != M88E1000_E_PHY_ID) {
143 ret_val = -E1000_ERR_PHY;
148 if (phy->id != M88E1000_I_PHY_ID) {
149 ret_val = -E1000_ERR_PHY;
154 ret_val = -E1000_ERR_PHY;
164 * e1000_init_nvm_params_82543 - Init NVM func ptrs.
165 * @hw: pointer to the HW structure
167 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw)
169 struct e1000_nvm_info *nvm = &hw->nvm;
171 DEBUGFUNC("e1000_init_nvm_params_82543");
173 nvm->type = e1000_nvm_eeprom_microwire;
175 nvm->delay_usec = 50;
176 nvm->address_bits = 6;
177 nvm->opcode_bits = 3;
179 /* Function Pointers */
180 nvm->ops.read = e1000_read_nvm_microwire;
181 nvm->ops.update = e1000_update_nvm_checksum_generic;
182 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
183 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
184 nvm->ops.write = e1000_write_nvm_microwire;
186 return E1000_SUCCESS;
190 * e1000_init_mac_params_82543 - Init MAC func ptrs.
191 * @hw: pointer to the HW structure
193 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw)
195 struct e1000_mac_info *mac = &hw->mac;
197 DEBUGFUNC("e1000_init_mac_params_82543");
200 switch (hw->device_id) {
201 case E1000_DEV_ID_82543GC_FIBER:
202 case E1000_DEV_ID_82544EI_FIBER:
203 hw->phy.media_type = e1000_media_type_fiber;
206 hw->phy.media_type = e1000_media_type_copper;
210 /* Set mta register count */
211 mac->mta_reg_count = 128;
212 /* Set rar entry count */
213 mac->rar_entry_count = E1000_RAR_ENTRIES;
215 /* Function pointers */
217 /* bus type/speed/width */
218 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
220 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
222 mac->ops.reset_hw = e1000_reset_hw_82543;
223 /* hw initialization */
224 mac->ops.init_hw = e1000_init_hw_82543;
226 mac->ops.setup_link = e1000_setup_link_82543;
227 /* physical interface setup */
228 mac->ops.setup_physical_interface =
229 (hw->phy.media_type == e1000_media_type_copper)
230 ? e1000_setup_copper_link_82543
231 : e1000_setup_fiber_link_82543;
233 mac->ops.check_for_link =
234 (hw->phy.media_type == e1000_media_type_copper)
235 ? e1000_check_for_copper_link_82543
236 : e1000_check_for_fiber_link_82543;
238 mac->ops.get_link_up_info =
239 (hw->phy.media_type == e1000_media_type_copper)
240 ? e1000_get_speed_and_duplex_copper_generic
241 : e1000_get_speed_and_duplex_fiber_serdes_generic;
242 /* multicast address update */
243 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
245 mac->ops.write_vfta = e1000_write_vfta_82543;
247 mac->ops.clear_vfta = e1000_clear_vfta_generic;
248 /* read mac address */
249 mac->ops.read_mac_addr = e1000_read_mac_addr_82543;
250 /* turn on/off LED */
251 mac->ops.led_on = e1000_led_on_82543;
252 mac->ops.led_off = e1000_led_off_82543;
253 /* clear hardware counters */
254 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543;
256 /* Set tbi compatibility */
257 if ((hw->mac.type != e1000_82543) ||
258 (hw->phy.media_type == e1000_media_type_fiber))
259 e1000_set_tbi_compatibility_82543(hw, FALSE);
261 return E1000_SUCCESS;
265 * e1000_init_function_pointers_82543 - Init func ptrs.
266 * @hw: pointer to the HW structure
268 * Called to initialize all function pointers and parameters.
270 void e1000_init_function_pointers_82543(struct e1000_hw *hw)
272 DEBUGFUNC("e1000_init_function_pointers_82543");
274 hw->mac.ops.init_params = e1000_init_mac_params_82543;
275 hw->nvm.ops.init_params = e1000_init_nvm_params_82543;
276 hw->phy.ops.init_params = e1000_init_phy_params_82543;
280 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status
281 * @hw: pointer to the HW structure
283 * Returns the current status of 10-bit Interface (TBI) compatibility
284 * (enabled/disabled).
286 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw)
288 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
291 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543");
293 if (hw->mac.type != e1000_82543) {
294 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
298 state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED)
306 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility
307 * @hw: pointer to the HW structure
308 * @state: enable/disable TBI compatibility
310 * Enables or disabled 10-bit Interface (TBI) compatibility.
312 void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state)
314 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
316 DEBUGFUNC("e1000_set_tbi_compatibility_82543");
318 if (hw->mac.type != e1000_82543) {
319 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
324 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED;
326 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED;
333 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status
334 * @hw: pointer to the HW structure
336 * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP)
337 * (enabled/disabled).
339 bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw)
341 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
344 DEBUGFUNC("e1000_tbi_sbp_enabled_82543");
346 if (hw->mac.type != e1000_82543) {
347 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
351 state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED)
359 * e1000_set_tbi_sbp_82543 - Set TBI SBP
360 * @hw: pointer to the HW structure
361 * @state: enable/disable TBI store bad packet
363 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP).
365 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state)
367 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
369 DEBUGFUNC("e1000_set_tbi_sbp_82543");
371 if (state && e1000_tbi_compatibility_enabled_82543(hw))
372 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED;
374 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED;
380 * e1000_init_phy_disabled_82543 - Returns init PHY status
381 * @hw: pointer to the HW structure
383 * Returns the current status of whether PHY initialization is disabled.
384 * True if PHY initialization is disabled else FALSE.
386 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw)
388 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
391 DEBUGFUNC("e1000_init_phy_disabled_82543");
393 if (hw->mac.type != e1000_82543) {
398 ret_val = dev_spec->init_phy_disabled;
405 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled
406 * @hw: pointer to the HW structure
407 * @stats: Struct containing statistic register values
408 * @frame_len: The length of the frame in question
409 * @mac_addr: The Ethernet destination address of the frame in question
410 * @max_frame_size: The maximum frame size
412 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
414 void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw,
415 struct e1000_hw_stats *stats, u32 frame_len,
416 u8 *mac_addr, u32 max_frame_size)
418 if (!(e1000_tbi_sbp_enabled_82543(hw)))
421 /* First adjust the frame length. */
424 * We need to adjust the statistics counters, since the hardware
425 * counters overcount this packet as a CRC error and undercount
426 * the packet as a good packet
428 /* This packet should not be counted as a CRC error. */
430 /* This packet does count as a Good Packet Received. */
433 /* Adjust the Good Octets received counters */
434 stats->gorc += frame_len;
437 * Is this a broadcast or multicast? Check broadcast first,
438 * since the test for a multicast frame will test positive on
441 if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff))
442 /* Broadcast packet */
444 else if (*mac_addr & 0x01)
445 /* Multicast packet */
449 * In this case, the hardware has overcounted the number of
452 if ((frame_len == max_frame_size) && (stats->roc > 0))
456 * Adjust the bin counters when the extra byte put the frame in the
457 * wrong bin. Remember that the frame_len was adjusted above.
459 if (frame_len == 64) {
462 } else if (frame_len == 127) {
465 } else if (frame_len == 255) {
468 } else if (frame_len == 511) {
471 } else if (frame_len == 1023) {
474 } else if (frame_len == 1522) {
483 * e1000_read_phy_reg_82543 - Read PHY register
484 * @hw: pointer to the HW structure
485 * @offset: register offset to be read
486 * @data: pointer to the read data
488 * Reads the PHY at offset and stores the information read to data.
490 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data)
493 s32 ret_val = E1000_SUCCESS;
495 DEBUGFUNC("e1000_read_phy_reg_82543");
497 if (offset > MAX_PHY_REG_ADDRESS) {
498 DEBUGOUT1("PHY Address %d is out of range\n", offset);
499 ret_val = -E1000_ERR_PARAM;
504 * We must first send a preamble through the MDIO pin to signal the
505 * beginning of an MII instruction. This is done by sending 32
506 * consecutive "1" bits.
508 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
511 * Now combine the next few fields that are required for a read
512 * operation. We use this method instead of calling the
513 * e1000_shift_out_mdi_bits routine five different times. The format
514 * of an MII read instruction consists of a shift out of 14 bits and
515 * is defined as follows:
516 * <Preamble><SOF><Op Code><Phy Addr><Offset>
517 * followed by a shift in of 18 bits. This first two bits shifted in
518 * are TurnAround bits used to avoid contention on the MDIO pin when a
519 * READ operation is performed. These two bits are thrown away
520 * followed by a shift in of 16 bits which contains the desired data.
522 mdic = (offset | (hw->phy.addr << 5) |
523 (PHY_OP_READ << 10) | (PHY_SOF << 12));
525 e1000_shift_out_mdi_bits_82543(hw, mdic, 14);
528 * Now that we've shifted out the read command to the MII, we need to
529 * "shift in" the 16-bit value (18 total bits) of the requested PHY
532 *data = e1000_shift_in_mdi_bits_82543(hw);
539 * e1000_write_phy_reg_82543 - Write PHY register
540 * @hw: pointer to the HW structure
541 * @offset: register offset to be written
542 * @data: pointer to the data to be written at offset
544 * Writes data to the PHY at offset.
546 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data)
549 s32 ret_val = E1000_SUCCESS;
551 DEBUGFUNC("e1000_write_phy_reg_82543");
553 if (offset > MAX_PHY_REG_ADDRESS) {
554 DEBUGOUT1("PHY Address %d is out of range\n", offset);
555 ret_val = -E1000_ERR_PARAM;
560 * We'll need to use the SW defined pins to shift the write command
561 * out to the PHY. We first send a preamble to the PHY to signal the
562 * beginning of the MII instruction. This is done by sending 32
563 * consecutive "1" bits.
565 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
568 * Now combine the remaining required fields that will indicate a
569 * write operation. We use this method instead of calling the
570 * e1000_shift_out_mdi_bits routine for each field in the command. The
571 * format of a MII write instruction is as follows:
572 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
574 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) |
575 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
579 e1000_shift_out_mdi_bits_82543(hw, mdic, 32);
586 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock
587 * @hw: pointer to the HW structure
588 * @ctrl: pointer to the control register
590 * Raise the management data input clock by setting the MDC bit in the control
593 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
596 * Raise the clock input to the Management Data Clock (by setting the
597 * MDC bit), and then delay a sufficient amount of time.
599 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC));
600 E1000_WRITE_FLUSH(hw);
605 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock
606 * @hw: pointer to the HW structure
607 * @ctrl: pointer to the control register
609 * Lower the management data input clock by clearing the MDC bit in the
612 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
615 * Lower the clock input to the Management Data Clock (by clearing the
616 * MDC bit), and then delay a sufficient amount of time.
618 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC));
619 E1000_WRITE_FLUSH(hw);
624 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY
625 * @hw: pointer to the HW structure
626 * @data: data to send to the PHY
627 * @count: number of bits to shift out
629 * We need to shift 'count' bits out to the PHY. So, the value in the
630 * "data" parameter will be shifted out to the PHY one bit at a time.
631 * In order to do this, "data" must be broken down into bits.
633 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
639 * We need to shift "count" number of bits out to the PHY. So, the
640 * value in the "data" parameter will be shifted out to the PHY one
641 * bit at a time. In order to do this, "data" must be broken down
647 ctrl = E1000_READ_REG(hw, E1000_CTRL);
649 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
650 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
654 * A "1" is shifted out to the PHY by setting the MDIO bit to
655 * "1" and then raising and lowering the Management Data Clock.
656 * A "0" is shifted out to the PHY by setting the MDIO bit to
657 * "0" and then raising and lowering the clock.
659 if (data & mask) ctrl |= E1000_CTRL_MDIO;
660 else ctrl &= ~E1000_CTRL_MDIO;
662 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
663 E1000_WRITE_FLUSH(hw);
667 e1000_raise_mdi_clk_82543(hw, &ctrl);
668 e1000_lower_mdi_clk_82543(hw, &ctrl);
675 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY
676 * @hw: pointer to the HW structure
678 * In order to read a register from the PHY, we need to shift 18 bits
679 * in from the PHY. Bits are "shifted in" by raising the clock input to
680 * the PHY (setting the MDC bit), and then reading the value of the data out
683 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw)
690 * In order to read a register from the PHY, we need to shift in a
691 * total of 18 bits from the PHY. The first two bit (turnaround)
692 * times are used to avoid contention on the MDIO pin when a read
693 * operation is performed. These two bits are ignored by us and
694 * thrown away. Bits are "shifted in" by raising the input to the
695 * Management Data Clock (setting the MDC bit) and then reading the
696 * value of the MDIO bit.
698 ctrl = E1000_READ_REG(hw, E1000_CTRL);
701 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
704 ctrl &= ~E1000_CTRL_MDIO_DIR;
705 ctrl &= ~E1000_CTRL_MDIO;
707 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
708 E1000_WRITE_FLUSH(hw);
711 * Raise and lower the clock before reading in the data. This accounts
712 * for the turnaround bits. The first clock occurred when we clocked
713 * out the last bit of the Register Address.
715 e1000_raise_mdi_clk_82543(hw, &ctrl);
716 e1000_lower_mdi_clk_82543(hw, &ctrl);
718 for (data = 0, i = 0; i < 16; i++) {
720 e1000_raise_mdi_clk_82543(hw, &ctrl);
721 ctrl = E1000_READ_REG(hw, E1000_CTRL);
722 /* Check to see if we shifted in a "1". */
723 if (ctrl & E1000_CTRL_MDIO)
725 e1000_lower_mdi_clk_82543(hw, &ctrl);
728 e1000_raise_mdi_clk_82543(hw, &ctrl);
729 e1000_lower_mdi_clk_82543(hw, &ctrl);
735 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY
736 * @hw: pointer to the HW structure
738 * Calls the function to force speed and duplex for the m88 PHY, and
739 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit,
740 * then call the function for polarity reversal workaround.
742 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw)
746 DEBUGFUNC("e1000_phy_force_speed_duplex_82543");
748 ret_val = e1000_phy_force_speed_duplex_m88(hw);
752 if (!hw->mac.autoneg &&
753 (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED))
754 ret_val = e1000_polarity_reversal_workaround_82543(hw);
761 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal
762 * @hw: pointer to the HW structure
764 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity
765 * inadvertently. To workaround the issue, we disable the transmitter on
766 * the PHY until we have established the link partner's link parameters.
768 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw)
770 s32 ret_val = E1000_SUCCESS;
775 if (!(hw->phy.ops.write_reg))
778 /* Polarity reversal workaround for forced 10F/10H links. */
780 /* Disable the transmitter on the PHY */
782 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
785 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
789 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
794 * This loop will early-out if the NO link condition has been met.
795 * In other words, DO NOT use e1000_phy_has_link_generic() here.
797 for (i = PHY_FORCE_TIME; i > 0; i--) {
799 * Read the MII Status Register and wait for Link Status bit
803 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
807 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
811 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
816 /* Recommended delay time after link has been lost */
817 msec_delay_irq(1000);
819 /* Now we will re-enable the transmitter on the PHY */
821 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
825 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
829 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
833 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
837 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
842 * Read the MII Status Register and wait for Link Status bit
845 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link);
854 * e1000_phy_hw_reset_82543 - PHY hardware reset
855 * @hw: pointer to the HW structure
857 * Sets the PHY_RESET_DIR bit in the extended device control register
858 * to put the PHY into a reset and waits for completion. Once the reset
859 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out
862 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw)
867 DEBUGFUNC("e1000_phy_hw_reset_82543");
870 * Read the Extended Device Control Register, assert the PHY_RESET_DIR
871 * bit to put the PHY into reset...
873 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
874 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
875 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
876 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
877 E1000_WRITE_FLUSH(hw);
881 /* ...then take it out of reset. */
882 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
883 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
884 E1000_WRITE_FLUSH(hw);
888 if (!(hw->phy.ops.get_cfg_done))
889 return E1000_SUCCESS;
891 ret_val = hw->phy.ops.get_cfg_done(hw);
897 * e1000_reset_hw_82543 - Reset hardware
898 * @hw: pointer to the HW structure
900 * This resets the hardware into a known state.
902 static s32 e1000_reset_hw_82543(struct e1000_hw *hw)
905 s32 ret_val = E1000_SUCCESS;
907 DEBUGFUNC("e1000_reset_hw_82543");
909 DEBUGOUT("Masking off all interrupts\n");
910 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
912 E1000_WRITE_REG(hw, E1000_RCTL, 0);
913 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
914 E1000_WRITE_FLUSH(hw);
916 e1000_set_tbi_sbp_82543(hw, FALSE);
919 * Delay to allow any outstanding PCI transactions to complete before
920 * resetting the device
924 ctrl = E1000_READ_REG(hw, E1000_CTRL);
926 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n");
927 if (hw->mac.type == e1000_82543) {
928 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
931 * The 82544 can't ACK the 64-bit write when issuing the
932 * reset, so use IO-mapping as a workaround.
934 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
938 * After MAC reset, force reload of NVM to restore power-on
939 * settings to device.
941 hw->nvm.ops.reload(hw);
944 /* Masking off and clearing any pending interrupts */
945 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
946 icr = E1000_READ_REG(hw, E1000_ICR);
952 * e1000_init_hw_82543 - Initialize hardware
953 * @hw: pointer to the HW structure
955 * This inits the hardware readying it for operation.
957 static s32 e1000_init_hw_82543(struct e1000_hw *hw)
959 struct e1000_mac_info *mac = &hw->mac;
960 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
965 DEBUGFUNC("e1000_init_hw_82543");
967 /* Disabling VLAN filtering */
968 E1000_WRITE_REG(hw, E1000_VET, 0);
969 mac->ops.clear_vfta(hw);
971 /* Setup the receive address. */
972 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
974 /* Zero out the Multicast HASH table */
975 DEBUGOUT("Zeroing the MTA\n");
976 for (i = 0; i < mac->mta_reg_count; i++) {
977 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
978 E1000_WRITE_FLUSH(hw);
982 * Set the PCI priority bit correctly in the CTRL register. This
983 * determines if the adapter gives priority to receives, or if it
984 * gives equal priority to transmits and receives.
986 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) {
987 ctrl = E1000_READ_REG(hw, E1000_CTRL);
988 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
991 e1000_pcix_mmrbc_workaround_generic(hw);
993 /* Setup link and flow control */
994 ret_val = mac->ops.setup_link(hw);
997 * Clear all of the statistics registers (clear on read). It is
998 * important that we do this after we have tried to establish link
999 * because the symbol error count will increment wildly if there
1002 e1000_clear_hw_cntrs_82543(hw);
1008 * e1000_setup_link_82543 - Setup flow control and link settings
1009 * @hw: pointer to the HW structure
1011 * Read the EEPROM to determine the initial polarity value and write the
1012 * extended device control register with the information before calling
1013 * the generic setup link function, which does the following:
1014 * Determines which flow control settings to use, then configures flow
1015 * control. Calls the appropriate media-specific link configuration
1016 * function. Assuming the adapter has a valid link partner, a valid link
1017 * should be established. Assumes the hardware has previously been reset
1018 * and the transmitter and receiver are not enabled.
1020 static s32 e1000_setup_link_82543(struct e1000_hw *hw)
1026 DEBUGFUNC("e1000_setup_link_82543");
1029 * Take the 4 bits from NVM word 0xF that determine the initial
1030 * polarity value for the SW controlled pins, and setup the
1031 * Extended Device Control reg with that info.
1032 * This is needed because one of the SW controlled pins is used for
1033 * signal detection. So this should be done before phy setup.
1035 if (hw->mac.type == e1000_82543) {
1036 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1038 DEBUGOUT("NVM Read Error\n");
1039 ret_val = -E1000_ERR_NVM;
1042 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) <<
1043 NVM_SWDPIO_EXT_SHIFT);
1044 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1047 ret_val = e1000_setup_link_generic(hw);
1054 * e1000_setup_copper_link_82543 - Configure copper link settings
1055 * @hw: pointer to the HW structure
1057 * Configures the link for auto-neg or forced speed and duplex. Then we check
1058 * for link, once link is established calls to configure collision distance
1059 * and flow control are called.
1061 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw)
1067 DEBUGFUNC("e1000_setup_copper_link_82543");
1069 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU;
1071 * With 82543, we need to force speed and duplex on the MAC
1072 * equal to what the PHY speed and duplex configuration is.
1073 * In addition, we need to perform a hardware reset on the
1074 * PHY to take it out of reset.
1076 if (hw->mac.type == e1000_82543) {
1077 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1078 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1079 ret_val = hw->phy.ops.reset(hw);
1082 hw->phy.reset_disable = FALSE;
1084 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1085 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1088 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */
1089 ret_val = e1000_copper_link_setup_m88(hw);
1093 if (hw->mac.autoneg) {
1095 * Setup autoneg and flow control advertisement and perform
1098 ret_val = e1000_copper_link_autoneg(hw);
1103 * PHY will be set to 10H, 10F, 100H or 100F
1104 * depending on user settings.
1106 DEBUGOUT("Forcing Speed and Duplex\n");
1107 ret_val = e1000_phy_force_speed_duplex_82543(hw);
1109 DEBUGOUT("Error Forcing Speed and Duplex\n");
1115 * Check link status. Wait up to 100 microseconds for link to become
1118 ret_val = e1000_phy_has_link_generic(hw,
1119 COPPER_LINK_UP_LIMIT,
1127 DEBUGOUT("Valid link established!!!\n");
1128 /* Config the MAC and PHY after link is up */
1129 if (hw->mac.type == e1000_82544) {
1130 e1000_config_collision_dist_generic(hw);
1132 ret_val = e1000_config_mac_to_phy_82543(hw);
1136 ret_val = e1000_config_fc_after_link_up_generic(hw);
1138 DEBUGOUT("Unable to establish link!!!\n");
1146 * e1000_setup_fiber_link_82543 - Setup link for fiber
1147 * @hw: pointer to the HW structure
1149 * Configures collision distance and flow control for fiber links. Upon
1150 * successful setup, poll for link.
1152 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw)
1157 DEBUGFUNC("e1000_setup_fiber_link_82543");
1159 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1161 /* Take the link out of reset */
1162 ctrl &= ~E1000_CTRL_LRST;
1164 e1000_config_collision_dist_generic(hw);
1166 ret_val = e1000_commit_fc_settings_generic(hw);
1170 DEBUGOUT("Auto-negotiation enabled\n");
1172 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1173 E1000_WRITE_FLUSH(hw);
1177 * For these adapters, the SW definable pin 1 is cleared when the
1178 * optics detect a signal. If we have a signal, then poll for a
1179 * "Link-Up" indication.
1181 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1182 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1184 DEBUGOUT("No signal detected\n");
1192 * e1000_check_for_copper_link_82543 - Check for link (Copper)
1193 * @hw: pointer to the HW structure
1195 * Checks the phy for link, if link exists, do the following:
1196 * - check for downshift
1197 * - do polarity workaround (if necessary)
1198 * - configure collision distance
1199 * - configure flow control after link up
1200 * - configure tbi compatibility
1202 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw)
1204 struct e1000_mac_info *mac = &hw->mac;
1210 DEBUGFUNC("e1000_check_for_copper_link_82543");
1212 if (!mac->get_link_status) {
1213 ret_val = E1000_SUCCESS;
1217 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1222 goto out; /* No link detected */
1224 mac->get_link_status = FALSE;
1226 e1000_check_downshift_generic(hw);
1229 * If we are forcing speed/duplex, then we can return since
1230 * we have already determined whether we have link or not.
1232 if (!mac->autoneg) {
1234 * If speed and duplex are forced to 10H or 10F, then we will
1235 * implement the polarity reversal workaround. We disable
1236 * interrupts first, and upon returning, place the devices
1237 * interrupt state to its previous value except for the link
1238 * status change interrupt which will happened due to the
1239 * execution of this workaround.
1241 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) {
1242 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
1243 ret_val = e1000_polarity_reversal_workaround_82543(hw);
1244 icr = E1000_READ_REG(hw, E1000_ICR);
1245 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC));
1246 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
1249 ret_val = -E1000_ERR_CONFIG;
1254 * We have a M88E1000 PHY and Auto-Neg is enabled. If we
1255 * have Si on board that is 82544 or newer, Auto
1256 * Speed Detection takes care of MAC speed/duplex
1257 * configuration. So we only need to configure Collision
1258 * Distance in the MAC. Otherwise, we need to force
1259 * speed/duplex on the MAC to the current PHY speed/duplex
1262 if (mac->type == e1000_82544)
1263 e1000_config_collision_dist_generic(hw);
1265 ret_val = e1000_config_mac_to_phy_82543(hw);
1267 DEBUGOUT("Error configuring MAC to PHY settings\n");
1273 * Configure Flow Control now that Auto-Neg has completed.
1274 * First, we need to restore the desired flow control
1275 * settings because we may have had to re-autoneg with a
1276 * different link partner.
1278 ret_val = e1000_config_fc_after_link_up_generic(hw);
1280 DEBUGOUT("Error configuring flow control\n");
1284 * At this point we know that we are on copper and we have
1285 * auto-negotiated link. These are conditions for checking the link
1286 * partner capability register. We use the link speed to determine if
1287 * TBI compatibility needs to be turned on or off. If the link is not
1288 * at gigabit speed, then TBI compatibility is not needed. If we are
1289 * at gigabit speed, we turn on TBI compatibility.
1291 if (e1000_tbi_compatibility_enabled_82543(hw)) {
1292 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1294 DEBUGOUT("Error getting link speed and duplex\n");
1297 if (speed != SPEED_1000) {
1299 * If link speed is not set to gigabit speed,
1300 * we do not need to enable TBI compatibility.
1302 if (e1000_tbi_sbp_enabled_82543(hw)) {
1304 * If we previously were in the mode,
1307 e1000_set_tbi_sbp_82543(hw, FALSE);
1308 rctl = E1000_READ_REG(hw, E1000_RCTL);
1309 rctl &= ~E1000_RCTL_SBP;
1310 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1314 * If TBI compatibility is was previously off,
1315 * turn it on. For compatibility with a TBI link
1316 * partner, we will store bad packets. Some
1317 * frames have an additional byte on the end and
1318 * will look like CRC errors to to the hardware.
1320 if (!e1000_tbi_sbp_enabled_82543(hw)) {
1321 e1000_set_tbi_sbp_82543(hw, TRUE);
1322 rctl = E1000_READ_REG(hw, E1000_RCTL);
1323 rctl |= E1000_RCTL_SBP;
1324 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1333 * e1000_check_for_fiber_link_82543 - Check for link (Fiber)
1334 * @hw: pointer to the HW structure
1336 * Checks for link up on the hardware. If link is not up and we have
1337 * a signal, then we need to force link up.
1339 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw)
1341 struct e1000_mac_info *mac = &hw->mac;
1342 u32 rxcw, ctrl, status;
1343 s32 ret_val = E1000_SUCCESS;
1345 DEBUGFUNC("e1000_check_for_fiber_link_82543");
1347 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1348 status = E1000_READ_REG(hw, E1000_STATUS);
1349 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1352 * If we don't have link (auto-negotiation failed or link partner
1353 * cannot auto-negotiate), the cable is plugged in (we have signal),
1354 * and our link partner is not trying to auto-negotiate with us (we
1355 * are receiving idles or data), we need to force link up. We also
1356 * need to give auto-negotiation time to complete, in case the cable
1357 * was just plugged in. The autoneg_failed flag does this.
1359 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */
1360 if ((!(ctrl & E1000_CTRL_SWDPIN1)) &&
1361 (!(status & E1000_STATUS_LU)) &&
1362 (!(rxcw & E1000_RXCW_C))) {
1363 if (mac->autoneg_failed == 0) {
1364 mac->autoneg_failed = 1;
1368 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
1370 /* Disable auto-negotiation in the TXCW register */
1371 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1373 /* Force link-up and also force full-duplex. */
1374 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1375 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1376 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1378 /* Configure Flow Control after forcing link up. */
1379 ret_val = e1000_config_fc_after_link_up_generic(hw);
1381 DEBUGOUT("Error configuring flow control\n");
1384 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
1386 * If we are forcing link and we are receiving /C/ ordered
1387 * sets, re-enable auto-negotiation in the TXCW register
1388 * and disable forced link in the Device Control register
1389 * in an attempt to auto-negotiate with our link partner.
1391 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
1392 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1393 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
1395 mac->serdes_has_link = TRUE;
1403 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings
1404 * @hw: pointer to the HW structure
1406 * For the 82543 silicon, we need to set the MAC to match the settings
1407 * of the PHY, even if the PHY is auto-negotiating.
1409 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw)
1412 s32 ret_val = E1000_SUCCESS;
1415 DEBUGFUNC("e1000_config_mac_to_phy_82543");
1417 if (!(hw->phy.ops.read_reg))
1420 /* Set the bits to force speed and duplex */
1421 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1422 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1423 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1426 * Set up duplex in the Device Control and Transmit Control
1427 * registers depending on negotiated values.
1429 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1433 ctrl &= ~E1000_CTRL_FD;
1434 if (phy_data & M88E1000_PSSR_DPLX)
1435 ctrl |= E1000_CTRL_FD;
1437 e1000_config_collision_dist_generic(hw);
1440 * Set up speed in the Device Control register depending on
1441 * negotiated values.
1443 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1444 ctrl |= E1000_CTRL_SPD_1000;
1445 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1446 ctrl |= E1000_CTRL_SPD_100;
1448 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1455 * e1000_write_vfta_82543 - Write value to VLAN filter table
1456 * @hw: pointer to the HW structure
1457 * @offset: the 32-bit offset in which to write the value to.
1458 * @value: the 32-bit value to write at location offset.
1460 * This writes a 32-bit value to a 32-bit offset in the VLAN filter
1463 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value)
1467 DEBUGFUNC("e1000_write_vfta_82543");
1469 if ((hw->mac.type == e1000_82544) && (offset & 1)) {
1470 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1);
1471 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
1472 E1000_WRITE_FLUSH(hw);
1473 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp);
1474 E1000_WRITE_FLUSH(hw);
1476 e1000_write_vfta_generic(hw, offset, value);
1481 * e1000_led_on_82543 - Turn on SW controllable LED
1482 * @hw: pointer to the HW structure
1484 * Turns the SW defined LED on.
1486 static s32 e1000_led_on_82543(struct e1000_hw *hw)
1488 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1490 DEBUGFUNC("e1000_led_on_82543");
1492 if (hw->mac.type == e1000_82544 &&
1493 hw->phy.media_type == e1000_media_type_copper) {
1494 /* Clear SW-definable Pin 0 to turn on the LED */
1495 ctrl &= ~E1000_CTRL_SWDPIN0;
1496 ctrl |= E1000_CTRL_SWDPIO0;
1498 /* Fiber 82544 and all 82543 use this method */
1499 ctrl |= E1000_CTRL_SWDPIN0;
1500 ctrl |= E1000_CTRL_SWDPIO0;
1502 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1504 return E1000_SUCCESS;
1508 * e1000_led_off_82543 - Turn off SW controllable LED
1509 * @hw: pointer to the HW structure
1511 * Turns the SW defined LED off.
1513 static s32 e1000_led_off_82543(struct e1000_hw *hw)
1515 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1517 DEBUGFUNC("e1000_led_off_82543");
1519 if (hw->mac.type == e1000_82544 &&
1520 hw->phy.media_type == e1000_media_type_copper) {
1521 /* Set SW-definable Pin 0 to turn off the LED */
1522 ctrl |= E1000_CTRL_SWDPIN0;
1523 ctrl |= E1000_CTRL_SWDPIO0;
1525 ctrl &= ~E1000_CTRL_SWDPIN0;
1526 ctrl |= E1000_CTRL_SWDPIO0;
1528 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1530 return E1000_SUCCESS;
1534 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters
1535 * @hw: pointer to the HW structure
1537 * Clears the hardware counters by reading the counter registers.
1539 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw)
1541 DEBUGFUNC("e1000_clear_hw_cntrs_82543");
1543 e1000_clear_hw_cntrs_base_generic(hw);
1545 E1000_READ_REG(hw, E1000_PRC64);
1546 E1000_READ_REG(hw, E1000_PRC127);
1547 E1000_READ_REG(hw, E1000_PRC255);
1548 E1000_READ_REG(hw, E1000_PRC511);
1549 E1000_READ_REG(hw, E1000_PRC1023);
1550 E1000_READ_REG(hw, E1000_PRC1522);
1551 E1000_READ_REG(hw, E1000_PTC64);
1552 E1000_READ_REG(hw, E1000_PTC127);
1553 E1000_READ_REG(hw, E1000_PTC255);
1554 E1000_READ_REG(hw, E1000_PTC511);
1555 E1000_READ_REG(hw, E1000_PTC1023);
1556 E1000_READ_REG(hw, E1000_PTC1522);
1558 E1000_READ_REG(hw, E1000_ALGNERRC);
1559 E1000_READ_REG(hw, E1000_RXERRC);
1560 E1000_READ_REG(hw, E1000_TNCRS);
1561 E1000_READ_REG(hw, E1000_CEXTERR);
1562 E1000_READ_REG(hw, E1000_TSCTC);
1563 E1000_READ_REG(hw, E1000_TSCTFC);
1567 * e1000_read_mac_addr_82543 - Read device MAC address
1568 * @hw: pointer to the HW structure
1570 * Reads the device MAC address from the EEPROM and stores the value.
1571 * Since devices with two ports use the same EEPROM, we increment the
1572 * last bit in the MAC address for the second port.
1575 s32 e1000_read_mac_addr_82543(struct e1000_hw *hw)
1577 s32 ret_val = E1000_SUCCESS;
1578 u16 offset, nvm_data, i;
1580 DEBUGFUNC("e1000_read_mac_addr");
1582 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
1584 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
1586 DEBUGOUT("NVM Read Error\n");
1589 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
1590 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
1593 /* Flip last bit of mac address if we're on second port */
1594 if (hw->bus.func == E1000_FUNC_1)
1595 hw->mac.perm_addr[5] ^= 1;
1597 for (i = 0; i < ETH_ADDR_LEN; i++)
1598 hw->mac.addr[i] = hw->mac.perm_addr[i];