2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $
33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.38 2008/08/17 04:32:34 sephe Exp $
37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
38 * available from http://www.sis.com.tw.
40 * This driver also supports the NatSemi DP83815. Datasheets are
41 * available from http://www.national.com.
43 * Written by Bill Paul <wpaul@ee.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
50 * simple TX and RX descriptors of 3 longwords in size. The receiver
51 * has a single perfect filter entry for the station address and a
52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
53 * transceiver while the 7016 requires an external transceiver chip.
54 * Both chips offer the standard bit-bang MII interface as well as
55 * an enchanced PHY interface which simplifies accessing MII registers.
57 * The only downside to this chipset is that RX descriptors must be
61 #include "opt_polling.h"
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 #include <sys/sockio.h>
67 #include <sys/malloc.h>
68 #include <sys/kernel.h>
69 #include <sys/socket.h>
70 #include <sys/sysctl.h>
71 #include <sys/serialize.h>
72 #include <sys/thread2.h>
75 #include <sys/interrupt.h>
78 #include <net/ifq_var.h>
79 #include <net/if_arp.h>
80 #include <net/ethernet.h>
81 #include <net/if_dl.h>
82 #include <net/if_media.h>
83 #include <net/if_types.h>
84 #include <net/vlan/if_vlan_var.h>
88 #include <dev/netif/mii_layer/mii.h>
89 #include <dev/netif/mii_layer/miivar.h>
91 #include <bus/pci/pcidevs.h>
92 #include <bus/pci/pcireg.h>
93 #include <bus/pci/pcivar.h>
95 #define SIS_USEIOSPACE
97 #include "if_sisreg.h"
99 /* "controller miibus0" required. See GENERIC if you get errors here. */
100 #include "miibus_if.h"
103 * Various supported device vendors/types and their names.
105 static struct sis_type sis_devs[] = {
106 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, "SiS 900 10/100BaseTX" },
107 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, "SiS 7016 10/100BaseTX" },
108 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
112 static int sis_probe(device_t);
113 static int sis_attach(device_t);
114 static int sis_detach(device_t);
116 static int sis_newbuf(struct sis_softc *, int, int);
117 static void sis_setup_rxdesc(struct sis_softc *, int);
118 static int sis_encap(struct sis_softc *, struct mbuf **, uint32_t *);
119 static void sis_rxeof(struct sis_softc *);
120 static void sis_rxeoc(struct sis_softc *);
121 static void sis_txeof(struct sis_softc *);
122 static void sis_intr(void *);
123 static void sis_tick(void *);
124 static void sis_start(struct ifnet *);
125 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
126 static void sis_init(void *);
127 static void sis_stop(struct sis_softc *);
128 static void sis_watchdog(struct ifnet *);
129 static void sis_shutdown(device_t);
130 static int sis_ifmedia_upd(struct ifnet *);
131 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
133 static uint16_t sis_reverse(uint16_t);
134 static void sis_delay(struct sis_softc *);
135 static void sis_eeprom_idle(struct sis_softc *);
136 static void sis_eeprom_putbyte(struct sis_softc *, int);
137 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *);
138 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int);
140 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int);
141 static void sis_read_mac(struct sis_softc *, device_t, caddr_t);
142 static device_t sis_find_bridge(device_t);
145 static void sis_mii_sync(struct sis_softc *);
146 static void sis_mii_send(struct sis_softc *, uint32_t, int);
147 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *);
148 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *);
149 static int sis_miibus_readreg(device_t, int, int);
150 static int sis_miibus_writereg(device_t, int, int, int);
151 static void sis_miibus_statchg(device_t);
153 static void sis_setmulti_sis(struct sis_softc *);
154 static void sis_setmulti_ns(struct sis_softc *);
155 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *);
156 static void sis_reset(struct sis_softc *);
157 static int sis_list_rx_init(struct sis_softc *);
158 static int sis_list_tx_init(struct sis_softc *);
160 static int sis_dma_alloc(device_t dev);
161 static void sis_dma_free(device_t dev);
162 #ifdef DEVICE_POLLING
163 static poll_handler_t sis_poll;
165 #ifdef SIS_USEIOSPACE
166 #define SIS_RES SYS_RES_IOPORT
167 #define SIS_RID SIS_PCI_LOIO
169 #define SIS_RES SYS_RES_MEMORY
170 #define SIS_RID SIS_PCI_LOMEM
173 static device_method_t sis_methods[] = {
174 /* Device interface */
175 DEVMETHOD(device_probe, sis_probe),
176 DEVMETHOD(device_attach, sis_attach),
177 DEVMETHOD(device_detach, sis_detach),
178 DEVMETHOD(device_shutdown, sis_shutdown),
181 DEVMETHOD(bus_print_child, bus_generic_print_child),
182 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
185 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
186 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
187 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
192 static driver_t sis_driver = {
195 sizeof(struct sis_softc)
198 static devclass_t sis_devclass;
200 DECLARE_DUMMY_MODULE(if_sis);
201 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0);
202 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
204 #define SIS_SETBIT(sc, reg, x) \
205 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
207 #define SIS_CLRBIT(sc, reg, x) \
208 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
211 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
214 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
217 * Routine to reverse the bits in a word. Stolen almost
218 * verbatim from /usr/games/fortune.
221 sis_reverse(uint16_t n)
223 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
224 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
225 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
226 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
232 sis_delay(struct sis_softc *sc)
236 for (idx = (300 / 33) + 1; idx > 0; idx--)
237 CSR_READ_4(sc, SIS_CSR);
241 sis_eeprom_idle(struct sis_softc *sc)
245 SIO_SET(SIS_EECTL_CSEL);
247 SIO_SET(SIS_EECTL_CLK);
250 for (i = 0; i < 25; i++) {
251 SIO_CLR(SIS_EECTL_CLK);
253 SIO_SET(SIS_EECTL_CLK);
257 SIO_CLR(SIS_EECTL_CLK);
259 SIO_CLR(SIS_EECTL_CSEL);
261 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
265 * Send a read command and address to the EEPROM, check for ACK.
268 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
272 d = addr | SIS_EECMD_READ;
275 * Feed in each bit and stobe the clock.
277 for (i = 0x400; i; i >>= 1) {
279 SIO_SET(SIS_EECTL_DIN);
281 SIO_CLR(SIS_EECTL_DIN);
283 SIO_SET(SIS_EECTL_CLK);
285 SIO_CLR(SIS_EECTL_CLK);
291 * Read a word of data stored in the EEPROM at address 'addr.'
294 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
299 /* Force EEPROM to idle state. */
302 /* Enter EEPROM access mode. */
304 SIO_CLR(SIS_EECTL_CLK);
306 SIO_SET(SIS_EECTL_CSEL);
310 * Send address of word we want to read.
312 sis_eeprom_putbyte(sc, addr);
315 * Start reading bits from EEPROM.
317 for (i = 0x8000; i; i >>= 1) {
318 SIO_SET(SIS_EECTL_CLK);
320 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
323 SIO_CLR(SIS_EECTL_CLK);
327 /* Turn off EEPROM access mode. */
334 * Read a sequence of words from the EEPROM.
337 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
340 uint16_t word = 0, *ptr;
342 for (i = 0; i < cnt; i++) {
343 sis_eeprom_getword(sc, off + i, &word);
344 ptr = (uint16_t *)(dest + (i * 2));
354 sis_find_bridge(device_t dev)
356 devclass_t pci_devclass;
357 device_t *pci_devices;
359 device_t *pci_children;
360 int pci_childcount = 0;
361 device_t *busp, *childp;
362 device_t child = NULL;
365 if ((pci_devclass = devclass_find("pci")) == NULL)
368 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
370 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
372 device_get_children(*busp, &pci_children, &pci_childcount);
373 for (j = 0, childp = pci_children; j < pci_childcount;
375 if (pci_get_vendor(*childp) == PCI_VENDOR_SIS &&
376 pci_get_device(*childp) == 0x0008) {
384 kfree(pci_devices, M_TEMP);
385 kfree(pci_children, M_TEMP);
390 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off,
396 bus_space_tag_t btag;
398 bridge = sis_find_bridge(dev);
401 reg = pci_read_config(bridge, 0x48, 1);
402 pci_write_config(bridge, 0x48, reg|0x40, 1);
405 btag = I386_BUS_SPACE_IO;
407 for (i = 0; i < cnt; i++) {
408 bus_space_write_1(btag, 0x0, 0x70, i + off);
409 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
412 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
416 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
418 uint32_t filtsave, csrsave;
420 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
421 csrsave = CSR_READ_4(sc, SIS_CSR);
423 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
424 CSR_WRITE_4(sc, SIS_CSR, 0);
426 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
428 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
429 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
430 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
431 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
432 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
433 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
435 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
436 CSR_WRITE_4(sc, SIS_CSR, csrsave);
441 * Sync the PHYs by setting data bit and strobing the clock 32 times.
444 sis_mii_sync(struct sis_softc *sc)
448 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
450 for (i = 0; i < 32; i++) {
451 SIO_SET(SIS_MII_CLK);
453 SIO_CLR(SIS_MII_CLK);
459 * Clock a series of bits through the MII.
462 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
466 SIO_CLR(SIS_MII_CLK);
468 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
470 SIO_SET(SIS_MII_DATA);
472 SIO_CLR(SIS_MII_DATA);
474 SIO_CLR(SIS_MII_CLK);
476 SIO_SET(SIS_MII_CLK);
481 * Read an PHY register through the MII.
484 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
489 * Set up frame for RX.
491 frame->mii_stdelim = SIS_MII_STARTDELIM;
492 frame->mii_opcode = SIS_MII_READOP;
493 frame->mii_turnaround = 0;
499 SIO_SET(SIS_MII_DIR);
504 * Send command/address info.
506 sis_mii_send(sc, frame->mii_stdelim, 2);
507 sis_mii_send(sc, frame->mii_opcode, 2);
508 sis_mii_send(sc, frame->mii_phyaddr, 5);
509 sis_mii_send(sc, frame->mii_regaddr, 5);
512 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
514 SIO_SET(SIS_MII_CLK);
518 SIO_CLR(SIS_MII_DIR);
521 SIO_CLR(SIS_MII_CLK);
523 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
524 SIO_SET(SIS_MII_CLK);
528 * Now try reading data bits. If the ack failed, we still
529 * need to clock through 16 cycles to keep the PHY(s) in sync.
532 for(i = 0; i < 16; i++) {
533 SIO_CLR(SIS_MII_CLK);
535 SIO_SET(SIS_MII_CLK);
541 for (i = 0x8000; i; i >>= 1) {
542 SIO_CLR(SIS_MII_CLK);
545 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
546 frame->mii_data |= i;
549 SIO_SET(SIS_MII_CLK);
555 SIO_CLR(SIS_MII_CLK);
557 SIO_SET(SIS_MII_CLK);
566 * Write to a PHY register through the MII.
569 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
572 * Set up frame for TX.
575 frame->mii_stdelim = SIS_MII_STARTDELIM;
576 frame->mii_opcode = SIS_MII_WRITEOP;
577 frame->mii_turnaround = SIS_MII_TURNAROUND;
580 * Turn on data output.
582 SIO_SET(SIS_MII_DIR);
586 sis_mii_send(sc, frame->mii_stdelim, 2);
587 sis_mii_send(sc, frame->mii_opcode, 2);
588 sis_mii_send(sc, frame->mii_phyaddr, 5);
589 sis_mii_send(sc, frame->mii_regaddr, 5);
590 sis_mii_send(sc, frame->mii_turnaround, 2);
591 sis_mii_send(sc, frame->mii_data, 16);
594 SIO_SET(SIS_MII_CLK);
596 SIO_CLR(SIS_MII_CLK);
602 SIO_CLR(SIS_MII_DIR);
608 sis_miibus_readreg(device_t dev, int phy, int reg)
610 struct sis_softc *sc;
611 struct sis_mii_frame frame;
613 sc = device_get_softc(dev);
615 if (sc->sis_type == SIS_TYPE_83815) {
619 * The NatSemi chip can take a while after
620 * a reset to come ready, during which the BMSR
621 * returns a value of 0. This is *never* supposed
622 * to happen: some of the BMSR bits are meant to
623 * be hardwired in the on position, and this can
624 * confuse the miibus code a bit during the probe
625 * and attach phase. So we make an effort to check
626 * for this condition and wait for it to clear.
628 if (!CSR_READ_4(sc, NS_BMSR))
630 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
633 * Chipsets < SIS_635 seem not to be able to read/write
634 * through mdio. Use the enhanced PHY access register
637 if (sc->sis_type == SIS_TYPE_900 &&
638 sc->sis_rev < SIS_REV_635) {
644 CSR_WRITE_4(sc, SIS_PHYCTL,
645 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
646 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
648 for (i = 0; i < SIS_TIMEOUT; i++) {
649 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
653 if (i == SIS_TIMEOUT) {
654 device_printf(dev, "PHY failed to come ready\n");
658 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
665 bzero((char *)&frame, sizeof(frame));
667 frame.mii_phyaddr = phy;
668 frame.mii_regaddr = reg;
669 sis_mii_readreg(sc, &frame);
671 return(frame.mii_data);
676 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
678 struct sis_softc *sc;
679 struct sis_mii_frame frame;
681 sc = device_get_softc(dev);
683 if (sc->sis_type == SIS_TYPE_83815) {
686 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
690 if (sc->sis_type == SIS_TYPE_900 &&
691 sc->sis_rev < SIS_REV_635) {
697 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
698 (reg << 6) | SIS_PHYOP_WRITE);
699 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
701 for (i = 0; i < SIS_TIMEOUT; i++) {
702 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
706 if (i == SIS_TIMEOUT)
707 device_printf(dev, "PHY failed to come ready\n");
709 bzero((char *)&frame, sizeof(frame));
711 frame.mii_phyaddr = phy;
712 frame.mii_regaddr = reg;
713 frame.mii_data = data;
714 sis_mii_writereg(sc, &frame);
720 sis_miibus_statchg(device_t dev)
722 struct sis_softc *sc;
724 sc = device_get_softc(dev);
729 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
735 /* Compute CRC for the address value. */
736 crc = 0xFFFFFFFF; /* initial value */
738 for (i = 0; i < 6; i++) {
740 for (j = 0; j < 8; j++) {
741 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
745 crc = (crc ^ 0x04c11db6) | carry;
750 * return the filter bit position
752 * The NatSemi chip has a 512-bit filter, which is
753 * different than the SiS, so we special-case it.
755 if (sc->sis_type == SIS_TYPE_83815)
757 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
764 sis_setmulti_ns(struct sis_softc *sc)
767 struct ifmultiaddr *ifma;
768 uint32_t h = 0, i, filtsave;
771 ifp = &sc->arpcom.ac_if;
773 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
774 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
775 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
780 * We have to explicitly enable the multicast hash table
781 * on the NatSemi chip if we want to use it, which we do.
783 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
784 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
786 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
788 /* first, zot all the existing hash bits */
789 for (i = 0; i < 32; i++) {
790 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
791 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
794 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
795 if (ifma->ifma_addr->sa_family != AF_LINK)
798 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
801 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
804 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
807 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
811 sis_setmulti_sis(struct sis_softc *sc)
814 struct ifmultiaddr *ifma;
815 uint32_t h, i, n, ctl;
818 ifp = &sc->arpcom.ac_if;
820 /* hash table size */
821 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
826 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
828 if (ifp->if_flags & IFF_BROADCAST)
829 ctl |= SIS_RXFILTCTL_BROAD;
831 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
832 ctl |= SIS_RXFILTCTL_ALLMULTI;
833 if (ifp->if_flags & IFF_PROMISC)
834 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
835 for (i = 0; i < n; i++)
838 for (i = 0; i < n; i++)
841 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
842 if (ifma->ifma_addr->sa_family != AF_LINK)
845 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
846 hashes[h >> 4] |= 1 << (h & 0xf);
850 ctl |= SIS_RXFILTCTL_ALLMULTI;
851 for (i = 0; i < n; i++)
856 for (i = 0; i < n; i++) {
857 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
858 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
861 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
865 sis_reset(struct sis_softc *sc)
867 struct ifnet *ifp = &sc->arpcom.ac_if;
870 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
872 for (i = 0; i < SIS_TIMEOUT; i++) {
873 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
877 if (i == SIS_TIMEOUT)
878 if_printf(ifp, "reset never completed\n");
880 /* Wait a little while for the chip to get its brains in order. */
884 * If this is a NetSemi chip, make sure to clear
887 if (sc->sis_type == SIS_TYPE_83815) {
888 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
889 CSR_WRITE_4(sc, NS_CLKRUN, 0);
894 * Probe for an SiS chip. Check the PCI vendor and device
895 * IDs against our list and return a device name if we find a match.
898 sis_probe(device_t dev)
904 while(t->sis_name != NULL) {
905 if ((pci_get_vendor(dev) == t->sis_vid) &&
906 (pci_get_device(dev) == t->sis_did)) {
907 device_set_desc(dev, t->sis_name);
917 * Attach the interface. Allocate softc structures, do ifmedia
918 * setup and ethernet/BPF attach.
921 sis_attach(device_t dev)
923 uint8_t eaddr[ETHER_ADDR_LEN];
925 struct sis_softc *sc;
927 int error, rid, waittime;
929 error = waittime = 0;
930 sc = device_get_softc(dev);
932 if (pci_get_device(dev) == PCI_PRODUCT_SIS_900)
933 sc->sis_type = SIS_TYPE_900;
934 if (pci_get_device(dev) == PCI_PRODUCT_SIS_7016)
935 sc->sis_type = SIS_TYPE_7016;
936 if (pci_get_vendor(dev) == PCI_VENDOR_NS)
937 sc->sis_type = SIS_TYPE_83815;
939 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
942 * Handle power management nonsense.
945 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF;
946 if (command == 0x01) {
948 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4);
949 if (command & SIS_PSTATE_MASK) {
950 uint32_t iobase, membase, irq;
952 /* Save important PCI config data. */
953 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4);
954 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4);
955 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4);
957 /* Reset the power state. */
958 device_printf(dev, "chip is in D%d power mode "
959 "-- setting to D0\n", command & SIS_PSTATE_MASK);
960 command &= 0xFFFFFFFC;
961 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4);
963 /* Restore PCI config data. */
964 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4);
965 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4);
966 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4);
971 * Map control/status registers.
973 command = pci_read_config(dev, PCIR_COMMAND, 4);
974 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
975 pci_write_config(dev, PCIR_COMMAND, command, 4);
976 command = pci_read_config(dev, PCIR_COMMAND, 4);
978 #ifdef SIS_USEIOSPACE
979 if (!(command & PCIM_CMD_PORTEN)) {
980 device_printf(dev, "failed to enable I/O ports!\n");
985 if (!(command & PCIM_CMD_MEMEN)) {
986 device_printf(dev, "failed to enable memory mapping!\n");
993 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE);
995 if (sc->sis_res == NULL) {
996 device_printf(dev, "couldn't map ports/memory\n");
1001 sc->sis_btag = rman_get_bustag(sc->sis_res);
1002 sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
1004 /* Allocate interrupt */
1006 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1007 RF_SHAREABLE | RF_ACTIVE);
1009 if (sc->sis_irq == NULL) {
1010 device_printf(dev, "couldn't map interrupt\n");
1015 /* Reset the adapter. */
1018 if (sc->sis_type == SIS_TYPE_900 &&
1019 (sc->sis_rev == SIS_REV_635 ||
1020 sc->sis_rev == SIS_REV_900B)) {
1021 SIO_SET(SIS_CFG_RND_CNT);
1022 SIO_SET(SIS_CFG_PERR_DETECT);
1026 * Get station address from the EEPROM.
1028 switch (pci_get_vendor(dev)) {
1031 * Reading the MAC address out of the EEPROM on
1032 * the NatSemi chip takes a bit more work than
1033 * you'd expect. The address spans 4 16-bit words,
1034 * with the first word containing only a single bit.
1035 * You have to shift everything over one bit to
1036 * get it aligned properly. Also, the bits are
1037 * stored backwards (the LSB is really the MSB,
1038 * and so on) so you have to reverse them in order
1039 * to get the MAC address into the form we want.
1040 * Why? Who the hell knows.
1045 sis_read_eeprom(sc, (caddr_t)&tmp,
1046 NS_EE_NODEADDR, 4, 0);
1048 /* Shift everything over one bit. */
1049 tmp[3] = tmp[3] >> 1;
1050 tmp[3] |= tmp[2] << 15;
1051 tmp[2] = tmp[2] >> 1;
1052 tmp[2] |= tmp[1] << 15;
1053 tmp[1] = tmp[1] >> 1;
1054 tmp[1] |= tmp[0] << 15;
1056 /* Now reverse all the bits. */
1057 tmp[3] = sis_reverse(tmp[3]);
1058 tmp[2] = sis_reverse(tmp[2]);
1059 tmp[1] = sis_reverse(tmp[1]);
1061 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
1064 case PCI_VENDOR_SIS:
1068 * If this is a SiS 630E chipset with an embedded
1069 * SiS 900 controller, we have to read the MAC address
1070 * from the APC CMOS RAM. Our method for doing this
1071 * is very ugly since we have to reach out and grab
1072 * ahold of hardware for which we cannot properly
1073 * allocate resources. This code is only compiled on
1074 * the i386 architecture since the SiS 630E chipset
1075 * is for x86 motherboards only. Note that there are
1076 * a lot of magic numbers in this hack. These are
1077 * taken from SiS's Linux driver. I'd like to replace
1078 * them with proper symbolic definitions, but that
1079 * requires some datasheets that I don't have access
1082 if (sc->sis_rev == SIS_REV_630S ||
1083 sc->sis_rev == SIS_REV_630E ||
1084 sc->sis_rev == SIS_REV_630EA1)
1085 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1087 else if (sc->sis_rev == SIS_REV_635 ||
1088 sc->sis_rev == SIS_REV_630ET)
1089 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1090 else if (sc->sis_rev == SIS_REV_96x) {
1092 * Allow to read EEPROM from LAN. It is shared
1093 * between a 1394 controller and the NIC and each
1094 * time we access it, we need to set SIS_EECMD_REQ.
1096 SIO_SET(SIS_EECMD_REQ);
1097 for (waittime = 0; waittime < SIS_TIMEOUT;
1099 /* Force EEPROM to idle state. */
1100 sis_eeprom_idle(sc);
1101 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1102 sis_read_eeprom(sc, (caddr_t)&eaddr,
1103 SIS_EE_NODEADDR, 3, 0);
1109 * Set SIS_EECTL_CLK to high, so a other master
1110 * can operate on the i2c bus.
1112 SIO_SET(SIS_EECTL_CLK);
1113 /* Refuse EEPROM access by LAN */
1114 SIO_SET(SIS_EECMD_DONE);
1117 sis_read_eeprom(sc, (caddr_t)&eaddr,
1118 SIS_EE_NODEADDR, 3, 0);
1122 callout_init(&sc->sis_timer);
1124 error = sis_dma_alloc(dev);
1128 ifp = &sc->arpcom.ac_if;
1130 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1131 ifp->if_mtu = ETHERMTU;
1132 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1133 ifp->if_ioctl = sis_ioctl;
1134 ifp->if_start = sis_start;
1135 ifp->if_watchdog = sis_watchdog;
1136 ifp->if_init = sis_init;
1137 ifp->if_baudrate = 10000000;
1138 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1139 ifq_set_ready(&ifp->if_snd);
1140 #ifdef DEVICE_POLLING
1141 ifp->if_poll = sis_poll;
1143 ifp->if_capenable = ifp->if_capabilities;
1148 if (mii_phy_probe(dev, &sc->sis_miibus,
1149 sis_ifmedia_upd, sis_ifmedia_sts)) {
1150 device_printf(dev, "MII without any PHY!\n");
1156 * Call MI attach routine.
1158 ether_ifattach(ifp, eaddr, NULL);
1161 * Tell the upper layer(s) we support long frames.
1163 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1165 error = bus_setup_intr(dev, sc->sis_irq, INTR_MPSAFE,
1168 ifp->if_serializer);
1171 device_printf(dev, "couldn't set up irq\n");
1172 ether_ifdetach(ifp);
1176 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sis_irq));
1177 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1187 * Shutdown hardware and free up resources. It is called in both the error case
1188 * and the normal detach case so it needs to be careful about only freeing
1189 * resources that have actually been allocated.
1192 sis_detach(device_t dev)
1194 struct sis_softc *sc = device_get_softc(dev);
1195 struct ifnet *ifp = &sc->arpcom.ac_if;
1198 if (device_is_attached(dev)) {
1199 lwkt_serialize_enter(ifp->if_serializer);
1202 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1203 lwkt_serialize_exit(ifp->if_serializer);
1205 ether_ifdetach(ifp);
1208 device_delete_child(dev, sc->sis_miibus);
1209 bus_generic_detach(dev);
1212 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1214 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1222 * Initialize the transmit descriptors.
1225 sis_list_tx_init(struct sis_softc *sc)
1227 struct sis_list_data *ld = &sc->sis_ldata;
1228 struct sis_chain_data *cd = &sc->sis_cdata;
1231 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1235 * Link the TX desc together
1237 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1;
1238 paddr = ld->sis_tx_paddr + (nexti * sizeof(struct sis_desc));
1239 ld->sis_tx_list[i].sis_next = paddr;
1241 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0;
1247 * Initialize the RX descriptors and allocate mbufs for them. Note that
1248 * we arrange the descriptors in a closed ring, so that the last descriptor
1249 * points back to the first.
1252 sis_list_rx_init(struct sis_softc *sc)
1254 struct sis_list_data *ld = &sc->sis_ldata;
1255 struct sis_chain_data *cd = &sc->sis_cdata;
1258 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1262 error = sis_newbuf(sc, i, 1);
1267 * Link the RX desc together
1269 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1;
1270 paddr = ld->sis_rx_paddr + (nexti * sizeof(struct sis_desc));
1271 ld->sis_rx_list[i].sis_next = paddr;
1273 cd->sis_rx_prod = 0;
1279 * Initialize an RX descriptor and attach an MBUF cluster.
1282 sis_newbuf(struct sis_softc *sc, int idx, int init)
1284 struct sis_chain_data *cd = &sc->sis_cdata;
1285 struct sis_rx_data *rd = &cd->sis_rx_data[idx];
1286 bus_dma_segment_t seg;
1291 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1294 if_printf(&sc->arpcom.ac_if, "can't alloc RX mbuf\n");
1297 m->m_len = m->m_pkthdr.len = MCLBYTES;
1299 /* Try loading the mbuf into tmp DMA map */
1300 error = bus_dmamap_load_mbuf_segment(cd->sis_rxbuf_tag,
1301 cd->sis_rx_tmpmap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
1305 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
1309 /* Unload the currently loaded mbuf */
1310 if (rd->sis_mbuf != NULL) {
1311 bus_dmamap_sync(cd->sis_rxbuf_tag, rd->sis_map,
1312 BUS_DMASYNC_POSTREAD);
1313 bus_dmamap_unload(cd->sis_rxbuf_tag, rd->sis_map);
1317 map = cd->sis_rx_tmpmap;
1318 cd->sis_rx_tmpmap = rd->sis_map;
1321 /* Save necessary information */
1323 rd->sis_paddr = seg.ds_addr;
1325 sis_setup_rxdesc(sc, idx);
1330 sis_setup_rxdesc(struct sis_softc *sc, int idx)
1332 struct sis_desc *c = &sc->sis_ldata.sis_rx_list[idx];
1334 /* Setup the RX desc */
1335 c->sis_ctl = SIS_RXLEN;
1336 c->sis_ptr = sc->sis_cdata.sis_rx_data[idx].sis_paddr;
1340 * A frame has been uploaded: pass the resulting mbuf chain up to
1341 * the higher level protocols.
1344 sis_rxeof(struct sis_softc *sc)
1346 struct ifnet *ifp = &sc->arpcom.ac_if;
1347 int i, total_len = 0;
1350 i = sc->sis_cdata.sis_rx_prod;
1351 while (SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) {
1352 struct sis_desc *cur_rx;
1353 struct sis_rx_data *rd;
1357 #ifdef DEVICE_POLLING
1358 if (ifp->if_flags & IFF_POLLING) {
1359 if (sc->rxcycles <= 0)
1363 #endif /* DEVICE_POLLING */
1365 cur_rx = &sc->sis_ldata.sis_rx_list[idx];
1366 rd = &sc->sis_cdata.sis_rx_data[idx];
1368 rxstat = cur_rx->sis_rxstat;
1369 total_len = SIS_RXBYTES(cur_rx);
1373 SIS_INC(i, SIS_RX_LIST_CNT);
1376 * If an error occurs, update stats, clear the
1377 * status word and leave the mbuf cluster in place:
1378 * it should simply get re-used next time this descriptor
1379 * comes up in the ring.
1381 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
1383 if (rxstat & SIS_RXSTAT_COLL)
1384 ifp->if_collisions++;
1385 sis_setup_rxdesc(sc, idx);
1389 /* No errors; receive the packet. */
1390 if (sis_newbuf(sc, idx, 0) == 0) {
1391 m->m_pkthdr.len = m->m_len = total_len;
1392 m->m_pkthdr.rcvif = ifp;
1395 sis_setup_rxdesc(sc, idx);
1400 ifp->if_input(ifp, m);
1402 sc->sis_cdata.sis_rx_prod = i;
1406 sis_rxeoc(struct sis_softc *sc)
1413 * A frame was downloaded to the chip. It's safe for us to clean up
1418 sis_txeof(struct sis_softc *sc)
1420 struct ifnet *ifp = &sc->arpcom.ac_if;
1421 struct sis_chain_data *cd = &sc->sis_cdata;
1425 * Go through our tx list and free mbufs for those
1426 * frames that have been transmitted.
1428 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0;
1429 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) {
1430 struct sis_desc *cur_tx;
1431 struct sis_tx_data *td;
1433 cur_tx = &sc->sis_ldata.sis_tx_list[idx];
1434 td = &cd->sis_tx_data[idx];
1436 if (SIS_OWNDESC(cur_tx))
1439 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE)
1442 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1444 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1445 ifp->if_collisions++;
1446 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1447 ifp->if_collisions++;
1450 ifp->if_collisions +=
1451 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
1454 if (td->sis_mbuf != NULL) {
1455 bus_dmamap_unload(cd->sis_txbuf_tag, td->sis_map);
1456 m_freem(td->sis_mbuf);
1457 td->sis_mbuf = NULL;
1461 if (idx != sc->sis_cdata.sis_tx_cons) {
1462 /* we freed up some buffers */
1463 sc->sis_cdata.sis_tx_cons = idx;
1466 if (cd->sis_tx_cnt == 0)
1468 if (!SIS_IS_OACTIVE(sc))
1469 ifp->if_flags &= ~IFF_OACTIVE;
1475 struct sis_softc *sc = xsc;
1476 struct mii_data *mii;
1477 struct ifnet *ifp = &sc->arpcom.ac_if;
1479 lwkt_serialize_enter(ifp->if_serializer);
1481 mii = device_get_softc(sc->sis_miibus);
1484 if (!sc->sis_link) {
1486 if (mii->mii_media_status & IFM_ACTIVE &&
1487 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1489 if (!ifq_is_empty(&ifp->if_snd))
1493 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
1494 lwkt_serialize_exit(ifp->if_serializer);
1497 #ifdef DEVICE_POLLING
1500 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1502 struct sis_softc *sc = ifp->if_softc;
1506 /* disable interrupts */
1507 CSR_WRITE_4(sc, SIS_IER, 0);
1509 case POLL_DEREGISTER:
1510 /* enable interrupts */
1511 CSR_WRITE_4(sc, SIS_IER, 1);
1515 * On the sis, reading the status register also clears it.
1516 * So before returning to intr mode we must make sure that all
1517 * possible pending sources of interrupts have been served.
1518 * In practice this means run to completion the *eof routines,
1519 * and then call the interrupt routine
1521 sc->rxcycles = count;
1524 if (!ifq_is_empty(&ifp->if_snd))
1527 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1530 /* Reading the ISR register clears all interrupts. */
1531 status = CSR_READ_4(sc, SIS_ISR);
1533 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1536 if (status & (SIS_ISR_RX_IDLE))
1537 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1539 if (status & SIS_ISR_SYSERR) {
1547 #endif /* DEVICE_POLLING */
1552 struct sis_softc *sc;
1557 ifp = &sc->arpcom.ac_if;
1559 /* Supress unwanted interrupts */
1560 if (!(ifp->if_flags & IFF_UP)) {
1565 /* Disable interrupts. */
1566 CSR_WRITE_4(sc, SIS_IER, 0);
1569 /* Reading the ISR register clears all interrupts. */
1570 status = CSR_READ_4(sc, SIS_ISR);
1572 if ((status & SIS_INTRS) == 0)
1576 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK |
1581 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE))
1584 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
1587 if (status & (SIS_ISR_RX_IDLE))
1588 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1590 if (status & SIS_ISR_SYSERR) {
1596 /* Re-enable interrupts. */
1597 CSR_WRITE_4(sc, SIS_IER, 1);
1599 if (!ifq_is_empty(&ifp->if_snd))
1604 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1605 * pointers to the fragment pointers.
1608 sis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx)
1610 struct sis_chain_data *cd = &sc->sis_cdata;
1611 struct sis_list_data *ld = &sc->sis_ldata;
1612 bus_dma_segment_t segs[SIS_NSEGS];
1614 int frag, cur, maxsegs, nsegs, error, i;
1616 maxsegs = SIS_TX_LIST_CNT - SIS_NSEGS_RESERVED - cd->sis_tx_cnt;
1617 KASSERT(maxsegs >= 1, ("not enough TX descs\n"));
1618 if (maxsegs > SIS_NSEGS)
1619 maxsegs = SIS_NSEGS;
1621 map = cd->sis_tx_data[*txidx].sis_map;
1622 error = bus_dmamap_load_mbuf_defrag(cd->sis_txbuf_tag, map, m_head,
1623 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1629 bus_dmamap_sync(cd->sis_txbuf_tag, map, BUS_DMASYNC_PREWRITE);
1631 cur = frag = *txidx;
1632 for (i = 0; i < nsegs; ++i) {
1633 struct sis_desc *f = &ld->sis_tx_list[frag];
1635 f->sis_ctl = SIS_CMDSTS_MORE | segs[i].ds_len;
1636 f->sis_ptr = segs[i].ds_addr;
1638 f->sis_ctl |= SIS_CMDSTS_OWN;
1641 SIS_INC(frag, SIS_TX_LIST_CNT);
1643 ld->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1644 ld->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
1647 cd->sis_tx_data[*txidx].sis_map = cd->sis_tx_data[cur].sis_map;
1648 cd->sis_tx_data[cur].sis_map = map;
1650 cd->sis_tx_data[cur].sis_mbuf = *m_head;
1652 cd->sis_tx_cnt += nsegs;
1659 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1660 * to the mbuf data regions directly in the transmit lists. We also save a
1661 * copy of the pointers since the transmit list fragment pointers are
1662 * physical addresses.
1666 sis_start(struct ifnet *ifp)
1668 struct sis_softc *sc = ifp->if_softc;
1669 int need_trans, error;
1672 if (!sc->sis_link) {
1673 ifq_purge(&ifp->if_snd);
1677 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1680 idx = sc->sis_cdata.sis_tx_prod;
1683 while (sc->sis_cdata.sis_tx_data[idx].sis_mbuf == NULL) {
1684 struct mbuf *m_head;
1687 * If there's no way we can send any packets, return now.
1689 if (SIS_IS_OACTIVE(sc)) {
1690 ifp->if_flags |= IFF_OACTIVE;
1694 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1698 error = sis_encap(sc, &m_head, &idx);
1701 if (sc->sis_cdata.sis_tx_cnt == 0) {
1704 ifp->if_flags |= IFF_OACTIVE;
1711 * If there's a BPF listener, bounce a copy of this frame
1714 BPF_MTAP(ifp, m_head);
1721 sc->sis_cdata.sis_tx_prod = idx;
1722 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1725 * Set a timeout in case the chip goes out to lunch.
1733 struct sis_softc *sc = xsc;
1734 struct ifnet *ifp = &sc->arpcom.ac_if;
1735 struct mii_data *mii;
1738 * Cancel pending I/O and free all RX/TX buffers.
1742 mii = device_get_softc(sc->sis_miibus);
1744 /* Set MAC address */
1745 if (sc->sis_type == SIS_TYPE_83815) {
1746 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1747 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1748 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1749 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1750 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1751 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1752 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1753 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1754 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1756 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1757 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1758 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1759 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1760 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1761 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1762 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1763 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1764 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1767 /* Init circular RX list. */
1768 if (sis_list_rx_init(sc)) {
1769 if_printf(ifp, "initialization failed: "
1770 "no memory for rx buffers\n");
1776 * Init tx descriptors.
1778 sis_list_tx_init(sc);
1781 * For the NatSemi chip, we have to explicitly enable the
1782 * reception of ARP frames, as well as turn on the 'perfect
1783 * match' filter where we store the station address, otherwise
1784 * we won't receive unicasts meant for this host.
1786 if (sc->sis_type == SIS_TYPE_83815) {
1787 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
1788 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
1791 /* If we want promiscuous mode, set the allframes bit. */
1792 if (ifp->if_flags & IFF_PROMISC)
1793 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1795 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1798 * Set the capture broadcast bit to capture broadcast frames.
1800 if (ifp->if_flags & IFF_BROADCAST)
1801 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1803 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1806 * Load the multicast filter.
1808 if (sc->sis_type == SIS_TYPE_83815)
1809 sis_setmulti_ns(sc);
1811 sis_setmulti_sis(sc);
1813 /* Turn the receive filter on */
1814 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
1817 * Load the address of the RX and TX lists.
1819 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_ldata.sis_rx_paddr);
1820 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_ldata.sis_tx_paddr);
1822 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
1823 * the PCI bus. When this bit is set, the Max DMA Burst Size
1824 * for TX/RX DMA should be no larger than 16 double words.
1826 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN)
1827 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
1829 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
1831 /* Accept Long Packets for VLAN support */
1832 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
1834 /* Set TX configuration */
1835 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)
1836 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
1838 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
1840 /* Set full/half duplex mode. */
1841 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1842 SIS_SETBIT(sc, SIS_TX_CFG,
1843 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1844 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1846 SIS_CLRBIT(sc, SIS_TX_CFG,
1847 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1848 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1852 * Enable interrupts.
1854 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
1855 #ifdef DEVICE_POLLING
1857 * ... only enable interrupts if we are not polling, make sure
1858 * they are off otherwise.
1860 if (ifp->if_flags & IFF_POLLING)
1861 CSR_WRITE_4(sc, SIS_IER, 0);
1863 #endif /* DEVICE_POLLING */
1864 CSR_WRITE_4(sc, SIS_IER, 1);
1866 /* Enable receiver and transmitter. */
1867 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
1868 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1875 * Page 75 of the DP83815 manual recommends the
1876 * following register settings "for optimum
1877 * performance." Note however that at least three
1878 * of the registers are listed as "reserved" in
1879 * the register map, so who knows what they do.
1881 if (sc->sis_type == SIS_TYPE_83815) {
1882 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
1883 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
1884 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
1885 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
1886 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
1889 ifp->if_flags |= IFF_RUNNING;
1890 ifp->if_flags &= ~IFF_OACTIVE;
1892 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
1896 * Set media options.
1899 sis_ifmedia_upd(struct ifnet *ifp)
1901 struct sis_softc *sc;
1902 struct mii_data *mii;
1906 mii = device_get_softc(sc->sis_miibus);
1908 if (mii->mii_instance) {
1909 struct mii_softc *miisc;
1910 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1911 mii_phy_reset(miisc);
1919 * Report current media status.
1922 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1924 struct sis_softc *sc;
1925 struct mii_data *mii;
1929 mii = device_get_softc(sc->sis_miibus);
1931 ifmr->ifm_active = mii->mii_media_active;
1932 ifmr->ifm_status = mii->mii_media_status;
1936 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1938 struct sis_softc *sc = ifp->if_softc;
1939 struct ifreq *ifr = (struct ifreq *) data;
1940 struct mii_data *mii;
1945 if (ifp->if_flags & IFF_UP) {
1948 if (ifp->if_flags & IFF_RUNNING)
1955 if (sc->sis_type == SIS_TYPE_83815)
1956 sis_setmulti_ns(sc);
1958 sis_setmulti_sis(sc);
1963 mii = device_get_softc(sc->sis_miibus);
1964 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1967 error = ether_ioctl(ifp, command, data);
1974 sis_watchdog(struct ifnet *ifp)
1976 struct sis_softc *sc;
1981 if_printf(ifp, "watchdog timeout\n");
1987 if (!ifq_is_empty(&ifp->if_snd))
1992 * Stop the adapter and free any mbufs allocated to the
1996 sis_stop(struct sis_softc *sc)
1998 struct ifnet *ifp = &sc->arpcom.ac_if;
1999 struct sis_list_data *ld = &sc->sis_ldata;
2000 struct sis_chain_data *cd = &sc->sis_cdata;
2003 callout_stop(&sc->sis_timer);
2005 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2008 CSR_WRITE_4(sc, SIS_IER, 0);
2009 CSR_WRITE_4(sc, SIS_IMR, 0);
2010 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2012 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2013 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2018 * Free data in the RX lists.
2020 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2021 struct sis_rx_data *rd = &cd->sis_rx_data[i];
2023 if (rd->sis_mbuf != NULL) {
2024 bus_dmamap_unload(cd->sis_rxbuf_tag, rd->sis_map);
2025 m_freem(rd->sis_mbuf);
2026 rd->sis_mbuf = NULL;
2029 bzero(ld->sis_rx_list, SIS_RX_LIST_SZ);
2032 * Free the TX list buffers.
2034 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2035 struct sis_tx_data *td = &cd->sis_tx_data[i];
2037 if (td->sis_mbuf != NULL) {
2038 bus_dmamap_unload(cd->sis_txbuf_tag, td->sis_map);
2039 m_freem(td->sis_mbuf);
2040 td->sis_mbuf = NULL;
2043 bzero(ld->sis_tx_list, SIS_TX_LIST_SZ);
2047 * Stop all chip I/O so that the kernel's probe routines don't
2048 * get confused by errant DMAs when rebooting.
2051 sis_shutdown(device_t dev)
2053 struct sis_softc *sc;
2056 sc = device_get_softc(dev);
2057 ifp = &sc->arpcom.ac_if;
2058 lwkt_serialize_enter(ifp->if_serializer);
2061 lwkt_serialize_exit(ifp->if_serializer);
2065 sis_dma_alloc(device_t dev)
2067 struct sis_softc *sc = device_get_softc(dev);
2068 struct sis_chain_data *cd = &sc->sis_cdata;
2069 struct sis_list_data *ld = &sc->sis_ldata;
2072 /* Create top level DMA tag */
2073 error = bus_dma_tag_create(NULL, /* parent */
2074 1, 0, /* alignment, boundary */
2075 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
2076 BUS_SPACE_MAXADDR, /* highaddr */
2077 NULL, NULL, /* filter, filterarg */
2078 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
2080 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
2082 &sc->sis_parent_tag);
2084 device_printf(dev, "could not create parent DMA tag\n");
2088 /* Allocate RX ring */
2089 ld->sis_rx_list = bus_dmamem_coherent_any(sc->sis_parent_tag,
2090 SIS_RING_ALIGN, SIS_RX_LIST_SZ,
2091 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2092 &ld->sis_rx_tag, &ld->sis_rx_dmamap,
2094 if (ld->sis_rx_list == NULL) {
2095 device_printf(dev, "could not allocate RX ring\n");
2099 /* Allocate TX ring */
2100 ld->sis_tx_list = bus_dmamem_coherent_any(sc->sis_parent_tag,
2101 SIS_RING_ALIGN, SIS_TX_LIST_SZ,
2102 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2103 &ld->sis_tx_tag, &ld->sis_tx_dmamap,
2105 if (ld->sis_tx_list == NULL) {
2106 device_printf(dev, "could not allocate TX ring\n");
2110 /* Create DMA tag for TX mbuf */
2111 error = bus_dma_tag_create(sc->sis_parent_tag,/* parent */
2112 1, 0, /* alignment, boundary */
2113 BUS_SPACE_MAXADDR, /* lowaddr */
2114 BUS_SPACE_MAXADDR, /* highaddr */
2115 NULL, NULL, /* filter, filterarg */
2116 MCLBYTES, /* maxsize */
2117 SIS_NSEGS, /* nsegments */
2118 MCLBYTES, /* maxsegsize */
2119 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,/* flags */
2120 &cd->sis_txbuf_tag);
2122 device_printf(dev, "could not create TX buf DMA tag\n");
2126 /* Create DMA maps for TX mbufs */
2127 for (i = 0; i < SIS_TX_LIST_CNT; ++i) {
2128 error = bus_dmamap_create(cd->sis_txbuf_tag, BUS_DMA_WAITOK,
2129 &cd->sis_tx_data[i].sis_map);
2133 for (j = 0; j < i; ++j) {
2134 bus_dmamap_destroy(cd->sis_txbuf_tag,
2135 cd->sis_tx_data[j].sis_map);
2137 bus_dma_tag_destroy(cd->sis_txbuf_tag);
2138 cd->sis_txbuf_tag = NULL;
2140 device_printf(dev, "could not create %dth "
2141 "TX buf DMA map\n", i);
2146 /* Create DMA tag for RX mbuf */
2147 error = bus_dma_tag_create(sc->sis_parent_tag,/* parent */
2148 SIS_RXBUF_ALIGN, 0, /* alignment, boundary */
2149 BUS_SPACE_MAXADDR, /* lowaddr */
2150 BUS_SPACE_MAXADDR, /* highaddr */
2151 NULL, NULL, /* filter, filterarg */
2152 MCLBYTES, /* maxsize */
2154 MCLBYTES, /* maxsegsize */
2155 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2156 BUS_DMA_ALIGNED, /* flags */
2157 &cd->sis_rxbuf_tag);
2159 device_printf(dev, "could not create RX buf DMA tag\n");
2163 /* Create tmp DMA map for loading RX mbuf */
2164 error = bus_dmamap_create(cd->sis_rxbuf_tag, BUS_DMA_WAITOK,
2165 &cd->sis_rx_tmpmap);
2167 device_printf(dev, "could not create RX buf tmp DMA map\n");
2168 bus_dma_tag_destroy(cd->sis_rxbuf_tag);
2169 cd->sis_rxbuf_tag = NULL;
2173 /* Create DMA maps for RX mbufs */
2174 for (i = 0; i < SIS_RX_LIST_CNT; ++i) {
2175 error = bus_dmamap_create(cd->sis_rxbuf_tag, BUS_DMA_WAITOK,
2176 &cd->sis_rx_data[i].sis_map);
2180 for (j = 0; j < i; ++j) {
2181 bus_dmamap_destroy(cd->sis_rxbuf_tag,
2182 cd->sis_rx_data[j].sis_map);
2184 bus_dmamap_destroy(cd->sis_rxbuf_tag,
2186 bus_dma_tag_destroy(cd->sis_rxbuf_tag);
2187 cd->sis_rxbuf_tag = NULL;
2189 device_printf(dev, "could not create %dth "
2190 "RX buf DMA map\n", i);
2198 sis_dma_free(device_t dev)
2200 struct sis_softc *sc = device_get_softc(dev);
2201 struct sis_list_data *ld = &sc->sis_ldata;
2202 struct sis_chain_data *cd = &sc->sis_cdata;
2206 if (ld->sis_tx_list != NULL) {
2207 bus_dmamap_unload(ld->sis_tx_tag, ld->sis_tx_dmamap);
2208 bus_dmamem_free(ld->sis_tx_tag, ld->sis_tx_list,
2210 bus_dma_tag_destroy(ld->sis_tx_tag);
2214 if (ld->sis_rx_list != NULL) {
2215 bus_dmamap_unload(ld->sis_rx_tag, ld->sis_rx_dmamap);
2216 bus_dmamem_free(ld->sis_rx_tag, ld->sis_rx_list,
2218 bus_dma_tag_destroy(ld->sis_rx_tag);
2221 /* Destroy DMA stuffs for TX mbufs */
2222 if (cd->sis_txbuf_tag != NULL) {
2223 for (i = 0; i < SIS_TX_LIST_CNT; ++i) {
2224 KKASSERT(cd->sis_tx_data[i].sis_mbuf == NULL);
2225 bus_dmamap_destroy(cd->sis_txbuf_tag,
2226 cd->sis_tx_data[i].sis_map);
2228 bus_dma_tag_destroy(cd->sis_txbuf_tag);
2231 /* Destroy DMA stuffs for RX mbufs */
2232 if (cd->sis_rxbuf_tag != NULL) {
2233 for (i = 0; i < SIS_RX_LIST_CNT; ++i) {
2234 KKASSERT(cd->sis_rx_data[i].sis_mbuf == NULL);
2235 bus_dmamap_destroy(cd->sis_rxbuf_tag,
2236 cd->sis_rx_data[i].sis_map);
2238 bus_dmamap_destroy(cd->sis_rxbuf_tag, cd->sis_rx_tmpmap);
2239 bus_dma_tag_destroy(cd->sis_rxbuf_tag);