sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.90 2008/03/10 12:59:51 sephe Exp $
  35  *
  36  */
  37
  38 /*
  39  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  40  *
  41  * Written by Bill Paul <wpaul@windriver.com>
  42  * Senior Engineer, Wind River Systems
  43  */
  44
  45 /*
  46  * The Broadcom BCM5700 is based on technology originally developed by
  47  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  48  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  49  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  50  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  51  * frames, highly configurable RX filtering, and 16 RX and TX queues
  52  * (which, along with RX filter rules, can be used for QOS applications).
  53  * Other features, such as TCP segmentation, may be available as part
  54  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  55  * firmware images can be stored in hardware and need not be compiled
  56  * into the driver.
  57  *
  58  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  59  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  60  *
  61  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  62  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  63  * does not support external SSRAM.
  64  *
  65  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  66  * brand name, which is functionally similar but lacks PCI-X support.
  67  *
  68  * Without external SSRAM, you can only have at most 4 TX rings,
  69  * and the use of the mini RX ring is disabled. This seems to imply
  70  * that these features are simply not available on the BCM5701. As a
  71  * result, this driver does not implement any support for the mini RX
  72  * ring.
  73  */
  74
  75 #include "opt_polling.h"
  76 #include <sys/param.h>
  77 #include <sys/bus.h>
  78 #include <sys/endian.h>
  79 #include <sys/kernel.h>
  80 #include <sys/ktr.h>
  81 #include <sys/mbuf.h>
  82 #include <sys/malloc.h>
  83 #include <sys/queue.h>
  84 #include <sys/rman.h>
  85 #include <sys/serialize.h>
  86 #include <sys/socket.h>
  87 #include <sys/sockio.h>
  88 #include <sys/sysctl.h>
  89
  90 #include <net/bpf.h>
  91 #include <net/ethernet.h>
  92 #include <net/if.h>
  93 #include <net/if_arp.h>
  94 #include <net/if_dl.h>
  95 #include <net/if_media.h>
  96 #include <net/if_types.h>
  97 #include <net/ifq_var.h>
  98 #include <net/vlan/if_vlan_var.h>
  99 #include <net/vlan/if_vlan_ether.h>
 100
 101 #include <dev/netif/mii_layer/mii.h>
 102 #include <dev/netif/mii_layer/miivar.h>
 103 #include <dev/netif/mii_layer/brgphyreg.h>
 104
 105 #include <bus/pci/pcidevs.h>
 106 #include <bus/pci/pcireg.h>
 107 #include <bus/pci/pcivar.h>
 108
 109 #include <dev/netif/bge/if_bgereg.h>
 110
 111 /* "device miibus" required.  See GENERIC if you get errors here. */
 112 #include "miibus_if.h"
 113
 114 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 115 #define BGE_MIN_FRAME           60
 116
 117 /*
 118  * Various supported device vendors/types and their names. Note: the
 119  * spec seems to indicate that the hardware still has Alteon's vendor
 120  * ID burned into it, though it will always be overriden by the vendor
 121  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 122  */
 123 #define BGE_DEVDESC_MAX         64      /* Maximum device description length */
 124
 125 static struct bge_type bge_devs[] = {
 126         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
 127                 "3COM 3C996 Gigabit Ethernet" },
 128
 129         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 130                 "Alteon BCM5700 Gigabit Ethernet" },
 131         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 132                 "Alteon BCM5701 Gigabit Ethernet" },
 133
 134         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 135                 "Altima AC1000 Gigabit Ethernet" },
 136         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 137                 "Altima AC1002 Gigabit Ethernet" },
 138         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 139                 "Altima AC9100 Gigabit Ethernet" },
 140
 141         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
 142                 "Apple BCM5701 Gigabit Ethernet" },
 143
 144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 145                 "Broadcom BCM5700 Gigabit Ethernet" },
 146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 147                 "Broadcom BCM5701 Gigabit Ethernet" },
 148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
 149                 "Broadcom BCM5702 Gigabit Ethernet" },
 150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 151                 "Broadcom BCM5702X Gigabit Ethernet" },
 152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 153                 "Broadcom BCM5702 Gigabit Ethernet" },
 154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
 155                 "Broadcom BCM5703 Gigabit Ethernet" },
 156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 157                 "Broadcom BCM5703X Gigabit Ethernet" },
 158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 159                 "Broadcom BCM5703 Gigabit Ethernet" },
 160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 161                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 163                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
 165                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 167                 "Broadcom BCM5705 Gigabit Ethernet" },
 168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
 169                 "Broadcom BCM5705F Gigabit Ethernet" },
 170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 171                 "Broadcom BCM5705K Gigabit Ethernet" },
 172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 173                 "Broadcom BCM5705M Gigabit Ethernet" },
 174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 175                 "Broadcom BCM5705M Gigabit Ethernet" },
 176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
 177                 "Broadcom BCM5714C Gigabit Ethernet" },
 178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
 179                 "Broadcom BCM5714S Gigabit Ethernet" },
 180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
 181                 "Broadcom BCM5715 Gigabit Ethernet" },
 182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
 183                 "Broadcom BCM5715S Gigabit Ethernet" },
 184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
 185                 "Broadcom BCM5720 Gigabit Ethernet" },
 186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 187                 "Broadcom BCM5721 Gigabit Ethernet" },
 188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
 189                 "Broadcom BCM5722 Gigabit Ethernet" },
 190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 191                 "Broadcom BCM5750 Gigabit Ethernet" },
 192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 193                 "Broadcom BCM5750M Gigabit Ethernet" },
 194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 195                 "Broadcom BCM5751 Gigabit Ethernet" },
 196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
 197                 "Broadcom BCM5751F Gigabit Ethernet" },
 198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 199                 "Broadcom BCM5751M Gigabit Ethernet" },
 200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
 201                 "Broadcom BCM5752 Gigabit Ethernet" },
 202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
 203                 "Broadcom BCM5752M Gigabit Ethernet" },
 204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
 205                 "Broadcom BCM5753 Gigabit Ethernet" },
 206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
 207                 "Broadcom BCM5753F Gigabit Ethernet" },
 208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
 209                 "Broadcom BCM5753M Gigabit Ethernet" },
 210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
 211                 "Broadcom BCM5754 Gigabit Ethernet" },
 212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
 213                 "Broadcom BCM5754M Gigabit Ethernet" },
 214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
 215                 "Broadcom BCM5755 Gigabit Ethernet" },
 216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
 217                 "Broadcom BCM5755M Gigabit Ethernet" },
 218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
 219                 "Broadcom BCM5756 Gigabit Ethernet" },
 220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
 221                 "Broadcom BCM5780 Gigabit Ethernet" },
 222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
 223                 "Broadcom BCM5780S Gigabit Ethernet" },
 224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
 225                 "Broadcom BCM5781 Gigabit Ethernet" },
 226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 227                 "Broadcom BCM5782 Gigabit Ethernet" },
 228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
 229                 "Broadcom BCM5786 Gigabit Ethernet" },
 230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
 231                 "Broadcom BCM5787 Gigabit Ethernet" },
 232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
 233                 "Broadcom BCM5787F Gigabit Ethernet" },
 234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
 235                 "Broadcom BCM5787M Gigabit Ethernet" },
 236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 237                 "Broadcom BCM5788 Gigabit Ethernet" },
 238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 239                 "Broadcom BCM5789 Gigabit Ethernet" },
 240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 241                 "Broadcom BCM5901 Fast Ethernet" },
 242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 243                 "Broadcom BCM5901A2 Fast Ethernet" },
 244         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
 245                 "Broadcom BCM5903M Fast Ethernet" },
 246
 247         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 248                 "SysKonnect Gigabit Ethernet" },
 249
 250         { 0, 0, NULL }
 251 };
 252
 253 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 254 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 255 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 256 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 257 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 258
 259 static int      bge_probe(device_t);
 260 static int      bge_attach(device_t);
 261 static int      bge_detach(device_t);
 262 static void     bge_txeof(struct bge_softc *);
 263 static void     bge_rxeof(struct bge_softc *);
 264
 265 static void     bge_tick(void *);
 266 static void     bge_stats_update(struct bge_softc *);
 267 static void     bge_stats_update_regs(struct bge_softc *);
 268 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 269
 270 #ifdef DEVICE_POLLING
 271 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 272 #endif
 273 static void     bge_intr(void *);
 274 static void     bge_enable_intr(struct bge_softc *);
 275 static void     bge_disable_intr(struct bge_softc *);
 276 static void     bge_start(struct ifnet *);
 277 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 278 static void     bge_init(void *);
 279 static void     bge_stop(struct bge_softc *);
 280 static void     bge_watchdog(struct ifnet *);
 281 static void     bge_shutdown(device_t);
 282 static int      bge_suspend(device_t);
 283 static int      bge_resume(device_t);
 284 static int      bge_ifmedia_upd(struct ifnet *);
 285 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 286
 287 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 288 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 289
 290 static void     bge_setmulti(struct bge_softc *);
 291 static void     bge_setpromisc(struct bge_softc *);
 292
 293 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 294 static void     bge_free_jumbo_mem(struct bge_softc *);
 295 static struct bge_jslot
 296                 *bge_jalloc(struct bge_softc *);
 297 static void     bge_jfree(void *);
 298 static void     bge_jref(void *);
 299 static int      bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
 300 static int      bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
 301 static int      bge_init_rx_ring_std(struct bge_softc *);
 302 static void     bge_free_rx_ring_std(struct bge_softc *);
 303 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 304 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 305 static void     bge_free_tx_ring(struct bge_softc *);
 306 static int      bge_init_tx_ring(struct bge_softc *);
 307
 308 static int      bge_chipinit(struct bge_softc *);
 309 static int      bge_blockinit(struct bge_softc *);
 310
 311 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 312 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 313 #ifdef notdef
 314 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 315 #endif
 316 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 317 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
 318
 319 static int      bge_miibus_readreg(device_t, int, int);
 320 static int      bge_miibus_writereg(device_t, int, int, int);
 321 static void     bge_miibus_statchg(device_t);
 322 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
 323 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
 324 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
 325
 326 static void     bge_reset(struct bge_softc *);
 327
 328 static void     bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 329 static void     bge_dma_map_mbuf(void *, bus_dma_segment_t *, int,
 330                                  bus_size_t, int);
 331 static int      bge_dma_alloc(struct bge_softc *);
 332 static void     bge_dma_free(struct bge_softc *);
 333 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
 334                                     bus_dma_tag_t *, bus_dmamap_t *,
 335                                     void **, bus_addr_t *);
 336 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 337
 338 static void     bge_coal_change(struct bge_softc *);
 339 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 340 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 341 static int      bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 342 static int      bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 343 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
 344
 345 /*
 346  * Set following tunable to 1 for some IBM blade servers with the DNLK
 347  * switch module. Auto negotiation is broken for those configurations.
 348  */
 349 static int      bge_fake_autoneg = 0;
 350 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
 351
 352 /* Interrupt moderation control variables. */
 353 static int      bge_rx_coal_ticks = 150;        /* usec */
 354 static int      bge_tx_coal_ticks = 1000000;    /* usec */
 355 static int      bge_rx_max_coal_bds = 16;
 356 static int      bge_tx_max_coal_bds = 32;
 357
 358 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
 359 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
 360 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
 361 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
 362
 363 #if !defined(KTR_IF_BGE)
 364 #define KTR_IF_BGE      KTR_ALL
 365 #endif
 366 KTR_INFO_MASTER(if_bge);
 367 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr", 0);
 368 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt", 0);
 369 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt", 0);
 370 #define logif(name)     KTR_LOG(if_bge_ ## name)
 371
 372 static device_method_t bge_methods[] = {
 373         /* Device interface */
 374         DEVMETHOD(device_probe,         bge_probe),
 375         DEVMETHOD(device_attach,        bge_attach),
 376         DEVMETHOD(device_detach,        bge_detach),
 377         DEVMETHOD(device_shutdown,      bge_shutdown),
 378         DEVMETHOD(device_suspend,       bge_suspend),
 379         DEVMETHOD(device_resume,        bge_resume),
 380
 381         /* bus interface */
 382         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 383         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 384
 385         /* MII interface */
 386         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 387         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 388         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 389
 390         { 0, 0 }
 391 };
 392
 393 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 394 static devclass_t bge_devclass;
 395
 396 DECLARE_DUMMY_MODULE(if_bge);
 397 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
 398 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 399
 400 static uint32_t
 401 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 402 {
 403         device_t dev = sc->bge_dev;
 404         uint32_t val;
 405
 406         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 407         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 408         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 409         return (val);
 410 }
 411
 412 static void
 413 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 414 {
 415         device_t dev = sc->bge_dev;
 416
 417         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 418         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 419         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 420 }
 421
 422 #ifdef notdef
 423 static uint32_t
 424 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 425 {
 426         device_t dev = sc->bge_dev;
 427
 428         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 429         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 430 }
 431 #endif
 432
 433 static void
 434 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 435 {
 436         device_t dev = sc->bge_dev;
 437
 438         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 439         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 440 }
 441
 442 static void
 443 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
 444 {
 445         CSR_WRITE_4(sc, off, val);
 446 }
 447
 448 /*
 449  * Read a byte of data stored in the EEPROM at address 'addr.' The
 450  * BCM570x supports both the traditional bitbang interface and an
 451  * auto access interface for reading the EEPROM. We use the auto
 452  * access method.
 453  */
 454 static uint8_t
 455 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 456 {
 457         int i;
 458         uint32_t byte = 0;
 459
 460         /*
 461          * Enable use of auto EEPROM access so we can avoid
 462          * having to use the bitbang method.
 463          */
 464         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 465
 466         /* Reset the EEPROM, load the clock period. */
 467         CSR_WRITE_4(sc, BGE_EE_ADDR,
 468             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 469         DELAY(20);
 470
 471         /* Issue the read EEPROM command. */
 472         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 473
 474         /* Wait for completion */
 475         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 476                 DELAY(10);
 477                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 478                         break;
 479         }
 480
 481         if (i == BGE_TIMEOUT) {
 482                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 483                 return(1);
 484         }
 485
 486         /* Get result. */
 487         byte = CSR_READ_4(sc, BGE_EE_DATA);
 488
 489         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 490
 491         return(0);
 492 }
 493
 494 /*
 495  * Read a sequence of bytes from the EEPROM.
 496  */
 497 static int
 498 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 499 {
 500         size_t i;
 501         int err;
 502         uint8_t byte;
 503
 504         for (byte = 0, err = 0, i = 0; i < len; i++) {
 505                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 506                 if (err)
 507                         break;
 508                 *(dest + i) = byte;
 509         }
 510
 511         return(err ? 1 : 0);
 512 }
 513
 514 static int
 515 bge_miibus_readreg(device_t dev, int phy, int reg)
 516 {
 517         struct bge_softc *sc;
 518         struct ifnet *ifp;
 519         uint32_t val, autopoll;
 520         int i;
 521
 522         sc = device_get_softc(dev);
 523         ifp = &sc->arpcom.ac_if;
 524
 525         /*
 526          * Broadcom's own driver always assumes the internal
 527          * PHY is at GMII address 1. On some chips, the PHY responds
 528          * to accesses at all addresses, which could cause us to
 529          * bogusly attach the PHY 32 times at probe type. Always
 530          * restricting the lookup to address 1 is simpler than
 531          * trying to figure out which chips revisions should be
 532          * special-cased.
 533          */
 534         if (phy != 1)
 535                 return(0);
 536
 537         /* Reading with autopolling on may trigger PCI errors */
 538         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 539         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 540                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 541                 DELAY(40);
 542         }
 543
 544         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
 545             BGE_MIPHY(phy)|BGE_MIREG(reg));
 546
 547         for (i = 0; i < BGE_TIMEOUT; i++) {
 548                 val = CSR_READ_4(sc, BGE_MI_COMM);
 549                 if (!(val & BGE_MICOMM_BUSY))
 550                         break;
 551         }
 552
 553         if (i == BGE_TIMEOUT) {
 554                 if_printf(ifp, "PHY read timed out\n");
 555                 val = 0;
 556                 goto done;
 557         }
 558
 559         val = CSR_READ_4(sc, BGE_MI_COMM);
 560
 561 done:
 562         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 563                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 564                 DELAY(40);
 565         }
 566
 567         if (val & BGE_MICOMM_READFAIL)
 568                 return(0);
 569
 570         return(val & 0xFFFF);
 571 }
 572
 573 static int
 574 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 575 {
 576         struct bge_softc *sc;
 577         uint32_t autopoll;
 578         int i;
 579
 580         sc = device_get_softc(dev);
 581
 582         /* Reading with autopolling on may trigger PCI errors */
 583         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 584         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 585                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 586                 DELAY(40);
 587         }
 588
 589         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
 590             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
 591
 592         for (i = 0; i < BGE_TIMEOUT; i++) {
 593                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
 594                         break;
 595         }
 596
 597         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 598                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 599                 DELAY(40);
 600         }
 601
 602         if (i == BGE_TIMEOUT) {
 603                 if_printf(&sc->arpcom.ac_if, "PHY read timed out\n");
 604                 return(0);
 605         }
 606
 607         return(0);
 608 }
 609
 610 static void
 611 bge_miibus_statchg(device_t dev)
 612 {
 613         struct bge_softc *sc;
 614         struct mii_data *mii;
 615
 616         sc = device_get_softc(dev);
 617         mii = device_get_softc(sc->bge_miibus);
 618
 619         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 620         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
 621                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 622         } else {
 623                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 624         }
 625
 626         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 627                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 628         } else {
 629                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 630         }
 631 }
 632
 633 /*
 634  * Memory management for jumbo frames.
 635  */
 636 static int
 637 bge_alloc_jumbo_mem(struct bge_softc *sc)
 638 {
 639         struct ifnet *ifp = &sc->arpcom.ac_if;
 640         struct bge_jslot *entry;
 641         uint8_t *ptr;
 642         bus_addr_t paddr;
 643         int i, error;
 644
 645         /*
 646          * Create tag for jumbo mbufs.
 647          * This is really a bit of a kludge. We allocate a special
 648          * jumbo buffer pool which (thanks to the way our DMA
 649          * memory allocation works) will consist of contiguous
 650          * pages. This means that even though a jumbo buffer might
 651          * be larger than a page size, we don't really need to
 652          * map it into more than one DMA segment. However, the
 653          * default mbuf tag will result in multi-segment mappings,
 654          * so we have to create a special jumbo mbuf tag that
 655          * lets us get away with mapping the jumbo buffers as
 656          * a single segment. I think eventually the driver should
 657          * be changed so that it uses ordinary mbufs and cluster
 658          * buffers, i.e. jumbo frames can span multiple DMA
 659          * descriptors. But that's a project for another day.
 660          */
 661
 662         /*
 663          * Create DMA stuffs for jumbo RX ring.
 664          */
 665         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 666                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
 667                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
 668                                     (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
 669                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 670         if (error) {
 671                 if_printf(ifp, "could not create jumbo RX ring\n");
 672                 return error;
 673         }
 674
 675         /*
 676          * Create DMA stuffs for jumbo buffer block.
 677          */
 678         error = bge_dma_block_alloc(sc, BGE_JMEM,
 679                                     &sc->bge_cdata.bge_jumbo_tag,
 680                                     &sc->bge_cdata.bge_jumbo_map,
 681                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
 682                                     &paddr);
 683         if (error) {
 684                 if_printf(ifp, "could not create jumbo buffer\n");
 685                 return error;
 686         }
 687
 688         SLIST_INIT(&sc->bge_jfree_listhead);
 689
 690         /*
 691          * Now divide it up into 9K pieces and save the addresses
 692          * in an array. Note that we play an evil trick here by using
 693          * the first few bytes in the buffer to hold the the address
 694          * of the softc structure for this interface. This is because
 695          * bge_jfree() needs it, but it is called by the mbuf management
 696          * code which will not pass it to us explicitly.
 697          */
 698         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
 699                 entry = &sc->bge_cdata.bge_jslots[i];
 700                 entry->bge_sc = sc;
 701                 entry->bge_buf = ptr;
 702                 entry->bge_paddr = paddr;
 703                 entry->bge_inuse = 0;
 704                 entry->bge_slot = i;
 705                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 706
 707                 ptr += BGE_JLEN;
 708                 paddr += BGE_JLEN;
 709         }
 710         return 0;
 711 }
 712
 713 static void
 714 bge_free_jumbo_mem(struct bge_softc *sc)
 715 {
 716         /* Destroy jumbo RX ring. */
 717         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 718                            sc->bge_cdata.bge_rx_jumbo_ring_map,
 719                            sc->bge_ldata.bge_rx_jumbo_ring);
 720
 721         /* Destroy jumbo buffer block. */
 722         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
 723                            sc->bge_cdata.bge_jumbo_map,
 724                            sc->bge_ldata.bge_jumbo_buf);
 725 }
 726
 727 /*
 728  * Allocate a jumbo buffer.
 729  */
 730 static struct bge_jslot *
 731 bge_jalloc(struct bge_softc *sc)
 732 {
 733         struct bge_jslot *entry;
 734
 735         lwkt_serialize_enter(&sc->bge_jslot_serializer);
 736         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 737         if (entry) {
 738                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 739                 entry->bge_inuse = 1;
 740         } else {
 741                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 742         }
 743         lwkt_serialize_exit(&sc->bge_jslot_serializer);
 744         return(entry);
 745 }
 746
 747 /*
 748  * Adjust usage count on a jumbo buffer.
 749  */
 750 static void
 751 bge_jref(void *arg)
 752 {
 753         struct bge_jslot *entry = (struct bge_jslot *)arg;
 754         struct bge_softc *sc = entry->bge_sc;
 755
 756         if (sc == NULL)
 757                 panic("bge_jref: can't find softc pointer!");
 758
 759         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 760                 panic("bge_jref: asked to reference buffer "
 761                     "that we don't manage!");
 762         } else if (entry->bge_inuse == 0) {
 763                 panic("bge_jref: buffer already free!");
 764         } else {
 765                 atomic_add_int(&entry->bge_inuse, 1);
 766         }
 767 }
 768
 769 /*
 770  * Release a jumbo buffer.
 771  */
 772 static void
 773 bge_jfree(void *arg)
 774 {
 775         struct bge_jslot *entry = (struct bge_jslot *)arg;
 776         struct bge_softc *sc = entry->bge_sc;
 777
 778         if (sc == NULL)
 779                 panic("bge_jfree: can't find softc pointer!");
 780
 781         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 782                 panic("bge_jfree: asked to free buffer that we don't manage!");
 783         } else if (entry->bge_inuse == 0) {
 784                 panic("bge_jfree: buffer already free!");
 785         } else {
 786                 /*
 787                  * Possible MP race to 0, use the serializer.  The atomic insn
 788                  * is still needed for races against bge_jref().
 789                  */
 790                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
 791                 atomic_subtract_int(&entry->bge_inuse, 1);
 792                 if (entry->bge_inuse == 0) {
 793                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 794                                           entry, jslot_link);
 795                 }
 796                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
 797         }
 798 }
 799
 800
 801 /*
 802  * Intialize a standard receive ring descriptor.
 803  */
 804 static int
 805 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
 806 {
 807         struct mbuf *m_new = NULL;
 808         struct bge_dmamap_arg ctx;
 809         bus_dma_segment_t seg;
 810         struct bge_rx_bd *r;
 811         int error;
 812
 813         if (m == NULL) {
 814                 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
 815                 if (m_new == NULL)
 816                         return ENOBUFS;
 817         } else {
 818                 m_new = m;
 819                 m_new->m_data = m_new->m_ext.ext_buf;
 820         }
 821         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 822
 823         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 824                 m_adj(m_new, ETHER_ALIGN);
 825
 826         ctx.bge_maxsegs = 1;
 827         ctx.bge_segs = &seg;
 828         error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag,
 829                                      sc->bge_cdata.bge_rx_std_dmamap[i],
 830                                      m_new, bge_dma_map_mbuf, &ctx,
 831                                      BUS_DMA_NOWAIT);
 832         if (error || ctx.bge_maxsegs == 0) {
 833                 if (m == NULL)
 834                         m_freem(m_new);
 835                 return ENOMEM;
 836         }
 837
 838         sc->bge_cdata.bge_rx_std_chain[i] = m_new;
 839
 840         r = &sc->bge_ldata.bge_rx_std_ring[i];
 841         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[0].ds_addr);
 842         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[0].ds_addr);
 843         r->bge_flags = BGE_RXBDFLAG_END;
 844         r->bge_len = m_new->m_len;
 845         r->bge_idx = i;
 846
 847         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
 848                         sc->bge_cdata.bge_rx_std_dmamap[i],
 849                         BUS_DMASYNC_PREREAD);
 850         return 0;
 851 }
 852
 853 /*
 854  * Initialize a jumbo receive ring descriptor. This allocates
 855  * a jumbo buffer from the pool managed internally by the driver.
 856  */
 857 static int
 858 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
 859 {
 860         struct mbuf *m_new = NULL;
 861         struct bge_jslot *buf;
 862         struct bge_rx_bd *r;
 863         bus_addr_t paddr;
 864
 865         if (m == NULL) {
 866                 /* Allocate the mbuf. */
 867                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
 868                 if (m_new == NULL)
 869                         return(ENOBUFS);
 870
 871                 /* Allocate the jumbo buffer */
 872                 buf = bge_jalloc(sc);
 873                 if (buf == NULL) {
 874                         m_freem(m_new);
 875                         if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
 876                             "-- packet dropped!\n");
 877                         return ENOBUFS;
 878                 }
 879
 880                 /* Attach the buffer to the mbuf. */
 881                 m_new->m_ext.ext_arg = buf;
 882                 m_new->m_ext.ext_buf = buf->bge_buf;
 883                 m_new->m_ext.ext_free = bge_jfree;
 884                 m_new->m_ext.ext_ref = bge_jref;
 885                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 886
 887                 m_new->m_flags |= M_EXT;
 888         } else {
 889                 KKASSERT(m->m_flags & M_EXT);
 890                 m_new = m;
 891                 buf = m_new->m_ext.ext_arg;
 892         }
 893         m_new->m_data = m_new->m_ext.ext_buf;
 894         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 895
 896         paddr = buf->bge_paddr;
 897         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
 898                 m_adj(m_new, ETHER_ALIGN);
 899                 paddr += ETHER_ALIGN;
 900         }
 901
 902         /* Set up the descriptor. */
 903         sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
 904
 905         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
 906         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr);
 907         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr);
 908         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 909         r->bge_len = m_new->m_len;
 910         r->bge_idx = i;
 911
 912         return 0;
 913 }
 914
 915 /*
 916  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
 917  * that's 1MB or memory, which is a lot. For now, we fill only the first
 918  * 256 ring entries and hope that our CPU is fast enough to keep up with
 919  * the NIC.
 920  */
 921 static int
 922 bge_init_rx_ring_std(struct bge_softc *sc)
 923 {
 924         int i;
 925
 926         for (i = 0; i < BGE_SSLOTS; i++) {
 927                 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
 928                         return(ENOBUFS);
 929         };
 930
 931         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
 932                         sc->bge_cdata.bge_rx_std_ring_map,
 933                         BUS_DMASYNC_PREWRITE);
 934
 935         sc->bge_std = i - 1;
 936         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
 937
 938         return(0);
 939 }
 940
 941 static void
 942 bge_free_rx_ring_std(struct bge_softc *sc)
 943 {
 944         int i;
 945
 946         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 947                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 948                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
 949                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
 950                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
 951                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
 952                 }
 953                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
 954                     sizeof(struct bge_rx_bd));
 955         }
 956 }
 957
 958 static int
 959 bge_init_rx_ring_jumbo(struct bge_softc *sc)
 960 {
 961         int i;
 962         struct bge_rcb *rcb;
 963
 964         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 965                 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
 966                         return(ENOBUFS);
 967         };
 968
 969         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 970                         sc->bge_cdata.bge_rx_jumbo_ring_map,
 971                         BUS_DMASYNC_PREWRITE);
 972
 973         sc->bge_jumbo = i - 1;
 974
 975         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
 976         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 977         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 978
 979         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
 980
 981         return(0);
 982 }
 983
 984 static void
 985 bge_free_rx_ring_jumbo(struct bge_softc *sc)
 986 {
 987         int i;
 988
 989         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 990                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
 991                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
 992                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
 993                 }
 994                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
 995                     sizeof(struct bge_rx_bd));
 996         }
 997 }
 998
 999 static void
1000 bge_free_tx_ring(struct bge_softc *sc)
1001 {
1002         int i;
1003
1004         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1005                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1006                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1007                                           sc->bge_cdata.bge_tx_dmamap[i]);
1008                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1009                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1010                 }
1011                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1012                     sizeof(struct bge_tx_bd));
1013         }
1014 }
1015
1016 static int
1017 bge_init_tx_ring(struct bge_softc *sc)
1018 {
1019         sc->bge_txcnt = 0;
1020         sc->bge_tx_saved_considx = 0;
1021         sc->bge_tx_prodidx = 0;
1022
1023         /* Initialize transmit producer index for host-memory send ring. */
1024         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1025
1026         /* 5700 b2 errata */
1027         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1028                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
1029
1030         CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1031         /* 5700 b2 errata */
1032         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1033                 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1034
1035         return(0);
1036 }
1037
1038 static void
1039 bge_setmulti(struct bge_softc *sc)
1040 {
1041         struct ifnet *ifp;
1042         struct ifmultiaddr *ifma;
1043         uint32_t hashes[4] = { 0, 0, 0, 0 };
1044         int h, i;
1045
1046         ifp = &sc->arpcom.ac_if;
1047
1048         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1049                 for (i = 0; i < 4; i++)
1050                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1051                 return;
1052         }
1053
1054         /* First, zot all the existing filters. */
1055         for (i = 0; i < 4; i++)
1056                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1057
1058         /* Now program new ones. */
1059         LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1060                 if (ifma->ifma_addr->sa_family != AF_LINK)
1061                         continue;
1062                 h = ether_crc32_le(
1063                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1064                     ETHER_ADDR_LEN) & 0x7f;
1065                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1066         }
1067
1068         for (i = 0; i < 4; i++)
1069                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1070 }
1071
1072 /*
1073  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1074  * self-test results.
1075  */
1076 static int
1077 bge_chipinit(struct bge_softc *sc)
1078 {
1079         int i;
1080         uint32_t dma_rw_ctl;
1081
1082         /* Set endian type before we access any non-PCI registers. */
1083         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1084
1085         /*
1086          * Check the 'ROM failed' bit on the RX CPU to see if
1087          * self-tests passed.
1088          */
1089         if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1090                 if_printf(&sc->arpcom.ac_if,
1091                           "RX CPU self-diagnostics failed!\n");
1092                 return(ENODEV);
1093         }
1094
1095         /* Clear the MAC control register */
1096         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1097
1098         /*
1099          * Clear the MAC statistics block in the NIC's
1100          * internal memory.
1101          */
1102         for (i = BGE_STATS_BLOCK;
1103             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1104                 BGE_MEMWIN_WRITE(sc, i, 0);
1105
1106         for (i = BGE_STATUS_BLOCK;
1107             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1108                 BGE_MEMWIN_WRITE(sc, i, 0);
1109
1110         /* Set up the PCI DMA control register. */
1111         if (sc->bge_flags & BGE_FLAG_PCIE) {
1112                 /* PCI Express */
1113                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1114                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1115                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1116         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1117                 /* PCI-X bus */
1118                 if (BGE_IS_5714_FAMILY(sc)) {
1119                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1120                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1121                         /* XXX magic values, Broadcom-supplied Linux driver */
1122                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1123                                 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1124                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1125                         } else {
1126                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1127                         }
1128                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1129                         /*
1130                          * The 5704 uses a different encoding of read/write
1131                          * watermarks.
1132                          */
1133                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1134                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1135                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1136                 } else {
1137                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1138                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1139                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1140                             (0x0F);
1141                 }
1142
1143                 /*
1144                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1145                  * for hardware bugs.
1146                  */
1147                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1148                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1149                         uint32_t tmp;
1150
1151                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1152                         if (tmp == 0x6 || tmp == 0x7)
1153                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1154                 }
1155         } else {
1156                 /* Conventional PCI bus */
1157                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1158                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1159                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1160                     (0x0F);
1161         }
1162
1163         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1164             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1165             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1166                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1167         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1168
1169         /*
1170          * Set up general mode register.
1171          */
1172         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1173             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1174             BGE_MODECTL_TX_NO_PHDR_CSUM);
1175
1176         /*
1177          * Disable memory write invalidate.  Apparently it is not supported
1178          * properly by these devices.
1179          */
1180         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1181
1182         /* Set the timer prescaler (always 66Mhz) */
1183         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1184
1185         return(0);
1186 }
1187
1188 static int
1189 bge_blockinit(struct bge_softc *sc)
1190 {
1191         struct bge_rcb *rcb;
1192         bus_size_t vrcb;
1193         bge_hostaddr taddr;
1194         uint32_t val;
1195         int i;
1196
1197         /*
1198          * Initialize the memory window pointer register so that
1199          * we can access the first 32K of internal NIC RAM. This will
1200          * allow us to set up the TX send ring RCBs and the RX return
1201          * ring RCBs, plus other things which live in NIC memory.
1202          */
1203         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1204
1205         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1206
1207         if (!BGE_IS_5705_PLUS(sc)) {
1208                 /* Configure mbuf memory pool */
1209                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1210                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1211                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1212                 else
1213                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1214
1215                 /* Configure DMA resource pool */
1216                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1217                     BGE_DMA_DESCRIPTORS);
1218                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1219         }
1220
1221         /* Configure mbuf pool watermarks */
1222         if (BGE_IS_5705_PLUS(sc)) {
1223                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1224                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1225         } else {
1226                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1227                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1228         }
1229         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1230
1231         /* Configure DMA resource watermarks */
1232         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1233         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1234
1235         /* Enable buffer manager */
1236         if (!BGE_IS_5705_PLUS(sc)) {
1237                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1238                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1239
1240                 /* Poll for buffer manager start indication */
1241                 for (i = 0; i < BGE_TIMEOUT; i++) {
1242                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1243                                 break;
1244                         DELAY(10);
1245                 }
1246
1247                 if (i == BGE_TIMEOUT) {
1248                         if_printf(&sc->arpcom.ac_if,
1249                                   "buffer manager failed to start\n");
1250                         return(ENXIO);
1251                 }
1252         }
1253
1254         /* Enable flow-through queues */
1255         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1256         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1257
1258         /* Wait until queue initialization is complete */
1259         for (i = 0; i < BGE_TIMEOUT; i++) {
1260                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1261                         break;
1262                 DELAY(10);
1263         }
1264
1265         if (i == BGE_TIMEOUT) {
1266                 if_printf(&sc->arpcom.ac_if,
1267                           "flow-through queue init failed\n");
1268                 return(ENXIO);
1269         }
1270
1271         /* Initialize the standard RX ring control block */
1272         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1273         rcb->bge_hostaddr.bge_addr_lo =
1274             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1275         rcb->bge_hostaddr.bge_addr_hi =
1276             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1277         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1278             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1279         if (BGE_IS_5705_PLUS(sc))
1280                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1281         else
1282                 rcb->bge_maxlen_flags =
1283                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1284         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1285         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1286         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1287         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1288         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1289
1290         /*
1291          * Initialize the jumbo RX ring control block
1292          * We set the 'ring disabled' bit in the flags
1293          * field until we're actually ready to start
1294          * using this ring (i.e. once we set the MTU
1295          * high enough to require it).
1296          */
1297         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1298                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1299
1300                 rcb->bge_hostaddr.bge_addr_lo =
1301                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1302                 rcb->bge_hostaddr.bge_addr_hi =
1303                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1304                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1305                     sc->bge_cdata.bge_rx_jumbo_ring_map,
1306                     BUS_DMASYNC_PREREAD);
1307                 rcb->bge_maxlen_flags =
1308                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1309                     BGE_RCB_FLAG_RING_DISABLED);
1310                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1311                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1312                     rcb->bge_hostaddr.bge_addr_hi);
1313                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1314                     rcb->bge_hostaddr.bge_addr_lo);
1315                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1316                     rcb->bge_maxlen_flags);
1317                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1318
1319                 /* Set up dummy disabled mini ring RCB */
1320                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1321                 rcb->bge_maxlen_flags =
1322                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1323                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1324                     rcb->bge_maxlen_flags);
1325         }
1326
1327         /*
1328          * Set the BD ring replentish thresholds. The recommended
1329          * values are 1/8th the number of descriptors allocated to
1330          * each ring.
1331          */
1332         if (BGE_IS_5705_PLUS(sc))
1333                 val = 8;
1334         else
1335                 val = BGE_STD_RX_RING_CNT / 8;
1336         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1337         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1338
1339         /*
1340          * Disable all unused send rings by setting the 'ring disabled'
1341          * bit in the flags field of all the TX send ring control blocks.
1342          * These are located in NIC memory.
1343          */
1344         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1345         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1346                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1347                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1348                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1349                 vrcb += sizeof(struct bge_rcb);
1350         }
1351
1352         /* Configure TX RCB 0 (we use only the first ring) */
1353         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1354         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1355         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1356         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1357         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1358             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1359         if (!BGE_IS_5705_PLUS(sc)) {
1360                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1361                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1362         }
1363
1364         /* Disable all unused RX return rings */
1365         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1366         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1367                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1368                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1369                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1370                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1371                     BGE_RCB_FLAG_RING_DISABLED));
1372                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1373                 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1374                     (i * (sizeof(uint64_t))), 0);
1375                 vrcb += sizeof(struct bge_rcb);
1376         }
1377
1378         /* Initialize RX ring indexes */
1379         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1380         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1381         CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1382
1383         /*
1384          * Set up RX return ring 0
1385          * Note that the NIC address for RX return rings is 0x00000000.
1386          * The return rings live entirely within the host, so the
1387          * nicaddr field in the RCB isn't used.
1388          */
1389         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1390         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1391         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1392         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1393         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1394         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1395             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1396
1397         /* Set random backoff seed for TX */
1398         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1399             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1400             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1401             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1402             BGE_TX_BACKOFF_SEED_MASK);
1403
1404         /* Set inter-packet gap */
1405         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1406
1407         /*
1408          * Specify which ring to use for packets that don't match
1409          * any RX rules.
1410          */
1411         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1412
1413         /*
1414          * Configure number of RX lists. One interrupt distribution
1415          * list, sixteen active lists, one bad frames class.
1416          */
1417         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1418
1419         /* Inialize RX list placement stats mask. */
1420         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1421         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1422
1423         /* Disable host coalescing until we get it set up */
1424         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1425
1426         /* Poll to make sure it's shut down. */
1427         for (i = 0; i < BGE_TIMEOUT; i++) {
1428                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1429                         break;
1430                 DELAY(10);
1431         }
1432
1433         if (i == BGE_TIMEOUT) {
1434                 if_printf(&sc->arpcom.ac_if,
1435                           "host coalescing engine failed to idle\n");
1436                 return(ENXIO);
1437         }
1438
1439         /* Set up host coalescing defaults */
1440         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1441         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1442         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1443         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1444         if (!BGE_IS_5705_PLUS(sc)) {
1445                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1446                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1447         }
1448         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1449         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1450
1451         /* Set up address of statistics block */
1452         if (!BGE_IS_5705_PLUS(sc)) {
1453                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1454                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1455                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1456                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1457
1458                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1459                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1460                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1461         }
1462
1463         /* Set up address of status block */
1464         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1465             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1466         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1467             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1468         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1469         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1470
1471         /* Turn on host coalescing state machine */
1472         CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1473
1474         /* Turn on RX BD completion state machine and enable attentions */
1475         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1476             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1477
1478         /* Turn on RX list placement state machine */
1479         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1480
1481         /* Turn on RX list selector state machine. */
1482         if (!BGE_IS_5705_PLUS(sc))
1483                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1484
1485         /* Turn on DMA, clear stats */
1486         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1487             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1488             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1489             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1490             ((sc->bge_flags & BGE_FLAG_TBI) ?
1491              BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1492
1493         /* Set misc. local control, enable interrupts on attentions */
1494         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1495
1496 #ifdef notdef
1497         /* Assert GPIO pins for PHY reset */
1498         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1499             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1500         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1501             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1502 #endif
1503
1504         /* Turn on DMA completion state machine */
1505         if (!BGE_IS_5705_PLUS(sc))
1506                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1507
1508         /* Turn on write DMA state machine */
1509         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1510         if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1511             sc->bge_asicrev == BGE_ASICREV_BCM5787)
1512                 val |= (1 << 29);       /* Enable host coalescing bug fix. */
1513         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1514
1515         /* Turn on read DMA state machine */
1516         CSR_WRITE_4(sc, BGE_RDMA_MODE,
1517             BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1518
1519         /* Turn on RX data completion state machine */
1520         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1521
1522         /* Turn on RX BD initiator state machine */
1523         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1524
1525         /* Turn on RX data and RX BD initiator state machine */
1526         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1527
1528         /* Turn on Mbuf cluster free state machine */
1529         if (!BGE_IS_5705_PLUS(sc))
1530                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1531
1532         /* Turn on send BD completion state machine */
1533         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1534
1535         /* Turn on send data completion state machine */
1536         CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1537
1538         /* Turn on send data initiator state machine */
1539         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1540
1541         /* Turn on send BD initiator state machine */
1542         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1543
1544         /* Turn on send BD selector state machine */
1545         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1546
1547         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1548         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1549             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1550
1551         /* ack/clear link change events */
1552         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1553             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1554             BGE_MACSTAT_LINK_CHANGED);
1555         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1556
1557         /* Enable PHY auto polling (for MII/GMII only) */
1558         if (sc->bge_flags & BGE_FLAG_TBI) {
1559                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1560         } else {
1561                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1562                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1563                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1564                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1565                             BGE_EVTENB_MI_INTERRUPT);
1566                 }
1567         }
1568
1569         /*
1570          * Clear any pending link state attention.
1571          * Otherwise some link state change events may be lost until attention
1572          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1573          * It's not necessary on newer BCM chips - perhaps enabling link
1574          * state change attentions implies clearing pending attention.
1575          */
1576         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1577             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1578             BGE_MACSTAT_LINK_CHANGED);
1579
1580         /* Enable link state change attentions. */
1581         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1582
1583         return(0);
1584 }
1585
1586 /*
1587  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1588  * against our list and return its name if we find a match. Note
1589  * that since the Broadcom controller contains VPD support, we
1590  * can get the device name string from the controller itself instead
1591  * of the compiled-in string. This is a little slow, but it guarantees
1592  * we'll always announce the right product name.
1593  */
1594 static int
1595 bge_probe(device_t dev)
1596 {
1597         struct bge_softc *sc;
1598         struct bge_type *t;
1599         char *descbuf;
1600         uint16_t product, vendor;
1601
1602         product = pci_get_device(dev);
1603         vendor = pci_get_vendor(dev);
1604
1605         for (t = bge_devs; t->bge_name != NULL; t++) {
1606                 if (vendor == t->bge_vid && product == t->bge_did)
1607                         break;
1608         }
1609
1610         if (t->bge_name == NULL)
1611                 return(ENXIO);
1612
1613         sc = device_get_softc(dev);
1614         descbuf = kmalloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK);
1615         ksnprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name,
1616             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1617         device_set_desc_copy(dev, descbuf);
1618         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL)
1619                 sc->bge_flags |= BGE_FLAG_NO_3LED;
1620         kfree(descbuf, M_TEMP);
1621         return(0);
1622 }
1623
1624 static int
1625 bge_attach(device_t dev)
1626 {
1627         struct ifnet *ifp;
1628         struct bge_softc *sc;
1629         uint32_t hwcfg = 0;
1630         uint32_t mac_addr = 0;
1631         int error = 0, rid;
1632         uint8_t ether_addr[ETHER_ADDR_LEN];
1633
1634         sc = device_get_softc(dev);
1635         sc->bge_dev = dev;
1636         callout_init(&sc->bge_stat_timer);
1637         lwkt_serialize_init(&sc->bge_jslot_serializer);
1638
1639         /*
1640          * Map control/status registers.
1641          */
1642         pci_enable_busmaster(dev);
1643
1644         rid = BGE_PCI_BAR0;
1645         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1646             RF_ACTIVE);
1647
1648         if (sc->bge_res == NULL) {
1649                 device_printf(dev, "couldn't map memory\n");
1650                 return ENXIO;
1651         }
1652
1653         sc->bge_btag = rman_get_bustag(sc->bge_res);
1654         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1655
1656         /* Save ASIC rev. */
1657         sc->bge_chipid =
1658             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1659             BGE_PCIMISCCTL_ASICREV;
1660         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1661         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1662
1663         /* Save chipset family. */
1664         switch (sc->bge_asicrev) {
1665         case BGE_ASICREV_BCM5700:
1666         case BGE_ASICREV_BCM5701:
1667         case BGE_ASICREV_BCM5703:
1668         case BGE_ASICREV_BCM5704:
1669                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1670                 break;
1671
1672         case BGE_ASICREV_BCM5714_A0:
1673         case BGE_ASICREV_BCM5780:
1674         case BGE_ASICREV_BCM5714:
1675                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1676                 /* Fall through */
1677
1678         case BGE_ASICREV_BCM5750:
1679         case BGE_ASICREV_BCM5752:
1680         case BGE_ASICREV_BCM5755:
1681         case BGE_ASICREV_BCM5787:
1682                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1683                 /* Fall through */
1684
1685         case BGE_ASICREV_BCM5705:
1686                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1687                 break;
1688         }
1689
1690         /*
1691          * Set various quirk flags.
1692          */
1693
1694         sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1695         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1696             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1697              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1698               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1699             sc->bge_asicrev == BGE_ASICREV_BCM5906)
1700                 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1701
1702         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1703             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1704                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1705
1706         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1707             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1708                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1709
1710         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1711                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1712
1713         if (BGE_IS_5705_PLUS(sc)) {
1714                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1715                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1716                         uint32_t product = pci_get_device(dev);
1717
1718                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1719                             product != PCI_PRODUCT_BROADCOM_BCM5756)
1720                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1721                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1722                                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1723                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1724                         sc->bge_flags |= BGE_FLAG_BER_BUG;
1725                 }
1726         }
1727
1728         /* Allocate interrupt */
1729         rid = 0;
1730
1731         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1732             RF_SHAREABLE | RF_ACTIVE);
1733
1734         if (sc->bge_irq == NULL) {
1735                 device_printf(dev, "couldn't map interrupt\n");
1736                 error = ENXIO;
1737                 goto fail;
1738         }
1739
1740         /*
1741          * Check if this is a PCI-X or PCI Express device.
1742          */
1743         if (BGE_IS_5705_PLUS(sc)) {
1744                 uint32_t reg;
1745
1746                 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
1747                 if ((reg & 0xff) == BGE_PCIE_CAPID)
1748                         sc->bge_flags |= BGE_FLAG_PCIE;
1749         } else {
1750                 /*
1751                  * Check if the device is in PCI-X Mode.
1752                  * (This bit is not valid on PCI Express controllers.)
1753                  */
1754                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1755                     BGE_PCISTATE_PCI_BUSMODE) == 0)
1756                         sc->bge_flags |= BGE_FLAG_PCIX;
1757         }
1758
1759         ifp = &sc->arpcom.ac_if;
1760         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1761
1762         /* Try to reset the chip. */
1763         bge_reset(sc);
1764
1765         if (bge_chipinit(sc)) {
1766                 device_printf(dev, "chip initialization failed\n");
1767                 error = ENXIO;
1768                 goto fail;
1769         }
1770
1771         /*
1772          * Get station address from the EEPROM.
1773          */
1774         mac_addr = bge_readmem_ind(sc, 0x0c14);
1775         if ((mac_addr >> 16) == 0x484b) {
1776                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1777                 ether_addr[1] = (uint8_t)mac_addr;
1778                 mac_addr = bge_readmem_ind(sc, 0x0c18);
1779                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1780                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1781                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1782                 ether_addr[5] = (uint8_t)mac_addr;
1783         } else if (bge_read_eeprom(sc, ether_addr,
1784             BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1785                 device_printf(dev, "failed to read station address\n");
1786                 error = ENXIO;
1787                 goto fail;
1788         }
1789
1790         /* 5705/5750 limits RX return ring to 512 entries. */
1791         if (BGE_IS_5705_PLUS(sc))
1792                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1793         else
1794                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1795
1796         error = bge_dma_alloc(sc);
1797         if (error)
1798                 goto fail;
1799
1800         /* Set default tuneable values. */
1801         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1802         sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
1803         sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
1804         sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
1805         sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
1806
1807         /* Set up ifnet structure */
1808         ifp->if_softc = sc;
1809         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1810         ifp->if_ioctl = bge_ioctl;
1811         ifp->if_start = bge_start;
1812 #ifdef DEVICE_POLLING
1813         ifp->if_poll = bge_poll;
1814 #endif
1815         ifp->if_watchdog = bge_watchdog;
1816         ifp->if_init = bge_init;
1817         ifp->if_mtu = ETHERMTU;
1818         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1819         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1820         ifq_set_ready(&ifp->if_snd);
1821
1822         /*
1823          * 5700 B0 chips do not support checksumming correctly due
1824          * to hardware bugs.
1825          */
1826         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
1827                 ifp->if_capabilities |= IFCAP_HWCSUM;
1828                 ifp->if_hwassist = BGE_CSUM_FEATURES;
1829         }
1830         ifp->if_capenable = ifp->if_capabilities;
1831
1832         /*
1833          * Figure out what sort of media we have by checking the
1834          * hardware config word in the first 32k of NIC internal memory,
1835          * or fall back to examining the EEPROM if necessary.
1836          * Note: on some BCM5700 cards, this value appears to be unset.
1837          * If that's the case, we have to rely on identifying the NIC
1838          * by its PCI subsystem ID, as we do below for the SysKonnect
1839          * SK-9D41.
1840          */
1841         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1842                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1843         else {
1844                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1845                                     sizeof(hwcfg))) {
1846                         device_printf(dev, "failed to read EEPROM\n");
1847                         error = ENXIO;
1848                         goto fail;
1849                 }
1850                 hwcfg = ntohl(hwcfg);
1851         }
1852
1853         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1854                 sc->bge_flags |= BGE_FLAG_TBI;
1855
1856         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1857         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1858                 sc->bge_flags |= BGE_FLAG_TBI;
1859
1860         if (sc->bge_flags & BGE_FLAG_TBI) {
1861                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1862                     bge_ifmedia_upd, bge_ifmedia_sts);
1863                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1864                 ifmedia_add(&sc->bge_ifmedia,
1865                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1866                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1867                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1868                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
1869         } else {
1870                 /*
1871                  * Do transceiver setup.
1872                  */
1873                 if (mii_phy_probe(dev, &sc->bge_miibus,
1874                     bge_ifmedia_upd, bge_ifmedia_sts)) {
1875                         device_printf(dev, "MII without any PHY!\n");
1876                         error = ENXIO;
1877                         goto fail;
1878                 }
1879         }
1880
1881         /*
1882          * When using the BCM5701 in PCI-X mode, data corruption has
1883          * been observed in the first few bytes of some received packets.
1884          * Aligning the packet buffer in memory eliminates the corruption.
1885          * Unfortunately, this misaligns the packet payloads.  On platforms
1886          * which do not support unaligned accesses, we will realign the
1887          * payloads by copying the received packets.
1888          */
1889         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1890             (sc->bge_flags & BGE_FLAG_PCIX))
1891                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
1892
1893         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1894             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1895                 sc->bge_link_upd = bge_bcm5700_link_upd;
1896                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
1897         } else if (sc->bge_flags & BGE_FLAG_TBI) {
1898                 sc->bge_link_upd = bge_tbi_link_upd;
1899                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1900         } else {
1901                 sc->bge_link_upd = bge_copper_link_upd;
1902                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1903         }
1904
1905         /*
1906          * Create sysctl nodes.
1907          */
1908         sysctl_ctx_init(&sc->bge_sysctl_ctx);
1909         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
1910                                               SYSCTL_STATIC_CHILDREN(_hw),
1911                                               OID_AUTO,
1912                                               device_get_nameunit(dev),
1913                                               CTLFLAG_RD, 0, "");
1914         if (sc->bge_sysctl_tree == NULL) {
1915                 device_printf(dev, "can't add sysctl node\n");
1916                 error = ENXIO;
1917                 goto fail;
1918         }
1919
1920         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1921                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1922                         OID_AUTO, "rx_coal_ticks",
1923                         CTLTYPE_INT | CTLFLAG_RW,
1924                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
1925                         "Receive coalescing ticks (usec).");
1926         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1927                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1928                         OID_AUTO, "tx_coal_ticks",
1929                         CTLTYPE_INT | CTLFLAG_RW,
1930                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
1931                         "Transmit coalescing ticks (usec).");
1932         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1933                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1934                         OID_AUTO, "rx_max_coal_bds",
1935                         CTLTYPE_INT | CTLFLAG_RW,
1936                         sc, 0, bge_sysctl_rx_max_coal_bds, "I",
1937                         "Receive max coalesced BD count.");
1938         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1939                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1940                         OID_AUTO, "tx_max_coal_bds",
1941                         CTLTYPE_INT | CTLFLAG_RW,
1942                         sc, 0, bge_sysctl_tx_max_coal_bds, "I",
1943                         "Transmit max coalesced BD count.");
1944
1945         /*
1946          * Call MI attach routine.
1947          */
1948         ether_ifattach(ifp, ether_addr, NULL);
1949
1950         error = bus_setup_intr(dev, sc->bge_irq, INTR_NETSAFE,
1951                                bge_intr, sc, &sc->bge_intrhand,
1952                                ifp->if_serializer);
1953         if (error) {
1954                 ether_ifdetach(ifp);
1955                 device_printf(dev, "couldn't set up irq\n");
1956                 goto fail;
1957         }
1958         return(0);
1959 fail:
1960         bge_detach(dev);
1961         return(error);
1962 }
1963
1964 static int
1965 bge_detach(device_t dev)
1966 {
1967         struct bge_softc *sc = device_get_softc(dev);
1968
1969         if (device_is_attached(dev)) {
1970                 struct ifnet *ifp = &sc->arpcom.ac_if;
1971
1972                 lwkt_serialize_enter(ifp->if_serializer);
1973                 bge_stop(sc);
1974                 bge_reset(sc);
1975                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1976                 lwkt_serialize_exit(ifp->if_serializer);
1977
1978                 ether_ifdetach(ifp);
1979         }
1980
1981         if (sc->bge_flags & BGE_FLAG_TBI)
1982                 ifmedia_removeall(&sc->bge_ifmedia);
1983         if (sc->bge_miibus)
1984                 device_delete_child(dev, sc->bge_miibus);
1985         bus_generic_detach(dev);
1986
1987         if (sc->bge_irq != NULL)
1988                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1989
1990         if (sc->bge_res != NULL)
1991                 bus_release_resource(dev, SYS_RES_MEMORY,
1992                     BGE_PCI_BAR0, sc->bge_res);
1993
1994         if (sc->bge_sysctl_tree != NULL)
1995                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
1996
1997         bge_dma_free(sc);
1998
1999         return 0;
2000 }
2001
2002 static void
2003 bge_reset(struct bge_softc *sc)
2004 {
2005         device_t dev;
2006         uint32_t cachesize, command, pcistate, reset;
2007         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2008         int i, val = 0;
2009
2010         dev = sc->bge_dev;
2011
2012         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) {
2013                 if (sc->bge_flags & BGE_FLAG_PCIE)
2014                         write_op = bge_writemem_direct;
2015                 else
2016                         write_op = bge_writemem_ind;
2017         } else {
2018                 write_op = bge_writereg_ind;
2019         }
2020
2021         /* Save some important PCI state. */
2022         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2023         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2024         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2025
2026         pci_write_config(dev, BGE_PCI_MISC_CTL,
2027             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2028             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2029
2030         /* Disable fastboot on controllers that support it. */
2031         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2032             sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2033             sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2034                 if (bootverbose)
2035                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2036                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2037         }
2038
2039         /*
2040          * Write the magic number to SRAM at offset 0xB50.
2041          * When firmware finishes its initialization it will
2042          * write ~BGE_MAGIC_NUMBER to the same location.
2043          */
2044         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2045
2046         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2047
2048         /* XXX: Broadcom Linux driver. */
2049         if (sc->bge_flags & BGE_FLAG_PCIE) {
2050                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2051                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2052                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2053                         /* Prevent PCIE link training during global reset */
2054                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2055                         reset |= (1<<29);
2056                 }
2057         }
2058
2059         /*
2060          * Set GPHY Power Down Override to leave GPHY
2061          * powered up in D0 uninitialized.
2062          */
2063         if (BGE_IS_5705_PLUS(sc))
2064                 reset |= 0x04000000;
2065
2066         /* Issue global reset */
2067         write_op(sc, BGE_MISC_CFG, reset);
2068
2069         DELAY(1000);
2070
2071         /* XXX: Broadcom Linux driver. */
2072         if (sc->bge_flags & BGE_FLAG_PCIE) {
2073                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2074                         uint32_t v;
2075
2076                         DELAY(500000); /* wait for link training to complete */
2077                         v = pci_read_config(dev, 0xc4, 4);
2078                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2079                 }
2080                 /*
2081                  * Set PCIE max payload size to 128 bytes and
2082                  * clear error status.
2083                  */
2084                 pci_write_config(dev, 0xd8, 0xf5000, 4);
2085         }
2086
2087         /* Reset some of the PCI state that got zapped by reset */
2088         pci_write_config(dev, BGE_PCI_MISC_CTL,
2089             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2090             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2091         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2092         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2093         write_op(sc, BGE_MISC_CFG, (65 << 1));
2094
2095         /* Enable memory arbiter. */
2096         if (BGE_IS_5714_FAMILY(sc)) {
2097                 uint32_t val;
2098
2099                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2100                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2101         } else {
2102                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2103         }
2104
2105         /*
2106          * Poll until we see the 1's complement of the magic number.
2107          * This indicates that the firmware initialization
2108          * is complete.
2109          */
2110         for (i = 0; i < BGE_TIMEOUT; i++) {
2111                 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2112                 if (val == ~BGE_MAGIC_NUMBER)
2113                         break;
2114                 DELAY(10);
2115         }
2116
2117         if (i == BGE_TIMEOUT) {
2118                 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out,"
2119                           "found 0x%08x\n", val);
2120                 return;
2121         }
2122
2123         /*
2124          * XXX Wait for the value of the PCISTATE register to
2125          * return to its original pre-reset state. This is a
2126          * fairly good indicator of reset completion. If we don't
2127          * wait for the reset to fully complete, trying to read
2128          * from the device's non-PCI registers may yield garbage
2129          * results.
2130          */
2131         for (i = 0; i < BGE_TIMEOUT; i++) {
2132                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2133                         break;
2134                 DELAY(10);
2135         }
2136
2137         if (sc->bge_flags & BGE_FLAG_PCIE) {
2138                 reset = bge_readmem_ind(sc, 0x7c00);
2139                 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2140         }
2141
2142         /* Fix up byte swapping */
2143         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2144             BGE_MODECTL_BYTESWAP_DATA);
2145
2146         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2147
2148         /*
2149          * The 5704 in TBI mode apparently needs some special
2150          * adjustment to insure the SERDES drive level is set
2151          * to 1.2V.
2152          */
2153         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2154             (sc->bge_flags & BGE_FLAG_TBI)) {
2155                 uint32_t serdescfg;
2156
2157                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2158                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2159                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2160         }
2161
2162         /* XXX: Broadcom Linux driver. */
2163         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2164             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2165                 uint32_t v;
2166
2167                 v = CSR_READ_4(sc, 0x7c00);
2168                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2169         }
2170
2171         DELAY(10000);
2172 }
2173
2174 /*
2175  * Frame reception handling. This is called if there's a frame
2176  * on the receive return list.
2177  *
2178  * Note: we have to be able to handle two possibilities here:
2179  * 1) the frame is from the jumbo recieve ring
2180  * 2) the frame is from the standard receive ring
2181  */
2182
2183 static void
2184 bge_rxeof(struct bge_softc *sc)
2185 {
2186         struct ifnet *ifp;
2187         int stdcnt = 0, jumbocnt = 0;
2188
2189         if (sc->bge_rx_saved_considx ==
2190             sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2191                 return;
2192
2193         ifp = &sc->arpcom.ac_if;
2194
2195         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2196                         sc->bge_cdata.bge_rx_return_ring_map,
2197                         BUS_DMASYNC_POSTREAD);
2198         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2199                         sc->bge_cdata.bge_rx_std_ring_map,
2200                         BUS_DMASYNC_POSTREAD);
2201         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2202                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2203                                 sc->bge_cdata.bge_rx_jumbo_ring_map,
2204                                 BUS_DMASYNC_POSTREAD);
2205         }
2206
2207         while (sc->bge_rx_saved_considx !=
2208                sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2209                 struct bge_rx_bd        *cur_rx;
2210                 uint32_t                rxidx;
2211                 struct mbuf             *m = NULL;
2212                 uint16_t                vlan_tag = 0;
2213                 int                     have_tag = 0;
2214
2215                 cur_rx =
2216             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2217
2218                 rxidx = cur_rx->bge_idx;
2219                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2220                 logif(rx_pkt);
2221
2222                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2223                         have_tag = 1;
2224                         vlan_tag = cur_rx->bge_vlan_tag;
2225                 }
2226
2227                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2228                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2229                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2230                         sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2231                         jumbocnt++;
2232                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2233                                 ifp->if_ierrors++;
2234                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2235                                 continue;
2236                         }
2237                         if (bge_newbuf_jumbo(sc,
2238                             sc->bge_jumbo, NULL) == ENOBUFS) {
2239                                 ifp->if_ierrors++;
2240                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2241                                 continue;
2242                         }
2243                 } else {
2244                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2245                         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2246                                         sc->bge_cdata.bge_rx_std_dmamap[rxidx],
2247                                         BUS_DMASYNC_POSTREAD);
2248                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2249                                 sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
2250                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2251                         sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2252                         stdcnt++;
2253                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2254                                 ifp->if_ierrors++;
2255                                 bge_newbuf_std(sc, sc->bge_std, m);
2256                                 continue;
2257                         }
2258                         if (bge_newbuf_std(sc, sc->bge_std,
2259                             NULL) == ENOBUFS) {
2260                                 ifp->if_ierrors++;
2261                                 bge_newbuf_std(sc, sc->bge_std, m);
2262                                 continue;
2263                         }
2264                 }
2265
2266                 ifp->if_ipackets++;
2267 #ifndef __i386__
2268                 /*
2269                  * The i386 allows unaligned accesses, but for other
2270                  * platforms we must make sure the payload is aligned.
2271                  */
2272                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2273                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2274                             cur_rx->bge_len);
2275                         m->m_data += ETHER_ALIGN;
2276                 }
2277 #endif
2278                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2279                 m->m_pkthdr.rcvif = ifp;
2280
2281                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2282                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2283                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2284                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2285                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2286                         }
2287                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2288                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2289                                 m->m_pkthdr.csum_data =
2290                                         cur_rx->bge_tcp_udp_csum;
2291                                 m->m_pkthdr.csum_flags |=
2292                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2293                         }
2294                 }
2295
2296                 /*
2297                  * If we received a packet with a vlan tag, pass it
2298                  * to vlan_input() instead of ether_input().
2299                  */
2300                 if (have_tag) {
2301                         VLAN_INPUT_TAG(m, vlan_tag);
2302                         have_tag = vlan_tag = 0;
2303                 } else {
2304                         ifp->if_input(ifp, m);
2305                 }
2306         }
2307
2308         if (stdcnt > 0) {
2309                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2310                                 sc->bge_cdata.bge_rx_std_ring_map,
2311                                 BUS_DMASYNC_PREWRITE);
2312         }
2313
2314         if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) {
2315                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2316                                 sc->bge_cdata.bge_rx_jumbo_ring_map,
2317                                 BUS_DMASYNC_PREWRITE);
2318         }
2319
2320         CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2321         if (stdcnt)
2322                 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2323         if (jumbocnt)
2324                 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2325 }
2326
2327 static void
2328 bge_txeof(struct bge_softc *sc)
2329 {
2330         struct bge_tx_bd *cur_tx = NULL;
2331         struct ifnet *ifp;
2332
2333         if (sc->bge_tx_saved_considx ==
2334             sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2335                 return;
2336
2337         ifp = &sc->arpcom.ac_if;
2338
2339         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
2340                         sc->bge_cdata.bge_tx_ring_map,
2341                         BUS_DMASYNC_POSTREAD);
2342
2343         /*
2344          * Go through our tx ring and free mbufs for those
2345          * frames that have been sent.
2346          */
2347         while (sc->bge_tx_saved_considx !=
2348                sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2349                 uint32_t idx = 0;
2350
2351                 idx = sc->bge_tx_saved_considx;
2352                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2353                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2354                         ifp->if_opackets++;
2355                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2356                         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2357                                         sc->bge_cdata.bge_tx_dmamap[idx],
2358                                         BUS_DMASYNC_POSTWRITE);
2359                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2360                             sc->bge_cdata.bge_tx_dmamap[idx]);
2361                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2362                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2363                 }
2364                 sc->bge_txcnt--;
2365                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2366                 logif(tx_pkt);
2367         }
2368
2369         if (cur_tx != NULL &&
2370             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2371             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2372                 ifp->if_flags &= ~IFF_OACTIVE;
2373
2374         if (sc->bge_txcnt == 0)
2375                 ifp->if_timer = 0;
2376
2377         if (!ifq_is_empty(&ifp->if_snd))
2378                 ifp->if_start(ifp);
2379 }
2380
2381 #ifdef DEVICE_POLLING
2382
2383 static void
2384 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2385 {
2386         struct bge_softc *sc = ifp->if_softc;
2387         uint32_t status;
2388
2389         switch(cmd) {
2390         case POLL_REGISTER:
2391                 bge_disable_intr(sc);
2392                 break;
2393         case POLL_DEREGISTER:
2394                 bge_enable_intr(sc);
2395                 break;
2396         case POLL_AND_CHECK_STATUS:
2397                 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2398                                 sc->bge_cdata.bge_status_map,
2399                                 BUS_DMASYNC_POSTREAD);
2400
2401                 /*
2402                  * Process link state changes.
2403                  */
2404                 status = CSR_READ_4(sc, BGE_MAC_STS);
2405                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2406                         sc->bge_link_evt = 0;
2407                         sc->bge_link_upd(sc, status);
2408                 }
2409                 /* fall through */
2410         case POLL_ONLY:
2411                 if (ifp->if_flags & IFF_RUNNING) {
2412                         bge_rxeof(sc);
2413                         bge_txeof(sc);
2414                 }
2415                 break;
2416         }
2417 }
2418
2419 #endif
2420
2421 static void
2422 bge_intr(void *xsc)
2423 {
2424         struct bge_softc *sc = xsc;
2425         struct ifnet *ifp = &sc->arpcom.ac_if;
2426         uint32_t status;
2427
2428         logif(intr);
2429
2430         /*
2431          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2432          * disable interrupts by writing nonzero like we used to, since with
2433          * our current organization this just gives complications and
2434          * pessimizations for re-enabling interrupts.  We used to have races
2435          * instead of the necessary complications.  Disabling interrupts
2436          * would just reduce the chance of a status update while we are
2437          * running (by switching to the interrupt-mode coalescence
2438          * parameters), but this chance is already very low so it is more
2439          * efficient to get another interrupt than prevent it.
2440          *
2441          * We do the ack first to ensure another interrupt if there is a
2442          * status update after the ack.  We don't check for the status
2443          * changing later because it is more efficient to get another
2444          * interrupt than prevent it, not quite as above (not checking is
2445          * a smaller optimization than not toggling the interrupt enable,
2446          * since checking doesn't involve PCI accesses and toggling require
2447          * the status check).  So toggling would probably be a pessimization
2448          * even with MSI.  It would only be needed for using a task queue.
2449          */
2450         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2451
2452         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2453                         sc->bge_cdata.bge_status_map,
2454                         BUS_DMASYNC_POSTREAD);
2455
2456         /*
2457          * Process link state changes.
2458          */
2459         status = CSR_READ_4(sc, BGE_MAC_STS);
2460         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2461                 sc->bge_link_evt = 0;
2462                 sc->bge_link_upd(sc, status);
2463         }
2464
2465         if (ifp->if_flags & IFF_RUNNING) {
2466                 /* Check RX return ring producer/consumer */
2467                 bge_rxeof(sc);
2468
2469                 /* Check TX ring producer/consumer */
2470                 bge_txeof(sc);
2471         }
2472
2473         if (sc->bge_coal_chg)
2474                 bge_coal_change(sc);
2475 }
2476
2477 static void
2478 bge_tick(void *xsc)
2479 {
2480         struct bge_softc *sc = xsc;
2481         struct ifnet *ifp = &sc->arpcom.ac_if;
2482
2483         lwkt_serialize_enter(ifp->if_serializer);
2484
2485         if (BGE_IS_5705_PLUS(sc))
2486                 bge_stats_update_regs(sc);
2487         else
2488                 bge_stats_update(sc);
2489
2490         if (sc->bge_flags & BGE_FLAG_TBI) {
2491                 /*
2492                  * Since in TBI mode auto-polling can't be used we should poll
2493                  * link status manually. Here we register pending link event
2494                  * and trigger interrupt.
2495                  */
2496                 sc->bge_link_evt++;
2497                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2498         } else if (!sc->bge_link) {
2499                 mii_tick(device_get_softc(sc->bge_miibus));
2500         }
2501
2502         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2503
2504         lwkt_serialize_exit(ifp->if_serializer);
2505 }
2506
2507 static void
2508 bge_stats_update_regs(struct bge_softc *sc)
2509 {
2510         struct ifnet *ifp = &sc->arpcom.ac_if;
2511         struct bge_mac_stats_regs stats;
2512         uint32_t *s;
2513         int i;
2514
2515         s = (uint32_t *)&stats;
2516         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2517                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2518                 s++;
2519         }
2520
2521         ifp->if_collisions +=
2522            (stats.dot3StatsSingleCollisionFrames +
2523            stats.dot3StatsMultipleCollisionFrames +
2524            stats.dot3StatsExcessiveCollisions +
2525            stats.dot3StatsLateCollisions) -
2526            ifp->if_collisions;
2527 }
2528
2529 static void
2530 bge_stats_update(struct bge_softc *sc)
2531 {
2532         struct ifnet *ifp = &sc->arpcom.ac_if;
2533         bus_size_t stats;
2534
2535         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2536
2537 #define READ_STAT(sc, stats, stat)      \
2538         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2539
2540         ifp->if_collisions +=
2541            (READ_STAT(sc, stats,
2542                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2543             READ_STAT(sc, stats,
2544                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2545             READ_STAT(sc, stats,
2546                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2547             READ_STAT(sc, stats,
2548                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2549            ifp->if_collisions;
2550
2551 #undef READ_STAT
2552
2553 #ifdef notdef
2554         ifp->if_collisions +=
2555            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2556            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2557            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2558            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2559            ifp->if_collisions;
2560 #endif
2561 }
2562
2563 /*
2564  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2565  * pointers to descriptors.
2566  */
2567 static int
2568 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2569 {
2570         struct bge_tx_bd *d = NULL;
2571         uint16_t csum_flags = 0;
2572         struct bge_dmamap_arg ctx;
2573         bus_dma_segment_t segs[BGE_NSEG_NEW];
2574         bus_dmamap_t map;
2575         int error, maxsegs, idx, i;
2576         struct mbuf *m_head = *m_head0;
2577
2578         if (m_head->m_pkthdr.csum_flags) {
2579                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2580                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2581                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2582                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2583                 if (m_head->m_flags & M_LASTFRAG)
2584                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2585                 else if (m_head->m_flags & M_FRAG)
2586                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2587         }
2588
2589         idx = *txidx;
2590         map = sc->bge_cdata.bge_tx_dmamap[idx];
2591
2592         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2593         KASSERT(maxsegs >= BGE_NSEG_SPARE,
2594                 ("not enough segments %d\n", maxsegs));
2595
2596         if (maxsegs > BGE_NSEG_NEW)
2597                 maxsegs = BGE_NSEG_NEW;
2598
2599         /*
2600          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2601          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2602          * but when such padded frames employ the bge IP/TCP checksum
2603          * offload, the hardware checksum assist gives incorrect results
2604          * (possibly from incorporating its own padding into the UDP/TCP
2605          * checksum; who knows).  If we pad such runts with zeros, the
2606          * onboard checksum comes out correct.  We do this by pretending
2607          * the mbuf chain has too many fragments so the coalescing code
2608          * below can assemble the packet into a single buffer that's
2609          * padded out to the mininum frame size.
2610          */
2611         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2612             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2613                 error = EFBIG;
2614         } else {
2615                 ctx.bge_segs = segs;
2616                 ctx.bge_maxsegs = maxsegs;
2617                 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2618                                              m_head, bge_dma_map_mbuf, &ctx,
2619                                              BUS_DMA_NOWAIT);
2620         }
2621         if (error == EFBIG || ctx.bge_maxsegs == 0) {
2622                 struct mbuf *m_new;
2623
2624                 m_new = m_defrag(m_head, MB_DONTWAIT);
2625                 if (m_new == NULL) {
2626                         if_printf(&sc->arpcom.ac_if,
2627                                   "could not defrag TX mbuf\n");
2628                         error = ENOBUFS;
2629                         goto back;
2630                 } else {
2631                         m_head = m_new;
2632                         *m_head0 = m_head;
2633                 }
2634
2635                 /*
2636                  * Manually pad short frames, and zero the pad space
2637                  * to avoid leaking data.
2638                  */
2639                 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2640                     m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2641                         int pad_len = BGE_MIN_FRAME - m_head->m_pkthdr.len;
2642
2643                         bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
2644                               pad_len);
2645                         m_head->m_pkthdr.len += pad_len;
2646                         m_head->m_len = m_head->m_pkthdr.len;
2647                 }
2648
2649                 ctx.bge_segs = segs;
2650                 ctx.bge_maxsegs = maxsegs;
2651                 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2652                                              m_head, bge_dma_map_mbuf, &ctx,
2653                                              BUS_DMA_NOWAIT);
2654                 if (error || ctx.bge_maxsegs == 0) {
2655                         if_printf(&sc->arpcom.ac_if,
2656                                   "could not defrag TX mbuf\n");
2657                         if (error == 0)
2658                                 error = EFBIG;
2659                         goto back;
2660                 }
2661         } else if (error) {
2662                 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
2663                 goto back;
2664         }
2665
2666         bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
2667
2668         for (i = 0; ; i++) {
2669                 d = &sc->bge_ldata.bge_tx_ring[idx];
2670
2671                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[i].ds_addr);
2672                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[i].ds_addr);
2673                 d->bge_len = segs[i].ds_len;
2674                 d->bge_flags = csum_flags;
2675
2676                 if (i == ctx.bge_maxsegs - 1)
2677                         break;
2678                 BGE_INC(idx, BGE_TX_RING_CNT);
2679         }
2680         /* Mark the last segment as end of packet... */
2681         d->bge_flags |= BGE_TXBDFLAG_END;
2682
2683         /* Set vlan tag to the first segment of the packet. */
2684         d = &sc->bge_ldata.bge_tx_ring[*txidx];
2685         if (m_head->m_flags & M_VLANTAG) {
2686                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2687                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
2688         } else {
2689                 d->bge_vlan_tag = 0;
2690         }
2691
2692         /*
2693          * Insure that the map for this transmission is placed at
2694          * the array index of the last descriptor in this chain.
2695          */
2696         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2697         sc->bge_cdata.bge_tx_dmamap[idx] = map;
2698         sc->bge_cdata.bge_tx_chain[idx] = m_head;
2699         sc->bge_txcnt += ctx.bge_maxsegs;
2700
2701         BGE_INC(idx, BGE_TX_RING_CNT);
2702         *txidx = idx;
2703 back:
2704         if (error) {
2705                 m_freem(m_head);
2706                 *m_head0 = NULL;
2707         }
2708         return error;
2709 }
2710
2711 /*
2712  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2713  * to the mbuf data regions directly in the transmit descriptors.
2714  */
2715 static void
2716 bge_start(struct ifnet *ifp)
2717 {
2718         struct bge_softc *sc = ifp->if_softc;
2719         struct mbuf *m_head = NULL;
2720         uint32_t prodidx;
2721         int need_trans;
2722
2723         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2724                 return;
2725
2726         prodidx = sc->bge_tx_prodidx;
2727
2728         need_trans = 0;
2729         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2730                 m_head = ifq_poll(&ifp->if_snd);
2731                 if (m_head == NULL)
2732                         break;
2733
2734                 /*
2735                  * XXX
2736                  * The code inside the if() block is never reached since we
2737                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2738                  * requests to checksum TCP/UDP in a fragmented packet.
2739                  *
2740                  * XXX
2741                  * safety overkill.  If this is a fragmented packet chain
2742                  * with delayed TCP/UDP checksums, then only encapsulate
2743                  * it if we have enough descriptors to handle the entire
2744                  * chain at once.
2745                  * (paranoia -- may not actually be needed)
2746                  */
2747                 if (m_head->m_flags & M_FIRSTFRAG &&
2748                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2749                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2750                             m_head->m_pkthdr.csum_data + 16) {
2751                                 ifp->if_flags |= IFF_OACTIVE;
2752                                 break;
2753                         }
2754                 }
2755
2756                 /*
2757                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2758                  * descriptors of the end of the ring.  Also make
2759                  * sure there are BGE_NSEG_SPARE descriptors for
2760                  * jumbo buffers' defragmentation.
2761                  */
2762                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2763                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
2764                         ifp->if_flags |= IFF_OACTIVE;
2765                         break;
2766                 }
2767
2768                 /*
2769                  * Dequeue the packet before encapsulation, since
2770                  * bge_encap() may free the packet if error happens.
2771                  */
2772                 ifq_dequeue(&ifp->if_snd, m_head);
2773
2774                 /*
2775                  * Pack the data into the transmit ring. If we
2776                  * don't have room, set the OACTIVE flag and wait
2777                  * for the NIC to drain the ring.
2778                  */
2779                 if (bge_encap(sc, &m_head, &prodidx)) {
2780                         ifp->if_flags |= IFF_OACTIVE;
2781                         break;
2782                 }
2783                 need_trans = 1;
2784
2785                 ETHER_BPF_MTAP(ifp, m_head);
2786         }
2787
2788         if (!need_trans)
2789                 return;
2790
2791         /* Transmit */
2792         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2793         /* 5700 b2 errata */
2794         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2795                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2796
2797         sc->bge_tx_prodidx = prodidx;
2798
2799         /*
2800          * Set a timeout in case the chip goes out to lunch.
2801          */
2802         ifp->if_timer = 5;
2803 }
2804
2805 static void
2806 bge_init(void *xsc)
2807 {
2808         struct bge_softc *sc = xsc;
2809         struct ifnet *ifp = &sc->arpcom.ac_if;
2810         uint16_t *m;
2811
2812         ASSERT_SERIALIZED(ifp->if_serializer);
2813
2814         if (ifp->if_flags & IFF_RUNNING)
2815                 return;
2816
2817         /* Cancel pending I/O and flush buffers. */
2818         bge_stop(sc);
2819         bge_reset(sc);
2820         bge_chipinit(sc);
2821
2822         /*
2823          * Init the various state machines, ring
2824          * control blocks and firmware.
2825          */
2826         if (bge_blockinit(sc)) {
2827                 if_printf(ifp, "initialization failure\n");
2828                 return;
2829         }
2830
2831         /* Specify MTU. */
2832         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2833             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2834
2835         /* Load our MAC address. */
2836         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2837         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2838         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2839
2840         /* Enable or disable promiscuous mode as needed. */
2841         bge_setpromisc(sc);
2842
2843         /* Program multicast filter. */
2844         bge_setmulti(sc);
2845
2846         /* Init RX ring. */
2847         bge_init_rx_ring_std(sc);
2848
2849         /*
2850          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2851          * memory to insure that the chip has in fact read the first
2852          * entry of the ring.
2853          */
2854         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2855                 uint32_t                v, i;
2856                 for (i = 0; i < 10; i++) {
2857                         DELAY(20);
2858                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2859                         if (v == (MCLBYTES - ETHER_ALIGN))
2860                                 break;
2861                 }
2862                 if (i == 10)
2863                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
2864         }
2865
2866         /* Init jumbo RX ring. */
2867         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2868                 bge_init_rx_ring_jumbo(sc);
2869
2870         /* Init our RX return ring index */
2871         sc->bge_rx_saved_considx = 0;
2872
2873         /* Init TX ring. */
2874         bge_init_tx_ring(sc);
2875
2876         /* Turn on transmitter */
2877         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2878
2879         /* Turn on receiver */
2880         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2881
2882         /* Tell firmware we're alive. */
2883         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2884
2885         /* Enable host interrupts if polling(4) is not enabled. */
2886         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2887 #ifdef DEVICE_POLLING
2888         if (ifp->if_flags & IFF_POLLING)
2889                 bge_disable_intr(sc);
2890         else
2891 #endif
2892         bge_enable_intr(sc);
2893
2894         bge_ifmedia_upd(ifp);
2895
2896         ifp->if_flags |= IFF_RUNNING;
2897         ifp->if_flags &= ~IFF_OACTIVE;
2898
2899         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2900 }
2901
2902 /*
2903  * Set media options.
2904  */
2905 static int
2906 bge_ifmedia_upd(struct ifnet *ifp)
2907 {
2908         struct bge_softc *sc = ifp->if_softc;
2909
2910         /* If this is a 1000baseX NIC, enable the TBI port. */
2911         if (sc->bge_flags & BGE_FLAG_TBI) {
2912                 struct ifmedia *ifm = &sc->bge_ifmedia;
2913
2914                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2915                         return(EINVAL);
2916
2917                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2918                 case IFM_AUTO:
2919                         /*
2920                          * The BCM5704 ASIC appears to have a special
2921                          * mechanism for programming the autoneg
2922                          * advertisement registers in TBI mode.
2923                          */
2924                         if (!bge_fake_autoneg &&
2925                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2926                                 uint32_t sgdig;
2927
2928                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
2929                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
2930                                 sgdig |= BGE_SGDIGCFG_AUTO |
2931                                          BGE_SGDIGCFG_PAUSE_CAP |
2932                                          BGE_SGDIGCFG_ASYM_PAUSE;
2933                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
2934                                             sgdig | BGE_SGDIGCFG_SEND);
2935                                 DELAY(5);
2936                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
2937                         }
2938                         break;
2939                 case IFM_1000_SX:
2940                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2941                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
2942                                     BGE_MACMODE_HALF_DUPLEX);
2943                         } else {
2944                                 BGE_SETBIT(sc, BGE_MAC_MODE,
2945                                     BGE_MACMODE_HALF_DUPLEX);
2946                         }
2947                         break;
2948                 default:
2949                         return(EINVAL);
2950                 }
2951         } else {
2952                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
2953
2954                 sc->bge_link_evt++;
2955                 sc->bge_link = 0;
2956                 if (mii->mii_instance) {
2957                         struct mii_softc *miisc;
2958
2959                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2960                                 mii_phy_reset(miisc);
2961                 }
2962                 mii_mediachg(mii);
2963         }
2964         return(0);
2965 }
2966
2967 /*
2968  * Report current media status.
2969  */
2970 static void
2971 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2972 {
2973         struct bge_softc *sc = ifp->if_softc;
2974
2975         if (sc->bge_flags & BGE_FLAG_TBI) {
2976                 ifmr->ifm_status = IFM_AVALID;
2977                 ifmr->ifm_active = IFM_ETHER;
2978                 if (CSR_READ_4(sc, BGE_MAC_STS) &
2979                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
2980                         ifmr->ifm_status |= IFM_ACTIVE;
2981                 } else {
2982                         ifmr->ifm_active |= IFM_NONE;
2983                         return;
2984                 }
2985
2986                 ifmr->ifm_active |= IFM_1000_SX;
2987                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2988                         ifmr->ifm_active |= IFM_HDX;
2989                 else
2990                         ifmr->ifm_active |= IFM_FDX;
2991         } else {
2992                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
2993
2994                 mii_pollstat(mii);
2995                 ifmr->ifm_active = mii->mii_media_active;
2996                 ifmr->ifm_status = mii->mii_media_status;
2997         }
2998 }
2999
3000 static int
3001 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3002 {
3003         struct bge_softc *sc = ifp->if_softc;
3004         struct ifreq *ifr = (struct ifreq *)data;
3005         int mask, error = 0;
3006
3007         ASSERT_SERIALIZED(ifp->if_serializer);
3008
3009         switch (command) {
3010         case SIOCSIFMTU:
3011                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3012                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3013                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3014                         error = EINVAL;
3015                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3016                         ifp->if_mtu = ifr->ifr_mtu;
3017                         ifp->if_flags &= ~IFF_RUNNING;
3018                         bge_init(sc);
3019                 }
3020                 break;
3021         case SIOCSIFFLAGS:
3022                 if (ifp->if_flags & IFF_UP) {
3023                         if (ifp->if_flags & IFF_RUNNING) {
3024                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3025
3026                                 /*
3027                                  * If only the state of the PROMISC flag
3028                                  * changed, then just use the 'set promisc
3029                                  * mode' command instead of reinitializing
3030                                  * the entire NIC. Doing a full re-init
3031                                  * means reloading the firmware and waiting
3032                                  * for it to start up, which may take a
3033                                  * second or two.  Similarly for ALLMULTI.
3034                                  */
3035                                 if (mask & IFF_PROMISC)
3036                                         bge_setpromisc(sc);
3037                                 if (mask & IFF_ALLMULTI)
3038                                         bge_setmulti(sc);
3039                         } else {
3040                                 bge_init(sc);
3041                         }
3042                 } else {
3043                         if (ifp->if_flags & IFF_RUNNING)
3044                                 bge_stop(sc);
3045                 }
3046                 sc->bge_if_flags = ifp->if_flags;
3047                 break;
3048         case SIOCADDMULTI:
3049         case SIOCDELMULTI:
3050                 if (ifp->if_flags & IFF_RUNNING)
3051                         bge_setmulti(sc);
3052                 break;
3053         case SIOCSIFMEDIA:
3054         case SIOCGIFMEDIA:
3055                 if (sc->bge_flags & BGE_FLAG_TBI) {
3056                         error = ifmedia_ioctl(ifp, ifr,
3057                             &sc->bge_ifmedia, command);
3058                 } else {
3059                         struct mii_data *mii;
3060
3061                         mii = device_get_softc(sc->bge_miibus);
3062                         error = ifmedia_ioctl(ifp, ifr,
3063                                               &mii->mii_media, command);
3064                 }
3065                 break;
3066         case SIOCSIFCAP:
3067                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3068                 if (mask & IFCAP_HWCSUM) {
3069                         ifp->if_capenable ^= IFCAP_HWCSUM;
3070                         if (IFCAP_HWCSUM & ifp->if_capenable)
3071                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3072                         else
3073                                 ifp->if_hwassist = 0;
3074                 }
3075                 break;
3076         default:
3077                 error = ether_ioctl(ifp, command, data);
3078                 break;
3079         }
3080         return error;
3081 }
3082
3083 static void
3084 bge_watchdog(struct ifnet *ifp)
3085 {
3086         struct bge_softc *sc = ifp->if_softc;
3087
3088         if_printf(ifp, "watchdog timeout -- resetting\n");
3089
3090         ifp->if_flags &= ~IFF_RUNNING;
3091         bge_init(sc);
3092
3093         ifp->if_oerrors++;
3094
3095         if (!ifq_is_empty(&ifp->if_snd))
3096                 ifp->if_start(ifp);
3097 }
3098
3099 /*
3100  * Stop the adapter and free any mbufs allocated to the
3101  * RX and TX lists.
3102  */
3103 static void
3104 bge_stop(struct bge_softc *sc)
3105 {
3106         struct ifnet *ifp = &sc->arpcom.ac_if;
3107         struct ifmedia_entry *ifm;
3108         struct mii_data *mii = NULL;
3109         int mtmp, itmp;
3110
3111         ASSERT_SERIALIZED(ifp->if_serializer);
3112
3113         if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
3114                 mii = device_get_softc(sc->bge_miibus);
3115
3116         callout_stop(&sc->bge_stat_timer);
3117
3118         /*
3119          * Disable all of the receiver blocks
3120          */
3121         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3122         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3123         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3124         if (!BGE_IS_5705_PLUS(sc))
3125                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3126         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3127         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3128         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3129
3130         /*
3131          * Disable all of the transmit blocks
3132          */
3133         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3134         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3135         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3136         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3137         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3138         if (!BGE_IS_5705_PLUS(sc))
3139                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3140         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3141
3142         /*
3143          * Shut down all of the memory managers and related
3144          * state machines.
3145          */
3146         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3147         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3148         if (!BGE_IS_5705_PLUS(sc))
3149                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3150         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3151         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3152         if (!BGE_IS_5705_PLUS(sc)) {
3153                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3154                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3155         }
3156
3157         /* Disable host interrupts. */
3158         bge_disable_intr(sc);
3159
3160         /*
3161          * Tell firmware we're shutting down.
3162          */
3163         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3164
3165         /* Free the RX lists. */
3166         bge_free_rx_ring_std(sc);
3167
3168         /* Free jumbo RX list. */
3169         if (BGE_IS_JUMBO_CAPABLE(sc))
3170                 bge_free_rx_ring_jumbo(sc);
3171
3172         /* Free TX buffers. */
3173         bge_free_tx_ring(sc);
3174
3175         /*
3176          * Isolate/power down the PHY, but leave the media selection
3177          * unchanged so that things will be put back to normal when
3178          * we bring the interface back up.
3179          *
3180          * 'mii' may be NULL in the following cases:
3181          * - The device uses TBI.
3182          * - bge_stop() is called by bge_detach().
3183          */
3184         if (mii != NULL) {
3185                 itmp = ifp->if_flags;
3186                 ifp->if_flags |= IFF_UP;
3187                 ifm = mii->mii_media.ifm_cur;
3188                 mtmp = ifm->ifm_media;
3189                 ifm->ifm_media = IFM_ETHER|IFM_NONE;
3190                 mii_mediachg(mii);
3191                 ifm->ifm_media = mtmp;
3192                 ifp->if_flags = itmp;
3193         }
3194
3195         sc->bge_link = 0;
3196         sc->bge_coal_chg = 0;
3197
3198         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3199
3200         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3201         ifp->if_timer = 0;
3202 }
3203
3204 /*
3205  * Stop all chip I/O so that the kernel's probe routines don't
3206  * get confused by errant DMAs when rebooting.
3207  */
3208 static void
3209 bge_shutdown(device_t dev)
3210 {
3211         struct bge_softc *sc = device_get_softc(dev);
3212         struct ifnet *ifp = &sc->arpcom.ac_if;
3213
3214         lwkt_serialize_enter(ifp->if_serializer);
3215         bge_stop(sc);
3216         bge_reset(sc);
3217         lwkt_serialize_exit(ifp->if_serializer);
3218 }
3219
3220 static int
3221 bge_suspend(device_t dev)
3222 {
3223         struct bge_softc *sc = device_get_softc(dev);
3224         struct ifnet *ifp = &sc->arpcom.ac_if;
3225
3226         lwkt_serialize_enter(ifp->if_serializer);
3227         bge_stop(sc);
3228         lwkt_serialize_exit(ifp->if_serializer);
3229
3230         return 0;
3231 }
3232
3233 static int
3234 bge_resume(device_t dev)
3235 {
3236         struct bge_softc *sc = device_get_softc(dev);
3237         struct ifnet *ifp = &sc->arpcom.ac_if;
3238
3239         lwkt_serialize_enter(ifp->if_serializer);
3240
3241         if (ifp->if_flags & IFF_UP) {
3242                 bge_init(sc);
3243
3244                 if (!ifq_is_empty(&ifp->if_snd))
3245                         ifp->if_start(ifp);
3246         }
3247
3248         lwkt_serialize_exit(ifp->if_serializer);
3249
3250         return 0;
3251 }
3252
3253 static void
3254 bge_setpromisc(struct bge_softc *sc)
3255 {
3256         struct ifnet *ifp = &sc->arpcom.ac_if;
3257
3258         if (ifp->if_flags & IFF_PROMISC)
3259                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3260         else
3261                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3262 }
3263
3264 static void
3265 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3266 {
3267         struct bge_dmamap_arg *ctx = arg;
3268
3269         if (error)
3270                 return;
3271
3272         KASSERT(nsegs == 1 && ctx->bge_maxsegs == 1,
3273                 ("only one segment is allowed\n"));
3274
3275         ctx->bge_segs[0] = *segs;
3276 }
3277
3278 static void
3279 bge_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs,
3280                  bus_size_t mapsz __unused, int error)
3281 {
3282         struct bge_dmamap_arg *ctx = arg;
3283         int i;
3284
3285         if (error)
3286                 return;
3287
3288         if (nsegs > ctx->bge_maxsegs) {
3289                 ctx->bge_maxsegs = 0;
3290                 return;
3291         }
3292
3293         ctx->bge_maxsegs = nsegs;
3294         for (i = 0; i < nsegs; ++i)
3295                 ctx->bge_segs[i] = segs[i];
3296 }
3297
3298 static void
3299 bge_dma_free(struct bge_softc *sc)
3300 {
3301         int i;
3302
3303         /* Destroy RX/TX mbuf DMA stuffs. */
3304         if (sc->bge_cdata.bge_mtag != NULL) {
3305                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3306                         if (sc->bge_cdata.bge_rx_std_dmamap[i]) {
3307                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3308                                     sc->bge_cdata.bge_rx_std_dmamap[i]);
3309                         }
3310                 }
3311
3312                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3313                         if (sc->bge_cdata.bge_tx_dmamap[i]) {
3314                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3315                                     sc->bge_cdata.bge_tx_dmamap[i]);
3316                         }
3317                 }
3318                 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3319         }
3320
3321         /* Destroy standard RX ring */
3322         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3323                            sc->bge_cdata.bge_rx_std_ring_map,
3324                            sc->bge_ldata.bge_rx_std_ring);
3325
3326         if (BGE_IS_JUMBO_CAPABLE(sc))
3327                 bge_free_jumbo_mem(sc);
3328
3329         /* Destroy RX return ring */
3330         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3331                            sc->bge_cdata.bge_rx_return_ring_map,
3332                            sc->bge_ldata.bge_rx_return_ring);
3333
3334         /* Destroy TX ring */
3335         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3336                            sc->bge_cdata.bge_tx_ring_map,
3337                            sc->bge_ldata.bge_tx_ring);
3338
3339         /* Destroy status block */
3340         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3341                            sc->bge_cdata.bge_status_map,
3342                            sc->bge_ldata.bge_status_block);
3343
3344         /* Destroy statistics block */
3345         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3346                            sc->bge_cdata.bge_stats_map,
3347                            sc->bge_ldata.bge_stats);
3348
3349         /* Destroy the parent tag */
3350         if (sc->bge_cdata.bge_parent_tag != NULL)
3351                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3352 }
3353
3354 static int
3355 bge_dma_alloc(struct bge_softc *sc)
3356 {
3357         struct ifnet *ifp = &sc->arpcom.ac_if;
3358         int nseg, i, error;
3359
3360         /*
3361          * Allocate the parent bus DMA tag appropriate for PCI.
3362          */
3363         error = bus_dma_tag_create(NULL, 1, 0,
3364                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3365                                    NULL, NULL,
3366                                    MAXBSIZE, BGE_NSEG_NEW,
3367                                    BUS_SPACE_MAXSIZE_32BIT,
3368                                    0, &sc->bge_cdata.bge_parent_tag);
3369         if (error) {
3370                 if_printf(ifp, "could not allocate parent dma tag\n");
3371                 return error;
3372         }
3373
3374         /*
3375          * Create DMA tag for mbufs.
3376          */
3377         nseg = BGE_NSEG_NEW;
3378         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3379                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3380                                    NULL, NULL,
3381                                    MCLBYTES * nseg, nseg, MCLBYTES,
3382                                    BUS_DMA_ALLOCNOW, &sc->bge_cdata.bge_mtag);
3383         if (error) {
3384                 if_printf(ifp, "could not allocate mbuf dma tag\n");
3385                 return error;
3386         }
3387
3388         /*
3389          * Create DMA maps for TX/RX mbufs.
3390          */
3391         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3392                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3393                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3394                 if (error) {
3395                         int j;
3396
3397                         for (j = 0; j < i; ++j) {
3398                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3399                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3400                         }
3401                         bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3402                         sc->bge_cdata.bge_mtag = NULL;
3403
3404                         if_printf(ifp, "could not create DMA map for RX\n");
3405                         return error;
3406                 }
3407         }
3408
3409         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3410                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3411                                           &sc->bge_cdata.bge_tx_dmamap[i]);
3412                 if (error) {
3413                         int j;
3414
3415                         for (j = 0; j < BGE_STD_RX_RING_CNT; ++j) {
3416                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3417                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3418                         }
3419                         for (j = 0; j < i; ++j) {
3420                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3421                                         sc->bge_cdata.bge_tx_dmamap[j]);
3422                         }
3423                         bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3424                         sc->bge_cdata.bge_mtag = NULL;
3425
3426                         if_printf(ifp, "could not create DMA map for TX\n");
3427                         return error;
3428                 }
3429         }
3430
3431         /*
3432          * Create DMA stuffs for standard RX ring.
3433          */
3434         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3435                                     &sc->bge_cdata.bge_rx_std_ring_tag,
3436                                     &sc->bge_cdata.bge_rx_std_ring_map,
3437                                     (void **)&sc->bge_ldata.bge_rx_std_ring,
3438                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
3439         if (error) {
3440                 if_printf(ifp, "could not create std RX ring\n");
3441                 return error;
3442         }
3443
3444         /*
3445          * Create jumbo buffer pool.
3446          */
3447         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3448                 error = bge_alloc_jumbo_mem(sc);
3449                 if (error) {
3450                         if_printf(ifp, "could not create jumbo buffer pool\n");
3451                         return error;
3452                 }
3453         }
3454
3455         /*
3456          * Create DMA stuffs for RX return ring.
3457          */
3458         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3459                                     &sc->bge_cdata.bge_rx_return_ring_tag,
3460                                     &sc->bge_cdata.bge_rx_return_ring_map,
3461                                     (void **)&sc->bge_ldata.bge_rx_return_ring,
3462                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
3463         if (error) {
3464                 if_printf(ifp, "could not create RX ret ring\n");
3465                 return error;
3466         }
3467
3468         /*
3469          * Create DMA stuffs for TX ring.
3470          */
3471         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3472                                     &sc->bge_cdata.bge_tx_ring_tag,
3473                                     &sc->bge_cdata.bge_tx_ring_map,
3474                                     (void **)&sc->bge_ldata.bge_tx_ring,
3475                                     &sc->bge_ldata.bge_tx_ring_paddr);
3476         if (error) {
3477                 if_printf(ifp, "could not create TX ring\n");
3478                 return error;
3479         }
3480
3481         /*
3482          * Create DMA stuffs for status block.
3483          */
3484         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3485                                     &sc->bge_cdata.bge_status_tag,
3486                                     &sc->bge_cdata.bge_status_map,
3487                                     (void **)&sc->bge_ldata.bge_status_block,
3488                                     &sc->bge_ldata.bge_status_block_paddr);
3489         if (error) {
3490                 if_printf(ifp, "could not create status block\n");
3491                 return error;
3492         }
3493
3494         /*
3495          * Create DMA stuffs for statistics block.
3496          */
3497         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3498                                     &sc->bge_cdata.bge_stats_tag,
3499                                     &sc->bge_cdata.bge_stats_map,
3500                                     (void **)&sc->bge_ldata.bge_stats,
3501                                     &sc->bge_ldata.bge_stats_paddr);
3502         if (error) {
3503                 if_printf(ifp, "could not create stats block\n");
3504                 return error;
3505         }
3506         return 0;
3507 }
3508
3509 static int
3510 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3511                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3512 {
3513         struct ifnet *ifp = &sc->arpcom.ac_if;
3514         struct bge_dmamap_arg ctx;
3515         bus_dma_segment_t seg;
3516         int error;
3517
3518         /*
3519          * Create DMA tag
3520          */
3521         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3522                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3523                                    NULL, NULL, size, 1, size, 0, tag);
3524         if (error) {
3525                 if_printf(ifp, "could not allocate dma tag\n");
3526                 return error;
3527         }
3528
3529         /*
3530          * Allocate DMA'able memory
3531          */
3532         error = bus_dmamem_alloc(*tag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3533                                  map);
3534         if (error) {
3535                 if_printf(ifp, "could not allocate dma memory\n");
3536                 bus_dma_tag_destroy(*tag);
3537                 *tag = NULL;
3538                 return error;
3539         }
3540
3541         /*
3542          * Load the DMA'able memory
3543          */
3544         ctx.bge_maxsegs = 1;
3545         ctx.bge_segs = &seg;
3546         error = bus_dmamap_load(*tag, *map, *addr, size, bge_dma_map_addr, &ctx,
3547                                 BUS_DMA_WAITOK);
3548         if (error) {
3549                 if_printf(ifp, "could not load dma memory\n");
3550                 bus_dmamem_free(*tag, *addr, *map);
3551                 bus_dma_tag_destroy(*tag);
3552                 *tag = NULL;
3553                 return error;
3554         }
3555         *paddr = ctx.bge_segs[0].ds_addr;
3556
3557         return 0;
3558 }
3559
3560 static void
3561 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3562 {
3563         if (tag != NULL) {
3564                 bus_dmamap_unload(tag, map);
3565                 bus_dmamem_free(tag, addr, map);
3566                 bus_dma_tag_destroy(tag);
3567         }
3568 }
3569
3570 /*
3571  * Grrr. The link status word in the status block does
3572  * not work correctly on the BCM5700 rev AX and BX chips,
3573  * according to all available information. Hence, we have
3574  * to enable MII interrupts in order to properly obtain
3575  * async link changes. Unfortunately, this also means that
3576  * we have to read the MAC status register to detect link
3577  * changes, thereby adding an additional register access to
3578  * the interrupt handler.
3579  *
3580  * XXX: perhaps link state detection procedure used for
3581  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3582  */
3583 static void
3584 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3585 {
3586         struct ifnet *ifp = &sc->arpcom.ac_if;
3587         struct mii_data *mii = device_get_softc(sc->bge_miibus);
3588
3589         mii_pollstat(mii);
3590
3591         if (!sc->bge_link &&
3592             (mii->mii_media_status & IFM_ACTIVE) &&
3593             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3594                 sc->bge_link++;
3595                 if (bootverbose)
3596                         if_printf(ifp, "link UP\n");
3597         } else if (sc->bge_link &&
3598             (!(mii->mii_media_status & IFM_ACTIVE) ||
3599             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3600                 sc->bge_link = 0;
3601                 if (bootverbose)
3602                         if_printf(ifp, "link DOWN\n");
3603         }
3604
3605         /* Clear the interrupt. */
3606         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3607         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3608         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3609 }
3610
3611 static void
3612 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3613 {
3614         struct ifnet *ifp = &sc->arpcom.ac_if;
3615
3616 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3617
3618         /*
3619          * Sometimes PCS encoding errors are detected in
3620          * TBI mode (on fiber NICs), and for some reason
3621          * the chip will signal them as link changes.
3622          * If we get a link change event, but the 'PCS
3623          * encoding error' bit in the MAC status register
3624          * is set, don't bother doing a link check.
3625          * This avoids spurious "gigabit link up" messages
3626          * that sometimes appear on fiber NICs during
3627          * periods of heavy traffic.
3628          */
3629         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3630                 if (!sc->bge_link) {
3631                         sc->bge_link++;
3632                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3633                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3634                                     BGE_MACMODE_TBI_SEND_CFGS);
3635                         }
3636                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3637
3638                         if (bootverbose)
3639                                 if_printf(ifp, "link UP\n");
3640
3641                         ifp->if_link_state = LINK_STATE_UP;
3642                         if_link_state_change(ifp);
3643                 }
3644         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3645                 if (sc->bge_link) {
3646                         sc->bge_link = 0;
3647
3648                         if (bootverbose)
3649                                 if_printf(ifp, "link DOWN\n");
3650
3651                         ifp->if_link_state = LINK_STATE_DOWN;
3652                         if_link_state_change(ifp);
3653                 }
3654         }
3655
3656 #undef PCS_ENCODE_ERR
3657
3658         /* Clear the attention. */
3659         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3660             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3661             BGE_MACSTAT_LINK_CHANGED);
3662 }
3663
3664 static void
3665 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3666 {
3667         /*
3668          * Check that the AUTOPOLL bit is set before
3669          * processing the event as a real link change.
3670          * Turning AUTOPOLL on and off in the MII read/write
3671          * functions will often trigger a link status
3672          * interrupt for no reason.
3673          */
3674         if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3675                 struct ifnet *ifp = &sc->arpcom.ac_if;
3676                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3677
3678                 mii_pollstat(mii);
3679
3680                 if (!sc->bge_link &&
3681                     (mii->mii_media_status & IFM_ACTIVE) &&
3682                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3683                         sc->bge_link++;
3684                         if (bootverbose)
3685                                 if_printf(ifp, "link UP\n");
3686                 } else if (sc->bge_link &&
3687                     (!(mii->mii_media_status & IFM_ACTIVE) ||
3688                     IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3689                         sc->bge_link = 0;
3690                         if (bootverbose)
3691                                 if_printf(ifp, "link DOWN\n");
3692                 }
3693         }
3694
3695         /* Clear the attention. */
3696         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3697             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3698             BGE_MACSTAT_LINK_CHANGED);
3699 }
3700
3701 static int
3702 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3703 {
3704         struct bge_softc *sc = arg1;
3705
3706         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3707                                    &sc->bge_rx_coal_ticks,
3708                                    BGE_RX_COAL_TICKS_CHG);
3709 }
3710
3711 static int
3712 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3713 {
3714         struct bge_softc *sc = arg1;
3715
3716         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3717                                    &sc->bge_tx_coal_ticks,
3718                                    BGE_TX_COAL_TICKS_CHG);
3719 }
3720
3721 static int
3722 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3723 {
3724         struct bge_softc *sc = arg1;
3725
3726         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3727                                    &sc->bge_rx_max_coal_bds,
3728                                    BGE_RX_MAX_COAL_BDS_CHG);
3729 }
3730
3731 static int
3732 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3733 {
3734         struct bge_softc *sc = arg1;
3735
3736         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3737                                    &sc->bge_tx_max_coal_bds,
3738                                    BGE_TX_MAX_COAL_BDS_CHG);
3739 }
3740
3741 static int
3742 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3743                     uint32_t coal_chg_mask)
3744 {
3745         struct bge_softc *sc = arg1;
3746         struct ifnet *ifp = &sc->arpcom.ac_if;
3747         int error = 0, v;
3748
3749         lwkt_serialize_enter(ifp->if_serializer);
3750
3751         v = *coal;
3752         error = sysctl_handle_int(oidp, &v, 0, req);
3753         if (!error && req->newptr != NULL) {
3754                 if (v < 0) {
3755                         error = EINVAL;
3756                 } else {
3757                         *coal = v;
3758                         sc->bge_coal_chg |= coal_chg_mask;
3759                 }
3760         }
3761
3762         lwkt_serialize_exit(ifp->if_serializer);
3763         return error;
3764 }
3765
3766 static void
3767 bge_coal_change(struct bge_softc *sc)
3768 {
3769         struct ifnet *ifp = &sc->arpcom.ac_if;
3770         uint32_t val;
3771
3772         ASSERT_SERIALIZED(ifp->if_serializer);
3773
3774         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
3775                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3776                             sc->bge_rx_coal_ticks);
3777                 DELAY(10);
3778                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3779
3780                 if (bootverbose) {
3781                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3782                                   sc->bge_rx_coal_ticks);
3783                 }
3784         }
3785
3786         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
3787                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3788                             sc->bge_tx_coal_ticks);
3789                 DELAY(10);
3790                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3791
3792                 if (bootverbose) {
3793                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3794                                   sc->bge_tx_coal_ticks);
3795                 }
3796         }
3797
3798         if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
3799                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3800                             sc->bge_rx_max_coal_bds);
3801                 DELAY(10);
3802                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3803
3804                 if (bootverbose) {
3805                         if_printf(ifp, "rx_max_coal_bds -> %u\n",
3806                                   sc->bge_rx_max_coal_bds);
3807                 }
3808         }
3809
3810         if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
3811                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3812                             sc->bge_tx_max_coal_bds);
3813                 DELAY(10);
3814                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3815
3816                 if (bootverbose) {
3817                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
3818                                   sc->bge_tx_max_coal_bds);
3819                 }
3820         }
3821
3822         sc->bge_coal_chg = 0;
3823 }
3824
3825 static void
3826 bge_enable_intr(struct bge_softc *sc)
3827 {
3828         struct ifnet *ifp = &sc->arpcom.ac_if;
3829
3830         lwkt_serialize_handler_enable(ifp->if_serializer);
3831
3832         /*
3833          * Enable interrupt.
3834          */
3835         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
3836
3837         /*
3838          * Unmask the interrupt when we stop polling.
3839          */
3840         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3841
3842         /*
3843          * Trigger another interrupt, since above writing
3844          * to interrupt mailbox0 may acknowledge pending
3845          * interrupt.
3846          */
3847         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3848 }
3849
3850 static void
3851 bge_disable_intr(struct bge_softc *sc)
3852 {
3853         struct ifnet *ifp = &sc->arpcom.ac_if;
3854
3855         /*
3856          * Mask the interrupt when we start polling.
3857          */
3858         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3859
3860         /*
3861          * Acknowledge possible asserted interrupt.
3862          */
3863         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3864
3865         lwkt_serialize_handler_disable(ifp->if_serializer);
3866 }