sys/dev/netif/bwi/bwirf.c

   1 /*
   2  * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
   3  *
   4  * This code is derived from software contributed to The DragonFly Project
   5  * by Sepherosa Ziehau <sepherosa@gmail.com>
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in
  15  *    the documentation and/or other materials provided with the
  16  *    distribution.
  17  * 3. Neither the name of The DragonFly Project nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific, prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  24  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  25  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  27  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  29  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  31  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  */
  34
  35 #include <sys/param.h>
  36 #include <sys/bitops.h>
  37 #include <sys/endian.h>
  38 #include <sys/kernel.h>
  39 #include <sys/bus.h>
  40 #include <sys/malloc.h>
  41 #include <sys/proc.h>
  42 #include <sys/rman.h>
  43 #include <sys/serialize.h>
  44 #include <sys/socket.h>
  45 #include <sys/sysctl.h>
  46
  47 #include <net/ethernet.h>
  48 #include <net/if.h>
  49 #include <net/bpf.h>
  50 #include <net/if_arp.h>
  51 #include <net/if_dl.h>
  52 #include <net/if_media.h>
  53 #include <net/ifq_var.h>
  54
  55 #include <netproto/802_11/ieee80211_radiotap.h>
  56 #include <netproto/802_11/ieee80211_var.h>
  57 #include <netproto/802_11/wlan_ratectl/onoe/ieee80211_onoe_param.h>
  58
  59 #include <bus/pci/pcireg.h>
  60 #include <bus/pci/pcivar.h>
  61 #include <bus/pci/pcidevs.h>
  62
  63 #include <dev/netif/bwi/if_bwireg.h>
  64 #include <dev/netif/bwi/if_bwivar.h>
  65 #include <dev/netif/bwi/bwiphy.h>
  66 #include <dev/netif/bwi/bwirf.h>
  67 #include <dev/netif/bwi/bwimac.h>
  68
  69 #define RF_LO_WRITE(mac, lo)    bwi_rf_lo_write((mac), (lo))
  70
  71 #define BWI_RF_2GHZ_CHAN(chan)                  \
  72         (ieee80211_ieee2mhz((chan), IEEE80211_CHAN_2GHZ) - 2400)
  73
  74 #define BWI_DEFAULT_IDLE_TSSI   52
  75
  76 struct rf_saveregs {
  77         uint16_t        phy_01;
  78         uint16_t        phy_03;
  79         uint16_t        phy_0a;
  80         uint16_t        phy_15;
  81         uint16_t        phy_2a;
  82         uint16_t        phy_30;
  83         uint16_t        phy_35;
  84         uint16_t        phy_60;
  85         uint16_t        phy_429;
  86         uint16_t        phy_802;
  87         uint16_t        phy_811;
  88         uint16_t        phy_812;
  89         uint16_t        phy_814;
  90         uint16_t        phy_815;
  91
  92         uint16_t        rf_43;
  93         uint16_t        rf_52;
  94         uint16_t        rf_7a;
  95 };
  96
  97 #define SAVE_RF_REG(mac, regs, n)       (regs)->rf_##n = RF_READ((mac), 0x##n)
  98 #define RESTORE_RF_REG(mac, regs, n)    RF_WRITE((mac), 0x##n, (regs)->rf_##n)
  99
 100 #define SAVE_PHY_REG(mac, regs, n)      (regs)->phy_##n = PHY_READ((mac), 0x##n)
 101 #define RESTORE_PHY_REG(mac, regs, n)   PHY_WRITE((mac), 0x##n, (regs)->phy_##n)
 102
 103 static int      bwi_rf_calc_txpower(int8_t *, uint8_t, const int16_t[]);
 104 static void     bwi_rf_workaround(struct bwi_mac *, u_int);
 105 static int      bwi_rf_gain_max_reached(struct bwi_mac *, int);
 106 static uint16_t bwi_rf_calibval(struct bwi_mac *);
 107 static uint16_t bwi_rf_get_tp_ctrl2(struct bwi_mac *);
 108
 109 static void     bwi_rf_lo_update_11b(struct bwi_mac *);
 110 static uint16_t bwi_rf_lo_measure_11b(struct bwi_mac *);
 111
 112 static void     bwi_rf_lo_update_11g(struct bwi_mac *);
 113 static uint32_t bwi_rf_lo_devi_measure(struct bwi_mac *, uint16_t);
 114 static void     bwi_rf_lo_measure_11g(struct bwi_mac *,
 115                         const struct bwi_rf_lo *, struct bwi_rf_lo *, uint8_t);
 116 static uint8_t  _bwi_rf_lo_update_11g(struct bwi_mac *, uint16_t);
 117 static void     bwi_rf_lo_write(struct bwi_mac *, const struct bwi_rf_lo *);
 118
 119 static void     bwi_rf_set_nrssi_ofs_11g(struct bwi_mac *);
 120 static void     bwi_rf_calc_nrssi_slope_11b(struct bwi_mac *);
 121 static void     bwi_rf_calc_nrssi_slope_11g(struct bwi_mac *);
 122 static void     bwi_rf_set_nrssi_thr_11b(struct bwi_mac *);
 123 static void     bwi_rf_set_nrssi_thr_11g(struct bwi_mac *);
 124
 125 static void     bwi_rf_init_sw_nrssi_table(struct bwi_mac *);
 126
 127 static int      bwi_rf_calc_rssi_bcm2050(struct bwi_mac *,
 128                         const struct bwi_rxbuf_hdr *);
 129 static int      bwi_rf_calc_rssi_bcm2053(struct bwi_mac *,
 130                         const struct bwi_rxbuf_hdr *);
 131 static int      bwi_rf_calc_rssi_bcm2060(struct bwi_mac *,
 132                         const struct bwi_rxbuf_hdr *);
 133
 134 static void     bwi_rf_on_11a(struct bwi_mac *);
 135 static void     bwi_rf_on_11bg(struct bwi_mac *);
 136
 137 static void     bwi_rf_off_11a(struct bwi_mac *);
 138 static void     bwi_rf_off_11bg(struct bwi_mac *);
 139 static void     bwi_rf_off_11g_rev5(struct bwi_mac *);
 140
 141 static const int8_t     bwi_txpower_map_11b[BWI_TSSI_MAX] =
 142         { BWI_TXPOWER_MAP_11B };
 143 static const int8_t     bwi_txpower_map_11g[BWI_TSSI_MAX] =
 144         { BWI_TXPOWER_MAP_11G };
 145
 146 static __inline int16_t
 147 bwi_nrssi_11g(struct bwi_mac *mac)
 148 {
 149         int16_t val;
 150
 151 #define NRSSI_11G_MASK          __BITS(13, 8)
 152
 153         val = (int16_t)__SHIFTOUT(PHY_READ(mac, 0x47f), NRSSI_11G_MASK);
 154         if (val >= 32)
 155                 val -= 64;
 156         return val;
 157
 158 #undef NRSSI_11G_MASK
 159 }
 160
 161 static __inline struct bwi_rf_lo *
 162 bwi_get_rf_lo(struct bwi_mac *mac, uint16_t rf_atten, uint16_t bbp_atten)
 163 {
 164         int n;
 165
 166         n = rf_atten + (14 * (bbp_atten / 2));
 167         KKASSERT(n < BWI_RFLO_MAX);
 168
 169         return &mac->mac_rf.rf_lo[n];
 170 }
 171
 172 static __inline int
 173 bwi_rf_lo_isused(struct bwi_mac *mac, const struct bwi_rf_lo *lo)
 174 {
 175         struct bwi_rf *rf = &mac->mac_rf;
 176         int idx;
 177
 178         idx = lo - rf->rf_lo;
 179         KKASSERT(idx >= 0 && idx < BWI_RFLO_MAX);
 180
 181         return isset(rf->rf_lo_used, idx);
 182 }
 183
 184 void
 185 bwi_rf_write(struct bwi_mac *mac, uint16_t ctrl, uint16_t data)
 186 {
 187         struct bwi_softc *sc = mac->mac_sc;
 188
 189         CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
 190         CSR_WRITE_2(sc, BWI_RF_DATA_LO, data);
 191 }
 192
 193 uint16_t
 194 bwi_rf_read(struct bwi_mac *mac, uint16_t ctrl)
 195 {
 196         struct bwi_rf *rf = &mac->mac_rf;
 197         struct bwi_softc *sc = mac->mac_sc;
 198
 199         ctrl |= rf->rf_ctrl_rd;
 200         if (rf->rf_ctrl_adj) {
 201                 /* XXX */
 202                 if (ctrl < 0x70)
 203                         ctrl += 0x80;
 204                 else if (ctrl < 0x80)
 205                         ctrl += 0x70;
 206         }
 207
 208         CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
 209         return CSR_READ_2(sc, BWI_RF_DATA_LO);
 210 }
 211
 212 int
 213 bwi_rf_attach(struct bwi_mac *mac)
 214 {
 215         struct bwi_softc *sc = mac->mac_sc;
 216         struct bwi_phy *phy = &mac->mac_phy;
 217         struct bwi_rf *rf = &mac->mac_rf;
 218         uint16_t type, manu;
 219         uint8_t rev;
 220
 221         /*
 222          * Get RF manufacture/type/revision
 223          */
 224         if (sc->sc_bbp_id == BWI_BBPID_BCM4317) {
 225                 /*
 226                  * Fake a BCM2050 RF
 227                  */
 228                 manu = BWI_RF_MANUFACT_BCM;
 229                 type = BWI_RF_T_BCM2050;
 230                 if (sc->sc_bbp_rev == 0)
 231                         rev = 3;
 232                 else if (sc->sc_bbp_rev == 1)
 233                         rev = 4;
 234                 else
 235                         rev = 5;
 236         } else {
 237                 uint32_t val;
 238
 239                 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
 240                 val = CSR_READ_2(sc, BWI_RF_DATA_HI);
 241                 val <<= 16;
 242
 243                 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
 244                 val |= CSR_READ_2(sc, BWI_RF_DATA_LO);
 245
 246                 manu = __SHIFTOUT(val, BWI_RFINFO_MANUFACT_MASK);
 247                 type = __SHIFTOUT(val, BWI_RFINFO_TYPE_MASK);
 248                 rev = __SHIFTOUT(val, BWI_RFINFO_REV_MASK);
 249         }
 250         device_printf(sc->sc_dev, "RF: manu 0x%03x, type 0x%04x, rev %u\n",
 251                       manu, type, rev);
 252
 253         /*
 254          * Verify whether the RF is supported
 255          */
 256         rf->rf_ctrl_rd = 0;
 257         rf->rf_ctrl_adj = 0;
 258         switch (phy->phy_mode) {
 259         case IEEE80211_MODE_11A:
 260                 if (manu != BWI_RF_MANUFACT_BCM ||
 261                     type != BWI_RF_T_BCM2060 ||
 262                     rev != 1) {
 263                         device_printf(sc->sc_dev, "only BCM2060 rev 1 RF "
 264                                       "is supported for 11A PHY\n");
 265                         return ENXIO;
 266                 }
 267                 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11A;
 268                 rf->rf_on = bwi_rf_on_11a;
 269                 rf->rf_off = bwi_rf_off_11a;
 270                 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2060;
 271                 break;
 272         case IEEE80211_MODE_11B:
 273                 if (type == BWI_RF_T_BCM2050) {
 274                         rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11BG;
 275                         rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2050;
 276                 } else if (type == BWI_RF_T_BCM2053) {
 277                         rf->rf_ctrl_adj = 1;
 278                         rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2053;
 279                 } else {
 280                         device_printf(sc->sc_dev, "only BCM2050/BCM2053 RF "
 281                                       "is supported for 11B PHY\n");
 282                         return ENXIO;
 283                 }
 284                 rf->rf_on = bwi_rf_on_11bg;
 285                 rf->rf_off = bwi_rf_off_11bg;
 286                 rf->rf_calc_nrssi_slope = bwi_rf_calc_nrssi_slope_11b;
 287                 rf->rf_set_nrssi_thr = bwi_rf_set_nrssi_thr_11b;
 288                 if (phy->phy_rev == 6)
 289                         rf->rf_lo_update = bwi_rf_lo_update_11g;
 290                 else
 291                         rf->rf_lo_update = bwi_rf_lo_update_11b;
 292                 break;
 293         case IEEE80211_MODE_11G:
 294                 if (type != BWI_RF_T_BCM2050) {
 295                         device_printf(sc->sc_dev, "only BCM2050 RF "
 296                                       "is supported for 11G PHY\n");
 297                         return ENXIO;
 298                 }
 299                 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11BG;
 300                 rf->rf_on = bwi_rf_on_11bg;
 301                 if (mac->mac_rev >= 5)
 302                         rf->rf_off = bwi_rf_off_11g_rev5;
 303                 else
 304                         rf->rf_off = bwi_rf_off_11bg;
 305                 rf->rf_calc_nrssi_slope = bwi_rf_calc_nrssi_slope_11g;
 306                 rf->rf_set_nrssi_thr = bwi_rf_set_nrssi_thr_11g;
 307                 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2050;
 308                 rf->rf_lo_update = bwi_rf_lo_update_11g;
 309                 break;
 310         default:
 311                 device_printf(sc->sc_dev, "unsupported PHY mode\n");
 312                 return ENXIO;
 313         }
 314
 315         rf->rf_type = type;
 316         rf->rf_rev = rev;
 317         rf->rf_manu = manu;
 318         rf->rf_curchan = IEEE80211_CHAN_ANY;
 319         rf->rf_ant_mode = BWI_ANT_MODE_AUTO;
 320         return 0;
 321 }
 322
 323 void
 324 bwi_rf_set_chan(struct bwi_mac *mac, u_int chan, int work_around)
 325 {
 326         struct bwi_softc *sc = mac->mac_sc;
 327
 328         if (chan == IEEE80211_CHAN_ANY)
 329                 return;
 330
 331         MOBJ_WRITE_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_CHAN, chan);
 332
 333         /* TODO: 11A */
 334
 335         if (work_around)
 336                 bwi_rf_workaround(mac, chan);
 337
 338         CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
 339
 340         if (chan == 14) {
 341                 if (sc->sc_locale == BWI_SPROM_LOCALE_JAPAN)
 342                         HFLAGS_CLRBITS(mac, BWI_HFLAG_NOT_JAPAN);
 343                 else
 344                         HFLAGS_SETBITS(mac, BWI_HFLAG_NOT_JAPAN);
 345                 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, (1 << 11)); /* XXX */
 346         } else {
 347                 CSR_CLRBITS_2(sc, BWI_RF_CHAN_EX, 0x840); /* XXX */
 348         }
 349         DELAY(8000);    /* DELAY(2000); */
 350
 351         mac->mac_rf.rf_curchan = chan;
 352 }
 353
 354 void
 355 bwi_rf_get_gains(struct bwi_mac *mac)
 356 {
 357 #define SAVE_PHY_MAX    15
 358 #define SAVE_RF_MAX     3
 359
 360         static const uint16_t save_rf_regs[SAVE_RF_MAX] =
 361         { 0x52, 0x43, 0x7a };
 362         static const uint16_t save_phy_regs[SAVE_PHY_MAX] = {
 363                 0x0429, 0x0001, 0x0811, 0x0812,
 364                 0x0814, 0x0815, 0x005a, 0x0059,
 365                 0x0058, 0x000a, 0x0003, 0x080f,
 366                 0x0810, 0x002b, 0x0015
 367         };
 368
 369         struct bwi_phy *phy = &mac->mac_phy;
 370         struct bwi_rf *rf = &mac->mac_rf;
 371         uint16_t save_phy[SAVE_PHY_MAX];
 372         uint16_t save_rf[SAVE_RF_MAX];
 373         uint16_t trsw;
 374         int i, j, loop1_max, loop1, loop2;
 375
 376         /*
 377          * Save PHY/RF registers for later restoration
 378          */
 379         for (i = 0; i < SAVE_PHY_MAX; ++i)
 380                 save_phy[i] = PHY_READ(mac, save_phy_regs[i]);
 381         PHY_READ(mac, 0x2d); /* dummy read */
 382
 383         for (i = 0; i < SAVE_RF_MAX; ++i)
 384                 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
 385
 386         PHY_CLRBITS(mac, 0x429, 0xc000);
 387         PHY_SETBITS(mac, 0x1, 0x8000);
 388
 389         PHY_SETBITS(mac, 0x811, 0x2);
 390         PHY_CLRBITS(mac, 0x812, 0x2);
 391         PHY_SETBITS(mac, 0x811, 0x1);
 392         PHY_CLRBITS(mac, 0x812, 0x1);
 393
 394         PHY_SETBITS(mac, 0x814, 0x1);
 395         PHY_CLRBITS(mac, 0x815, 0x1);
 396         PHY_SETBITS(mac, 0x814, 0x2);
 397         PHY_CLRBITS(mac, 0x815, 0x2);
 398
 399         PHY_SETBITS(mac, 0x811, 0xc);
 400         PHY_SETBITS(mac, 0x812, 0xc);
 401         PHY_SETBITS(mac, 0x811, 0x30);
 402         PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x10);
 403
 404         PHY_WRITE(mac, 0x5a, 0x780);
 405         PHY_WRITE(mac, 0x59, 0xc810);
 406         PHY_WRITE(mac, 0x58, 0xd);
 407         PHY_SETBITS(mac, 0xa, 0x2000);
 408
 409         PHY_SETBITS(mac, 0x814, 0x4);
 410         PHY_CLRBITS(mac, 0x815, 0x4);
 411
 412         PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40);
 413
 414         if (rf->rf_rev == 8) {
 415                 loop1_max = 15;
 416                 RF_WRITE(mac, 0x43, loop1_max);
 417         } else {
 418                 loop1_max = 9;
 419                 RF_WRITE(mac, 0x52, 0x0);
 420                 RF_FILT_SETBITS(mac, 0x43, 0xfff0, loop1_max);
 421         }
 422
 423         bwi_phy_set_bbp_atten(mac, 11);
 424
 425         if (phy->phy_rev >= 3)
 426                 PHY_WRITE(mac, 0x80f, 0xc020);
 427         else
 428                 PHY_WRITE(mac, 0x80f, 0x8020);
 429         PHY_WRITE(mac, 0x810, 0);
 430
 431         PHY_FILT_SETBITS(mac, 0x2b, 0xffc0, 0x1);
 432         PHY_FILT_SETBITS(mac, 0x2b, 0xc0ff, 0x800);
 433         PHY_SETBITS(mac, 0x811, 0x100);
 434         PHY_CLRBITS(mac, 0x812, 0x3000);
 435
 436         if ((mac->mac_sc->sc_card_flags & BWI_CARD_F_EXT_LNA) &&
 437             phy->phy_rev >= 7) {
 438                 PHY_SETBITS(mac, 0x811, 0x800);
 439                 PHY_SETBITS(mac, 0x812, 0x8000);
 440         }
 441         RF_CLRBITS(mac, 0x7a, 0xff08);
 442
 443         /*
 444          * Find out 'loop1/loop2', which will be used to calculate
 445          * max loopback gain later
 446          */
 447         j = 0;
 448         for (i = 0; i < loop1_max; ++i) {
 449                 for (j = 0; j < 16; ++j) {
 450                         RF_WRITE(mac, 0x43, i);
 451
 452                         if (bwi_rf_gain_max_reached(mac, j))
 453                                 goto loop1_exit;
 454                 }
 455         }
 456 loop1_exit:
 457         loop1 = i;
 458         loop2 = j;
 459
 460         /*
 461          * Find out 'trsw', which will be used to calculate
 462          * TRSW(TX/RX switch) RX gain later
 463          */
 464         if (loop2 >= 8) {
 465                 PHY_SETBITS(mac, 0x812, 0x30);
 466                 trsw = 0x1b;
 467                 for (i = loop2 - 8; i < 16; ++i) {
 468                         trsw -= 3;
 469                         if (bwi_rf_gain_max_reached(mac, i))
 470                                 break;
 471                 }
 472         } else {
 473                 trsw = 0x18;
 474         }
 475
 476         /*
 477          * Restore saved PHY/RF registers
 478          */
 479         /* First 4 saved PHY registers need special processing */
 480         for (i = 4; i < SAVE_PHY_MAX; ++i)
 481                 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]);
 482
 483         bwi_phy_set_bbp_atten(mac, mac->mac_tpctl.bbp_atten);
 484
 485         for (i = 0; i < SAVE_RF_MAX; ++i)
 486                 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
 487
 488         PHY_WRITE(mac, save_phy_regs[2], save_phy[2] | 0x3);
 489         DELAY(10);
 490         PHY_WRITE(mac, save_phy_regs[2], save_phy[2]);
 491         PHY_WRITE(mac, save_phy_regs[3], save_phy[3]);
 492         PHY_WRITE(mac, save_phy_regs[0], save_phy[0]);
 493         PHY_WRITE(mac, save_phy_regs[1], save_phy[1]);
 494
 495         /*
 496          * Calculate gains
 497          */
 498         rf->rf_lo_gain = (loop2 * 6) - (loop1 * 4) - 11;
 499         rf->rf_rx_gain = trsw * 2;
 500         DPRINTF(mac->mac_sc, BWI_DBG_RF | BWI_DBG_INIT,
 501                 "lo gain: %u, rx gain: %u\n",
 502                 rf->rf_lo_gain, rf->rf_rx_gain);
 503
 504 #undef SAVE_RF_MAX
 505 #undef SAVE_PHY_MAX
 506 }
 507
 508 void
 509 bwi_rf_init(struct bwi_mac *mac)
 510 {
 511         struct bwi_rf *rf = &mac->mac_rf;
 512
 513         if (rf->rf_type == BWI_RF_T_BCM2060) {
 514                 /* TODO: 11A */
 515         } else {
 516                 if (rf->rf_flags & BWI_RF_F_INITED)
 517                         RF_WRITE(mac, 0x78, rf->rf_calib);
 518                 else
 519                         bwi_rf_init_bcm2050(mac);
 520         }
 521 }
 522
 523 static void
 524 bwi_rf_off_11a(struct bwi_mac *mac)
 525 {
 526         RF_WRITE(mac, 0x4, 0xff);
 527         RF_WRITE(mac, 0x5, 0xfb);
 528
 529         PHY_SETBITS(mac, 0x10, 0x8);
 530         PHY_SETBITS(mac, 0x11, 0x8);
 531
 532         PHY_WRITE(mac, 0x15, 0xaa00);
 533 }
 534
 535 static void
 536 bwi_rf_off_11bg(struct bwi_mac *mac)
 537 {
 538         PHY_WRITE(mac, 0x15, 0xaa00);
 539 }
 540
 541 static void
 542 bwi_rf_off_11g_rev5(struct bwi_mac *mac)
 543 {
 544         PHY_SETBITS(mac, 0x811, 0x8c);
 545         PHY_CLRBITS(mac, 0x812, 0x8c);
 546 }
 547
 548 static void
 549 bwi_rf_workaround(struct bwi_mac *mac, u_int chan)
 550 {
 551         struct bwi_softc *sc = mac->mac_sc;
 552         struct bwi_rf *rf = &mac->mac_rf;
 553
 554         if (chan == IEEE80211_CHAN_ANY) {
 555                 if_printf(&mac->mac_sc->sc_ic.ic_if,
 556                           "%s invalid channel!!\n", __func__);
 557                 return;
 558         }
 559
 560         if (rf->rf_type != BWI_RF_T_BCM2050 || rf->rf_rev >= 6)
 561                 return;
 562
 563         if (chan <= 10)
 564                 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan + 4));
 565         else
 566                 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(1));
 567         DELAY(1000);
 568         CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
 569 }
 570
 571 static __inline struct bwi_rf_lo *
 572 bwi_rf_lo_find(struct bwi_mac *mac, const struct bwi_tpctl *tpctl)
 573 {
 574         uint16_t rf_atten, bbp_atten;
 575         int remap_rf_atten;
 576
 577         remap_rf_atten = 1;
 578         if (tpctl == NULL) {
 579                 bbp_atten = 2;
 580                 rf_atten = 3;
 581         } else {
 582                 if (tpctl->tp_ctrl1 == 3)
 583                         remap_rf_atten = 0;
 584
 585                 bbp_atten = tpctl->bbp_atten;
 586                 rf_atten = tpctl->rf_atten;
 587
 588                 if (bbp_atten > 6)
 589                         bbp_atten = 6;
 590         }
 591
 592         if (remap_rf_atten) {
 593 #define MAP_MAX 10
 594                 static const uint16_t map[MAP_MAX] =
 595                 { 11, 10, 11, 12, 13, 12, 13, 12, 13, 12 };
 596
 597 #if 0
 598                 KKASSERT(rf_atten < MAP_MAX);
 599                 rf_atten = map[rf_atten];
 600 #else
 601                 if (rf_atten >= MAP_MAX) {
 602                         rf_atten = 0;   /* XXX */
 603                 } else {
 604                         rf_atten = map[rf_atten];
 605                 }
 606 #endif
 607 #undef MAP_MAX
 608         }
 609
 610         return bwi_get_rf_lo(mac, rf_atten, bbp_atten);
 611 }
 612
 613 void
 614 bwi_rf_lo_adjust(struct bwi_mac *mac, const struct bwi_tpctl *tpctl)
 615 {
 616         const struct bwi_rf_lo *lo;
 617
 618         lo = bwi_rf_lo_find(mac, tpctl);
 619         RF_LO_WRITE(mac, lo);
 620 }
 621
 622 static void
 623 bwi_rf_lo_write(struct bwi_mac *mac, const struct bwi_rf_lo *lo)
 624 {
 625         uint16_t val;
 626
 627         val = (uint8_t)lo->ctrl_lo;
 628         val |= ((uint8_t)lo->ctrl_hi) << 8;
 629
 630         PHY_WRITE(mac, BWI_PHYR_RF_LO, val);
 631 }
 632
 633 static int
 634 bwi_rf_gain_max_reached(struct bwi_mac *mac, int idx)
 635 {
 636         PHY_FILT_SETBITS(mac, 0x812, 0xf0ff, idx << 8);
 637         PHY_FILT_SETBITS(mac, 0x15, 0xfff, 0xa000);
 638         PHY_SETBITS(mac, 0x15, 0xf000);
 639
 640         DELAY(20);
 641
 642         return (PHY_READ(mac, 0x2d) >= 0xdfc);
 643 }
 644
 645 /* XXX use bitmap array */
 646 static __inline uint16_t
 647 bitswap4(uint16_t val)
 648 {
 649         uint16_t ret;
 650
 651         ret = (val & 0x8) >> 3;
 652         ret |= (val & 0x4) >> 1;
 653         ret |= (val & 0x2) << 1;
 654         ret |= (val & 0x1) << 3;
 655         return ret;
 656 }
 657
 658 static __inline uint16_t
 659 bwi_phy812_value(struct bwi_mac *mac, uint16_t lpd)
 660 {
 661         struct bwi_softc *sc = mac->mac_sc;
 662         struct bwi_phy *phy = &mac->mac_phy;
 663         struct bwi_rf *rf = &mac->mac_rf;
 664         uint16_t lo_gain, ext_lna, loop;
 665
 666         if ((phy->phy_flags & BWI_PHY_F_LINKED) == 0)
 667                 return 0;
 668
 669         lo_gain = rf->rf_lo_gain;
 670         if (rf->rf_rev == 8)
 671                 lo_gain += 0x3e;
 672         else
 673                 lo_gain += 0x26;
 674
 675         if (lo_gain >= 0x46) {
 676                 lo_gain -= 0x46;
 677                 ext_lna = 0x3000;
 678         } else if (lo_gain >= 0x3a) {
 679                 lo_gain -= 0x3a;
 680                 ext_lna = 0x1000;
 681         } else if (lo_gain >= 0x2e) {
 682                 lo_gain -= 0x2e;
 683                 ext_lna = 0x2000;
 684         } else {
 685                 lo_gain -= 0x10;
 686                 ext_lna = 0;
 687         }
 688
 689         for (loop = 0; loop < 16; ++loop) {
 690                 lo_gain -= (6 * loop);
 691                 if (lo_gain < 6)
 692                         break;
 693         }
 694
 695         if (phy->phy_rev >= 7 && (sc->sc_card_flags & BWI_CARD_F_EXT_LNA)) {
 696                 if (ext_lna)
 697                         ext_lna |= 0x8000;
 698                 ext_lna |= (loop << 8);
 699                 switch (lpd) {
 700                 case 0x011:
 701                         return 0x8f92;
 702                 case 0x001:
 703                         return (0x8092 | ext_lna);
 704                 case 0x101:
 705                         return (0x2092 | ext_lna);
 706                 case 0x100:
 707                         return (0x2093 | ext_lna);
 708                 default:
 709                         panic("unsupported lpd\n");
 710                 }
 711         } else {
 712                 ext_lna |= (loop << 8);
 713                 switch (lpd) {
 714                 case 0x011:
 715                         return 0xf92;
 716                 case 0x001:
 717                 case 0x101:
 718                         return (0x92 | ext_lna);
 719                 case 0x100:
 720                         return (0x93 | ext_lna);
 721                 default:
 722                         panic("unsupported lpd\n");
 723                 }
 724         }
 725
 726         panic("never reached\n");
 727         return 0;
 728 }
 729
 730 void
 731 bwi_rf_init_bcm2050(struct bwi_mac *mac)
 732 {
 733 #define SAVE_RF_MAX             3
 734 #define SAVE_PHY_COMM_MAX       4
 735 #define SAVE_PHY_11G_MAX        6
 736
 737         static const uint16_t save_rf_regs[SAVE_RF_MAX] =
 738         { 0x0043, 0x0051, 0x0052 };
 739         static const uint16_t save_phy_regs_comm[SAVE_PHY_COMM_MAX] =
 740         { 0x0015, 0x005a, 0x0059, 0x0058 };
 741         static const uint16_t save_phy_regs_11g[SAVE_PHY_11G_MAX] =
 742         { 0x0811, 0x0812, 0x0814, 0x0815, 0x0429, 0x0802 };
 743
 744         uint16_t save_rf[SAVE_RF_MAX];
 745         uint16_t save_phy_comm[SAVE_PHY_COMM_MAX];
 746         uint16_t save_phy_11g[SAVE_PHY_11G_MAX];
 747         uint16_t phyr_35, phyr_30 = 0, rfr_78, phyr_80f = 0, phyr_810 = 0;
 748         uint16_t bphy_ctrl = 0, bbp_atten, rf_chan_ex;
 749         uint16_t phy812_val;
 750         uint16_t calib;
 751         uint32_t test_lim, test;
 752         struct bwi_softc *sc = mac->mac_sc;
 753         struct bwi_phy *phy = &mac->mac_phy;
 754         struct bwi_rf *rf = &mac->mac_rf;
 755         int i;
 756
 757         /*
 758          * Save registers for later restoring
 759          */
 760         for (i = 0; i < SAVE_RF_MAX; ++i)
 761                 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
 762         for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
 763                 save_phy_comm[i] = PHY_READ(mac, save_phy_regs_comm[i]);
 764
 765         if (phy->phy_mode == IEEE80211_MODE_11B) {
 766                 phyr_30 = PHY_READ(mac, 0x30);
 767                 bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL);
 768
 769                 PHY_WRITE(mac, 0x30, 0xff);
 770                 CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x3f3f);
 771         } else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
 772                 for (i = 0; i < SAVE_PHY_11G_MAX; ++i) {
 773                         save_phy_11g[i] =
 774                                 PHY_READ(mac, save_phy_regs_11g[i]);
 775                 }
 776
 777                 PHY_SETBITS(mac, 0x814, 0x3);
 778                 PHY_CLRBITS(mac, 0x815, 0x3);
 779                 PHY_CLRBITS(mac, 0x429, 0x8000);
 780                 PHY_CLRBITS(mac, 0x802, 0x3);
 781
 782                 phyr_80f = PHY_READ(mac, 0x80f);
 783                 phyr_810 = PHY_READ(mac, 0x810);
 784
 785                 if (phy->phy_rev >= 3)
 786                         PHY_WRITE(mac, 0x80f, 0xc020);
 787                 else
 788                         PHY_WRITE(mac, 0x80f, 0x8020);
 789                 PHY_WRITE(mac, 0x810, 0);
 790
 791                 phy812_val = bwi_phy812_value(mac, 0x011);
 792                 PHY_WRITE(mac, 0x812, phy812_val);
 793                 if (phy->phy_rev < 7 ||
 794                     (sc->sc_card_flags & BWI_CARD_F_EXT_LNA) == 0)
 795                         PHY_WRITE(mac, 0x811, 0x1b3);
 796                 else
 797                         PHY_WRITE(mac, 0x811, 0x9b3);
 798         }
 799         CSR_SETBITS_2(sc, BWI_RF_ANTDIV, 0x8000);
 800
 801         phyr_35 = PHY_READ(mac, 0x35);
 802         PHY_CLRBITS(mac, 0x35, 0x80);
 803
 804         bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
 805         rf_chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
 806
 807         if (phy->phy_version == 0) {
 808                 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
 809         } else {
 810                 if (phy->phy_version >= 2)
 811                         PHY_FILT_SETBITS(mac, 0x3, 0xffbf, 0x40);
 812                 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, 0x2000);
 813         }
 814
 815         calib = bwi_rf_calibval(mac);
 816
 817         if (phy->phy_mode == IEEE80211_MODE_11B)
 818                 RF_WRITE(mac, 0x78, 0x26);
 819
 820         if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
 821                 phy812_val = bwi_phy812_value(mac, 0x011);
 822                 PHY_WRITE(mac, 0x812, phy812_val);
 823         }
 824
 825         PHY_WRITE(mac, 0x15, 0xbfaf);
 826         PHY_WRITE(mac, 0x2b, 0x1403);
 827
 828         if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
 829                 phy812_val = bwi_phy812_value(mac, 0x001);
 830                 PHY_WRITE(mac, 0x812, phy812_val);
 831         }
 832
 833         PHY_WRITE(mac, 0x15, 0xbfa0);
 834
 835         RF_SETBITS(mac, 0x51, 0x4);
 836         if (rf->rf_rev == 8) {
 837                 RF_WRITE(mac, 0x43, 0x1f);
 838         } else {
 839                 RF_WRITE(mac, 0x52, 0);
 840                 RF_FILT_SETBITS(mac, 0x43, 0xfff0, 0x9);
 841         }
 842
 843         test_lim = 0;
 844         PHY_WRITE(mac, 0x58, 0);
 845         for (i = 0; i < 16; ++i) {
 846                 PHY_WRITE(mac, 0x5a, 0x480);
 847                 PHY_WRITE(mac, 0x59, 0xc810);
 848
 849                 PHY_WRITE(mac, 0x58, 0xd);
 850                 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
 851                         phy812_val = bwi_phy812_value(mac, 0x101);
 852                         PHY_WRITE(mac, 0x812, phy812_val);
 853                 }
 854                 PHY_WRITE(mac, 0x15, 0xafb0);
 855                 DELAY(10);
 856
 857                 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
 858                         phy812_val = bwi_phy812_value(mac, 0x101);
 859                         PHY_WRITE(mac, 0x812, phy812_val);
 860                 }
 861                 PHY_WRITE(mac, 0x15, 0xefb0);
 862                 DELAY(10);
 863
 864                 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
 865                         phy812_val = bwi_phy812_value(mac, 0x100);
 866                         PHY_WRITE(mac, 0x812, phy812_val);
 867                 }
 868                 PHY_WRITE(mac, 0x15, 0xfff0);
 869                 DELAY(20);
 870
 871                 test_lim += PHY_READ(mac, 0x2d);
 872
 873                 PHY_WRITE(mac, 0x58, 0);
 874                 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
 875                         phy812_val = bwi_phy812_value(mac, 0x101);
 876                         PHY_WRITE(mac, 0x812, phy812_val);
 877                 }
 878                 PHY_WRITE(mac, 0x15, 0xafb0);
 879         }
 880         ++test_lim;
 881         test_lim >>= 9;
 882
 883         DELAY(10);
 884
 885         test = 0;
 886         PHY_WRITE(mac, 0x58, 0);
 887         for (i = 0; i < 16; ++i) {
 888                 int j;
 889
 890                 rfr_78 = (bitswap4(i) << 1) | 0x20;
 891                 RF_WRITE(mac, 0x78, rfr_78);
 892                 DELAY(10);
 893
 894                 /* NB: This block is slight different than the above one */
 895                 for (j = 0; j < 16; ++j) {
 896                         PHY_WRITE(mac, 0x5a, 0xd80);
 897                         PHY_WRITE(mac, 0x59, 0xc810);
 898
 899                         PHY_WRITE(mac, 0x58, 0xd);
 900                         if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
 901                             phy->phy_rev >= 2) {
 902                                 phy812_val = bwi_phy812_value(mac, 0x101);
 903                                 PHY_WRITE(mac, 0x812, phy812_val);
 904                         }
 905                         PHY_WRITE(mac, 0x15, 0xafb0);
 906                         DELAY(10);
 907
 908                         if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
 909                             phy->phy_rev >= 2) {
 910                                 phy812_val = bwi_phy812_value(mac, 0x101);
 911                                 PHY_WRITE(mac, 0x812, phy812_val);
 912                         }
 913                         PHY_WRITE(mac, 0x15, 0xefb0);
 914                         DELAY(10);
 915
 916                         if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
 917                             phy->phy_rev >= 2) {
 918                                 phy812_val = bwi_phy812_value(mac, 0x100);
 919                                 PHY_WRITE(mac, 0x812, phy812_val);
 920                         }
 921                         PHY_WRITE(mac, 0x15, 0xfff0);
 922                         DELAY(10);
 923
 924                         test += PHY_READ(mac, 0x2d);
 925
 926                         PHY_WRITE(mac, 0x58, 0);
 927                         if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
 928                             phy->phy_rev >= 2) {
 929                                 phy812_val = bwi_phy812_value(mac, 0x101);
 930                                 PHY_WRITE(mac, 0x812, phy812_val);
 931                         }
 932                         PHY_WRITE(mac, 0x15, 0xafb0);
 933                 }
 934
 935                 ++test;
 936                 test >>= 8;
 937
 938                 if (test > test_lim)
 939                         break;
 940         }
 941         if (i > 15)
 942                 rf->rf_calib = rfr_78;
 943         else
 944                 rf->rf_calib = calib;
 945         if (rf->rf_calib != 0xffff) {
 946                 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_INIT,
 947                         "RF calibration value: 0x%04x\n", rf->rf_calib);
 948                 rf->rf_flags |= BWI_RF_F_INITED;
 949         }
 950
 951         /*
 952          * Restore trashes registers
 953          */
 954         PHY_WRITE(mac, save_phy_regs_comm[0], save_phy_comm[0]);
 955
 956         for (i = 0; i < SAVE_RF_MAX; ++i) {
 957                 int pos = (i + 1) % SAVE_RF_MAX;
 958
 959                 RF_WRITE(mac, save_rf_regs[pos], save_rf[pos]);
 960         }
 961         for (i = 1; i < SAVE_PHY_COMM_MAX; ++i)
 962                 PHY_WRITE(mac, save_phy_regs_comm[i], save_phy_comm[i]);
 963
 964         CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
 965         if (phy->phy_version != 0)
 966                 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, rf_chan_ex);
 967
 968         PHY_WRITE(mac, 0x35, phyr_35);
 969         bwi_rf_workaround(mac, rf->rf_curchan);
 970
 971         if (phy->phy_mode == IEEE80211_MODE_11B) {
 972                 PHY_WRITE(mac, 0x30, phyr_30);
 973                 CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);
 974         } else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
 975                 /* XXX Spec only says when PHY is linked (gmode) */
 976                 CSR_CLRBITS_2(sc, BWI_RF_ANTDIV, 0x8000);
 977
 978                 for (i = 0; i < SAVE_PHY_11G_MAX; ++i) {
 979                         PHY_WRITE(mac, save_phy_regs_11g[i],
 980                                   save_phy_11g[i]);
 981                 }
 982
 983                 PHY_WRITE(mac, 0x80f, phyr_80f);
 984                 PHY_WRITE(mac, 0x810, phyr_810);
 985         }
 986
 987 #undef SAVE_PHY_11G_MAX
 988 #undef SAVE_PHY_COMM_MAX
 989 #undef SAVE_RF_MAX
 990 }
 991
 992 static uint16_t
 993 bwi_rf_calibval(struct bwi_mac *mac)
 994 {
 995         /* http://bcm-specs.sipsolutions.net/RCCTable */
 996         static const uint16_t rf_calibvals[] = {
 997                 0x2, 0x3, 0x1, 0xf, 0x6, 0x7, 0x5, 0xf,
 998                 0xa, 0xb, 0x9, 0xf, 0xe, 0xf, 0xd, 0xf
 999         };
1000         uint16_t val, calib;
1001         int idx;
1002
1003         val = RF_READ(mac, BWI_RFR_BBP_ATTEN);
1004         idx = __SHIFTOUT(val, BWI_RFR_BBP_ATTEN_CALIB_IDX);
1005         KKASSERT(idx < (int)(NELEM(rf_calibvals)));
1006
1007         calib = rf_calibvals[idx] << 1;
1008         if (val & BWI_RFR_BBP_ATTEN_CALIB_BIT)
1009                 calib |= 0x1;
1010         calib |= 0x20;
1011
1012         return calib;
1013 }
1014
1015 static __inline int32_t
1016 _bwi_adjust_devide(int32_t num, int32_t den)
1017 {
1018         if (num < 0)
1019                 return (num / den);
1020         else
1021                 return (num + den / 2) / den;
1022 }
1023
1024 /*
1025  * http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table
1026  * "calculating table entries"
1027  */
1028 static int
1029 bwi_rf_calc_txpower(int8_t *txpwr, uint8_t idx, const int16_t pa_params[])
1030 {
1031         int32_t m1, m2, f, dbm;
1032         int i;
1033
1034         m1 = _bwi_adjust_devide(16 * pa_params[0] + idx * pa_params[1], 32);
1035         m2 = imax(_bwi_adjust_devide(32768 + idx * pa_params[2], 256), 1);
1036
1037 #define ITER_MAX        16
1038
1039         f = 256;
1040         for (i = 0; i < ITER_MAX; ++i) {
1041                 int32_t q, d;
1042
1043                 q = _bwi_adjust_devide(
1044                         f * 4096 - _bwi_adjust_devide(m2 * f, 16) * f, 2048);
1045                 d = abs(q - f);
1046                 f = q;
1047
1048                 if (d < 2)
1049                         break;
1050         }
1051         if (i == ITER_MAX)
1052                 return EINVAL;
1053
1054 #undef ITER_MAX
1055
1056         dbm = _bwi_adjust_devide(m1 * f, 8192);
1057         if (dbm < -127)
1058                 dbm = -127;
1059         else if (dbm > 128)
1060                 dbm = 128;
1061
1062         *txpwr = dbm;
1063         return 0;
1064 }
1065
1066 int
1067 bwi_rf_map_txpower(struct bwi_mac *mac)
1068 {
1069         struct bwi_softc *sc = mac->mac_sc;
1070         struct bwi_rf *rf = &mac->mac_rf;
1071         struct bwi_phy *phy = &mac->mac_phy;
1072         uint16_t sprom_ofs, val, mask;
1073         int16_t pa_params[3];
1074         int error = 0, i, ant_gain, reg_txpower_max;
1075
1076         /*
1077          * Find out max TX power
1078          */
1079         val = bwi_read_sprom(sc, BWI_SPROM_MAX_TXPWR);
1080         if (phy->phy_mode == IEEE80211_MODE_11A) {
1081                 rf->rf_txpower_max = __SHIFTOUT(val,
1082                                      BWI_SPROM_MAX_TXPWR_MASK_11A);
1083         } else {
1084                 rf->rf_txpower_max = __SHIFTOUT(val,
1085                                      BWI_SPROM_MAX_TXPWR_MASK_11BG);
1086
1087                 if ((sc->sc_card_flags & BWI_CARD_F_PA_GPIO9) &&
1088                     phy->phy_mode == IEEE80211_MODE_11G)
1089                         rf->rf_txpower_max -= 3;
1090         }
1091         if (rf->rf_txpower_max <= 0) {
1092                 device_printf(sc->sc_dev, "invalid max txpower in sprom\n");
1093                 rf->rf_txpower_max = 74;
1094         }
1095         DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1096                 "max txpower from sprom: %d dBm\n", rf->rf_txpower_max);
1097
1098         /*
1099          * Find out region/domain max TX power, which is adjusted
1100          * by antenna gain and 1.5 dBm fluctuation as mentioned
1101          * in v3 spec.
1102          */
1103         val = bwi_read_sprom(sc, BWI_SPROM_ANT_GAIN);
1104         if (phy->phy_mode == IEEE80211_MODE_11A)
1105                 ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11A);
1106         else
1107                 ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11BG);
1108         if (ant_gain == 0xff) {
1109                 device_printf(sc->sc_dev, "invalid antenna gain in sprom\n");
1110                 ant_gain = 2;
1111         }
1112         ant_gain *= 4;
1113         DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1114                 "ant gain %d dBm\n", ant_gain);
1115
1116         reg_txpower_max = 90 - ant_gain - 6;    /* XXX magic number */
1117         DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1118                 "region/domain max txpower %d dBm\n", reg_txpower_max);
1119
1120         /*
1121          * Force max TX power within region/domain TX power limit
1122          */
1123         if (rf->rf_txpower_max > reg_txpower_max)
1124                 rf->rf_txpower_max = reg_txpower_max;
1125         DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1126                 "max txpower %d dBm\n", rf->rf_txpower_max);
1127
1128         /*
1129          * Create TSSI to TX power mapping
1130          */
1131
1132         if (sc->sc_bbp_id == BWI_BBPID_BCM4301 &&
1133             rf->rf_type != BWI_RF_T_BCM2050) {
1134                 rf->rf_idle_tssi0 = BWI_DEFAULT_IDLE_TSSI;
1135                 bcopy(bwi_txpower_map_11b, rf->rf_txpower_map0,
1136                       sizeof(rf->rf_txpower_map0));
1137                 goto back;
1138         }
1139
1140 #define IS_VALID_PA_PARAM(p)    ((p) != 0 && (p) != -1)
1141
1142         /*
1143          * Extract PA parameters
1144          */
1145         if (phy->phy_mode == IEEE80211_MODE_11A)
1146                 sprom_ofs = BWI_SPROM_PA_PARAM_11A;
1147         else
1148                 sprom_ofs = BWI_SPROM_PA_PARAM_11BG;
1149         for (i = 0; i < NELEM(pa_params); ++i)
1150                 pa_params[i] = (int16_t)bwi_read_sprom(sc, sprom_ofs + (i * 2));
1151
1152         for (i = 0; i < NELEM(pa_params); ++i) {
1153                 /*
1154                  * If one of the PA parameters from SPROM is not valid,
1155                  * fall back to the default values, if there are any.
1156                  */
1157                 if (!IS_VALID_PA_PARAM(pa_params[i])) {
1158                         const int8_t *txpower_map;
1159
1160                         if (phy->phy_mode == IEEE80211_MODE_11A) {
1161                                 if_printf(&sc->sc_ic.ic_if,
1162                                           "no tssi2dbm table for 11a PHY\n");
1163                                 return ENXIO;
1164                         }
1165
1166                         if (phy->phy_mode == IEEE80211_MODE_11G) {
1167                                 DPRINTF(sc,
1168                                 BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1169                                 "%s\n", "use default 11g TSSI map");
1170                                 txpower_map = bwi_txpower_map_11g;
1171                         } else {
1172                                 DPRINTF(sc,
1173                                 BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1174                                 "%s\n", "use default 11b TSSI map");
1175                                 txpower_map = bwi_txpower_map_11b;
1176                         }
1177
1178                         rf->rf_idle_tssi0 = BWI_DEFAULT_IDLE_TSSI;
1179                         bcopy(txpower_map, rf->rf_txpower_map0,
1180                               sizeof(rf->rf_txpower_map0));
1181                         goto back;
1182                 }
1183         }
1184
1185         /*
1186          * All of the PA parameters from SPROM are valid.
1187          */
1188
1189         /*
1190          * Extract idle TSSI from SPROM.
1191          */
1192         val = bwi_read_sprom(sc, BWI_SPROM_IDLE_TSSI);
1193         DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1194                 "sprom idle tssi: 0x%04x\n", val);
1195
1196         if (phy->phy_mode == IEEE80211_MODE_11A)
1197                 mask = BWI_SPROM_IDLE_TSSI_MASK_11A;
1198         else
1199                 mask = BWI_SPROM_IDLE_TSSI_MASK_11BG;
1200
1201         rf->rf_idle_tssi0 = (int)__SHIFTOUT(val, mask);
1202         if (!IS_VALID_PA_PARAM(rf->rf_idle_tssi0))
1203                 rf->rf_idle_tssi0 = 62;
1204
1205 #undef IS_VALID_PA_PARAM
1206
1207         /*
1208          * Calculate TX power map, which is indexed by TSSI
1209          */
1210         DPRINTF(sc, BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1211                 "%s\n", "TSSI-TX power map:");
1212         for (i = 0; i < BWI_TSSI_MAX; ++i) {
1213                 error = bwi_rf_calc_txpower(&rf->rf_txpower_map0[i], i,
1214                                             pa_params);
1215                 if (error) {
1216                         if_printf(&sc->sc_ic.ic_if,
1217                                   "bwi_rf_calc_txpower failed\n");
1218                         break;
1219                 }
1220
1221 #ifdef BWI_DEBUG
1222                 if (i != 0 && i % 8 == 0) {
1223                         _DPRINTF(sc,
1224                         BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1225                         "%s\n", "");
1226                 }
1227 #endif
1228                 _DPRINTF(sc, BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1229                          "%d ", rf->rf_txpower_map0[i]);
1230         }
1231         _DPRINTF(sc, BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1232                  "%s\n", "");
1233 back:
1234         DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1235                 "idle tssi0: %d\n", rf->rf_idle_tssi0);
1236         return error;
1237 }
1238
1239 static void
1240 bwi_rf_lo_update_11g(struct bwi_mac *mac)
1241 {
1242         struct bwi_softc *sc = mac->mac_sc;
1243         struct ifnet *ifp = &sc->sc_ic.ic_if;
1244         struct bwi_rf *rf = &mac->mac_rf;
1245         struct bwi_phy *phy = &mac->mac_phy;
1246         struct bwi_tpctl *tpctl = &mac->mac_tpctl;
1247         struct rf_saveregs regs;
1248         uint16_t ant_div, chan_ex;
1249         uint8_t devi_ctrl;
1250         u_int orig_chan;
1251
1252         DPRINTF(sc, BWI_DBG_RF | BWI_DBG_INIT, "%s enter\n", __func__);
1253
1254         /*
1255          * Save RF/PHY registers for later restoration
1256          */
1257         orig_chan = rf->rf_curchan;
1258         bzero(&regs, sizeof(regs));
1259
1260         if (phy->phy_flags & BWI_PHY_F_LINKED) {
1261                 SAVE_PHY_REG(mac, &regs, 429);
1262                 SAVE_PHY_REG(mac, &regs, 802);
1263
1264                 PHY_WRITE(mac, 0x429, regs.phy_429 & 0x7fff);
1265                 PHY_WRITE(mac, 0x802, regs.phy_802 & 0xfffc);
1266         }
1267
1268         ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1269         CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div | 0x8000);
1270         chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1271
1272         SAVE_PHY_REG(mac, &regs, 15);
1273         SAVE_PHY_REG(mac, &regs, 2a);
1274         SAVE_PHY_REG(mac, &regs, 35);
1275         SAVE_PHY_REG(mac, &regs, 60);
1276         SAVE_RF_REG(mac, &regs, 43);
1277         SAVE_RF_REG(mac, &regs, 7a);
1278         SAVE_RF_REG(mac, &regs, 52);
1279         if (phy->phy_flags & BWI_PHY_F_LINKED) {
1280                 SAVE_PHY_REG(mac, &regs, 811);
1281                 SAVE_PHY_REG(mac, &regs, 812);
1282                 SAVE_PHY_REG(mac, &regs, 814);
1283                 SAVE_PHY_REG(mac, &regs, 815);
1284         }
1285
1286         /* Force to channel 6 */
1287         bwi_rf_set_chan(mac, 6, 0);
1288
1289         if (phy->phy_flags & BWI_PHY_F_LINKED) {
1290                 PHY_WRITE(mac, 0x429, regs.phy_429 & 0x7fff);
1291                 PHY_WRITE(mac, 0x802, regs.phy_802 & 0xfffc);
1292                 bwi_mac_dummy_xmit(mac);
1293         }
1294         RF_WRITE(mac, 0x43, 0x6);
1295
1296         bwi_phy_set_bbp_atten(mac, 2);
1297
1298         CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0);
1299
1300         PHY_WRITE(mac, 0x2e, 0x7f);
1301         PHY_WRITE(mac, 0x80f, 0x78);
1302         PHY_WRITE(mac, 0x35, regs.phy_35 & 0xff7f);
1303         RF_WRITE(mac, 0x7a, regs.rf_7a & 0xfff0);
1304         PHY_WRITE(mac, 0x2b, 0x203);
1305         PHY_WRITE(mac, 0x2a, 0x8a3);
1306
1307         if (phy->phy_flags & BWI_PHY_F_LINKED) {
1308                 PHY_WRITE(mac, 0x814, regs.phy_814 | 0x3);
1309                 PHY_WRITE(mac, 0x815, regs.phy_815 & 0xfffc);
1310                 PHY_WRITE(mac, 0x811, 0x1b3);
1311                 PHY_WRITE(mac, 0x812, 0xb2);
1312         }
1313
1314         if ((ifp->if_flags & IFF_RUNNING) == 0)
1315                 tpctl->tp_ctrl2 = bwi_rf_get_tp_ctrl2(mac);
1316         PHY_WRITE(mac, 0x80f, 0x8078);
1317
1318         /*
1319          * Measure all RF LO
1320          */
1321         devi_ctrl = _bwi_rf_lo_update_11g(mac, regs.rf_7a);
1322
1323         /*
1324          * Restore saved RF/PHY registers
1325          */
1326         if (phy->phy_flags & BWI_PHY_F_LINKED) {
1327                 PHY_WRITE(mac, 0x15, 0xe300);
1328                 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa0);
1329                 DELAY(5);
1330                 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa2);
1331                 DELAY(2);
1332                 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa3);
1333         } else {
1334                 PHY_WRITE(mac, 0x15, devi_ctrl | 0xefa0);
1335         }
1336
1337         if ((ifp->if_flags & IFF_RUNNING) == 0)
1338                 tpctl = NULL;
1339         bwi_rf_lo_adjust(mac, tpctl);
1340
1341         PHY_WRITE(mac, 0x2e, 0x807f);
1342         if (phy->phy_flags & BWI_PHY_F_LINKED)
1343                 PHY_WRITE(mac, 0x2f, 0x202);
1344         else
1345                 PHY_WRITE(mac, 0x2f, 0x101);
1346
1347         CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
1348
1349         RESTORE_PHY_REG(mac, &regs, 15);
1350         RESTORE_PHY_REG(mac, &regs, 2a);
1351         RESTORE_PHY_REG(mac, &regs, 35);
1352         RESTORE_PHY_REG(mac, &regs, 60);
1353
1354         RESTORE_RF_REG(mac, &regs, 43);
1355         RESTORE_RF_REG(mac, &regs, 7a);
1356
1357         regs.rf_52 &= 0xf0;
1358         regs.rf_52 |= (RF_READ(mac, 0x52) & 0xf);
1359         RF_WRITE(mac, 0x52, regs.rf_52);
1360
1361         CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
1362
1363         if (phy->phy_flags & BWI_PHY_F_LINKED) {
1364                 RESTORE_PHY_REG(mac, &regs, 811);
1365                 RESTORE_PHY_REG(mac, &regs, 812);
1366                 RESTORE_PHY_REG(mac, &regs, 814);
1367                 RESTORE_PHY_REG(mac, &regs, 815);
1368                 RESTORE_PHY_REG(mac, &regs, 429);
1369                 RESTORE_PHY_REG(mac, &regs, 802);
1370         }
1371
1372         bwi_rf_set_chan(mac, orig_chan, 1);
1373 }
1374
1375 static uint32_t
1376 bwi_rf_lo_devi_measure(struct bwi_mac *mac, uint16_t ctrl)
1377 {
1378         struct bwi_phy *phy = &mac->mac_phy;
1379         uint32_t devi = 0;
1380         int i;
1381
1382         if (phy->phy_flags & BWI_PHY_F_LINKED)
1383                 ctrl <<= 8;
1384
1385         for (i = 0; i < 8; ++i) {
1386                 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1387                         PHY_WRITE(mac, 0x15, 0xe300);
1388                         PHY_WRITE(mac, 0x812, ctrl | 0xb0);
1389                         DELAY(5);
1390                         PHY_WRITE(mac, 0x812, ctrl | 0xb2);
1391                         DELAY(2);
1392                         PHY_WRITE(mac, 0x812, ctrl | 0xb3);
1393                         DELAY(4);
1394                         PHY_WRITE(mac, 0x15, 0xf300);
1395                 } else {
1396                         PHY_WRITE(mac, 0x15, ctrl | 0xefa0);
1397                         DELAY(2);
1398                         PHY_WRITE(mac, 0x15, ctrl | 0xefe0);
1399                         DELAY(4);
1400                         PHY_WRITE(mac, 0x15, ctrl | 0xffe0);
1401                 }
1402                 DELAY(8);
1403                 devi += PHY_READ(mac, 0x2d);
1404         }
1405         return devi;
1406 }
1407
1408 static uint16_t
1409 bwi_rf_get_tp_ctrl2(struct bwi_mac *mac)
1410 {
1411         uint32_t devi_min;
1412         uint16_t tp_ctrl2 = 0;
1413         int i;
1414
1415         RF_WRITE(mac, 0x52, 0);
1416         DELAY(10);
1417         devi_min = bwi_rf_lo_devi_measure(mac, 0);
1418
1419         for (i = 0; i < 16; ++i) {
1420                 uint32_t devi;
1421
1422                 RF_WRITE(mac, 0x52, i);
1423                 DELAY(10);
1424                 devi = bwi_rf_lo_devi_measure(mac, 0);
1425
1426                 if (devi < devi_min) {
1427                         devi_min = devi;
1428                         tp_ctrl2 = i;
1429                 }
1430         }
1431         return tp_ctrl2;
1432 }
1433
1434 static uint8_t
1435 _bwi_rf_lo_update_11g(struct bwi_mac *mac, uint16_t orig_rf7a)
1436 {
1437 #define RF_ATTEN_LISTSZ 14
1438 #define BBP_ATTEN_MAX   4       /* half */
1439
1440         static const int rf_atten_list[RF_ATTEN_LISTSZ] =
1441         { 3, 1, 5, 7, 9, 2, 0, 4, 6, 8, 1, 2, 3, 4 };
1442         static const int rf_atten_init_list[RF_ATTEN_LISTSZ] =
1443         { 0, 3, 1, 5, 7, 3, 2, 0, 4, 6, -1, -1, -1, -1 };
1444         static const int rf_lo_measure_order[RF_ATTEN_LISTSZ] =
1445         { 3, 1, 5, 7, 9, 2, 0, 4, 6, 8, 10, 11, 12, 13 };
1446
1447         struct ifnet *ifp = &mac->mac_sc->sc_ic.ic_if;
1448         struct bwi_rf_lo lo_save, *lo;
1449         uint8_t devi_ctrl = 0;
1450         int idx, adj_rf7a = 0;
1451
1452         bzero(&lo_save, sizeof(lo_save));
1453         for (idx = 0; idx < RF_ATTEN_LISTSZ; ++idx) {
1454                 int init_rf_atten = rf_atten_init_list[idx];
1455                 int rf_atten = rf_atten_list[idx];
1456                 int bbp_atten;
1457
1458                 for (bbp_atten = 0; bbp_atten < BBP_ATTEN_MAX; ++bbp_atten) {
1459                         uint16_t tp_ctrl2, rf7a;
1460
1461                         if ((ifp->if_flags & IFF_RUNNING) == 0) {
1462                                 if (idx == 0) {
1463                                         bzero(&lo_save, sizeof(lo_save));
1464                                 } else if (init_rf_atten < 0) {
1465                                         lo = bwi_get_rf_lo(mac,
1466                                                 rf_atten, 2 * bbp_atten);
1467                                         bcopy(lo, &lo_save, sizeof(lo_save));
1468                                 } else {
1469                                         lo = bwi_get_rf_lo(mac,
1470                                                 init_rf_atten, 0);
1471                                         bcopy(lo, &lo_save, sizeof(lo_save));
1472                                 }
1473
1474                                 devi_ctrl = 0;
1475                                 adj_rf7a = 0;
1476
1477                                 /*
1478                                  * XXX
1479                                  * Linux driver overflows 'val'
1480                                  */
1481                                 if (init_rf_atten >= 0) {
1482                                         int val;
1483
1484                                         val = rf_atten * 2 + bbp_atten;
1485                                         if (val > 14) {
1486                                                 adj_rf7a = 1;
1487                                                 if (val > 17)
1488                                                         devi_ctrl = 1;
1489                                                 if (val > 19)
1490                                                         devi_ctrl = 2;
1491                                         }
1492                                 }
1493                         } else {
1494                                 lo = bwi_get_rf_lo(mac,
1495                                         rf_atten, 2 * bbp_atten);
1496                                 if (!bwi_rf_lo_isused(mac, lo))
1497                                         continue;
1498                                 bcopy(lo, &lo_save, sizeof(lo_save));
1499
1500                                 devi_ctrl = 3;
1501                                 adj_rf7a = 0;
1502                         }
1503
1504                         RF_WRITE(mac, BWI_RFR_ATTEN, rf_atten);
1505
1506                         tp_ctrl2 = mac->mac_tpctl.tp_ctrl2;
1507                         if (init_rf_atten < 0)
1508                                 tp_ctrl2 |= (3 << 4);
1509                         RF_WRITE(mac, BWI_RFR_TXPWR, tp_ctrl2);
1510
1511                         DELAY(10);
1512
1513                         bwi_phy_set_bbp_atten(mac, bbp_atten * 2);
1514
1515                         rf7a = orig_rf7a & 0xfff0;
1516                         if (adj_rf7a)
1517                                 rf7a |= 0x8;
1518                         RF_WRITE(mac, 0x7a, rf7a);
1519
1520                         lo = bwi_get_rf_lo(mac,
1521                                 rf_lo_measure_order[idx], bbp_atten * 2);
1522                         bwi_rf_lo_measure_11g(mac, &lo_save, lo, devi_ctrl);
1523                 }
1524         }
1525         return devi_ctrl;
1526
1527 #undef RF_ATTEN_LISTSZ
1528 #undef BBP_ATTEN_MAX
1529 }
1530
1531 static void
1532 bwi_rf_lo_measure_11g(struct bwi_mac *mac, const struct bwi_rf_lo *src_lo,
1533         struct bwi_rf_lo *dst_lo, uint8_t devi_ctrl)
1534 {
1535 #define LO_ADJUST_MIN   1
1536 #define LO_ADJUST_MAX   8
1537 #define LO_ADJUST(hi, lo)       { .ctrl_hi = hi, .ctrl_lo = lo }
1538         static const struct bwi_rf_lo rf_lo_adjust[LO_ADJUST_MAX] = {
1539                 LO_ADJUST(1,    1),
1540                 LO_ADJUST(1,    0),
1541                 LO_ADJUST(1,    -1),
1542                 LO_ADJUST(0,    -1),
1543                 LO_ADJUST(-1,   -1),
1544                 LO_ADJUST(-1,   0),
1545                 LO_ADJUST(-1,   1),
1546                 LO_ADJUST(0,    1)
1547         };
1548 #undef LO_ADJUST
1549
1550         struct bwi_rf_lo lo_min;
1551         uint32_t devi_min;
1552         int found, loop_count, adjust_state;
1553
1554         bcopy(src_lo, &lo_min, sizeof(lo_min));
1555         RF_LO_WRITE(mac, &lo_min);
1556         devi_min = bwi_rf_lo_devi_measure(mac, devi_ctrl);
1557
1558         loop_count = 12;        /* XXX */
1559         adjust_state = 0;
1560         do {
1561                 struct bwi_rf_lo lo_base;
1562                 int i, fin;
1563
1564                 found = 0;
1565                 if (adjust_state == 0) {
1566                         i = LO_ADJUST_MIN;
1567                         fin = LO_ADJUST_MAX;
1568                 } else if (adjust_state % 2 == 0) {
1569                         i = adjust_state - 1;
1570                         fin = adjust_state + 1;
1571                 } else {
1572                         i = adjust_state - 2;
1573                         fin = adjust_state + 2;
1574                 }
1575
1576                 if (i < LO_ADJUST_MIN)
1577                         i += LO_ADJUST_MAX;
1578                 KKASSERT(i <= LO_ADJUST_MAX && i >= LO_ADJUST_MIN);
1579
1580                 if (fin > LO_ADJUST_MAX)
1581                         fin -= LO_ADJUST_MAX;
1582                 KKASSERT(fin <= LO_ADJUST_MAX && fin >= LO_ADJUST_MIN);
1583
1584                 bcopy(&lo_min, &lo_base, sizeof(lo_base));
1585                 for (;;) {
1586                         struct bwi_rf_lo lo;
1587
1588                         lo.ctrl_hi = lo_base.ctrl_hi +
1589                                 rf_lo_adjust[i - 1].ctrl_hi;
1590                         lo.ctrl_lo = lo_base.ctrl_lo +
1591                                 rf_lo_adjust[i - 1].ctrl_lo;
1592
1593                         if (abs(lo.ctrl_lo) < 9 && abs(lo.ctrl_hi) < 9) {
1594                                 uint32_t devi;
1595
1596                                 RF_LO_WRITE(mac, &lo);
1597                                 devi = bwi_rf_lo_devi_measure(mac, devi_ctrl);
1598                                 if (devi < devi_min) {
1599                                         devi_min = devi;
1600                                         adjust_state = i;
1601                                         found = 1;
1602                                         bcopy(&lo, &lo_min, sizeof(lo_min));
1603                                 }
1604                         }
1605                         if (i == fin)
1606                                 break;
1607                         if (i == LO_ADJUST_MAX)
1608                                 i = LO_ADJUST_MIN;
1609                         else
1610                                 ++i;
1611                 }
1612         } while (loop_count-- && found);
1613
1614         bcopy(&lo_min, dst_lo, sizeof(*dst_lo));
1615
1616 #undef LO_ADJUST_MIN
1617 #undef LO_ADJUST_MAX
1618 }
1619
1620 static void
1621 bwi_rf_calc_nrssi_slope_11b(struct bwi_mac *mac)
1622 {
1623 #define SAVE_RF_MAX     3
1624 #define SAVE_PHY_MAX    8
1625
1626         static const uint16_t save_rf_regs[SAVE_RF_MAX] =
1627         { 0x7a, 0x52, 0x43 };
1628         static const uint16_t save_phy_regs[SAVE_PHY_MAX] =
1629         { 0x30, 0x26, 0x15, 0x2a, 0x20, 0x5a, 0x59, 0x58 };
1630
1631         struct bwi_softc *sc = mac->mac_sc;
1632         struct bwi_rf *rf = &mac->mac_rf;
1633         struct bwi_phy *phy = &mac->mac_phy;
1634         uint16_t save_rf[SAVE_RF_MAX];
1635         uint16_t save_phy[SAVE_PHY_MAX];
1636         uint16_t ant_div, bbp_atten, chan_ex;
1637         int16_t nrssi[2];
1638         int i;
1639
1640         /*
1641          * Save RF/PHY registers for later restoration
1642          */
1643         for (i = 0; i < SAVE_RF_MAX; ++i)
1644                 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
1645         for (i = 0; i < SAVE_PHY_MAX; ++i)
1646                 save_phy[i] = PHY_READ(mac, save_phy_regs[i]);
1647
1648         ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1649         bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
1650         chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1651
1652         /*
1653          * Calculate nrssi0
1654          */
1655         if (phy->phy_rev >= 5)
1656                 RF_CLRBITS(mac, 0x7a, 0xff80);
1657         else
1658                 RF_CLRBITS(mac, 0x7a, 0xfff0);
1659         PHY_WRITE(mac, 0x30, 0xff);
1660
1661         CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x7f7f);
1662
1663         PHY_WRITE(mac, 0x26, 0);
1664         PHY_SETBITS(mac, 0x15, 0x20);
1665         PHY_WRITE(mac, 0x2a, 0x8a3);
1666         RF_SETBITS(mac, 0x7a, 0x80);
1667
1668         nrssi[0] = (int16_t)PHY_READ(mac, 0x27);
1669
1670         /*
1671          * Calculate nrssi1
1672          */
1673         RF_CLRBITS(mac, 0x7a, 0xff80);
1674         if (phy->phy_version >= 2)
1675                 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x40);
1676         else if (phy->phy_version == 0)
1677                 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
1678         else
1679                 CSR_CLRBITS_2(sc, BWI_RF_CHAN_EX, 0xdfff);
1680
1681         PHY_WRITE(mac, 0x20, 0x3f3f);
1682         PHY_WRITE(mac, 0x15, 0xf330);
1683
1684         RF_WRITE(mac, 0x5a, 0x60);
1685         RF_CLRBITS(mac, 0x43, 0xff0f);
1686
1687         PHY_WRITE(mac, 0x5a, 0x480);
1688         PHY_WRITE(mac, 0x59, 0x810);
1689         PHY_WRITE(mac, 0x58, 0xd);
1690
1691         DELAY(20);
1692
1693         nrssi[1] = (int16_t)PHY_READ(mac, 0x27);
1694
1695         /*
1696          * Restore saved RF/PHY registers
1697          */
1698         PHY_WRITE(mac, save_phy_regs[0], save_phy[0]);
1699         RF_WRITE(mac, save_rf_regs[0], save_rf[0]);
1700
1701         CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
1702
1703         for (i = 1; i < 4; ++i)
1704                 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]);
1705
1706         bwi_rf_workaround(mac, rf->rf_curchan);
1707
1708         if (phy->phy_version != 0)
1709                 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
1710
1711         for (; i < SAVE_PHY_MAX; ++i)
1712                 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]);
1713
1714         for (i = 1; i < SAVE_RF_MAX; ++i)
1715                 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
1716
1717         /*
1718          * Install calculated narrow RSSI values
1719          */
1720         if (nrssi[0] == nrssi[1])
1721                 rf->rf_nrssi_slope = 0x10000;
1722         else
1723                 rf->rf_nrssi_slope = 0x400000 / (nrssi[0] - nrssi[1]);
1724         if (nrssi[0] <= -4) {
1725                 rf->rf_nrssi[0] = nrssi[0];
1726                 rf->rf_nrssi[1] = nrssi[1];
1727         }
1728
1729 #undef SAVE_RF_MAX
1730 #undef SAVE_PHY_MAX
1731 }
1732
1733 static void
1734 bwi_rf_set_nrssi_ofs_11g(struct bwi_mac *mac)
1735 {
1736 #define SAVE_RF_MAX             2
1737 #define SAVE_PHY_COMM_MAX       10
1738 #define SAVE_PHY6_MAX           8
1739
1740         static const uint16_t save_rf_regs[SAVE_RF_MAX] =
1741         { 0x7a, 0x43 };
1742         static const uint16_t save_phy_comm_regs[SAVE_PHY_COMM_MAX] = {
1743                 0x0001, 0x0811, 0x0812, 0x0814,
1744                 0x0815, 0x005a, 0x0059, 0x0058,
1745                 0x000a, 0x0003
1746         };
1747         static const uint16_t save_phy6_regs[SAVE_PHY6_MAX] = {
1748                 0x002e, 0x002f, 0x080f, 0x0810,
1749                 0x0801, 0x0060, 0x0014, 0x0478
1750         };
1751
1752         struct bwi_phy *phy = &mac->mac_phy;
1753         uint16_t save_rf[SAVE_RF_MAX];
1754         uint16_t save_phy_comm[SAVE_PHY_COMM_MAX];
1755         uint16_t save_phy6[SAVE_PHY6_MAX];
1756         uint16_t rf7b = 0xffff;
1757         int16_t nrssi;
1758         int i, phy6_idx = 0;
1759
1760         for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
1761                 save_phy_comm[i] = PHY_READ(mac, save_phy_comm_regs[i]);
1762         for (i = 0; i < SAVE_RF_MAX; ++i)
1763                 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
1764
1765         PHY_CLRBITS(mac, 0x429, 0x8000);
1766         PHY_FILT_SETBITS(mac, 0x1, 0x3fff, 0x4000);
1767         PHY_SETBITS(mac, 0x811, 0xc);
1768         PHY_FILT_SETBITS(mac, 0x812, 0xfff3, 0x4);
1769         PHY_CLRBITS(mac, 0x802, 0x3);
1770
1771         if (phy->phy_rev >= 6) {
1772                 for (i = 0; i < SAVE_PHY6_MAX; ++i)
1773                         save_phy6[i] = PHY_READ(mac, save_phy6_regs[i]);
1774
1775                 PHY_WRITE(mac, 0x2e, 0);
1776                 PHY_WRITE(mac, 0x2f, 0);
1777                 PHY_WRITE(mac, 0x80f, 0);
1778                 PHY_WRITE(mac, 0x810, 0);
1779                 PHY_SETBITS(mac, 0x478, 0x100);
1780                 PHY_SETBITS(mac, 0x801, 0x40);
1781                 PHY_SETBITS(mac, 0x60, 0x40);
1782                 PHY_SETBITS(mac, 0x14, 0x200);
1783         }
1784
1785         RF_SETBITS(mac, 0x7a, 0x70);
1786         RF_SETBITS(mac, 0x7a, 0x80);
1787
1788         DELAY(30);
1789
1790         nrssi = bwi_nrssi_11g(mac);
1791         if (nrssi == 31) {
1792                 for (i = 7; i >= 4; --i) {
1793                         RF_WRITE(mac, 0x7b, i);
1794                         DELAY(20);
1795                         nrssi = bwi_nrssi_11g(mac);
1796                         if (nrssi < 31 && rf7b == 0xffff)
1797                                 rf7b = i;
1798                 }
1799                 if (rf7b == 0xffff)
1800                         rf7b = 4;
1801         } else {
1802                 struct bwi_gains gains;
1803
1804                 RF_CLRBITS(mac, 0x7a, 0xff80);
1805
1806                 PHY_SETBITS(mac, 0x814, 0x1);
1807                 PHY_CLRBITS(mac, 0x815, 0x1);
1808                 PHY_SETBITS(mac, 0x811, 0xc);
1809                 PHY_SETBITS(mac, 0x812, 0xc);
1810                 PHY_SETBITS(mac, 0x811, 0x30);
1811                 PHY_SETBITS(mac, 0x812, 0x30);
1812                 PHY_WRITE(mac, 0x5a, 0x480);
1813                 PHY_WRITE(mac, 0x59, 0x810);
1814                 PHY_WRITE(mac, 0x58, 0xd);
1815                 if (phy->phy_version == 0)
1816                         PHY_WRITE(mac, 0x3, 0x122);
1817                 else
1818                         PHY_SETBITS(mac, 0xa, 0x2000);
1819                 PHY_SETBITS(mac, 0x814, 0x4);
1820                 PHY_CLRBITS(mac, 0x815, 0x4);
1821                 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40);
1822                 RF_SETBITS(mac, 0x7a, 0xf);
1823
1824                 bzero(&gains, sizeof(gains));
1825                 gains.tbl_gain1 = 3;
1826                 gains.tbl_gain2 = 0;
1827                 gains.phy_gain = 1;
1828                 bwi_set_gains(mac, &gains);
1829
1830                 RF_FILT_SETBITS(mac, 0x43, 0xf0, 0xf);
1831                 DELAY(30);
1832
1833                 nrssi = bwi_nrssi_11g(mac);
1834                 if (nrssi == -32) {
1835                         for (i = 0; i < 4; ++i) {
1836                                 RF_WRITE(mac, 0x7b, i);
1837                                 DELAY(20);
1838                                 nrssi = bwi_nrssi_11g(mac);
1839                                 if (nrssi > -31 && rf7b == 0xffff)
1840                                         rf7b = i;
1841                         }
1842                         if (rf7b == 0xffff)
1843                                 rf7b = 3;
1844                 } else {
1845                         rf7b = 0;
1846                 }
1847         }
1848         RF_WRITE(mac, 0x7b, rf7b);
1849
1850         /*
1851          * Restore saved RF/PHY registers
1852          */
1853         if (phy->phy_rev >= 6) {
1854                 for (phy6_idx = 0; phy6_idx < 4; ++phy6_idx) {
1855                         PHY_WRITE(mac, save_phy6_regs[phy6_idx],
1856                                   save_phy6[phy6_idx]);
1857                 }
1858         }
1859
1860         /* Saved PHY registers 0, 1, 2 are handled later */
1861         for (i = 3; i < SAVE_PHY_COMM_MAX; ++i)
1862                 PHY_WRITE(mac, save_phy_comm_regs[i], save_phy_comm[i]);
1863
1864         for (i = SAVE_RF_MAX - 1; i >= 0; --i)
1865                 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
1866
1867         PHY_SETBITS(mac, 0x802, 0x3);
1868         PHY_SETBITS(mac, 0x429, 0x8000);
1869
1870         bwi_set_gains(mac, NULL);
1871
1872         if (phy->phy_rev >= 6) {
1873                 for (; phy6_idx < SAVE_PHY6_MAX; ++phy6_idx) {
1874                         PHY_WRITE(mac, save_phy6_regs[phy6_idx],
1875                                   save_phy6[phy6_idx]);
1876                 }
1877         }
1878
1879         PHY_WRITE(mac, save_phy_comm_regs[0], save_phy_comm[0]);
1880         PHY_WRITE(mac, save_phy_comm_regs[2], save_phy_comm[2]);
1881         PHY_WRITE(mac, save_phy_comm_regs[1], save_phy_comm[1]);
1882
1883 #undef SAVE_RF_MAX
1884 #undef SAVE_PHY_COMM_MAX
1885 #undef SAVE_PHY6_MAX
1886 }
1887
1888 static void
1889 bwi_rf_calc_nrssi_slope_11g(struct bwi_mac *mac)
1890 {
1891 #define SAVE_RF_MAX             3
1892 #define SAVE_PHY_COMM_MAX       4
1893 #define SAVE_PHY3_MAX           8
1894
1895         static const uint16_t save_rf_regs[SAVE_RF_MAX] =
1896         { 0x7a, 0x52, 0x43 };
1897         static const uint16_t save_phy_comm_regs[SAVE_PHY_COMM_MAX] =
1898         { 0x15, 0x5a, 0x59, 0x58 };
1899         static const uint16_t save_phy3_regs[SAVE_PHY3_MAX] = {
1900                 0x002e, 0x002f, 0x080f, 0x0810,
1901                 0x0801, 0x0060, 0x0014, 0x0478
1902         };
1903
1904         struct bwi_softc *sc = mac->mac_sc;
1905         struct bwi_phy *phy = &mac->mac_phy;
1906         struct bwi_rf *rf = &mac->mac_rf;
1907         uint16_t save_rf[SAVE_RF_MAX];
1908         uint16_t save_phy_comm[SAVE_PHY_COMM_MAX];
1909         uint16_t save_phy3[SAVE_PHY3_MAX];
1910         uint16_t ant_div, bbp_atten, chan_ex;
1911         struct bwi_gains gains;
1912         int16_t nrssi[2];
1913         int i, phy3_idx = 0;
1914
1915         if (rf->rf_rev >= 9)
1916                 return;
1917         else if (rf->rf_rev == 8)
1918                 bwi_rf_set_nrssi_ofs_11g(mac);
1919
1920         PHY_CLRBITS(mac, 0x429, 0x8000);
1921         PHY_CLRBITS(mac, 0x802, 0x3);
1922
1923         /*
1924          * Save RF/PHY registers for later restoration
1925          */
1926         ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1927         CSR_SETBITS_2(sc, BWI_RF_ANTDIV, 0x8000);
1928
1929         for (i = 0; i < SAVE_RF_MAX; ++i)
1930                 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
1931         for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
1932                 save_phy_comm[i] = PHY_READ(mac, save_phy_comm_regs[i]);
1933
1934         bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
1935         chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1936
1937         if (phy->phy_rev >= 3) {
1938                 for (i = 0; i < SAVE_PHY3_MAX; ++i)
1939                         save_phy3[i] = PHY_READ(mac, save_phy3_regs[i]);
1940
1941                 PHY_WRITE(mac, 0x2e, 0);
1942                 PHY_WRITE(mac, 0x810, 0);
1943
1944                 if (phy->phy_rev == 4 || phy->phy_rev == 6 ||
1945                     phy->phy_rev == 7) {
1946                         PHY_SETBITS(mac, 0x478, 0x100);
1947                         PHY_SETBITS(mac, 0x810, 0x40);
1948                 } else if (phy->phy_rev == 3 || phy->phy_rev == 5) {
1949                         PHY_CLRBITS(mac, 0x810, 0x40);
1950                 }
1951
1952                 PHY_SETBITS(mac, 0x60, 0x40);
1953                 PHY_SETBITS(mac, 0x14, 0x200);
1954         }
1955
1956         /*
1957          * Calculate nrssi0
1958          */
1959         RF_SETBITS(mac, 0x7a, 0x70);
1960
1961         bzero(&gains, sizeof(gains));
1962         gains.tbl_gain1 = 0;
1963         gains.tbl_gain2 = 8;
1964         gains.phy_gain = 0;
1965         bwi_set_gains(mac, &gains);
1966
1967         RF_CLRBITS(mac, 0x7a, 0xff08);
1968         if (phy->phy_rev >= 2) {
1969                 PHY_FILT_SETBITS(mac, 0x811, 0xffcf, 0x30);
1970                 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x10);
1971         }
1972
1973         RF_SETBITS(mac, 0x7a, 0x80);
1974         DELAY(20);
1975         nrssi[0] = bwi_nrssi_11g(mac);
1976
1977         /*
1978          * Calculate nrssi1
1979          */
1980         RF_CLRBITS(mac, 0x7a, 0xff80);
1981         if (phy->phy_version >= 2)
1982                 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40);
1983         CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, 0x2000);
1984
1985         RF_SETBITS(mac, 0x7a, 0xf);
1986         PHY_WRITE(mac, 0x15, 0xf330);
1987         if (phy->phy_rev >= 2) {
1988                 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x20);
1989                 PHY_FILT_SETBITS(mac, 0x811, 0xffcf, 0x20);
1990         }
1991
1992         bzero(&gains, sizeof(gains));
1993         gains.tbl_gain1 = 3;
1994         gains.tbl_gain2 = 0;
1995         gains.phy_gain = 1;
1996         bwi_set_gains(mac, &gains);
1997
1998         if (rf->rf_rev == 8) {
1999                 RF_WRITE(mac, 0x43, 0x1f);
2000         } else {
2001                 RF_FILT_SETBITS(mac, 0x52, 0xff0f, 0x60);
2002                 RF_FILT_SETBITS(mac, 0x43, 0xfff0, 0x9);
2003         }
2004         PHY_WRITE(mac, 0x5a, 0x480);
2005         PHY_WRITE(mac, 0x59, 0x810);
2006         PHY_WRITE(mac, 0x58, 0xd);
2007         DELAY(20);
2008
2009         nrssi[1] = bwi_nrssi_11g(mac);
2010
2011         /*
2012          * Install calculated narrow RSSI values
2013          */
2014         if (nrssi[1] == nrssi[0])
2015                 rf->rf_nrssi_slope = 0x10000;
2016         else
2017                 rf->rf_nrssi_slope = 0x400000 / (nrssi[0] - nrssi[1]);
2018         if (nrssi[0] >= -4) {
2019                 rf->rf_nrssi[0] = nrssi[1];
2020                 rf->rf_nrssi[1] = nrssi[0];
2021         }
2022
2023         /*
2024          * Restore saved RF/PHY registers
2025          */
2026         if (phy->phy_rev >= 3) {
2027                 for (phy3_idx = 0; phy3_idx < 4; ++phy3_idx) {
2028                         PHY_WRITE(mac, save_phy3_regs[phy3_idx],
2029                                   save_phy3[phy3_idx]);
2030                 }
2031         }
2032         if (phy->phy_rev >= 2) {
2033                 PHY_CLRBITS(mac, 0x812, 0x30);
2034                 PHY_CLRBITS(mac, 0x811, 0x30);
2035         }
2036
2037         for (i = 0; i < SAVE_RF_MAX; ++i)
2038                 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
2039
2040         CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
2041         CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
2042         CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
2043
2044         for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
2045                 PHY_WRITE(mac, save_phy_comm_regs[i], save_phy_comm[i]);
2046
2047         bwi_rf_workaround(mac, rf->rf_curchan);
2048         PHY_SETBITS(mac, 0x802, 0x3);
2049         bwi_set_gains(mac, NULL);
2050         PHY_SETBITS(mac, 0x429, 0x8000);
2051
2052         if (phy->phy_rev >= 3) {
2053                 for (; phy3_idx < SAVE_PHY3_MAX; ++phy3_idx) {
2054                         PHY_WRITE(mac, save_phy3_regs[phy3_idx],
2055                                   save_phy3[phy3_idx]);
2056                 }
2057         }
2058
2059         bwi_rf_init_sw_nrssi_table(mac);
2060         bwi_rf_set_nrssi_thr_11g(mac);
2061
2062 #undef SAVE_RF_MAX
2063 #undef SAVE_PHY_COMM_MAX
2064 #undef SAVE_PHY3_MAX
2065 }
2066
2067 static void
2068 bwi_rf_init_sw_nrssi_table(struct bwi_mac *mac)
2069 {
2070         struct bwi_rf *rf = &mac->mac_rf;
2071         int d, i;
2072
2073         d = 0x1f - rf->rf_nrssi[0];
2074         for (i = 0; i < BWI_NRSSI_TBLSZ; ++i) {
2075                 int val;
2076
2077                 val = (((i - d) * rf->rf_nrssi_slope) / 0x10000) + 0x3a;
2078                 if (val < 0)
2079                         val = 0;
2080                 else if (val > 0x3f)
2081                         val = 0x3f;
2082
2083                 rf->rf_nrssi_table[i] = val;
2084         }
2085 }
2086
2087 void
2088 bwi_rf_init_hw_nrssi_table(struct bwi_mac *mac, uint16_t adjust)
2089 {
2090         int i;
2091
2092         for (i = 0; i < BWI_NRSSI_TBLSZ; ++i) {
2093                 int16_t val;
2094
2095                 val = bwi_nrssi_read(mac, i);
2096
2097                 val -= adjust;
2098                 if (val < -32)
2099                         val = -32;
2100                 else if (val > 31)
2101                         val = 31;
2102
2103                 bwi_nrssi_write(mac, i, val);
2104         }
2105 }
2106
2107 static void
2108 bwi_rf_set_nrssi_thr_11b(struct bwi_mac *mac)
2109 {
2110         struct bwi_rf *rf = &mac->mac_rf;
2111         int32_t thr;
2112
2113         if (rf->rf_type != BWI_RF_T_BCM2050 ||
2114             (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) == 0)
2115                 return;
2116
2117         /*
2118          * Calculate nrssi threshold
2119          */
2120         if (rf->rf_rev >= 6) {
2121                 thr = (rf->rf_nrssi[1] - rf->rf_nrssi[0]) * 32;
2122                 thr += 20 * (rf->rf_nrssi[0] + 1);
2123                 thr /= 40;
2124         } else {
2125                 thr = rf->rf_nrssi[1] - 5;
2126         }
2127         if (thr < 0)
2128                 thr = 0;
2129         else if (thr > 0x3e)
2130                 thr = 0x3e;
2131
2132         PHY_READ(mac, BWI_PHYR_NRSSI_THR_11B);  /* dummy read */
2133         PHY_WRITE(mac, BWI_PHYR_NRSSI_THR_11B, (((uint16_t)thr) << 8) | 0x1c);
2134
2135         if (rf->rf_rev >= 6) {
2136                 PHY_WRITE(mac, 0x87, 0xe0d);
2137                 PHY_WRITE(mac, 0x86, 0xc0b);
2138                 PHY_WRITE(mac, 0x85, 0xa09);
2139                 PHY_WRITE(mac, 0x84, 0x808);
2140                 PHY_WRITE(mac, 0x83, 0x808);
2141                 PHY_WRITE(mac, 0x82, 0x604);
2142                 PHY_WRITE(mac, 0x81, 0x302);
2143                 PHY_WRITE(mac, 0x80, 0x100);
2144         }
2145 }
2146
2147 static __inline int32_t
2148 _nrssi_threshold(const struct bwi_rf *rf, int32_t val)
2149 {
2150         val *= (rf->rf_nrssi[1] - rf->rf_nrssi[0]);
2151         val += (rf->rf_nrssi[0] << 6);
2152         if (val < 32)
2153                 val += 31;
2154         else
2155                 val += 32;
2156         val >>= 6;
2157         if (val < -31)
2158                 val = -31;
2159         else if (val > 31)
2160                 val = 31;
2161         return val;
2162 }
2163
2164 static void
2165 bwi_rf_set_nrssi_thr_11g(struct bwi_mac *mac)
2166 {
2167         int32_t thr1, thr2;
2168         uint16_t thr;
2169
2170         /*
2171          * Find the two nrssi thresholds
2172          */
2173         if ((mac->mac_phy.phy_flags & BWI_PHY_F_LINKED) == 0 ||
2174             (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) == 0) {
2175                 int16_t nrssi;
2176
2177                 nrssi = bwi_nrssi_read(mac, 0x20);
2178                 if (nrssi >= 32)
2179                         nrssi -= 64;
2180
2181                 if (nrssi < 3) {
2182                         thr1 = 0x2b;
2183                         thr2 = 0x27;
2184                 } else {
2185                         thr1 = 0x2d;
2186                         thr2 = 0x2b;
2187                 }
2188         } else {
2189                 /* TODO Interfere mode */
2190                 thr1 = _nrssi_threshold(&mac->mac_rf, 0x11);
2191                 thr2 = _nrssi_threshold(&mac->mac_rf, 0xe);
2192         }
2193
2194 #define NRSSI_THR1_MASK __BITS(5, 0)
2195 #define NRSSI_THR2_MASK __BITS(11, 6)
2196
2197         thr = __SHIFTIN((uint32_t)thr1, NRSSI_THR1_MASK) |
2198               __SHIFTIN((uint32_t)thr2, NRSSI_THR2_MASK);
2199         PHY_FILT_SETBITS(mac, BWI_PHYR_NRSSI_THR_11G, 0xf000, thr);
2200
2201 #undef NRSSI_THR1_MASK
2202 #undef NRSSI_THR2_MASK
2203 }
2204
2205 void
2206 bwi_rf_clear_tssi(struct bwi_mac *mac)
2207 {
2208         /* XXX use function pointer */
2209         if (mac->mac_phy.phy_mode == IEEE80211_MODE_11A) {
2210                 /* TODO:11A */
2211         } else {
2212                 uint16_t val;
2213                 int i;
2214
2215                 val = __SHIFTIN(BWI_INVALID_TSSI, BWI_LO_TSSI_MASK) |
2216                       __SHIFTIN(BWI_INVALID_TSSI, BWI_HI_TSSI_MASK);
2217
2218                 for (i = 0; i < 2; ++i) {
2219                         MOBJ_WRITE_2(mac, BWI_COMM_MOBJ,
2220                                 BWI_COMM_MOBJ_TSSI_DS + (i * 2), val);
2221                 }
2222
2223                 for (i = 0; i < 2; ++i) {
2224                         MOBJ_WRITE_2(mac, BWI_COMM_MOBJ,
2225                                 BWI_COMM_MOBJ_TSSI_OFDM + (i * 2), val);
2226                 }
2227         }
2228 }
2229
2230 void
2231 bwi_rf_clear_state(struct bwi_rf *rf)
2232 {
2233         int i;
2234
2235         rf->rf_flags &= ~BWI_RF_CLEAR_FLAGS;
2236         bzero(rf->rf_lo, sizeof(rf->rf_lo));
2237         bzero(rf->rf_lo_used, sizeof(rf->rf_lo_used));
2238
2239         rf->rf_nrssi_slope = 0;
2240         rf->rf_nrssi[0] = BWI_INVALID_NRSSI;
2241         rf->rf_nrssi[1] = BWI_INVALID_NRSSI;
2242
2243         for (i = 0; i < BWI_NRSSI_TBLSZ; ++i)
2244                 rf->rf_nrssi_table[i] = i;
2245
2246         rf->rf_lo_gain = 0;
2247         rf->rf_rx_gain = 0;
2248
2249         bcopy(rf->rf_txpower_map0, rf->rf_txpower_map,
2250               sizeof(rf->rf_txpower_map));
2251         rf->rf_idle_tssi = rf->rf_idle_tssi0;
2252 }
2253
2254 static void
2255 bwi_rf_on_11a(struct bwi_mac *mac)
2256 {
2257         /* TODO:11A */
2258 }
2259
2260 static void
2261 bwi_rf_on_11bg(struct bwi_mac *mac)
2262 {
2263         struct bwi_phy *phy = &mac->mac_phy;
2264
2265         PHY_WRITE(mac, 0x15, 0x8000);
2266         PHY_WRITE(mac, 0x15, 0xcc00);
2267         if (phy->phy_flags & BWI_PHY_F_LINKED)
2268                 PHY_WRITE(mac, 0x15, 0xc0);
2269         else
2270                 PHY_WRITE(mac, 0x15, 0);
2271
2272         bwi_rf_set_chan(mac, 6 /* XXX */, 1);
2273 }
2274
2275 void
2276 bwi_rf_set_ant_mode(struct bwi_mac *mac, int ant_mode)
2277 {
2278         struct bwi_softc *sc = mac->mac_sc;
2279         struct bwi_phy *phy = &mac->mac_phy;
2280         uint16_t val;
2281
2282         KKASSERT(ant_mode == BWI_ANT_MODE_0 ||
2283                  ant_mode == BWI_ANT_MODE_1 ||
2284                  ant_mode == BWI_ANT_MODE_AUTO);
2285
2286         HFLAGS_CLRBITS(mac, BWI_HFLAG_AUTO_ANTDIV);
2287
2288         if (phy->phy_mode == IEEE80211_MODE_11B) {
2289                 /* NOTE: v4/v3 conflicts, take v3 */
2290                 if (mac->mac_rev == 2)
2291                         val = BWI_ANT_MODE_AUTO;
2292                 else
2293                         val = ant_mode;
2294                 val <<= 7;
2295                 PHY_FILT_SETBITS(mac, 0x3e2, 0xfe7f, val);
2296         } else {        /* 11a/g */
2297                 /* XXX reg/value naming */
2298                 val = ant_mode << 7;
2299                 PHY_FILT_SETBITS(mac, 0x401, 0x7e7f, val);
2300
2301                 if (ant_mode == BWI_ANT_MODE_AUTO)
2302                         PHY_CLRBITS(mac, 0x42b, 0x100);
2303
2304                 if (phy->phy_mode == IEEE80211_MODE_11A) {
2305                         /* TODO:11A */
2306                 } else {        /* 11g */
2307                         if (ant_mode == BWI_ANT_MODE_AUTO)
2308                                 PHY_SETBITS(mac, 0x48c, 0x2000);
2309                         else
2310                                 PHY_CLRBITS(mac, 0x48c, 0x2000);
2311
2312                         if (phy->phy_rev >= 2) {
2313                                 PHY_SETBITS(mac, 0x461, 0x10);
2314                                 PHY_FILT_SETBITS(mac, 0x4ad, 0xff00, 0x15);
2315                                 if (phy->phy_rev == 2) {
2316                                         PHY_WRITE(mac, 0x427, 0x8);
2317                                 } else {
2318                                         PHY_FILT_SETBITS(mac, 0x427,
2319                                                          0xff00, 0x8);
2320                                 }
2321
2322                                 if (phy->phy_rev >= 6)
2323                                         PHY_WRITE(mac, 0x49b, 0xdc);
2324                         }
2325                 }
2326         }
2327
2328         /* XXX v4 set AUTO_ANTDIV unconditionally */
2329         if (ant_mode == BWI_ANT_MODE_AUTO)
2330                 HFLAGS_SETBITS(mac, BWI_HFLAG_AUTO_ANTDIV);
2331
2332         val = ant_mode << 8;
2333         MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_BEACON,
2334                             0xfc3f, val);
2335         MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_ACK,
2336                             0xfc3f, val);
2337         MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_PROBE_RESP,
2338                             0xfc3f, val);
2339
2340         /* XXX what's these */
2341         if (phy->phy_mode == IEEE80211_MODE_11B)
2342                 CSR_SETBITS_2(sc, 0x5e, 0x4);
2343
2344         CSR_WRITE_4(sc, 0x100, 0x1000000);
2345         if (mac->mac_rev < 5)
2346                 CSR_WRITE_4(sc, 0x10c, 0x1000000);
2347
2348         mac->mac_rf.rf_ant_mode = ant_mode;
2349 }
2350
2351 int
2352 bwi_rf_get_latest_tssi(struct bwi_mac *mac, int8_t tssi[], uint16_t ofs)
2353 {
2354         int i;
2355
2356         for (i = 0; i < 4; ) {
2357                 uint16_t val;
2358
2359                 val = MOBJ_READ_2(mac, BWI_COMM_MOBJ, ofs + i);
2360                 tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_LO_TSSI_MASK);
2361                 tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_HI_TSSI_MASK);
2362         }
2363
2364         for (i = 0; i < 4; ++i) {
2365                 if (tssi[i] == BWI_INVALID_TSSI)
2366                         return EINVAL;
2367         }
2368         return 0;
2369 }
2370
2371 int
2372 bwi_rf_tssi2dbm(struct bwi_mac *mac, int8_t tssi, int8_t *txpwr)
2373 {
2374         struct bwi_rf *rf = &mac->mac_rf;
2375         int pwr_idx;
2376
2377         pwr_idx = rf->rf_idle_tssi + (int)tssi - rf->rf_base_tssi;
2378 #if 0
2379         if (pwr_idx < 0 || pwr_idx >= BWI_TSSI_MAX)
2380                 return EINVAL;
2381 #else
2382         if (pwr_idx < 0)
2383                 pwr_idx = 0;
2384         else if (pwr_idx >= BWI_TSSI_MAX)
2385                 pwr_idx = BWI_TSSI_MAX - 1;
2386 #endif
2387
2388         *txpwr = rf->rf_txpower_map[pwr_idx];
2389         return 0;
2390 }
2391
2392 static int
2393 bwi_rf_calc_rssi_bcm2050(struct bwi_mac *mac, const struct bwi_rxbuf_hdr *hdr)
2394 {
2395         uint16_t flags1, flags3;
2396         int rssi, lna_gain;
2397
2398         rssi = hdr->rxh_rssi;
2399         flags1 = le16toh(hdr->rxh_flags1);
2400         flags3 = le16toh(hdr->rxh_flags3);
2401
2402 #define NEW_BCM2050_RSSI
2403 #ifdef NEW_BCM2050_RSSI
2404         if (flags1 & BWI_RXH_F1_OFDM) {
2405                 if (rssi > 127)
2406                         rssi -= 256;
2407                 if (flags3 & BWI_RXH_F3_BCM2050_RSSI)
2408                         rssi += 17;
2409                 else
2410                         rssi -= 4;
2411                 return rssi;
2412         }
2413
2414         if (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) {
2415                 struct bwi_rf *rf = &mac->mac_rf;
2416
2417                 if (rssi >= BWI_NRSSI_TBLSZ)
2418                         rssi = BWI_NRSSI_TBLSZ - 1;
2419
2420                 rssi = ((31 - (int)rf->rf_nrssi_table[rssi]) * -131) / 128;
2421                 rssi -= 67;
2422         } else {
2423                 rssi = ((31 - rssi) * -149) / 128;
2424                 rssi -= 68;
2425         }
2426
2427         if (mac->mac_phy.phy_mode != IEEE80211_MODE_11G)
2428                 return rssi;
2429
2430         if (flags3 & BWI_RXH_F3_BCM2050_RSSI)
2431                 rssi += 20;
2432
2433         lna_gain = __SHIFTOUT(le16toh(hdr->rxh_phyinfo),
2434                               BWI_RXH_PHYINFO_LNAGAIN);
2435         DPRINTF(mac->mac_sc, BWI_DBG_RF | BWI_DBG_RX,
2436                 "lna_gain %d, phyinfo 0x%04x\n",
2437                 lna_gain, le16toh(hdr->rxh_phyinfo));
2438         switch (lna_gain) {
2439         case 0:
2440                 rssi += 27;
2441                 break;
2442         case 1:
2443                 rssi += 6;
2444                 break;
2445         case 2:
2446                 rssi += 12;
2447                 break;
2448         case 3:
2449                 /*
2450                  * XXX
2451                  * According to v3 spec, we should do _nothing_ here,
2452                  * but it seems that the result RSSI will be too low
2453                  * (relative to what ath(4) says).  Raise it a little
2454                  * bit.
2455                  */
2456                 rssi += 5;
2457                 break;
2458         default:
2459                 panic("impossible lna gain %d", lna_gain);
2460         }
2461 #else   /* !NEW_BCM2050_RSSI */
2462         lna_gain = 0; /* shut up gcc warning */
2463
2464         if (flags1 & BWI_RXH_F1_OFDM) {
2465                 if (rssi > 127)
2466                         rssi -= 256;
2467                 rssi = (rssi * 73) / 64;
2468
2469                 if (flags3 & BWI_RXH_F3_BCM2050_RSSI)
2470                         rssi += 25;
2471                 else
2472                         rssi -= 3;
2473                 return rssi;
2474         }
2475
2476         if (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) {
2477                 struct bwi_rf *rf = &mac->mac_rf;
2478
2479                 if (rssi >= BWI_NRSSI_TBLSZ)
2480                         rssi = BWI_NRSSI_TBLSZ - 1;
2481
2482                 rssi = ((31 - (int)rf->rf_nrssi_table[rssi]) * -131) / 128;
2483                 rssi -= 57;
2484         } else {
2485                 rssi = ((31 - rssi) * -149) / 128;
2486                 rssi -= 68;
2487         }
2488
2489         if (mac->mac_phy.phy_mode != IEEE80211_MODE_11G)
2490                 return rssi;
2491
2492         if (flags3 & BWI_RXH_F3_BCM2050_RSSI)
2493                 rssi += 25;
2494 #endif  /* NEW_BCM2050_RSSI */
2495         return rssi;
2496 }
2497
2498 static int
2499 bwi_rf_calc_rssi_bcm2053(struct bwi_mac *mac, const struct bwi_rxbuf_hdr *hdr)
2500 {
2501         uint16_t flags1;
2502         int rssi;
2503
2504         rssi = (((int)hdr->rxh_rssi - 11) * 103) / 64;
2505
2506         flags1 = le16toh(hdr->rxh_flags1);
2507         if (flags1 & BWI_RXH_F1_BCM2053_RSSI)
2508                 rssi -= 109;
2509         else
2510                 rssi -= 83;
2511         return rssi;
2512 }
2513
2514 static int
2515 bwi_rf_calc_rssi_bcm2060(struct bwi_mac *mac, const struct bwi_rxbuf_hdr *hdr)
2516 {
2517         int rssi;
2518
2519         rssi = hdr->rxh_rssi;
2520         if (rssi > 127)
2521                 rssi -= 256;
2522         return rssi;
2523 }
2524
2525 static uint16_t
2526 bwi_rf_lo_measure_11b(struct bwi_mac *mac)
2527 {
2528         uint16_t val;
2529         int i;
2530
2531         val = 0;
2532         for (i = 0; i < 10; ++i) {
2533                 PHY_WRITE(mac, 0x15, 0xafa0);
2534                 DELAY(1);
2535                 PHY_WRITE(mac, 0x15, 0xefa0);
2536                 DELAY(10);
2537                 PHY_WRITE(mac, 0x15, 0xffa0);
2538                 DELAY(40);
2539
2540                 val += PHY_READ(mac, 0x2c);
2541         }
2542         return val;
2543 }
2544
2545 static void
2546 bwi_rf_lo_update_11b(struct bwi_mac *mac)
2547 {
2548         struct bwi_softc *sc = mac->mac_sc;
2549         struct bwi_rf *rf = &mac->mac_rf;
2550         struct rf_saveregs regs;
2551         uint16_t rf_val, phy_val, min_val, val;
2552         uint16_t rf52, bphy_ctrl;
2553         int i;
2554
2555         DPRINTF(sc, BWI_DBG_RF | BWI_DBG_INIT, "%s enter\n", __func__);
2556
2557         bzero(&regs, sizeof(regs));
2558         bphy_ctrl = 0;
2559
2560         /*
2561          * Save RF/PHY registers for later restoration
2562          */
2563         SAVE_PHY_REG(mac, &regs, 15);
2564         rf52 = RF_READ(mac, 0x52) & 0xfff0;
2565         if (rf->rf_type == BWI_RF_T_BCM2050) {
2566                 SAVE_PHY_REG(mac, &regs, 0a);
2567                 SAVE_PHY_REG(mac, &regs, 2a);
2568                 SAVE_PHY_REG(mac, &regs, 35);
2569                 SAVE_PHY_REG(mac, &regs, 03);
2570                 SAVE_PHY_REG(mac, &regs, 01);
2571                 SAVE_PHY_REG(mac, &regs, 30);
2572
2573                 SAVE_RF_REG(mac, &regs, 43);
2574                 SAVE_RF_REG(mac, &regs, 7a);
2575
2576                 bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL);
2577
2578                 SAVE_RF_REG(mac, &regs, 52);
2579                 regs.rf_52 &= 0xf0;
2580
2581                 PHY_WRITE(mac, 0x30, 0xff);
2582                 CSR_WRITE_2(sc, BWI_PHY_CTRL, 0x3f3f);
2583                 PHY_WRITE(mac, 0x35, regs.phy_35 & 0xff7f);
2584                 RF_WRITE(mac, 0x7a, regs.rf_7a & 0xfff0);
2585         }
2586
2587         PHY_WRITE(mac, 0x15, 0xb000);
2588
2589         if (rf->rf_type == BWI_RF_T_BCM2050) {
2590                 PHY_WRITE(mac, 0x2b, 0x203);
2591                 PHY_WRITE(mac, 0x2a, 0x8a3);
2592         } else {
2593                 PHY_WRITE(mac, 0x2b, 0x1402);
2594         }
2595
2596         /*
2597          * Setup RF signal
2598          */
2599         rf_val = 0;
2600         min_val = UINT16_MAX;
2601
2602         for (i = 0; i < 4; ++i) {
2603                 RF_WRITE(mac, 0x52, rf52 | i);
2604                 bwi_rf_lo_measure_11b(mac);     /* Ignore return value */
2605         }
2606         for (i = 0; i < 10; ++i) {
2607                 RF_WRITE(mac, 0x52, rf52 | i);
2608
2609                 val = bwi_rf_lo_measure_11b(mac) / 10;
2610                 if (val < min_val) {
2611                         min_val = val;
2612                         rf_val = i;
2613                 }
2614         }
2615         RF_WRITE(mac, 0x52, rf52 | rf_val);
2616
2617         /*
2618          * Setup PHY signal
2619          */
2620         phy_val = 0;
2621         min_val = UINT16_MAX;
2622
2623         for (i = -4; i < 5; i += 2) {
2624                 int j;
2625
2626                 for (j = -4; j < 5; j += 2) {
2627                         uint16_t phy2f;
2628
2629                         phy2f = (0x100 * i) + j;
2630                         if (j < 0)
2631                                 phy2f += 0x100;
2632                         PHY_WRITE(mac, 0x2f, phy2f);
2633
2634                         val = bwi_rf_lo_measure_11b(mac) / 10;
2635                         if (val < min_val) {
2636                                 min_val = val;
2637                                 phy_val = phy2f;
2638                         }
2639                 }
2640         }
2641         PHY_WRITE(mac, 0x2f, phy_val + 0x101);
2642
2643         /*
2644          * Restore saved RF/PHY registers
2645          */
2646         if (rf->rf_type == BWI_RF_T_BCM2050) {
2647                 RESTORE_PHY_REG(mac, &regs, 0a);
2648                 RESTORE_PHY_REG(mac, &regs, 2a);
2649                 RESTORE_PHY_REG(mac, &regs, 35);
2650                 RESTORE_PHY_REG(mac, &regs, 03);
2651                 RESTORE_PHY_REG(mac, &regs, 01);
2652                 RESTORE_PHY_REG(mac, &regs, 30);
2653
2654                 RESTORE_RF_REG(mac, &regs, 43);
2655                 RESTORE_RF_REG(mac, &regs, 7a);
2656
2657                 RF_FILT_SETBITS(mac, 0x52, 0xf, regs.rf_52);
2658
2659                 CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);
2660         }
2661         RESTORE_PHY_REG(mac, &regs, 15);
2662
2663         bwi_rf_workaround(mac, rf->rf_curchan);
2664 }