1 /**************************************************************************
3 ** $FreeBSD: src/sys/pci/pcisupport.c,v 1.154.2.15 2003/04/29 15:55:06 simokawa Exp $
4 ** $DragonFly: src/sys/bus/pci/pcisupport.c,v 1.2 2003/06/17 04:28:57 dillon Exp $
6 ** Device driver for DEC/INTEL PCI chipsets.
10 **-------------------------------------------------------------------------
12 ** Written for FreeBSD by
13 ** wolf@cologne.de Wolfgang Stanglmeier
14 ** se@mi.Uni-Koeln.de Stefan Esser
16 **-------------------------------------------------------------------------
18 ** Copyright (c) 1994,1995 Stefan Esser. All rights reserved.
20 ** Redistribution and use in source and binary forms, with or without
21 ** modification, are permitted provided that the following conditions
23 ** 1. Redistributions of source code must retain the above copyright
24 ** notice, this list of conditions and the following disclaimer.
25 ** 2. Redistributions in binary form must reproduce the above copyright
26 ** notice, this list of conditions and the following disclaimer in the
27 ** documentation and/or other materials provided with the distribution.
28 ** 3. The name of the author may not be used to endorse or promote products
29 ** derived from this software without specific prior written permission.
31 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
32 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
33 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
34 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
35 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
36 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
40 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 ***************************************************************************
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/malloc.h>
51 #include <sys/kernel.h>
54 #include <pci/pcivar.h>
55 #include <pci/pcireg.h>
58 #include <vm/vm_object.h>
61 /*---------------------------------------------------------
63 ** Intel chipsets for 486 / Pentium processor
65 **---------------------------------------------------------
68 static void chipset_attach(device_t dev, int unit);
80 fixbushigh_i1225(device_t dev)
84 sublementarybus = pci_read_config(dev, 0x41, 1);
85 if (sublementarybus != 0xff) {
86 pci_set_secondarybus(dev, sublementarybus + 1);
87 pci_set_subordinatebus(dev, sublementarybus + 1);
92 fixwsc_natoma(device_t dev)
96 pmccfg = pci_read_config(dev, 0x50, 2);
98 if (pmccfg & 0x8000) {
99 printf("Correcting Natoma config for SMP\n");
101 pci_write_config(dev, 0x50, pmccfg, 2);
104 if ((pmccfg & 0x8000) == 0) {
105 printf("Correcting Natoma config for non-SMP\n");
107 pci_write_config(dev, 0x50, pmccfg, 2);
114 #define M_XX 0 /* end of list */
115 #define M_EQ 1 /* mask and return true if equal */
116 #define M_NE 2 /* mask and return true if not equal */
117 #define M_TR 3 /* don't read config, always true */
118 #define M_EN 4 /* mask and print "enabled" if true, "disabled" if false */
119 #define M_NN 5 /* opposite sense of M_EN */
121 static const struct condmsg conf82425ex[] =
123 { 0x00, 0x00, 0x00, M_TR, "\tClock " },
124 { 0x50, 0x06, 0x00, M_EQ, "25" },
125 { 0x50, 0x06, 0x02, M_EQ, "33" },
126 { 0x50, 0x04, 0x04, M_EQ, "??", },
127 { 0x00, 0x00, 0x00, M_TR, "MHz, L1 Cache " },
128 { 0x50, 0x01, 0x00, M_EQ, "Disabled\n" },
129 { 0x50, 0x09, 0x01, M_EQ, "Write-through\n" },
130 { 0x50, 0x09, 0x09, M_EQ, "Write-back\n" },
132 { 0x00, 0x00, 0x00, M_TR, "\tL2 Cache " },
133 { 0x52, 0x07, 0x00, M_EQ, "Disabled" },
134 { 0x52, 0x0f, 0x01, M_EQ, "64KB Write-through" },
135 { 0x52, 0x0f, 0x02, M_EQ, "128KB Write-through" },
136 { 0x52, 0x0f, 0x03, M_EQ, "256KB Write-through" },
137 { 0x52, 0x0f, 0x04, M_EQ, "512KB Write-through" },
138 { 0x52, 0x0f, 0x01, M_EQ, "64KB Write-back" },
139 { 0x52, 0x0f, 0x02, M_EQ, "128KB Write-back" },
140 { 0x52, 0x0f, 0x03, M_EQ, "256KB Write-back" },
141 { 0x52, 0x0f, 0x04, M_EQ, "512KB Write-back" },
142 { 0x53, 0x01, 0x00, M_EQ, ", 3-" },
143 { 0x53, 0x01, 0x01, M_EQ, ", 2-" },
144 { 0x53, 0x06, 0x00, M_EQ, "3-3-3" },
145 { 0x53, 0x06, 0x02, M_EQ, "2-2-2" },
146 { 0x53, 0x06, 0x04, M_EQ, "1-1-1" },
147 { 0x53, 0x06, 0x06, M_EQ, "?-?-?" },
148 { 0x53, 0x18, 0x00, M_EQ, "/4-2-2-2\n" },
149 { 0x53, 0x18, 0x08, M_EQ, "/3-2-2-2\n" },
150 { 0x53, 0x18, 0x10, M_EQ, "/?-?-?-?\n" },
151 { 0x53, 0x18, 0x18, M_EQ, "/2-1-1-1\n" },
153 { 0x56, 0x00, 0x00, M_TR, "\tDRAM: " },
154 { 0x56, 0x02, 0x02, M_EQ, "Fast Code Read, " },
155 { 0x56, 0x04, 0x04, M_EQ, "Fast Data Read, " },
156 { 0x56, 0x08, 0x08, M_EQ, "Fast Write, " },
157 { 0x57, 0x20, 0x20, M_EQ, "Pipelined CAS" },
158 { 0x57, 0x2e, 0x00, M_NE, "\n\t" },
159 { 0x57, 0x00, 0x00, M_TR, "Timing: RAS: " },
160 { 0x57, 0x07, 0x00, M_EQ, "4" },
161 { 0x57, 0x07, 0x01, M_EQ, "3" },
162 { 0x57, 0x07, 0x02, M_EQ, "2" },
163 { 0x57, 0x07, 0x04, M_EQ, "1.5" },
164 { 0x57, 0x07, 0x05, M_EQ, "1" },
165 { 0x57, 0x00, 0x00, M_TR, " Clocks, CAS Read: " },
166 { 0x57, 0x18, 0x00, M_EQ, "3/1", },
167 { 0x57, 0x18, 0x00, M_EQ, "2/1", },
168 { 0x57, 0x18, 0x00, M_EQ, "1.5/0.5", },
169 { 0x57, 0x18, 0x00, M_EQ, "1/1", },
170 { 0x57, 0x00, 0x00, M_TR, ", CAS Write: " },
171 { 0x57, 0x20, 0x00, M_EQ, "2/1", },
172 { 0x57, 0x20, 0x20, M_EQ, "1/1", },
173 { 0x57, 0x00, 0x00, M_TR, "\n" },
175 { 0x40, 0x01, 0x01, M_EQ, "\tCPU-to-PCI Byte Merging\n" },
176 { 0x40, 0x02, 0x02, M_EQ, "\tCPU-to-PCI Bursting\n" },
177 { 0x40, 0x04, 0x04, M_EQ, "\tPCI Posted Writes\n" },
178 { 0x40, 0x20, 0x00, M_EQ, "\tDRAM Parity Disabled\n" },
180 { 0x48, 0x03, 0x01, M_EQ, "\tPCI IDE controller: Primary (1F0h-1F7h,3F6h,3F7h)" },
181 { 0x48, 0x03, 0x02, M_EQ, "\tPCI IDE controller: Secondary (170h-177h,376h,377h)" },
182 { 0x4d, 0x01, 0x01, M_EQ, "\tRTC (70-77h)\n" },
183 { 0x4d, 0x02, 0x02, M_EQ, "\tKeyboard (60,62,64,66h)\n" },
184 { 0x4d, 0x08, 0x08, M_EQ, "\tIRQ12/M Mouse Function\n" },
190 static const struct condmsg conf82424zx[] =
192 { 0x00, 0x00, 0x00, M_TR, "\tCPU: " },
193 { 0x50, 0xe0, 0x00, M_EQ, "486DX" },
194 { 0x50, 0xe0, 0x20, M_EQ, "486SX" },
195 { 0x50, 0xe0, 0x40, M_EQ, "486DX2 or 486DX4" },
196 { 0x50, 0xe0, 0x80, M_EQ, "Overdrive (writeback)" },
198 { 0x00, 0x00, 0x00, M_TR, ", bus=" },
199 { 0x50, 0x03, 0x00, M_EQ, "25MHz" },
200 { 0x50, 0x03, 0x01, M_EQ, "33MHz" },
201 { 0x53, 0x01, 0x01, M_TR, ", CPU->Memory posting "},
202 { 0x53, 0x01, 0x00, M_EQ, "OFF" },
203 { 0x53, 0x01, 0x01, M_EQ, "ON" },
205 { 0x56, 0x30, 0x00, M_NE, "\n\tWarning:" },
206 { 0x56, 0x20, 0x00, M_NE, " NO cache parity!" },
207 { 0x56, 0x10, 0x00, M_NE, " NO DRAM parity!" },
208 { 0x55, 0x04, 0x04, M_EQ, "\n\tWarning: refresh OFF! " },
210 { 0x00, 0x00, 0x00, M_TR, "\n\tCache: " },
211 { 0x52, 0x01, 0x00, M_EQ, "None" },
212 { 0x52, 0xc1, 0x01, M_EQ, "64KB" },
213 { 0x52, 0xc1, 0x41, M_EQ, "128KB" },
214 { 0x52, 0xc1, 0x81, M_EQ, "256KB" },
215 { 0x52, 0xc1, 0xc1, M_EQ, "512KB" },
216 { 0x52, 0x03, 0x01, M_EQ, " writethrough" },
217 { 0x52, 0x03, 0x03, M_EQ, " writeback" },
219 { 0x52, 0x01, 0x01, M_EQ, ", cache clocks=" },
220 { 0x52, 0x05, 0x01, M_EQ, "3-1-1-1" },
221 { 0x52, 0x05, 0x05, M_EQ, "2-1-1-1" },
223 { 0x00, 0x00, 0x00, M_TR, "\n\tDRAM:" },
224 { 0x55, 0x43, 0x00, M_NE, " page mode" },
225 { 0x55, 0x02, 0x02, M_EQ, " code fetch" },
226 { 0x55, 0x43, 0x43, M_EQ, "," },
227 { 0x55, 0x43, 0x42, M_EQ, " and" },
228 { 0x55, 0x40, 0x40, M_EQ, " read" },
229 { 0x55, 0x03, 0x03, M_EQ, " and" },
230 { 0x55, 0x43, 0x41, M_EQ, " and" },
231 { 0x55, 0x01, 0x01, M_EQ, " write" },
232 { 0x55, 0x43, 0x00, M_NE, "," },
234 { 0x00, 0x00, 0x00, M_TR, " memory clocks=" },
235 { 0x55, 0x20, 0x00, M_EQ, "X-2-2-2" },
236 { 0x55, 0x20, 0x20, M_EQ, "X-1-2-1" },
238 { 0x00, 0x00, 0x00, M_TR, "\n\tCPU->PCI: posting " },
239 { 0x53, 0x02, 0x00, M_NE, "ON" },
240 { 0x53, 0x02, 0x00, M_EQ, "OFF" },
241 { 0x00, 0x00, 0x00, M_TR, ", burst mode " },
242 { 0x54, 0x02, 0x00, M_NE, "ON" },
243 { 0x54, 0x02, 0x00, M_EQ, "OFF" },
244 { 0x00, 0x00, 0x00, M_TR, "\n\tPCI->Memory: posting " },
245 { 0x54, 0x01, 0x00, M_NE, "ON" },
246 { 0x54, 0x01, 0x00, M_EQ, "OFF" },
248 { 0x00, 0x00, 0x00, M_TR, "\n" },
254 static const struct condmsg conf82434lx[] =
256 { 0x00, 0x00, 0x00, M_TR, "\tCPU: " },
257 { 0x50, 0xe3, 0x82, M_EQ, "Pentium, 60MHz" },
258 { 0x50, 0xe3, 0x83, M_EQ, "Pentium, 66MHz" },
259 { 0x50, 0xe3, 0xa2, M_EQ, "Pentium, 90MHz" },
260 { 0x50, 0xe3, 0xa3, M_EQ, "Pentium, 100MHz" },
261 { 0x50, 0xc2, 0x82, M_NE, "(unknown)" },
262 { 0x50, 0x04, 0x00, M_EQ, " (primary cache OFF)" },
264 { 0x53, 0x01, 0x01, M_TR, ", CPU->Memory posting "},
265 { 0x53, 0x01, 0x01, M_NE, "OFF" },
266 { 0x53, 0x01, 0x01, M_EQ, "ON" },
268 { 0x53, 0x08, 0x00, M_NE, ", read around write"},
270 { 0x70, 0x04, 0x00, M_EQ, "\n\tWarning: Cache parity disabled!" },
271 { 0x57, 0x20, 0x00, M_NE, "\n\tWarning: DRAM parity mask!" },
272 { 0x57, 0x01, 0x00, M_EQ, "\n\tWarning: refresh OFF! " },
274 { 0x00, 0x00, 0x00, M_TR, "\n\tCache: " },
275 { 0x52, 0x01, 0x00, M_EQ, "None" },
276 { 0x52, 0x81, 0x01, M_EQ, "" },
277 { 0x52, 0xc1, 0x81, M_EQ, "256KB" },
278 { 0x52, 0xc1, 0xc1, M_EQ, "512KB" },
279 { 0x52, 0x03, 0x01, M_EQ, " writethrough" },
280 { 0x52, 0x03, 0x03, M_EQ, " writeback" },
282 { 0x52, 0x01, 0x01, M_EQ, ", cache clocks=" },
283 { 0x52, 0x21, 0x01, M_EQ, "3-2-2-2/4-2-2-2" },
284 { 0x52, 0x21, 0x21, M_EQ, "3-1-1-1" },
286 { 0x52, 0x01, 0x01, M_EQ, "\n\tCache flags: " },
287 { 0x52, 0x11, 0x11, M_EQ, " cache-all" },
288 { 0x52, 0x09, 0x09, M_EQ, " byte-control" },
289 { 0x52, 0x05, 0x05, M_EQ, " powersaver" },
291 { 0x00, 0x00, 0x00, M_TR, "\n\tDRAM:" },
292 { 0x57, 0x10, 0x00, M_EQ, " page mode" },
294 { 0x00, 0x00, 0x00, M_TR, " memory clocks=" },
295 { 0x57, 0xc0, 0x00, M_EQ, "X-4-4-4 (70ns)" },
296 { 0x57, 0xc0, 0x40, M_EQ, "X-4-4-4/X-3-3-3 (60ns)" },
297 { 0x57, 0xc0, 0x80, M_EQ, "???" },
298 { 0x57, 0xc0, 0xc0, M_EQ, "X-3-3-3 (50ns)" },
299 { 0x58, 0x02, 0x02, M_EQ, ", RAS-wait" },
300 { 0x58, 0x01, 0x01, M_EQ, ", CAS-wait" },
302 { 0x00, 0x00, 0x00, M_TR, "\n\tCPU->PCI: posting " },
303 { 0x53, 0x02, 0x02, M_EQ, "ON" },
304 { 0x53, 0x02, 0x00, M_EQ, "OFF" },
305 { 0x00, 0x00, 0x00, M_TR, ", burst mode " },
306 { 0x54, 0x02, 0x00, M_NE, "ON" },
307 { 0x54, 0x02, 0x00, M_EQ, "OFF" },
308 { 0x54, 0x04, 0x00, M_TR, ", PCI clocks=" },
309 { 0x54, 0x04, 0x00, M_EQ, "2-2-2-2" },
310 { 0x54, 0x04, 0x00, M_NE, "2-1-1-1" },
311 { 0x00, 0x00, 0x00, M_TR, "\n\tPCI->Memory: posting " },
312 { 0x54, 0x01, 0x00, M_NE, "ON" },
313 { 0x54, 0x01, 0x00, M_EQ, "OFF" },
315 { 0x57, 0x01, 0x01, M_EQ, "\n\tRefresh:" },
316 { 0x57, 0x03, 0x03, M_EQ, " CAS#/RAS#(Hidden)" },
317 { 0x57, 0x03, 0x01, M_EQ, " RAS#Only" },
318 { 0x57, 0x05, 0x05, M_EQ, " BurstOf4" },
320 { 0x00, 0x00, 0x00, M_TR, "\n" },
326 static const struct condmsg conf82378[] =
328 { 0x00, 0x00, 0x00, M_TR, "\tBus Modes:" },
329 { 0x41, 0x04, 0x04, M_EQ, " Bus Park," },
330 { 0x41, 0x02, 0x02, M_EQ, " Bus Lock," },
331 { 0x41, 0x02, 0x00, M_EQ, " Resource Lock," },
332 { 0x41, 0x01, 0x01, M_EQ, " GAT" },
333 { 0x4d, 0x20, 0x20, M_EQ, "\n\tCoprocessor errors enabled" },
334 { 0x4d, 0x10, 0x10, M_EQ, "\n\tMouse function enabled" },
336 { 0x4e, 0x30, 0x10, M_EQ, "\n\tIDE controller: Primary (1F0h-1F7h,3F6h,3F7h)" },
337 { 0x4e, 0x30, 0x30, M_EQ, "\n\tIDE controller: Secondary (170h-177h,376h,377h)" },
338 { 0x4e, 0x28, 0x08, M_EQ, "\n\tFloppy controller: 3F0h,3F1h " },
339 { 0x4e, 0x24, 0x04, M_EQ, "\n\tFloppy controller: 3F2h-3F7h " },
340 { 0x4e, 0x28, 0x28, M_EQ, "\n\tFloppy controller: 370h,371h " },
341 { 0x4e, 0x24, 0x24, M_EQ, "\n\tFloppy controller: 372h-377h " },
342 { 0x4e, 0x02, 0x02, M_EQ, "\n\tKeyboard controller: 60h,62h,64h,66h" },
343 { 0x4e, 0x01, 0x01, M_EQ, "\n\tRTC: 70h-77h" },
345 { 0x4f, 0x80, 0x80, M_EQ, "\n\tConfiguration RAM: 0C00h,0800h-08FFh" },
346 { 0x4f, 0x40, 0x40, M_EQ, "\n\tPort 92: enabled" },
347 { 0x4f, 0x03, 0x00, M_EQ, "\n\tSerial Port A: COM1 (3F8h-3FFh)" },
348 { 0x4f, 0x03, 0x01, M_EQ, "\n\tSerial Port A: COM2 (2F8h-2FFh)" },
349 { 0x4f, 0x0c, 0x00, M_EQ, "\n\tSerial Port B: COM1 (3F8h-3FFh)" },
350 { 0x4f, 0x0c, 0x04, M_EQ, "\n\tSerial Port B: COM2 (2F8h-2FFh)" },
351 { 0x4f, 0x30, 0x00, M_EQ, "\n\tParallel Port: LPT1 (3BCh-3BFh)" },
352 { 0x4f, 0x30, 0x04, M_EQ, "\n\tParallel Port: LPT2 (378h-37Fh)" },
353 { 0x4f, 0x30, 0x20, M_EQ, "\n\tParallel Port: LPT3 (278h-27Fh)" },
354 { 0x00, 0x00, 0x00, M_TR, "\n" },
360 static const struct condmsg conf82437fx[] =
362 /* PCON -- PCI Control Register */
363 { 0x00, 0x00, 0x00, M_TR, "\tCPU Inactivity timer: " },
364 { 0x50, 0xe0, 0xe0, M_EQ, "8" },
365 { 0x50, 0xe0, 0xd0, M_EQ, "7" },
366 { 0x50, 0xe0, 0xc0, M_EQ, "6" },
367 { 0x50, 0xe0, 0xb0, M_EQ, "5" },
368 { 0x50, 0xe0, 0xa0, M_EQ, "4" },
369 { 0x50, 0xe0, 0x90, M_EQ, "3" },
370 { 0x50, 0xe0, 0x80, M_EQ, "2" },
371 { 0x50, 0xe0, 0x00, M_EQ, "1" },
372 { 0x00, 0x00, 0x00, M_TR, " clocks\n\tPeer Concurrency: " },
373 { 0x50, 0x08, 0x08, M_EN, 0 },
374 { 0x00, 0x00, 0x00, M_TR, "\n\tCPU-to-PCI Write Bursting: " },
375 { 0x50, 0x04, 0x00, M_NN, 0 },
376 { 0x00, 0x00, 0x00, M_TR, "\n\tPCI Streaming: " },
377 { 0x50, 0x02, 0x00, M_NN, 0 },
378 { 0x00, 0x00, 0x00, M_TR, "\n\tBus Concurrency: " },
379 { 0x50, 0x01, 0x00, M_NN, 0 },
381 /* CC -- Cache Control Regsiter */
382 { 0x00, 0x00, 0x00, M_TR, "\n\tCache:" },
383 { 0x52, 0xc0, 0x80, M_EQ, " 512K" },
384 { 0x52, 0xc0, 0x40, M_EQ, " 256K" },
385 { 0x52, 0xc0, 0x00, M_EQ, " NO" },
386 { 0x52, 0x30, 0x00, M_EQ, " pipelined-burst" },
387 { 0x52, 0x30, 0x10, M_EQ, " burst" },
388 { 0x52, 0x30, 0x20, M_EQ, " asynchronous" },
389 { 0x52, 0x30, 0x30, M_EQ, " dual-bank pipelined-burst" },
390 { 0x00, 0x00, 0x00, M_TR, " secondary; L1 " },
391 { 0x52, 0x01, 0x00, M_EN, 0 },
392 { 0x00, 0x00, 0x00, M_TR, "\n" },
394 /* DRAMC -- DRAM Control Register */
395 { 0x57, 0x07, 0x00, M_EQ, "Warning: refresh OFF!\n" },
396 { 0x00, 0x00, 0x00, M_TR, "\tDRAM:" },
397 { 0x57, 0xc0, 0x00, M_EQ, " no memory hole" },
398 { 0x57, 0xc0, 0x40, M_EQ, " 512K-640K memory hole" },
399 { 0x57, 0xc0, 0x80, M_EQ, " 15M-16M memory hole" },
400 { 0x57, 0x07, 0x01, M_EQ, ", 50 MHz refresh" },
401 { 0x57, 0x07, 0x02, M_EQ, ", 60 MHz refresh" },
402 { 0x57, 0x07, 0x03, M_EQ, ", 66 MHz refresh" },
404 /* DRAMT = DRAM Timing Register */
405 { 0x00, 0x00, 0x00, M_TR, "\n\tRead burst timing: " },
406 { 0x58, 0x60, 0x00, M_EQ, "x-4-4-4/x-4-4-4" },
407 { 0x58, 0x60, 0x20, M_EQ, "x-3-3-3/x-4-4-4" },
408 { 0x58, 0x60, 0x40, M_EQ, "x-2-2-2/x-3-3-3" },
409 { 0x58, 0x60, 0x60, M_EQ, "???" },
410 { 0x00, 0x00, 0x00, M_TR, "\n\tWrite burst timing: " },
411 { 0x58, 0x18, 0x00, M_EQ, "x-4-4-4" },
412 { 0x58, 0x18, 0x08, M_EQ, "x-3-3-3" },
413 { 0x58, 0x18, 0x10, M_EQ, "x-2-2-2" },
414 { 0x58, 0x18, 0x18, M_EQ, "???" },
415 { 0x00, 0x00, 0x00, M_TR, "\n\tRAS-CAS delay: " },
416 { 0x58, 0x04, 0x00, M_EQ, "3" },
417 { 0x58, 0x04, 0x04, M_EQ, "2" },
418 { 0x00, 0x00, 0x00, M_TR, " clocks\n" },
424 static const struct condmsg conf82437vx[] =
426 /* PCON -- PCI Control Register */
427 { 0x00, 0x00, 0x00, M_TR, "\n\tPCI Concurrency: " },
428 { 0x50, 0x08, 0x08, M_EN, 0 },
430 /* CC -- Cache Control Regsiter */
431 { 0x00, 0x00, 0x00, M_TR, "\n\tCache:" },
432 { 0x52, 0xc0, 0x80, M_EQ, " 512K" },
433 { 0x52, 0xc0, 0x40, M_EQ, " 256K" },
434 { 0x52, 0xc0, 0x00, M_EQ, " NO" },
435 { 0x52, 0x30, 0x00, M_EQ, " pipelined-burst" },
436 { 0x52, 0x30, 0x10, M_EQ, " burst" },
437 { 0x52, 0x30, 0x20, M_EQ, " asynchronous" },
438 { 0x52, 0x30, 0x30, M_EQ, " dual-bank pipelined-burst" },
439 { 0x00, 0x00, 0x00, M_TR, " secondary; L1 " },
440 { 0x52, 0x01, 0x00, M_EN, 0 },
441 { 0x00, 0x00, 0x00, M_TR, "\n" },
443 /* DRAMC -- DRAM Control Register */
444 { 0x57, 0x07, 0x00, M_EQ, "Warning: refresh OFF!\n" },
445 { 0x00, 0x00, 0x00, M_TR, "\tDRAM:" },
446 { 0x57, 0xc0, 0x00, M_EQ, " no memory hole" },
447 { 0x57, 0xc0, 0x40, M_EQ, " 512K-640K memory hole" },
448 { 0x57, 0xc0, 0x80, M_EQ, " 15M-16M memory hole" },
449 { 0x57, 0x07, 0x01, M_EQ, ", 50 MHz refresh" },
450 { 0x57, 0x07, 0x02, M_EQ, ", 60 MHz refresh" },
451 { 0x57, 0x07, 0x03, M_EQ, ", 66 MHz refresh" },
453 /* DRAMT = DRAM Timing Register */
454 { 0x00, 0x00, 0x00, M_TR, "\n\tRead burst timing: " },
455 { 0x58, 0x60, 0x00, M_EQ, "x-4-4-4/x-4-4-4" },
456 { 0x58, 0x60, 0x20, M_EQ, "x-3-3-3/x-4-4-4" },
457 { 0x58, 0x60, 0x40, M_EQ, "x-2-2-2/x-3-3-3" },
458 { 0x58, 0x60, 0x60, M_EQ, "???" },
459 { 0x00, 0x00, 0x00, M_TR, "\n\tWrite burst timing: " },
460 { 0x58, 0x18, 0x00, M_EQ, "x-4-4-4" },
461 { 0x58, 0x18, 0x08, M_EQ, "x-3-3-3" },
462 { 0x58, 0x18, 0x10, M_EQ, "x-2-2-2" },
463 { 0x58, 0x18, 0x18, M_EQ, "???" },
464 { 0x00, 0x00, 0x00, M_TR, "\n\tRAS-CAS delay: " },
465 { 0x58, 0x04, 0x00, M_EQ, "3" },
466 { 0x58, 0x04, 0x04, M_EQ, "2" },
467 { 0x00, 0x00, 0x00, M_TR, " clocks\n" },
473 static const struct condmsg conf82371fb[] =
475 /* IORT -- ISA I/O Recovery Timer Register */
476 { 0x00, 0x00, 0x00, M_TR, "\tI/O Recovery Timing: 8-bit " },
477 { 0x4c, 0x40, 0x00, M_EQ, "3.5" },
478 { 0x4c, 0x78, 0x48, M_EQ, "1" },
479 { 0x4c, 0x78, 0x50, M_EQ, "2" },
480 { 0x4c, 0x78, 0x58, M_EQ, "3" },
481 { 0x4c, 0x78, 0x60, M_EQ, "4" },
482 { 0x4c, 0x78, 0x68, M_EQ, "5" },
483 { 0x4c, 0x78, 0x70, M_EQ, "6" },
484 { 0x4c, 0x78, 0x78, M_EQ, "7" },
485 { 0x4c, 0x78, 0x40, M_EQ, "8" },
486 { 0x00, 0x00, 0x00, M_TR, " clocks, 16-bit " },
487 { 0x4c, 0x04, 0x00, M_EQ, "3.5" },
488 { 0x4c, 0x07, 0x05, M_EQ, "1" },
489 { 0x4c, 0x07, 0x06, M_EQ, "2" },
490 { 0x4c, 0x07, 0x07, M_EQ, "3" },
491 { 0x4c, 0x07, 0x04, M_EQ, "4" },
492 { 0x00, 0x00, 0x00, M_TR, " clocks\n" },
494 /* XBCS -- X-Bus Chip Select Register */
495 { 0x00, 0x00, 0x00, M_TR, "\tExtended BIOS: " },
496 { 0x4e, 0x80, 0x80, M_EN, 0 },
497 { 0x00, 0x00, 0x00, M_TR, "\n\tLower BIOS: " },
498 { 0x4e, 0x40, 0x40, M_EN, 0 },
499 { 0x00, 0x00, 0x00, M_TR, "\n\tCoprocessor IRQ13: " },
500 { 0x4e, 0x20, 0x20, M_EN, 0 },
501 { 0x00, 0x00, 0x00, M_TR, "\n\tMouse IRQ12: " },
502 { 0x4e, 0x10, 0x10, M_EN, 0 },
503 { 0x00, 0x00, 0x00, M_TR, "\n" },
505 { 0x00, 0x00, 0x00, M_TR, "\tInterrupt Routing: " },
507 { 0x00, 0x00, 0x00, M_TR, n ": " }, \
508 { x, 0x80, 0x80, M_EQ, "disabled" }, \
509 { x, 0xc0, 0x40, M_EQ, "[shared] " }, \
510 { x, 0x8f, 0x03, M_EQ, "IRQ3" }, \
511 { x, 0x8f, 0x04, M_EQ, "IRQ4" }, \
512 { x, 0x8f, 0x05, M_EQ, "IRQ5" }, \
513 { x, 0x8f, 0x06, M_EQ, "IRQ6" }, \
514 { x, 0x8f, 0x07, M_EQ, "IRQ7" }, \
515 { x, 0x8f, 0x09, M_EQ, "IRQ9" }, \
516 { x, 0x8f, 0x0a, M_EQ, "IRQ10" }, \
517 { x, 0x8f, 0x0b, M_EQ, "IRQ11" }, \
518 { x, 0x8f, 0x0c, M_EQ, "IRQ12" }, \
519 { x, 0x8f, 0x0e, M_EQ, "IRQ14" }, \
520 { x, 0x8f, 0x0f, M_EQ, "IRQ15" }
522 /* Interrupt routing */
527 PIRQ(0x70, "\n\t\tMB0"),
530 { 0x00, 0x00, 0x00, M_TR, "\n" },
534 /* XXX - do DMA routing, too? */
538 static const struct condmsg conf82371fb2[] =
540 /* IDETM -- IDE Timing Register */
541 { 0x00, 0x00, 0x00, M_TR, "\tPrimary IDE: " },
542 { 0x41, 0x80, 0x80, M_EN, 0 },
543 { 0x00, 0x00, 0x00, M_TR, "\n\tSecondary IDE: " },
544 { 0x43, 0x80, 0x80, M_EN, 0 },
545 { 0x00, 0x00, 0x00, M_TR, "\n" },
552 writeconfig (device_t dev, const struct condmsg *tbl)
554 while (tbl->flags != M_XX) {
555 const char *text = 0;
557 if (tbl->flags == M_TR) {
560 unsigned char v = pci_read_config(dev, tbl->port, 1);
561 switch (tbl->flags) {
563 if ((v & tbl->mask) == tbl->value) text = tbl->text;
566 if ((v & tbl->mask) != tbl->value) text = tbl->text;
569 text = (v & tbl->mask) ? "enabled" : "disabled";
572 text = (v & tbl->mask) ? "disabled" : "enabled";
575 if (text) printf ("%s", text);
580 #ifdef DUMPCONFIGSPACE
582 dumpconfigspace (device_t dev)
585 printf ("configuration space registers:");
586 for (reg = 0; reg < 0x100; reg+=4) {
587 if ((reg & 0x0f) == 0)
588 printf ("\n%02x:\t", reg);
589 printf ("%08x ", pci_read_config(dev, reg, 4));
593 #endif /* DUMPCONFIGSPACE */
595 #endif /* PCI_QUIET */
599 chipset_attach (device_t dev, int unit)
605 switch (pci_get_devid(dev)) {
607 writeconfig (dev, conf82425ex);
610 writeconfig (dev, conf82424zx);
613 writeconfig (dev, conf82434lx);
616 writeconfig (dev, conf82378);
619 writeconfig (dev, conf82437fx);
622 writeconfig (dev, conf82437vx);
626 writeconfig (dev, conf82371fb);
630 writeconfig (dev, conf82371fb2);
633 case 0x00011011: /* DEC 21050 */
634 case 0x00221014: /* IBM xxx */
635 writeconfig (dev, conf_pci2pci);
639 #endif /* PCI_QUIET */
643 pci_bridge_type(device_t dev)
645 char *descr, tmpbuf[120];
647 if (pci_get_class(dev) != PCIC_BRIDGE)
650 switch (pci_get_subclass(dev)) {
651 case PCIS_BRIDGE_HOST: strcpy(tmpbuf, "Host to PCI"); break;
652 case PCIS_BRIDGE_ISA: strcpy(tmpbuf, "PCI to ISA"); break;
653 case PCIS_BRIDGE_EISA: strcpy(tmpbuf, "PCI to EISA"); break;
654 case PCIS_BRIDGE_MCA: strcpy(tmpbuf, "PCI to MCA"); break;
655 case PCIS_BRIDGE_PCI: strcpy(tmpbuf, "PCI to PCI"); break;
656 case PCIS_BRIDGE_PCMCIA: strcpy(tmpbuf, "PCI to PCMCIA"); break;
657 case PCIS_BRIDGE_NUBUS: strcpy(tmpbuf, "PCI to NUBUS"); break;
658 case PCIS_BRIDGE_CARDBUS: strcpy(tmpbuf, "PCI to CardBus"); break;
659 case PCIS_BRIDGE_OTHER: strcpy(tmpbuf, "PCI to Other"); break;
661 snprintf(tmpbuf, sizeof(tmpbuf),
662 "PCI to 0x%x", pci_get_subclass(dev));
665 snprintf(tmpbuf+strlen(tmpbuf), sizeof(tmpbuf)-strlen(tmpbuf),
666 " bridge (vendor=%04x device=%04x)",
667 pci_get_vendor(dev), pci_get_device(dev));
668 descr = malloc (strlen(tmpbuf) +1, M_DEVBUF, M_WAITOK);
669 strcpy(descr, tmpbuf);
674 pcib_match(device_t dev)
676 switch (pci_get_devid(dev)) {
677 /* Intel -- vendor 0x8086 */
679 return ("Intel 82443LX (440 LX) PCI-PCI (AGP) bridge");
681 return ("Intel 82443BX (440 BX) PCI-PCI (AGP) bridge");
683 return ("Intel 82443GX (440 GX) PCI-PCI (AGP) bridge");
685 return ("Intel 82454NX PCI Expander Bridge");
687 return ("Intel 82801BA/BAM (ICH2) PCI-PCI (AGP) bridge");
689 return ("Intel 82380FB mobile PCI to PCI bridge");
691 return ("Intel 82801AA (ICH) Hub to PCI bridge");
693 return ("Intel 82801AB (ICH0) Hub to PCI bridge");
695 return ("Intel 82801BA/BAM (ICH2) Hub to PCI bridge");
697 return ("Intel 82845 PCI-PCI (AGP) bridge");
699 /* VLSI -- vendor 0x1004 */
701 return ("VLSI 82C534 Eagle II PCI Bus bridge");
703 return ("VLSI 82C538 Eagle II PCI Docking bridge");
705 /* VIA Technologies -- vendor 0x1106 */
707 return ("VIA 8363 (Apollo KT133) PCI-PCI (AGP) bridge");
709 return ("VIA 82C598MVP (Apollo MVP3) PCI-PCI (AGP) bridge");
710 /* Exclude the ACPI function of VT82Cxxx series */
716 /* AcerLabs -- vendor 0x10b9 */
717 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
718 /* id is '10b9" but the register always shows "10b9". -Foxfair */
720 return ("AcerLabs M5247 PCI-PCI(AGP Supported) bridge");
721 case 0x524310b9:/* 5243 seems like 5247, need more info to divide*/
722 return ("AcerLabs M5243 PCI-PCI bridge");
724 /* AMD -- vendor 0x1022 */
726 return ("AMD-751 PCI-PCI (1x/2x AGP) bridge");
728 return ("AMD-761 PCI-PCI (4x AGP) bridge");
730 /* DEC -- vendor 0x1011 */
732 return ("DEC 21050 PCI-PCI bridge");
734 return ("DEC 21052 PCI-PCI bridge");
736 return ("DEC 21150 PCI-PCI bridge");
738 return ("DEC 21152 PCI-PCI bridge");
740 return ("DEC 21153 PCI-PCI bridge");
742 return ("DEC 21154 PCI-PCI bridge");
746 return ("IBM 82351 PCI-PCI bridge");
747 /* UMC United Microelectronics 0x1060 */
749 return ("UMC UM8881 HB4 486 PCI Chipset");
752 if (pci_get_class(dev) == PCIC_BRIDGE
753 && pci_get_subclass(dev) == PCIS_BRIDGE_PCI)
754 return pci_bridge_type(dev);
759 static int pcib_probe(device_t dev)
763 desc = pcib_match(dev);
765 device_set_desc_copy(dev, desc);
772 static int pcib_attach(device_t dev)
776 chipset_attach(dev, device_get_unit(dev));
778 secondary = pci_get_secondarybus(dev);
780 device_add_child(dev, "pci", secondary);
781 return bus_generic_attach(dev);
787 pcib_read_ivar(device_t dev, device_t child, int which, u_long *result)
789 if (which == PCIB_IVAR_HOSE) {
791 * Pass up to parent bus.
793 *result = pci_get_hose(dev);
800 * Route an interrupt across a PCI bridge.
803 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
809 device_printf(pcib, "Hi!\n");
813 * The PCI standard defines a swizzle of the child-side device/intpin
814 * to the parent-side intpin as follows.
816 * device = device on child bus
817 * child_intpin = intpin on child bus slot (0-3)
818 * parent_intpin = intpin on parent bus slot (0-3)
820 * parent_intpin = (device + child_intpin) % 4
822 parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4;
825 * Our parent is a PCI bus. Its parent must export the pci interface
826 * which includes the ability to route interrupts.
828 bus = device_get_parent(pcib);
829 intnum = PCI_ROUTE_INTERRUPT(device_get_parent(bus), pcib,
831 device_printf(pcib, "routed slot %d INT%c to irq %d\n",
832 pci_get_slot(dev), 'A' + pin - 1, intnum);
836 static device_method_t pcib_methods[] = {
837 /* Device interface */
838 DEVMETHOD(device_probe, pcib_probe),
839 DEVMETHOD(device_attach, pcib_attach),
840 DEVMETHOD(device_shutdown, bus_generic_shutdown),
841 DEVMETHOD(device_suspend, bus_generic_suspend),
842 DEVMETHOD(device_resume, bus_generic_resume),
845 DEVMETHOD(bus_print_child, bus_generic_print_child),
846 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
847 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
848 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
849 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
850 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
851 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
852 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
855 DEVMETHOD(pci_route_interrupt, pcib_route_interrupt),
859 static driver_t pcib_driver = {
865 static devclass_t pcib_devclass;
867 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
870 eisab_match(device_t dev)
872 switch (pci_get_devid(dev)) {
874 /* Recognize this specifically, it has PCI-HOST class (!) */
875 return ("Intel 82375EB PCI-EISA bridge");
877 if (pci_get_class(dev) == PCIC_BRIDGE
878 && pci_get_subclass(dev) == PCIS_BRIDGE_EISA)
879 return pci_bridge_type(dev);
885 isab_match(device_t dev)
889 switch (pci_get_devid(dev)) {
891 rev = pci_get_revid(dev);
893 return ("Intel 82378ZB PCI to ISA bridge");
894 return ("Intel 82378IB PCI to ISA bridge");
896 return ("Intel 82371FB PCI to ISA bridge");
898 return ("Intel 82371SB PCI to ISA bridge");
900 return ("Intel 82371AB PCI to ISA bridge");
902 return ("Intel 82443MX PCI to ISA bridge");
904 return ("Intel 82801AA (ICH) PCI to LPC bridge");
906 return ("Intel 82801AB (ICH0) PCI to LPC bridge");
908 return ("Intel 82801BA/BAM (ICH2) PCI to LPC bridge");
910 /* VLSI -- vendor 0x1004 */
912 return ("VLSI 82C593 PCI to ISA bridge");
914 /* VIA Technologies -- vendor 0x1106 */
915 case 0x05861106: /* south bridge section */
916 return ("VIA 82C586 PCI-ISA bridge");
918 return ("VIA 82C596B PCI-ISA bridge");
920 return ("VIA 82C686 PCI-ISA bridge");
922 /* AcerLabs -- vendor 0x10b9 */
923 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
924 /* id is '10b9" but the register always shows "10b9". -Foxfair */
926 return ("AcerLabs M1533 portable PCI-ISA bridge");
928 return ("AcerLabs M1543 desktop PCI-ISA bridge");
930 /* SiS -- vendor 0x1039 */
932 return ("SiS 85c503 PCI-ISA bridge");
934 /* Cyrix -- vendor 0x1078 */
936 return ("Cyrix Cx5510 PCI-ISA bridge");
938 return ("Cyrix Cx5530 PCI-ISA bridge");
940 /* NEC -- vendor 0x1033 */
941 /* The "C-bus" is 16-bits bus on PC98. */
943 return ("NEC 0001 PCI to PC-98 C-bus bridge");
945 return ("NEC 002C PCI to PC-98 C-bus bridge");
947 return ("NEC 003B PCI to PC-98 C-bus bridge");
948 /* UMC United Microelectronics 0x1060 */
950 return ("UMC UM8886 ISA Bridge with EIDE");
952 /* Cypress -- vendor 0x1080 */
954 if (pci_get_class(dev) == PCIC_BRIDGE
955 && pci_get_subclass(dev) == PCIS_BRIDGE_ISA)
956 return ("Cypress 82C693 PCI-ISA bridge");
959 /* ServerWorks -- vendor 0x1166 */
961 return ("ServerWorks IB6566 PCI to ISA bridge");
964 if (pci_get_class(dev) == PCIC_BRIDGE
965 && pci_get_subclass(dev) == PCIS_BRIDGE_ISA)
966 return pci_bridge_type(dev);
972 isab_probe(device_t dev)
978 desc = eisab_match(dev);
982 desc = isab_match(dev);
985 * For a PCI-EISA bridge, add both eisa and isa.
986 * Only add one instance of eisa or isa for now.
988 device_set_desc_copy(dev, desc);
989 if (is_eisa && !devclass_get_device(devclass_find("eisa"), 0))
990 device_add_child(dev, "eisa", -1);
992 if (!devclass_get_device(devclass_find("isa"), 0))
993 device_add_child(dev, "isa", -1);
1000 isab_attach(device_t dev)
1002 chipset_attach(dev, device_get_unit(dev));
1003 return bus_generic_attach(dev);
1006 static device_method_t isab_methods[] = {
1007 /* Device interface */
1008 DEVMETHOD(device_probe, isab_probe),
1009 DEVMETHOD(device_attach, isab_attach),
1010 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1011 DEVMETHOD(device_suspend, bus_generic_suspend),
1012 DEVMETHOD(device_resume, bus_generic_resume),
1015 DEVMETHOD(bus_print_child, bus_generic_print_child),
1016 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
1017 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
1018 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1019 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1020 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1021 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1026 static driver_t isab_driver = {
1032 static devclass_t isab_devclass;
1034 DRIVER_MODULE(isab, pci, isab_driver, isab_devclass, 0, 0);
1037 pci_usb_match(device_t dev)
1039 switch (pci_get_devid(dev)) {
1041 /* Intel -- vendor 0x8086 */
1043 return ("Intel 82371SB (PIIX3) USB controller");
1045 return ("Intel 82371AB/EB (PIIX4) USB controller");
1047 return ("Intel 82801AA (ICH) USB controller");
1049 return ("Intel 82801AB (ICH0) USB controller");
1051 return ("Intel 82801BA/BAM (ICH2) USB controller USB-A");
1053 return ("Intel 82801BA/BAM (ICH2) USB controller USB-B");
1055 /* VIA Technologies -- vendor 0x1106 (0x1107 on the Apollo Master) */
1057 return ("VIA 83C572 USB controller");
1059 /* AcerLabs -- vendor 0x10b9 */
1061 return ("AcerLabs M5237 (Aladdin-V) USB controller");
1063 /* OPTi -- vendor 0x1045 */
1065 return ("OPTi 82C861 (FireLink) USB controller");
1067 /* NEC -- vendor 0x1033 */
1069 return ("NEC uPD 9210 USB controller");
1071 /* CMD Tech -- vendor 0x1095 */
1073 return ("CMD Tech 670 (USB0670) USB controller");
1075 return ("CMD Tech 673 (USB0673) USB controller");
1078 if (pci_get_class(dev) == PCIC_SERIALBUS
1079 && pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
1080 if (pci_get_progif(dev) == 0x00 /* UHCI */ ) {
1081 return ("UHCI USB controller");
1082 } else if (pci_get_progif(dev) == 0x10 /* OHCI */ ) {
1083 return ("OHCI USB controller");
1085 return ("USB controller");
1092 pci_ata_match(device_t dev)
1095 switch (pci_get_devid(dev)) {
1097 /* Intel -- vendor 0x8086 */
1099 return ("Intel PIIX ATA controller");
1101 return ("Intel PIIX3 ATA controller");
1103 return ("Intel PIIX4 ATA controller");
1105 return ("Intel 82371MX mobile PCI ATA accelerator (MPIIX)");
1107 /* Promise -- vendor 0x105a */
1109 return ("Promise Ultra/33 ATA controller");
1111 return ("Promise Ultra/66 ATA controller");
1113 /* AcerLabs -- vendor 0x10b9 */
1115 return ("AcerLabs Aladdin ATA controller");
1117 /* VIA Technologies -- vendor 0x1106 (0x1107 on the Apollo Master) */
1119 switch (pci_read_config(dev, 0x08, 1)) {
1121 return ("VIA 85C586 ATA controller");
1123 return ("VIA 85C586 ATA controller");
1127 return ("VIA Apollo ATA controller");
1129 /* CMD Tech -- vendor 0x1095 */
1131 return ("CMD 640 ATA controller");
1133 return ("CMD 646 ATA controller");
1135 /* Cypress -- vendor 0x1080 */
1137 return ("Cypress 82C693 ATA controller");
1139 /* Cyrix -- vendor 0x1078 */
1141 return ("Cyrix 5530 ATA controller");
1143 /* SiS -- vendor 0x1039 */
1145 return ("SiS 5591 ATA controller");
1147 /* Highpoint tech -- vendor 0x1103 */
1149 return ("HighPoint HPT366 ATA controller");
1152 if (pci_get_class(dev) == PCIC_STORAGE &&
1153 pci_get_subclass(dev) == PCIS_STORAGE_IDE)
1154 return ("Unknown PCI ATA controller");
1161 chip_match(device_t dev)
1165 switch (pci_get_devid(dev)) {
1166 /* Intel -- vendor 0x8086 */
1168 /* Silently ignore this one! What is it, anyway ??? */
1172 * On my laptop (Tecra 8000DVD), this device has a
1173 * bogus subclass 0x80 so make sure that it doesn't
1174 * match the generic 'chip' driver by accident.
1178 fixbushigh_i1225(dev);
1179 return ("Intel 824?? host to PCI bridge");
1181 return ("Intel 82443LX (440 LX) host to PCI bridge");
1183 return ("Intel 82443BX (440 BX) host to PCI bridge");
1185 return ("Intel 82443BX host to PCI bridge (AGP disabled)");
1187 return ("Intel 82443GX host to PCI bridge");
1189 return ("Intel 82443GX host to AGP bridge");
1191 return ("Intel 82443GX host to PCI bridge (AGP disabled)");
1193 return ("Intel 82454KX/GX (Orion) host to PCI bridge");
1195 return ("Intel 82451NX Memory and I/O controller");
1197 return ("Intel 82425EX PCI system controller");
1199 return ("Intel 82424ZX (Saturn) cache DRAM controller");
1201 rev = pci_get_revid(dev);
1202 if (rev == 16 || rev == 17)
1203 return ("Intel 82434NX (Neptune) PCI cache memory controller");
1204 return ("Intel 82434LX (Mercury) PCI cache memory controller");
1206 return ("Intel 82437FX PCI cache memory controller");
1208 return ("Intel 82437MX mobile PCI cache memory controller");
1210 return ("Intel 82439HX PCI cache memory controller");
1212 return ("Intel 82437VX PCI cache memory controller");
1214 return ("Intel 82439TX System controller (MTXC)");
1216 return ("Intel 82371AB Power management controller");
1218 return ("Intel 82443MX Power management controller");
1221 return ("Intel 82440FX (Natoma) PCI and memory controller");
1223 return ("Intel 82453KX/GX (Orion) PCI memory controller");
1225 return ("Intel 82810 (i810 GMCH) Host To Hub bridge");
1227 return ("Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge");
1229 return ("Intel 82810E (i810E GMCH) Host To Hub bridge");
1231 return ("Intel 82801AA (ICH) AC'97 Audio Controller");
1233 return ("Intel 82801AB (ICH0) AC'97 Audio Controller");
1235 /* Sony -- vendor 0x104d */
1237 return ("Sony CXD1947A FireWire Host Controller");
1239 /* SiS -- vendor 0x1039 */
1241 return ("SiS 85c496 PCI/VL Bridge");
1243 return ("SiS 85c501");
1245 return ("SiS 85c601");
1247 return ("SiS 5591 host to PCI bridge");
1249 return ("SiS 5591 host to AGP bridge");
1251 /* VLSI -- vendor 0x1004 */
1253 return ("VLSI 82C592 Host to PCI bridge");
1255 return ("VLSI 82C532 Eagle II Peripheral controller");
1257 return ("VLSI 82C535 Eagle II System controller");
1259 return ("VLSI 82C147 IrDA controller");
1261 /* VIA Technologies -- vendor 0x1106 (0x1107 on the Apollo Master) */
1263 return ("VIA 82C570 (Apollo Master) system controller");
1265 return ("VIA 82C585 (Apollo VP1/VPX) system controller");
1268 return ("VIA 82C595 (Apollo VP2) system controller");
1270 return ("VIA 82C597 (Apollo VP3) system controller");
1271 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */
1272 /* totally. Please let me know if anything wrong. -F */
1273 /* XXX need info on the MVP3 -- any takers? */
1275 return ("VIA 82C598MVP (Apollo MVP3) host bridge");
1281 return ("VIA 82C686 AC97 Audio");
1283 return ("VIA 82C686 AC97 Modem");
1285 /* AMD -- vendor 0x1022 */
1287 return ("AMD-751 host to PCI bridge");
1289 return ("AMD-761 host to PCI bridge");
1291 /* NEC -- vendor 0x1033 */
1293 return ("NEC 0002 PCI to PC-98 local bus bridge");
1295 return ("NEC 0016 PCI to PC-98 local bus bridge");
1297 /* AcerLabs -- vendor 0x10b9 */
1298 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
1299 /* id is '10b9" but the register always shows "10b9". -Foxfair */
1301 return ("AcerLabs M1541 (Aladdin-V) PCI host bridge");
1303 return ("AcerLabs M15x3 Power Management Unit");
1305 /* OPTi -- vendor 0x1045 */
1307 return ("Opti 82C557 (Viper-M) host to PCI bridge");
1309 return ("Opti 82C558 (Viper-M) ISA+IDE");
1311 return ("OPTi 82C822 host to PCI Bridge");
1313 /* Texas Instruments -- vendor 0x104c */
1315 return ("Texas Instruments PCI1225 CardBus controller");
1317 return ("Texas Instruments PCI1410 CardBus controller");
1319 return ("Texas Instruments PCI1420 CardBus controller");
1321 return ("Texas Instruments PCI1450 CardBus controller");
1323 return ("Texas Instruments PCI1451 CardBus controller");
1325 /* NeoMagic -- vendor 0x10c8 */
1327 return ("NeoMagic MagicMedia 256AX Audio controller");
1329 return ("NeoMagic MagicMedia 256ZX Audio controller");
1331 /* ESS Technology Inc -- vendor 0x125d */
1333 return ("ESS Technology Maestro 2E Audio controller");
1335 /* Toshiba -- vendor 0x1179 */
1337 return ("Toshiba Fast Infra Red controller");
1339 /* NEC -- vendor 0x1033 */
1341 /* PCI to C-bus bridge */
1342 /* The following chipsets are PCI to PC98 C-bus bridge.
1343 * The C-bus is the 16-bits bus on PC98 and it should be probed as
1344 * PCI to ISA bridge. Because class of the C-bus is not defined,
1345 * C-bus bridges are recognized as "other bridge." To make C-bus
1346 * bridge be recognized as ISA bridge, this function returns NULL.
1354 if (pci_get_class(dev) == PCIC_BRIDGE
1355 && pci_get_subclass(dev) != PCIS_BRIDGE_PCI
1356 && pci_get_subclass(dev) != PCIS_BRIDGE_ISA
1357 && pci_get_subclass(dev) != PCIS_BRIDGE_EISA)
1358 return pci_bridge_type(dev);
1363 static int chip_probe(device_t dev)
1367 desc = chip_match(dev);
1369 if (pci_get_class(dev) == PCIC_BRIDGE
1370 && pci_get_subclass(dev) == PCIS_BRIDGE_HOST) {
1372 * Suppress printing this device since the nexus
1373 * has already described it.
1378 device_set_desc_copy(dev, desc);
1379 return -10000; /* Low match priority */
1385 static int chip_attach(device_t dev)
1387 chipset_attach(dev, device_get_unit(dev));
1392 static device_method_t chip_methods[] = {
1393 /* Device interface */
1394 DEVMETHOD(device_probe, chip_probe),
1395 DEVMETHOD(device_attach, chip_attach),
1400 static driver_t chip_driver = {
1406 static devclass_t chip_devclass;
1408 DRIVER_MODULE(chip, pci, chip_driver, chip_devclass, 0, 0);
1410 /*---------------------------------------------------------
1412 ** Catchall driver for VGA devices
1414 ** By Garrett Wollman
1415 ** <wollman@halloran-eldar.lcs.mit.edu>
1417 **---------------------------------------------------------
1420 const char* pci_vga_match(device_t dev)
1422 u_int id = pci_get_devid(dev);
1423 const char *vendor, *chip, *type;
1425 vendor = chip = type = 0;
1426 switch (id & 0xffff) {
1431 chip = "i740"; break;
1435 vendor = "NeoMagic";
1438 chip = "MagicGraph 128ZV"; break;
1440 chip = "MagicGraph 128XD"; break;
1442 chip = "MagicMedia 256AV"; break;
1444 chip = "MagicMedia 256ZX"; break;
1449 type = "graphics accelerator";
1452 chip = "Voodoo"; break;
1454 chip = "Voodoo 2"; break;
1456 chip = "Voodoo Banshee"; break;
1458 chip = "Voodoo 3"; break;
1463 type = "graphics accelerator";
1466 chip = "MGA 2085PX"; break;
1468 chip = "MGA Millennium 2064W"; break;
1470 chip = "MGA 1024SG/1064SG/1164SG"; break;
1472 chip = "MGA Millennium II 2164W"; break;
1474 chip = "MGA Millennium II 2164WA-B AG"; break;
1476 chip = "MGA G200"; break;
1478 chip = "MGA G200 AGP"; break;
1480 chip = "MGA G400 AGP"; break;
1482 chip = "MGA Impression"; break;
1484 chip = "MGA G100"; break;
1486 chip = "MGA G100 AGP"; break;
1488 chip = "MGA G550 AGP"; break;
1494 type = "graphics accelerator";
1497 chip = "Mach32"; break;
1499 chip = "Mach64-CT"; break;
1501 chip = "Mach64-CX"; break;
1503 chip = "Mach64-ET"; break;
1506 chip = "Mach64-VT"; break;
1508 chip = "Mach64-GB"; break;
1510 chip = "Mach64-GD"; break;
1512 chip = "Mach64-GI"; break;
1514 chip = "Mach64-GM"; break;
1516 chip = "Mach64-GN"; break;
1518 chip = "Mach64-GO"; break;
1520 chip = "Mach64-GP"; break;
1522 chip = "Mach64-GQ"; break;
1524 chip = "Mach64-GR"; break;
1526 chip = "Mach64-GS"; break;
1528 chip = "Mach64-GT"; break;
1530 chip = "Mach64-GU"; break;
1532 chip = "Mach64-GV"; break;
1534 chip = "Mach64-GW"; break;
1536 chip = "Mach64-GX"; break;
1538 chip = "Mobility-1"; break;
1540 chip = "RageMobility-P/M"; break;
1542 chip = "Mach64-GZ"; break;
1544 chip = "Rage128-RE"; break;
1546 chip = "Rage128-RF"; break;
1548 chip = "Rage128-RK"; break;
1550 chip = "Rage128-RL"; break;
1554 vendor = "Avance Logic";
1557 chip = "ALG2301"; break;
1559 chip = "ALG2302"; break;
1563 vendor = "Tseng Labs";
1564 type = "graphics accelerator";
1570 chip = "ET4000 W32P"; break;
1572 chip = "ET6000/ET6100"; break;
1574 chip = "ET6300"; break;
1579 type = "graphics accelerator";
1582 chip = "P9000"; break;
1584 chip = "P9100"; break;
1588 vendor = "Cirrus Logic";
1591 chip = "GD7548"; break;
1593 chip = "GD7555"; break;
1595 chip = "GD7556"; break;
1597 chip = "GD5430"; break;
1600 chip = "GD5434"; break;
1602 chip = "GD5436"; break;
1604 chip = "GD5446"; break;
1606 chip = "GD5480"; break;
1608 chip = "GD5462"; break;
1611 chip = "GD5464"; break;
1613 chip = "GD5465"; break;
1615 chip = "GD7542"; break;
1617 chip = "GD7543"; break;
1619 chip = "GD7541"; break;
1624 break; /* let default deal with it */
1626 vendor = "Chips & Technologies";
1629 chip = "64310"; break;
1631 chip = "65545"; break;
1633 chip = "65548"; break;
1635 chip = "69000"; break;
1637 chip = "65550"; break;
1639 chip = "65554"; break;
1641 chip = "65555"; break;
1643 chip = "68554"; break;
1650 type = "PCI to PC-98 Core Graph bridge";
1658 chip = "86c201"; break;
1660 chip = "86c202"; break;
1662 chip = "86c205"; break;
1664 chip = "86c215"; break;
1666 chip = "86c225"; break;
1668 chip = "5597/98"; break;
1670 chip = "6326"; break;
1672 chip = "530/620"; break;
1676 vendor = "Number Nine";
1677 type = "graphics accelerator";
1680 chip = "Imagine 128"; break;
1682 chip = "Imagine 128 II"; break;
1686 vendor = "Alliance";
1689 chip = "PM6410"; break;
1691 chip = "PM6422"; break;
1693 chip = "PMAT24"; break;
1697 vendor = "Rendition Verite";
1700 chip = "V1000"; break;
1702 chip = "V2000"; break;
1706 vendor = "Sigma Designs";
1707 if ((id >> 16) == 0x6401)
1708 chip = "REALmagic64/GX";
1712 type = "graphics accelerator";
1715 chip = "Trio"; break;
1717 chip = "Aurora 64"; break;
1719 chip = "Trio 64UV+"; break;
1721 chip = "Trio 64V2/DX/GX"; break;
1723 chip = "Plato"; break;
1725 chip = "Trio3D"; break;
1727 chip = "868"; break;
1729 chip = "928"; break;
1732 chip = "864"; break;
1735 chip = "964"; break;
1737 chip = "968"; break;
1739 chip = "ViRGE"; break;
1741 chip = "ViRGE VX"; break;
1743 chip = "ViRGE DX/GX"; break;
1745 chip = "ViRGE GX2"; break;
1747 chip = "Trio3D/2X"; break;
1750 chip = "Savage3D"; break;
1752 chip = "Savage 4"; break;
1754 chip = "ViRGE MX"; break;
1756 chip = "ViRGE MX+"; break;
1760 vendor = "ARK Logic";
1763 chip = "1000PV"; break;
1765 chip = "2000PV"; break;
1767 chip = "2000MT"; break;
1769 chip = "2000MI"; break;
1774 type = "graphics accelerator";
1777 chip = "300SX"; break;
1779 chip = "500TX"; break;
1781 chip = "Delta"; break;
1783 chip = "PerMedia"; break;
1788 type = "graphics accelerator";
1791 chip = "NV1"; break;
1793 chip = "Riva TNT"; break;
1795 chip = "Riva TNT2"; break;
1797 chip = "Riva Ultra TNT2"; break;
1799 chip = "Riva Vanta TNT2"; break;
1801 chip = "Riva Ultra Vanta TNT2"; break;
1803 chip = "Riva Integrated TNT2"; break;
1805 chip = "GeForce 256"; break;
1807 chip = "GeForce DDR"; break;
1809 chip = "Quadro"; break;
1813 chip = "GeForce2 GTS"; break;
1815 chip = "Quadro2"; break;
1819 vendor = "NVidia/SGS-Thomson";
1820 type = "graphics accelerator";
1823 chip = "Riva128"; break;
1827 vendor = "SGS-Thomson";
1830 chip = "STG2000"; break;
1837 chip = "82810 (i810 GMCH)"; break;
1839 chip = "82810-DC100 (i810-DC100 GMCH)"; break;
1841 chip = "82810E (i810E GMCH)"; break;
1843 chip = "i740 AGP"; break;
1847 vendor = "Intergraphics";
1850 chip = "IGA-1680"; break;
1852 chip = "IGA-1682"; break;
1857 if (vendor && chip) {
1862 type = "SVGA controller";
1864 len = strlen(vendor) + strlen(chip) + strlen(type) + 4;
1865 MALLOC(buf, char *, len, M_TEMP, M_NOWAIT);
1867 sprintf(buf, "%s %s %s", vendor, chip, type);
1871 switch (pci_get_class(dev)) {
1874 if (pci_get_subclass(dev) != PCIS_OLD_VGA)
1877 type = "VGA-compatible display device";
1882 if (pci_get_subclass(dev) == PCIS_DISPLAY_VGA)
1883 type = "VGA-compatible display device";
1886 * If it isn't a vga display device,
1887 * don't pretend we found one.
1898 * If we got here, we know for sure it's some sort of display
1899 * device, but we weren't able to identify it specifically.
1900 * At a minimum we can return the type, but we'd like to
1901 * identify the vendor and chip ID if at all possible.
1902 * (Some of the checks above intentionally don't bother for
1903 * vendors where we know the chip ID is the same as the
1910 len = strlen(vendor) + strlen(type) + 2 + 6 + 4 + 1;
1911 MALLOC(buf, char *, len, M_TEMP, M_NOWAIT);
1913 sprintf(buf, "%s model %04x %s", vendor, id >> 16, type);
1919 /*---------------------------------------------------------
1921 ** Devices to ignore
1923 **---------------------------------------------------------
1927 ign_probe (device_t dev)
1929 switch (pci_get_devid(dev)) {
1931 case 0x10001042ul: /* wd */
1933 /* return ("SMC FDC 37c665");*/
1939 ign_attach (device_t dev)
1944 static device_method_t ign_methods[] = {
1945 /* Device interface */
1946 DEVMETHOD(device_probe, ign_probe),
1947 DEVMETHOD(device_attach, ign_attach),
1952 static driver_t ign_driver = {
1958 static devclass_t ign_devclass;
1960 DRIVER_MODULE(ign, pci, ign_driver, ign_devclass, 0, 0);