2 * Aic7xxx register and scratch ram definitions.
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
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13 * without modification.
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17 * including a substantially similar Disclaimer requirement for further
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21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
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40 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.reg,v 1.20.2.14 2003/06/10 03:26:08 gibbs Exp $
41 * $DragonFly: src/sys/dev/disk/aic7xxx/aic7xxx.reg,v 1.2 2003/06/17 04:28:22 dillon Exp $
43 VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#39 $"
46 * This file is processed by the aic7xxx_asm utility for use in assembling
47 * firmware for the aic7xxx family of SCSI host adapters as well as to generate
48 * a C header file for use in the kernel portion of the Aic7xxx driver.
50 * All page numbers refer to the Adaptec AIC-7770 Data Book available from
51 * Adaptec's Technical Documents Department 1-800-934-2766
55 * SCSI Sequence Control (p. 3-11).
56 * Each bit, when set starts a specific SCSI sequence on the bus
72 * SCSI Transfer Control 0 Register (pp. 3-13).
73 * Controls the SCSI module data path.
88 * SCSI Transfer Control 1 Register (pp. 3-14,15).
89 * Controls the SCSI module data path.
100 field STPWEN 0x01 /* Powered Termination */
104 * SCSI Control Signal Read Register (p. 3-15).
105 * Reads the actual state of the SCSI bus pins
119 * Possible phases in SCSISIGI
121 mask PHASE_MASK CDI|IOI|MSGI
124 mask P_DATAOUT_DT P_DATAOUT|MSGI
125 mask P_DATAIN_DT P_DATAIN|MSGI
127 mask P_MESGOUT CDI|MSGI
128 mask P_STATUS CDI|IOI
129 mask P_MESGIN CDI|IOI|MSGI
133 * SCSI Control Signal Write Register (p. 3-16).
134 * Writing to this register modifies the control signals on the bus. Only
135 * those signals that are allowed in the current mode (Initiator/Target) are
150 * Possible phases to write into SCSISIG0
152 mask PHASE_MASK CDI|IOI|MSGI
156 mask P_MESGOUT CDI|MSGI
157 mask P_STATUS CDI|IOI
158 mask P_MESGIN CDI|IOI|MSGI
162 * SCSI Rate Control (p. 3-17).
163 * Contents of this register determine the Synchronous SCSI data transfer
164 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the
165 * SOFS (3:0) bits disables synchronous data transfers. Any offset value
166 * greater than 0 enables synchronous transfers.
171 field WIDEXFER 0x80 /* Wide transfer control */
172 field ENABLE_CRC 0x40 /* CRC for D-Phases */
173 field SINGLE_EDGE 0x10 /* Disable DT Transfers */
174 mask SXFR 0x70 /* Sync transfer rate */
175 mask SXFR_ULTRA2 0x0f /* Sync transfer rate */
176 mask SOFS 0x0f /* Sync offset */
181 * Contains the ID of the board and the current target on the
187 mask TID 0xf0 /* Target ID mask */
189 field TWIN_CHNLB 0x80
190 mask OID 0x0f /* Our ID mask */
192 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book)
193 * The aic7890/91 allow an offset of up to 127 transfers in both wide
197 mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */
201 * SCSI Latched Data (p. 3-19).
202 * Read/Write latches used to transfer data on the SCSI bus during
203 * Automatic or Manual PIO mode. SCSIDATH can be used for the
204 * upper byte of a 16bit wide asynchronouse data phase transfer.
217 * SCSI Transfer Count (pp. 3-19,20)
218 * These registers count down the number of bytes transferred
219 * across the SCSI bus. The counter is decremented only once
220 * the data has been safely transferred. SDONE in SSTAT0 is
221 * set when STCNT goes to 0
229 /* ALT_MODE registers (Ultra2 and Ultra160 chips) */
233 field AUTORSTDIS 0x10
235 mask ASYNC_SETUP 0x07
238 /* ALT_MODE register on Ultra160 chips */
239 register OPTIONMODE {
242 field AUTORATEEN 0x80
244 field ATNMGMNTEN 0x20
245 field BUSFREEREV 0x10
246 field EXPPHASEDIS 0x08
247 field SCSIDATL_IMGEN 0x04
248 field AUTO_MSGOUT_DE 0x02
249 field DIS_MSGIN_DUALEDGE 0x01
250 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE
253 /* ALT_MODE register on Ultra160 chips */
254 register TARGCRCCNT {
261 * Clear SCSI Interrupt 0 (p. 3-20)
262 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
269 field CLRSELINGO 0x10
271 field CLRIOERR 0x08 /* Ultra2 Only */
272 field CLRSPIORDY 0x02
276 * SCSI Status 0 (p. 3-21)
277 * Contains one set of SCSI Interrupt codes
278 * These are most likely of interest to the sequencer
283 field TARGET 0x80 /* Board acting as target */
284 field SELDO 0x40 /* Selection Done */
285 field SELDI 0x20 /* Board has been selected */
286 field SELINGO 0x10 /* Selection In Progress */
287 field SWRAP 0x08 /* 24bit counter wrap */
288 field IOERR 0x08 /* LVD Tranceiver mode changed */
289 field SDONE 0x04 /* STCNT = 0x000000 */
290 field SPIORDY 0x02 /* SCSI PIO Ready */
291 field DMADONE 0x01 /* DMA transfer completed */
295 * Clear SCSI Interrupt 1 (p. 3-23)
296 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
301 field CLRSELTIMEO 0x80
303 field CLRSCSIRSTI 0x20
304 field CLRBUSFREE 0x08
305 field CLRSCSIPERR 0x04
306 field CLRPHASECHG 0x02
307 field CLRREQINIT 0x01
311 * SCSI Status 1 (p. 3-24)
327 * SCSI Status 2 (pp. 3-25,26)
333 field SHVALID 0x40 /* Shaddow Layer non-zero */
334 field EXP_ACTIVE 0x10 /* SCSI Expander Active */
335 field CRCVALERR 0x08 /* CRC doesn't match (U3 only) */
336 field CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */
337 field CRCREQERR 0x02 /* Illegal CRC packet req (U3 only) */
338 field DUAL_EDGE_ERR 0x01 /* Incorrect data phase (U3 only) */
343 * SCSI Status 3 (p. 3-26)
354 * SCSI ID for the aic7890/91 chips
356 register SCSIID_ULTRA2 {
359 mask TID 0xf0 /* Target ID mask */
360 mask OID 0x0f /* Our ID mask */
364 * SCSI Interrupt Mode 1 (p. 3-28)
365 * Setting any bit will enable the corresponding function
366 * in SIMODE0 to interrupt via the IRQ pin.
375 field ENIOERR 0x08 /* LVD Tranceiver mode changes */
382 * SCSI Interrupt Mode 1 (pp. 3-28,29)
383 * Setting any bit will enable the corresponding function
384 * in SIMODE1 to interrupt via the IRQ pin.
392 field ENPHASEMIS 0x10
394 field ENSCSIPERR 0x04
395 field ENPHASECHG 0x02
400 * SCSI Data Bus (High) (p. 3-29)
401 * This register reads data on the SCSI Data bus directly.
414 * SCSI/Host Address (p. 3-30)
415 * These registers hold the host address for the byte about to be
416 * transferred on the SCSI bus. They are counted up in the same
417 * manner as STCNT is counted down. SHADDR should always be used
418 * to determine the address of the last byte transferred since HADDR
419 * can be skewed by write ahead.
428 * Selection Timeout Timer (p. 3-30)
443 * Selection/Reselection ID (p. 3-31)
444 * Upper four bits are the device id. The ONEBIT is set when the re/selecting
445 * device did not set its own ID.
457 field ENSCAMSELO 0x80
458 field CLRSCAMSELID 0x40
465 * Target Mode Selecting in ID bitmask (aic7890/91/96/97)
474 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book)
475 * Indicates if external logic has been attached to the chip to
476 * perform the tasks of accessing a serial eeprom, testing termination
477 * strength, and performing cable detection. On the aic7860, most of
478 * these features are handled on chip, but on the aic7855 an attached
479 * aic3800 does the grunt work.
487 field EXT_BRDCTL 0x10 /* External Board control */
488 field SEEPROM 0x08 /* External serial eeprom logic */
489 field EEPROM 0x04 /* Writable external BIOS ROM */
490 field ROM 0x02 /* Logic for accessing external ROM */
491 field SSPIOCPS 0x01 /* Termination and cable detection */
504 /* 7890 Definitions */
508 field BRDRW_ULTRA2 0x02
509 field BRDSTB_ULTRA2 0x01
513 * Serial EEPROM Control (p. 4-92 in 7870 Databook)
514 * Controls the reading and writing of an external serial 1-bit
515 * EEPROM Device. In order to access the serial EEPROM, you must
516 * first set the SEEMS bit that generates a request to the memory
517 * port for access to the serial EEPROM device. When the memory
518 * port is not busy servicing another request, it reconfigures
519 * to allow access to the serial EEPROM. When this happens, SEERDY
520 * gets set high to verify that the memory port access has been
523 * After successful arbitration for the memory port, the SEECS bit of
524 * the SEECTL register is connected to the chip select. The SEECK,
525 * SEEDO, and SEEDI are connected to the clock, data out, and data in
526 * lines respectively. The SEERDY bit of SEECTL is useful in that it
527 * gives us an 800 nsec timer. After a write to the SEECTL register,
528 * the SEERDY goes high 800 nsec later. The one exception to this is
529 * when we first request access to the memory port. The SEERDY goes
530 * high to signify that access has been granted and, for this case, has
533 * See 93cx6.c for detailed information on the protocol necessary to
534 * read the serial EEPROM.
548 * SCSI Block Control (p. 3-32)
549 * Controls Bus type and channel selection. In a twin channel configuration
550 * addresses 0x00-0x1e are gated to the appropriate channel based on this
551 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices
557 field DIAGLEDEN 0x80 /* Aic78X0 only */
558 field DIAGLEDON 0x40 /* Aic78X0 only */
559 field AUTOFLUSHDIS 0x20
561 field ENAB40 0x08 /* LVD transceiver active */
562 field ENAB20 0x04 /* SE/HVD transceiver active */
564 field XCVR 0x01 /* External transceiver active */
568 * Sequencer Control (p. 3-33)
569 * Error detection mode and speed configuration
578 field BRKADRINTEN 0x08
585 * Sequencer RAM Data (p. 3-34)
586 * Single byte window into the Scratch Ram area starting at the address
587 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write
588 * four bytes in succession. The SEQADDRs will increment after the most
589 * significant byte is written
597 * Sequencer Address Registers (p. 3-35)
598 * Only the first bit of SEQADDR1 holds addressing information
608 mask SEQADDR1_MASK 0x01
613 * We cheat by passing arguments in the Accumulator up to the kernel driver
680 * Board Control (p. 3-43)
690 * On the aic78X0 chips, Board Control is replaced by the DSCommand
693 register DSCOMMAND0 {
696 field CACHETHEN 0x80 /* Cache Threshold enable */
697 field DPARCKEN 0x40 /* Data Parity Check Enable */
698 field MPARCKEN 0x20 /* Memory Parity Check Enable */
699 field EXTREQLCK 0x10 /* External Request Lock */
700 /* aic7890/91/96/97 only */
701 field INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */
702 field RAMPS 0x04 /* External SCB RAM Present */
703 field USCBSIZE32 0x02 /* Use 32byte SCB Page Size */
704 field CIOPARCKEN 0x01 /* Internal bus parity error enable */
707 register DSCOMMAND1 {
710 mask DSLATT 0xfc /* PCI latency timer (non-ultra2) */
711 field HADDLDSEL1 0x02 /* Host Address Load Select Bits */
712 field HADDLDSEL0 0x01
716 * Bus On/Off Time (p. 3-44) aic7770 only
726 * Bus Speed (p. 3-45) aic7770 only
734 mask DFTHRSH_100 0xc0
738 /* aic7850/55/60/70/80/95 only */
739 register DSPCISTATUS {
741 mask DFTHRSH_100 0xc0
744 /* aic7890/91/96/97 only */
745 register HS_MAILBOX {
747 mask HOST_MAILBOX 0xF0
748 mask SEQ_MAILBOX 0x0F
749 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */
752 const HOST_MAILBOX_SHIFT 4
753 const SEQ_MAILBOX_SHIFT 0
756 * Host Control (p. 3-47) R/W
757 * Overall host control of the device.
768 field CHIPRSTACK 0x01
772 * Host Address (p. 3-48)
773 * This register contains the address of the byte about
774 * to be transferred across the host bus.
789 * SCB Pointer (p. 3-49)
790 * Gate one of the SCBs into the SCBARRAY window.
798 * Interrupt Status (p. 3-50)
799 * Status for system interrupts
808 mask BAD_PHASE SEQINT /* unknown scsi bus phase */
809 mask SEND_REJECT 0x10|SEQINT /* sending a message reject */
810 mask PROTO_VIOLATION 0x20|SEQINT /* SCSI protocol violation */
811 mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */
812 mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */
813 mask PDATA_REINIT 0x50|SEQINT /*
814 * Returned to data phase
816 * transfer pointers to be
817 * recalculated from the
820 mask HOST_MSG_LOOP 0x60|SEQINT /*
821 * The bus is ready for the
822 * host to perform another
823 * message transaction. This
824 * mechanism is used for things
825 * like sync/wide negotiation
826 * that require a kernel based
827 * message state engine.
829 mask BAD_STATUS 0x70|SEQINT /* Bad status from target */
830 mask PERR_DETECTED 0x80|SEQINT /*
831 * Either the phase_lock
832 * or inb_next routine has
833 * noticed a parity error.
835 mask DATA_OVERRUN 0x90|SEQINT /*
836 * Target attempted to write
837 * beyond the bounds of its
840 mask MKMSG_FAILED 0xa0|SEQINT /*
841 * Target completed command
842 * without honoring our ATN
843 * request to issue a message.
845 mask MISSED_BUSFREE 0xb0|SEQINT /*
846 * The sequencer never saw
847 * the bus go free after
848 * either a command complete
849 * or disconnect message.
851 mask SCB_MISMATCH 0xc0|SEQINT /*
852 * Downloaded SCB's tag does
853 * not match the entry we
854 * intended to download.
856 mask NO_FREE_SCB 0xd0|SEQINT /*
857 * get_free_or_disc_scb failed.
859 mask OUT_OF_RANGE 0xe0|SEQINT
861 mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */
862 mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT)
866 * Hard Error (p. 3-53)
867 * Reporting of catastrophic errors. You usually cannot recover from
868 * these without a full board reset.
873 field CIOPARERR 0x80 /* Ultra2 only */
874 field PCIERRSTAT 0x40 /* PCI only */
875 field MPARERR 0x20 /* PCI only */
876 field DPARERR 0x10 /* PCI only */
884 * Clear Interrupt Status (p. 3-52)
889 field CLRPARERR 0x10 /* PCI only */
890 field CLRBRKADRINT 0x08
891 field CLRSCSIINT 0x04
899 field PRELOADEN 0x80 /* aic7890 only */
914 field PRELOAD_AVAIL 0x80
916 field FIFOQWDEMP 0x20
940 * SCB Auto Increment (p. 3-59)
941 * Byte offset into the SCB Array and an optional bit to allow auto
942 * incrementing of the address during download and upload operations
948 mask SCBCNT_MASK 0x1f
952 * Queue In FIFO (p. 3-60)
953 * Input queue for queued SCBs (commands that the seqencer has yet to start)
961 * Queue In Count (p. 3-60)
962 * Number of queued SCBs
970 * Queue Out FIFO (p. 3-61)
971 * Queue of SCBs that have completed and await the host
978 register CRCCONTROL1 {
982 field CRCVALCHKEN 0x40
983 field CRCENDCHKEN 0x20
984 field CRCREQCHKEN 0x10
985 field TARGCRCENDEN 0x08
986 field TARGCRCCNTEN 0x04
991 * Queue Out Count (p. 3-61)
992 * Number of queued SCBs in the Out FIFO
1002 field STATUS_PHASE 0x20
1003 field COMMAND_PHASE 0x10
1004 field MSG_IN_PHASE 0x08
1005 field MSG_OUT_PHASE 0x04
1006 field DATA_IN_PHASE 0x02
1007 field DATA_OUT_PHASE 0x01
1008 mask DATA_PHASE_MASK 0x03
1021 * SCB Definition (p. 5-4)
1029 alias SCB_RESIDUAL_DATACNT
1032 SCB_RESIDUAL_SGPTR {
1041 SCB_TARGET_DATA_DIR {
1052 * The last byte is really the high address bits for
1056 field SG_LAST_SEG 0x80 /* In the fourth byte */
1057 mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */
1061 field SG_RESID_VALID 0x04 /* In the first byte */
1062 field SG_FULL_RESID 0x02 /* In the first byte */
1063 field SG_LIST_NULL 0x01 /* In the first byte */
1067 field TARGET_SCB 0x80
1068 field STATUS_RCVD 0x80
1071 field MK_MESSAGE 0x10
1073 field DISCONNECTED 0x04
1074 mask SCB_TAG_TYPE 0x03
1078 field TWIN_CHNLB 0x80
1084 field SCB_XFERLEN_ODD 0x80
1111 const SCB_UPLOAD_SIZE 32
1112 const SCB_DOWNLOAD_SIZE 32
1113 const SCB_DOWNLOAD_SIZE_64 48
1115 const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */
1117 /* --------------------- AHA-2840-only definitions -------------------- */
1119 register SEECTL_2840 {
1127 register STATUS_2840 {
1130 field EEPROM_TF 0x80
1136 /* --------------------- AIC-7870-only definitions -------------------- */
1159 field SG_FETCH_NEEDED 0x02 /* Bit used for software state */
1160 field CCSGRESET 0x01
1169 field CCSCBDONE 0x80
1170 field ARRDONE 0x40 /* SCB Array prefetch done */
1174 field CCSCBRESET 0x01
1177 register CCSCBADDR {
1186 * SCB bank address (7895/7896/97 only)
1197 register HNSCB_QOFF {
1201 register SNSCB_QOFF {
1205 register SDSCB_QOFF {
1209 register QOFF_CTLSTA {
1211 field SCB_AVAIL 0x40
1212 field SNSCB_ROLLOVER 0x20
1213 field SDSCB_ROLLOVER 0x10
1215 mask SCB_QSIZE_256 0x06
1218 register DFF_THRSH {
1220 mask WR_DFTHRSH 0x70
1221 mask RD_DFTHRSH 0x07
1222 mask RD_DFTHRSH_MIN 0x00
1223 mask RD_DFTHRSH_25 0x01
1224 mask RD_DFTHRSH_50 0x02
1225 mask RD_DFTHRSH_63 0x03
1226 mask RD_DFTHRSH_75 0x04
1227 mask RD_DFTHRSH_85 0x05
1228 mask RD_DFTHRSH_90 0x06
1229 mask RD_DFTHRSH_MAX 0x07
1230 mask WR_DFTHRSH_MIN 0x00
1231 mask WR_DFTHRSH_25 0x10
1232 mask WR_DFTHRSH_50 0x20
1233 mask WR_DFTHRSH_63 0x30
1234 mask WR_DFTHRSH_75 0x40
1235 mask WR_DFTHRSH_85 0x50
1236 mask WR_DFTHRSH_90 0x60
1237 mask WR_DFTHRSH_MAX 0x70
1240 register SG_CACHE_PRE {
1243 mask SG_ADDR_MASK 0xf8
1245 field LAST_SEG_DONE 0x01
1248 register SG_CACHE_SHADOW {
1251 mask SG_ADDR_MASK 0xf8
1253 field LAST_SEG_DONE 0x01
1255 /* ---------------------- Scratch RAM Offsets ------------------------- */
1256 /* These offsets are either to values that are initialized by the board's
1257 * BIOS or are specified by the sequencer code.
1259 * The host adapter card (at least the BIOS) uses 20-2f for SCSI
1260 * device information, 32-33 and 5a-5f as well. As it turns out, the
1261 * BIOS trashes 20-2f, writing the synchronous negotiation results
1262 * on top of the BIOS values, so we re-use those for our per-target
1263 * scratchspace (actually a value that can be copied directly into
1264 * SCSIRATE). The kernel driver will enable synchronous negotiation
1265 * for all targets that have a value other than 0 in the lower four
1266 * bits of the target scratch space. This should work regardless of
1267 * whether the bios has been installed.
1275 * 1 byte per target starting at this address for configuration values
1282 * Bit vector of targets that have ULTRA enabled as set by
1283 * the BIOS. The Sequencer relies on a per-SCB field to
1284 * control whether to enable Ultra transfers or not. During
1285 * initialization, we read this field and reuse it for 2
1286 * entries in the busy target table.
1293 * Bit vector of targets that have disconnection disabled as set by
1294 * the BIOS. The Sequencer relies in a per-SCB field to control the
1295 * disconnect priveldge. During initialization, we read this field
1296 * and reuse it for 2 entries in the busy target table.
1301 CMDSIZE_TABLE_TAIL {
1305 * Partial transfer past cacheline end to be
1306 * transferred using an extra S/G.
1310 alias TARG_IMMEDIATE_SCB
1313 * SCBID of the next SCB to be started by the controller.
1319 * Single byte buffer used to designate the type or message
1320 * to send to a target.
1325 /* Parameters for DMA Logic */
1328 field PRELOADEN 0x80
1332 field SDMAENACK 0x10
1334 field HDMAENACK 0x08
1335 field DIRECTION 0x04 /* Set indicates PCI->SCSI */
1336 field FIFOFLUSH 0x02
1337 field FIFORESET 0x01
1341 field NOT_IDENTIFIED 0x80
1342 field NO_CDB_SENT 0x40
1343 field TARGET_CMD_IS_TAGGED 0x40
1346 field TARG_CMD_PENDING 0x10
1347 field CMDPHASE_PENDING 0x08
1348 field DPHASE_PENDING 0x04
1349 field SPHASE_PENDING 0x02
1350 field NO_DISCONNECT 0x01
1353 * Temporary storage for the
1354 * target/channel/lun of a
1355 * reconnecting target
1364 * The last bus phase as seen by the sequencer.
1371 mask PHASE_MASK CDI|IOI|MSGI
1375 mask P_MESGOUT CDI|MSGI
1376 mask P_STATUS CDI|IOI
1377 mask P_MESGIN CDI|IOI|MSGI
1381 * head of list of SCBs awaiting
1388 * head of list of SCBs that are
1389 * disconnected. Used for SCB
1396 * head of list of SCBs that are
1397 * not in use. Used for SCB paging.
1403 * head of list of SCBs that have
1404 * completed but have not been
1405 * put into the qoutfifo.
1411 * Address of the hardware scb array in the host.
1417 * Base address of our shared data with the kernel driver in host
1418 * memory. This includes the qoutfifo and target mode
1419 * incoming command queue.
1434 * Kernel and sequencer offsets into the queue of
1435 * incoming target mode command descriptors. The
1436 * queue is full when the KERNEL_TQINPOS == TQINPOS.
1447 mask SEND_SENSE 0x40
1449 mask MSGOUT_PHASEMIS 0x10
1450 mask EXIT_MSG_LOOP 0x08
1451 mask CONT_MSG_LOOP 0x04
1452 mask CONT_TARG_SESSION 0x02
1461 * Snapshot of MSG_OUT taken after each message is sent.
1468 * Sequences the kernel driver has okayed for us. This allows
1469 * the driver to do things like prevent initiator or target
1477 field ENAUTOATNO 0x08
1478 field ENAUTOATNI 0x04
1479 field ENAUTOATNP 0x02
1487 * These scratch ram locations are initialized by the 274X BIOS.
1488 * We reuse them after capturing the BIOS settings during
1493 * The initiator specified tag for this target mode transaction.
1497 field HA_274_EXTENDED_TRANS 0x01
1504 field TARGET_MSG_PENDING 0x02
1512 * These are reserved registers in the card's scratch ram on the 2742.
1513 * The EISA configuraiton chip is mapped here. On Rev E. of the
1514 * aic7770, the sequencer can use this area for scratch, but the
1515 * host cannot directly access these registers. On later chips, this
1516 * area can be read and written by both the host and the sequencer.
1517 * Even on later chips, many of these locations are initialized by
1523 field RESET_SCSI 0x40
1525 mask HSCSIID 0x07 /* our SCSI ID */
1526 mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */
1531 field EDGE_TRIG 0x80
1542 mask BIOSDISABLED 0x30
1543 field CHANNEL_B_PRIMARY 0x08
1552 * Per target SCSI offset values for Ultra2 controllers.
1560 const SCB_LIST_NULL 0xff
1561 const TARGET_CMD_CMPLT 0xfe
1563 const CCSGADDR_MAX 0x80
1564 const CCSGRAM_MAXSEGS 16
1566 /* WDTR Message values */
1567 const BUS_8_BIT 0x00
1568 const BUS_16_BIT 0x01
1569 const BUS_32_BIT 0x02
1571 /* Offset maximums */
1572 const MAX_OFFSET_8BIT 0x0f
1573 const MAX_OFFSET_16BIT 0x08
1574 const MAX_OFFSET_ULTRA2 0x7f
1575 const MAX_OFFSET 0x7f
1578 /* Target mode command processing constants */
1579 const CMD_GROUP_CODE_SHIFT 0x05
1581 const STATUS_BUSY 0x08
1582 const STATUS_QUEUE_FULL 0x28
1583 const TARGET_DATA_IN 1
1586 * Downloaded (kernel inserted) constants
1588 /* Offsets into the SCBID array where different data is stored */
1589 const QOUTFIFO_OFFSET download
1590 const QINFIFO_OFFSET download
1591 const CACHESIZE_MASK download
1592 const INVERTED_CACHESIZE_MASK download
1593 const SG_PREFETCH_CNT download
1594 const SG_PREFETCH_ALIGN_MASK download
1595 const SG_PREFETCH_ADDR_MASK download