2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-dma.c,v 1.35.2.31 2003/05/07 16:46:11 jhb Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-dma.c,v 1.2 2003/06/17 04:28:22 dillon Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/malloc.h>
39 #include <sys/devicestat.h>
42 #include <pci/pcivar.h>
43 #include <machine/bus.h>
45 #include <dev/ata/ata-all.h>
48 static void cyrix_timing(struct ata_channel *, int, int);
49 static void promise_timing(struct ata_channel *, int, int);
50 static void hpt_timing(struct ata_channel *, int, int);
51 static int hpt_cable80(struct ata_channel *);
56 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
58 #define ATAPI_DEVICE(ch, device) \
59 ((device == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || \
60 (device == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE))
63 ata_dmaalloc(struct ata_channel *ch, int device)
67 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) {
68 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^
69 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) {
70 ata_printf(ch, device, "dmatab crosses page boundary, no DMA\n");
71 free(dmatab, M_DEVBUF);
79 ata_dmainit(struct ata_channel *ch, int device,
80 int apiomode, int wdmamode, int udmamode)
82 struct ata_device *atadev = &ch->device[ATA_DEV(device)];
83 device_t parent = device_get_parent(ch->dev);
84 int devno = (ch->unit << 1) + ATA_DEV(device);
87 /* set our most pessimistic default mode */
88 atadev->mode = ATA_PIO;
93 /* if simplex controller, only allow DMA on primary channel */
95 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
96 ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) &
97 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
98 if (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) {
99 ata_prtdev(atadev, "simplex device, DMA on primary only\n");
104 /* DMA engine address alignment is usually 1 word (2 bytes) */
108 if (udmamode > 2 && !ch->device[ATA_DEV(device)].param->hwres_cblid) {
109 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
113 switch (ch->chiptype) {
115 case 0x24db8086: /* Intel ICH5 */
116 case 0x24cb8086: /* Intel ICH4 */
117 case 0x248a8086: /* Intel ICH3 mobile */
118 case 0x248b8086: /* Intel ICH3 */
119 case 0x244a8086: /* Intel ICH2 mobile */
120 case 0x244b8086: /* Intel ICH2 */
122 int32_t mask48, new48;
125 word54 = pci_read_config(parent, 0x54, 2);
126 if (word54 & (0x10 << devno)) {
127 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
128 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
130 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n",
131 (error) ? "failed" : "success");
133 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
134 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
135 pci_write_config(parent, 0x48,
136 (pci_read_config(parent, 0x48, 4) &
137 ~mask48) | new48, 4);
138 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
139 atadev->mode = ATA_UDMA5;
144 /* make sure eventual ATA100 mode from the BIOS is disabled */
145 pci_write_config(parent, 0x54,
146 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
149 case 0x24118086: /* Intel ICH */
150 case 0x76018086: /* Intel ICH */
152 int32_t mask48, new48;
155 word54 = pci_read_config(parent, 0x54, 2);
156 if (word54 & (0x10 << devno)) {
157 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
158 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
160 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n",
161 (error) ? "failed" : "success");
163 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
164 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
165 pci_write_config(parent, 0x48,
166 (pci_read_config(parent, 0x48, 4) &
167 ~mask48) | new48, 4);
168 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
169 atadev->mode = ATA_UDMA4;
174 /* make sure eventual ATA66 mode from the BIOS is disabled */
175 pci_write_config(parent, 0x54,
176 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
179 case 0x71118086: /* Intel PIIX4 */
180 case 0x84CA8086: /* Intel PIIX4 */
181 case 0x71998086: /* Intel PIIX4e */
182 case 0x24218086: /* Intel ICH0 */
184 int32_t mask48, new48;
186 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
187 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
189 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n",
190 (error) ? "failed" : "success");
192 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
193 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
194 pci_write_config(parent, 0x48,
195 (pci_read_config(parent, 0x48, 4) &
196 ~mask48) | new48, 4);
197 atadev->mode = ATA_UDMA2;
201 /* make sure eventual ATA33 mode from the BIOS is disabled */
202 pci_write_config(parent, 0x48,
203 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
206 case 0x70108086: /* Intel PIIX3 */
207 if (wdmamode >= 2 && apiomode >= 4) {
208 int32_t mask40, new40, mask44, new44;
210 /* if SITRE not set doit for both channels */
211 if (!((pci_read_config(parent,0x40,4)>>(ch->unit<<8))&0x4000)) {
212 new40 = pci_read_config(parent, 0x40, 4);
213 new44 = pci_read_config(parent, 0x44, 4);
214 if (!(new40 & 0x00004000)) {
215 new44 &= ~0x0000000f;
216 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
218 if (!(new40 & 0x40000000)) {
219 new44 &= ~0x000000f0;
220 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
223 pci_write_config(parent, 0x40, new40, 4);
224 pci_write_config(parent, 0x44, new44, 4);
226 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
227 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
229 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
230 (error) ? "failed" : "success");
232 if (device == ATA_MASTER) {
250 pci_write_config(parent, 0x40,
251 (pci_read_config(parent, 0x40, 4) & ~mask40)|
253 pci_write_config(parent, 0x44,
254 (pci_read_config(parent, 0x44, 4) & ~mask44)|
256 atadev->mode = ATA_WDMA2;
260 /* we could set PIO mode timings, but we assume the BIOS did that */
263 case 0x12308086: /* Intel PIIX */
264 if (wdmamode >= 2 && apiomode >= 4) {
267 word40 = pci_read_config(parent, 0x40, 4);
268 word40 >>= ch->unit * 16;
270 /* Check for timing config usable for DMA on controller */
271 if (!((word40 & 0x3300) == 0x2300 &&
272 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
275 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
276 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
278 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
279 (error) ? "failed" : "success");
281 atadev->mode = ATA_WDMA2;
287 case 0x522910b9: /* AcerLabs Aladdin IV/V */
288 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
289 if (pci_get_revid(parent) < 0xc2 &&
290 ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
291 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
294 if (udmamode >= 5 && pci_get_revid(parent) >= 0xc4) {
295 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
296 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
298 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n",
299 (error) ? "failed" : "success");
301 int32_t word54 = pci_read_config(parent, 0x54, 4);
303 pci_write_config(parent, 0x4b,
304 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
305 word54 &= ~(0x000f000f << (devno << 2));
306 word54 |= (0x000f0005 << (devno << 2));
307 pci_write_config(parent, 0x54, word54, 4);
308 pci_write_config(parent, 0x53,
309 pci_read_config(parent, 0x53, 1) | 0x03, 1);
310 atadev->mode = ATA_UDMA5;
314 if (udmamode >= 4 && pci_get_revid(parent) >= 0xc2) {
315 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
316 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
318 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n",
319 (error) ? "failed" : "success");
321 int32_t word54 = pci_read_config(parent, 0x54, 4);
323 pci_write_config(parent, 0x4b,
324 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
325 word54 &= ~(0x000f000f << (devno << 2));
326 word54 |= (0x00080005 << (devno << 2));
327 pci_write_config(parent, 0x54, word54, 4);
328 pci_write_config(parent, 0x53,
329 pci_read_config(parent, 0x53, 1) | 0x03, 1);
330 atadev->mode = ATA_UDMA4;
334 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) {
335 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
336 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
338 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n",
339 (error) ? "failed" : "success");
341 int32_t word54 = pci_read_config(parent, 0x54, 4);
343 word54 &= ~(0x000f000f << (devno << 2));
344 word54 |= (0x000a0005 << (devno << 2));
345 pci_write_config(parent, 0x54, word54, 4);
346 pci_write_config(parent, 0x53,
347 pci_read_config(parent, 0x53, 1) | 0x03, 1);
348 ch->flags |= ATA_ATAPI_DMA_RO;
349 atadev->mode = ATA_UDMA2;
354 /* make sure eventual UDMA mode from the BIOS is disabled */
355 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
356 ~(0x0008 << (devno << 2)), 2);
358 if (wdmamode >= 2 && apiomode >= 4) {
359 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
360 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
362 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n",
363 (error) ? "failed" : "success");
365 pci_write_config(parent, 0x53,
366 pci_read_config(parent, 0x53, 1) | 0x03, 1);
367 ch->flags |= ATA_ATAPI_DMA_RO;
368 atadev->mode = ATA_WDMA2;
372 pci_write_config(parent, 0x53,
373 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
374 /* we could set PIO mode timings, but we assume the BIOS did that */
377 case 0x01bc10de: /* nVIDIA nForce */
378 case 0x74411022: /* AMD 768 */
379 case 0x74111022: /* AMD 766 */
380 case 0x74091022: /* AMD 756 */
381 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686, 8231,8233,8235 */
383 int via_modes[5][7] = {
384 { 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* ATA33 */
385 { 0x00, 0x00, 0xea, 0x00, 0xe8, 0x00, 0x00 }, /* ATA66 */
386 { 0x00, 0x00, 0xf4, 0x00, 0xf1, 0xf0, 0x00 }, /* ATA100 */
387 { 0x00, 0x00, 0xf6, 0x00, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
388 { 0x00, 0x00, 0xc0, 0x00, 0xc5, 0xc6, 0x00 }}; /* AMD/nVIDIA */
392 if (ata_find_dev(parent, 0x31471106, 0) || /* 8233a */
393 ata_find_dev(parent, 0x31771106, 0)) { /* 8235 */
394 udmamode = imin(udmamode, 6);
395 reg_val = via_modes[3];
397 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */
398 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */
399 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */
400 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */
401 udmamode = imin(udmamode, 5);
402 reg_val = via_modes[2];
404 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */
405 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */
406 udmamode = imin(udmamode, 4);
407 reg_val = via_modes[1];
409 else if (ata_find_dev(parent, 0x06861106, 0)) { /* 82C686 */
410 udmamode = imin(udmamode, 2);
411 reg_val = via_modes[1];
413 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */
414 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */
415 udmamode = imin(udmamode, 2);
416 reg_val = via_modes[0];
418 else if (ch->chiptype == 0x74411022 || /* AMD 768 */
419 ch->chiptype == 0x74111022) { /* AMD 766 */
420 udmamode = imin(udmamode, 5);
421 reg_val = via_modes[4];
424 else if (ch->chiptype == 0x74091022) { /* AMD 756 */
425 udmamode = imin(udmamode, 4);
426 reg_val = via_modes[4];
429 else if (ch->chiptype == 0x01bc10de) { /* nVIDIA */
430 udmamode = imin(udmamode, 5);
431 reg_val = via_modes[4];
438 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
439 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
441 ata_prtdev(atadev, "%s setting UDMA6 on %s chip\n",
442 (error) ? "failed" : "success", chip);
444 pci_write_config(parent, 0x53 - devno, reg_val[6], 1);
445 atadev->mode = ATA_UDMA6;
450 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
451 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
453 ata_prtdev(atadev, "%s setting UDMA5 on %s chip\n",
454 (error) ? "failed" : "success", chip);
456 pci_write_config(parent, 0x53 - devno, reg_val[5], 1);
457 atadev->mode = ATA_UDMA5;
462 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
463 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
465 ata_prtdev(atadev, "%s setting UDMA4 on %s chip\n",
466 (error) ? "failed" : "success", chip);
468 pci_write_config(parent, 0x53 - devno, reg_val[4], 1);
469 atadev->mode = ATA_UDMA4;
474 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
475 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
477 ata_prtdev(atadev, "%s setting UDMA2 on %s chip\n",
478 (error) ? "failed" : "success", chip);
480 pci_write_config(parent, 0x53 - devno, reg_val[2], 1);
481 atadev->mode = ATA_UDMA2;
485 if (wdmamode >= 2 && apiomode >= 4) {
486 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
487 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
489 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n",
490 (error) ? "failed" : "success", chip);
492 pci_write_config(parent, 0x53 - devno, 0x0b, 1);
493 pci_write_config(parent, 0x4b - devno, 0x31, 1);
494 atadev->mode = ATA_WDMA2;
499 /* we could set PIO mode timings, but we assume the BIOS did that */
502 case 0x55131039: /* SiS 5591 */
503 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */
504 ata_find_dev(parent, 0x06331039, 0) || /* SiS 633 */
505 ata_find_dev(parent, 0x06351039, 0) || /* SiS 635 */
506 ata_find_dev(parent, 0x06401039, 0) || /* SiS 640 */
507 ata_find_dev(parent, 0x06451039, 0) || /* SiS 645 */
508 ata_find_dev(parent, 0x06501039, 0) || /* SiS 650 */
509 ata_find_dev(parent, 0x07301039, 0) || /* SiS 730 */
510 ata_find_dev(parent, 0x07331039, 0) || /* SiS 733 */
511 ata_find_dev(parent, 0x07351039, 0) || /* SiS 735 */
512 ata_find_dev(parent, 0x07401039, 0) || /* SiS 740 */
513 ata_find_dev(parent, 0x07451039, 0) || /* SiS 745 */
514 ata_find_dev(parent, 0x07501039, 0)) { /* SiS 750 */
515 int8_t reg = 0x40 + (devno << 1);
516 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
519 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
520 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
522 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n",
523 (error) ? "failed" : "success");
525 pci_write_config(parent, reg, val | 0x8000, 2);
526 atadev->mode = ATA_UDMA5;
531 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
532 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
534 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
535 (error) ? "failed" : "success");
537 pci_write_config(parent, reg, val | 0x9000, 2);
538 atadev->mode = ATA_UDMA4;
543 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
544 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
546 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
547 (error) ? "failed" : "success");
549 pci_write_config(parent, reg, val | 0xb000, 2);
550 atadev->mode = ATA_UDMA2;
554 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */
555 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */
556 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */
557 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */
558 int8_t reg = 0x40 + (devno << 1);
559 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
562 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
563 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
565 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
566 (error) ? "failed" : "success");
568 pci_write_config(parent, reg, val | 0x9000, 2);
569 atadev->mode = ATA_UDMA4;
574 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
575 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
577 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
578 (error) ? "failed" : "success");
580 pci_write_config(parent, reg, val | 0xa000, 2);
581 atadev->mode = ATA_UDMA2;
585 } else if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) {
586 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
587 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
589 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
590 (error) ? "failed" : "success");
592 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
593 atadev->mode = ATA_UDMA2;
597 if (wdmamode >=2 && apiomode >= 4) {
598 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
599 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
601 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n",
602 (error) ? "failed" : "success");
604 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
605 atadev->mode = ATA_WDMA2;
609 /* we could set PIO mode timings, but we assume the BIOS did that */
612 case 0x06801095: /* SiI 0680 ATA133 controller */
614 u_int8_t ureg = 0xac + (ATA_DEV(device) * 0x02) + (ch->unit * 0x10);
615 u_int8_t uval = pci_read_config(parent, ureg, 1);
616 u_int8_t mreg = ch->unit ? 0x84 : 0x80;
617 u_int8_t mask = ATA_DEV(device) ? 0x30 : 0x03;
618 u_int8_t mode = pci_read_config(parent, mreg, 1);
620 /* enable UDMA mode */
621 pci_write_config(parent, mreg,
622 (mode & ~mask) | (device ? 0x30 : 0x03), 1);
624 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
625 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
627 ata_prtdev(atadev, "%s setting UDMA6 on SiI chip\n",
628 (error) ? "failed" : "success");
630 pci_write_config(parent, ureg, (uval & 0x3f) | 0x01, 1);
631 atadev->mode = ATA_UDMA6;
636 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
637 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
639 ata_prtdev(atadev, "%s setting UDMA5 on SiI chip\n",
640 (error) ? "failed" : "success");
642 pci_write_config(parent, ureg, (uval & 0x3f) | 0x02, 1);
643 atadev->mode = ATA_UDMA5;
648 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
649 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
651 ata_prtdev(atadev, "%s setting UDMA4 on SiI chip\n",
652 (error) ? "failed" : "success");
654 pci_write_config(parent, ureg, (uval & 0x3f) | 0x03, 1);
655 atadev->mode = ATA_UDMA4;
660 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
661 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
663 ata_prtdev(atadev, "%s setting UDMA2 on SiI chip\n",
664 (error) ? "failed" : "success");
666 pci_write_config(parent, ureg, (uval & 0x3f) | 0x07, 1);
667 atadev->mode = ATA_UDMA2;
672 /* disable UDMA mode and enable WDMA mode */
673 pci_write_config(parent, mreg,
674 (mode & ~mask) | (device ? 0x20 : 0x02), 1);
675 if (wdmamode >= 2 && apiomode >= 4) {
676 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
677 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
679 ata_prtdev(atadev, "%s setting WDMA2 on SiI chip\n",
680 (error) ? "failed" : "success");
682 pci_write_config(parent, ureg - 0x4, 0x10c1, 2);
683 atadev->mode = ATA_WDMA2;
688 /* restore PIO mode */
689 pci_write_config(parent, mreg, mode, 1);
691 /* we could set PIO mode timings, but we assume the BIOS did that */
695 case 0x06491095: /* CMD 649 ATA100 controller */
699 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
700 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
702 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n",
703 (error) ? "failed" : "success");
705 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1);
706 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
707 umode |= (device == ATA_MASTER ? 0x05 : 0x0a);
708 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1);
709 atadev->mode = ATA_UDMA5;
715 case 0x06481095: /* CMD 648 ATA66 controller */
719 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
720 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
722 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n",
723 (error) ? "failed" : "success");
725 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1);
726 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
727 umode |= (device == ATA_MASTER ? 0x15 : 0x4a);
728 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1);
729 atadev->mode = ATA_UDMA4;
736 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
737 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
739 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n",
740 (error) ? "failed" : "success");
742 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1);
743 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
744 umode |= (device == ATA_MASTER ? 0x11 : 0x42);
745 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1);
746 atadev->mode = ATA_UDMA2;
750 /* make sure eventual UDMA mode from the BIOS is disabled */
751 pci_write_config(parent, ch->unit ? 0x7b : 0x73,
752 pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1)&
753 ~(device == ATA_MASTER ? 0x35 : 0xca), 1);
756 case 0x06461095: /* CMD 646 ATA controller */
757 if (wdmamode >= 2 && apiomode >= 4) {
758 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
759 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
761 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n",
762 error ? "failed" : "success");
764 int32_t offset = (devno < 3) ? (devno << 1) : 7;
766 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
767 atadev->mode = ATA_WDMA2;
771 /* we could set PIO mode timings, but we assume the BIOS did that */
774 case 0xc6931080: /* Cypress 82c693 ATA controller */
775 if (wdmamode >= 2 && apiomode >= 4) {
776 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
777 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
779 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n",
780 error ? "failed" : "success");
782 pci_write_config(ch->dev, ch->unit ? 0x4e:0x4c, 0x2020, 2);
783 atadev->mode = ATA_WDMA2;
787 /* we could set PIO mode timings, but we assume the BIOS did that */
790 case 0x01021078: /* Cyrix 5530 ATA33 controller */
791 ch->alignment = 0xf; /* DMA engine requires 16 byte alignment */
793 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
794 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
796 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n",
797 (error) ? "failed" : "success");
799 cyrix_timing(ch, devno, ATA_UDMA2);
800 atadev->mode = ATA_UDMA2;
804 if (wdmamode >= 2 && apiomode >= 4) {
805 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
806 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
808 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n",
809 (error) ? "failed" : "success");
811 cyrix_timing(ch, devno, ATA_WDMA2);
812 atadev->mode = ATA_WDMA2;
816 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
817 ATA_PIO0 + apiomode, ATA_C_F_SETXFER,
820 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n",
821 (error) ? "failed" : "success",
822 ata_mode2str(ATA_PIO0 + apiomode));
823 cyrix_timing(ch, devno, ATA_PIO0 + apiomode);
824 atadev->mode = ATA_PIO0 + apiomode;
827 case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */
828 if (udmamode >= 5 && pci_get_revid(parent) >= 0x92) {
829 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
830 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
832 ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n",
833 (error) ? "failed" : "success");
837 pci_write_config(parent, 0x54,
838 pci_read_config(parent, 0x54, 1) |
840 reg56 = pci_read_config(parent, 0x56, 2);
841 reg56 &= ~(0xf << (devno * 4));
842 reg56 |= (0x5 << (devno * 4));
843 pci_write_config(parent, 0x56, reg56, 2);
844 atadev->mode = ATA_UDMA5;
849 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
850 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
852 ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n",
853 (error) ? "failed" : "success");
857 pci_write_config(parent, 0x54,
858 pci_read_config(parent, 0x54, 1) |
860 reg56 = pci_read_config(parent, 0x56, 2);
861 reg56 &= ~(0xf << (devno * 4));
862 reg56 |= (0x4 << (devno * 4));
863 pci_write_config(parent, 0x56, reg56, 2);
864 atadev->mode = ATA_UDMA4;
870 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */
872 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
873 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
875 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n",
876 (error) ? "failed" : "success");
880 pci_write_config(parent, 0x54,
881 pci_read_config(parent, 0x54, 1) |
883 reg56 = pci_read_config(parent, 0x56, 2);
884 reg56 &= ~(0xf << (devno * 4));
885 reg56 |= (0x2 << (devno * 4));
886 pci_write_config(parent, 0x56, reg56, 2);
887 atadev->mode = ATA_UDMA2;
891 if (wdmamode >= 2 && apiomode >= 4) {
892 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
893 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
895 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n",
896 (error) ? "failed" : "success");
898 int offset = (ch->unit * 2) + (device == ATA_MASTER);
899 int word44 = pci_read_config(parent, 0x44, 4);
901 pci_write_config(parent, 0x54,
902 pci_read_config(parent, 0x54, 1) &
903 ~(0x01 << devno), 1);
904 word44 &= ~(0xff << (offset << 8));
905 word44 |= (0x20 << (offset << 8));
906 pci_write_config(parent, 0x44, 0x20, 4);
907 atadev->mode = ATA_WDMA2;
911 /* we could set PIO mode timings, but we assume the BIOS did that */
914 case 0x4d69105a: /* Promise TX2 ATA133 controllers */
915 case 0x5275105a: /* Promise TX2 ATA133 controllers */
916 case 0x6269105a: /* Promise TX2 ATA133 controllers */
917 case 0x7275105a: /* Promise TX2 ATA133 controllers */
918 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
919 if (udmamode >= 6 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
920 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
921 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
923 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n",
924 (error) ? "failed" : "success");
926 atadev->mode = ATA_UDMA6;
932 case 0x4d68105a: /* Promise TX2 ATA100 controllers */
933 case 0x6268105a: /* Promise TX2 ATA100 controllers */
934 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
935 if (udmamode >= 5 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
936 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
937 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
939 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
940 (error) ? "failed" : "success");
942 atadev->mode = ATA_UDMA5;
946 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
947 if (udmamode >= 4 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
948 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
949 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
951 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
952 (error) ? "failed" : "success");
954 atadev->mode = ATA_UDMA4;
959 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
960 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
962 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n",
963 (error) ? "failed" : "success");
965 atadev->mode = ATA_UDMA2;
969 if (wdmamode >= 2 && apiomode >= 4) {
970 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
971 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
973 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
974 (error) ? "failed" : "success");
976 atadev->mode = ATA_WDMA2;
982 case 0x0d30105a: /* Promise OEM ATA100 controllers */
983 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */
984 if (!ATAPI_DEVICE(ch, device) && udmamode >= 5 &&
985 !(pci_read_config(parent, 0x50, 2)&(ch->unit ? 1<<11 : 1<<10))){
986 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
987 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
989 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
990 (error) ? "failed" : "success");
992 promise_timing(ch, devno, ATA_UDMA5);
993 atadev->mode = ATA_UDMA5;
999 case 0x0d38105a: /* Promise FastTrak 66 controllers */
1000 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */
1001 if (!ATAPI_DEVICE(ch, device) && udmamode >= 4 &&
1002 !(pci_read_config(parent, 0x50, 2)&(ch->unit ? 1<<11 : 1<<10))){
1003 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1004 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1006 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
1007 (error) ? "failed" : "success");
1009 promise_timing(ch, devno, ATA_UDMA4);
1010 atadev->mode = ATA_UDMA4;
1016 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */
1017 if (!ATAPI_DEVICE(ch, device) && udmamode >= 2) {
1018 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1019 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1021 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n",
1022 (error) ? "failed" : "success");
1024 promise_timing(ch, devno, ATA_UDMA2);
1025 atadev->mode = ATA_UDMA2;
1029 if (!ATAPI_DEVICE(ch, device) && wdmamode >= 2 && apiomode >= 4) {
1030 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1031 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1033 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
1034 (error) ? "failed" : "success");
1036 promise_timing(ch, devno, ATA_WDMA2);
1037 atadev->mode = ATA_WDMA2;
1041 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1042 ATA_PIO0 + apiomode,
1043 ATA_C_F_SETXFER, ATA_WAIT_READY);
1045 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n",
1046 (error) ? "failed" : "success",
1047 (apiomode >= 0) ? apiomode : 0);
1048 promise_timing(ch, devno, ATA_PIO0 + apiomode);
1049 atadev->mode = ATA_PIO0 + apiomode;
1052 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */
1053 case 0x00051103: /* HighPoint HPT372 controllers */
1054 case 0x00081103: /* HighPoint HPT374 controllers */
1055 if (!ATAPI_DEVICE(ch, device) && udmamode >= 6 && hpt_cable80(ch) &&
1056 ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x05) ||
1057 (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01) ||
1058 (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07))) {
1059 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1060 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
1062 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n",
1063 (error) ? "failed" : "success");
1065 hpt_timing(ch, devno, ATA_UDMA6);
1066 atadev->mode = ATA_UDMA6;
1070 if (!ATAPI_DEVICE(ch, device) && udmamode >= 5 && hpt_cable80(ch) &&
1071 ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x03) ||
1072 (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01) ||
1073 (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07))) {
1074 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1075 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1077 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n",
1078 (error) ? "failed" : "success");
1080 hpt_timing(ch, devno, ATA_UDMA5);
1081 atadev->mode = ATA_UDMA5;
1085 if (!ATAPI_DEVICE(ch, device) && udmamode >= 4 && hpt_cable80(ch)) {
1086 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1087 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1089 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n",
1090 (error) ? "failed" : "success");
1092 hpt_timing(ch, devno, ATA_UDMA4);
1093 atadev->mode = ATA_UDMA4;
1097 if (!ATAPI_DEVICE(ch, device) && udmamode >= 2) {
1098 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1099 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1101 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n",
1102 (error) ? "failed" : "success");
1104 hpt_timing(ch, devno, ATA_UDMA2);
1105 atadev->mode = ATA_UDMA2;
1109 if (!ATAPI_DEVICE(ch, device) && wdmamode >= 2 && apiomode >= 4) {
1110 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1111 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1113 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n",
1114 (error) ? "failed" : "success");
1116 hpt_timing(ch, devno, ATA_WDMA2);
1117 atadev->mode = ATA_WDMA2;
1121 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1122 ATA_PIO0 + apiomode,
1123 ATA_C_F_SETXFER, ATA_WAIT_READY);
1125 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n",
1126 (error) ? "failed" : "success",
1127 (apiomode >= 0) ? apiomode : 0);
1128 hpt_timing(ch, devno, ATA_PIO0 + apiomode);
1129 atadev->mode = ATA_PIO0 + apiomode;
1132 case 0x000116ca: /* Cenatek Rocket Drive controller */
1133 if (wdmamode >= 0 &&
1134 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) &
1135 ((device==ATA_MASTER)?ATA_BMSTAT_DMA_MASTER:ATA_BMSTAT_DMA_SLAVE)))
1136 atadev->mode = ATA_DMA;
1138 atadev->mode = ATA_PIO;
1141 default: /* unknown controller chip */
1142 /* better not try generic DMA on ATAPI devices it almost never works */
1143 if ((device == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) ||
1144 (device == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE))
1147 /* if controller says its setup for DMA take the easy way out */
1148 /* the downside is we dont know what DMA mode we are in */
1149 if ((udmamode >= 0 || wdmamode >= 2) &&
1150 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) &
1151 ((device==ATA_MASTER) ?
1152 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) {
1153 atadev->mode = ATA_DMA;
1157 /* well, we have no support for this, but try anyways */
1158 if ((wdmamode >= 2 && apiomode >= 4) && ch->r_bmio) {
1159 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1160 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1162 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n",
1163 (error) ? "failed" : "success");
1165 atadev->mode = ATA_WDMA2;
1170 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode,
1171 ATA_C_F_SETXFER, ATA_WAIT_READY);
1173 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n",
1174 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
1176 atadev->mode = ATA_PIO0 + apiomode;
1179 ata_prtdev(atadev, "using PIO mode set by BIOS\n");
1180 atadev->mode = ATA_PIO;
1185 ata_dmasetup(struct ata_channel *ch, int device, struct ata_dmaentry *dmatab,
1186 caddr_t data, int32_t count)
1188 u_int32_t dma_count, dma_base;
1191 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) {
1192 ata_printf(ch, device, "non aligned DMA transfer attempted\n");
1197 ata_printf(ch, device, "zero length DMA transfer attempted\n");
1201 dma_base = vtophys(data);
1202 dma_count = imin(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
1207 dmatab[i].base = dma_base;
1208 dmatab[i].count = (dma_count & 0xffff);
1210 if (i >= ATA_DMA_ENTRIES) {
1211 ata_printf(ch, device, "too many segments in DMA table\n");
1214 dma_base = vtophys(data);
1215 dma_count = imin(count, PAGE_SIZE);
1216 data += imin(count, PAGE_SIZE);
1217 count -= imin(count, PAGE_SIZE);
1219 dmatab[i].base = dma_base;
1220 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
1225 ata_dmastart(struct ata_channel *ch, int device,
1226 struct ata_dmaentry *dmatab, int dir)
1228 ch->flags |= ATA_DMA_ACTIVE;
1229 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab));
1230 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
1231 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1232 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) |
1233 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1234 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1235 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
1239 ata_dmadone(struct ata_channel *ch)
1243 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1244 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1245 ch->flags &= ~ATA_DMA_ACTIVE;
1246 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
1247 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1248 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1249 return error & ATA_BMSTAT_MASK;
1253 ata_dmastatus(struct ata_channel *ch)
1255 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1259 cyrix_timing(struct ata_channel *ch, int devno, int mode)
1261 u_int32_t reg20 = 0x0000e132;
1262 u_int32_t reg24 = 0x00017771;
1265 case ATA_PIO0: reg20 = 0x0000e132; break;
1266 case ATA_PIO1: reg20 = 0x00018121; break;
1267 case ATA_PIO2: reg20 = 0x00024020; break;
1268 case ATA_PIO3: reg20 = 0x00032010; break;
1269 case ATA_PIO4: reg20 = 0x00040010; break;
1270 case ATA_WDMA2: reg24 = 0x00002020; break;
1271 case ATA_UDMA2: reg24 = 0x00911030; break;
1273 ATA_OUTL(ch->r_bmio, (devno << 3) + 0x20, reg20);
1274 ATA_OUTL(ch->r_bmio, (devno << 3) + 0x24, reg24);
1278 promise_timing(struct ata_channel *ch, int devno, int mode)
1280 u_int32_t timing = 0;
1281 struct promise_timing {
1283 u_int8_t prefetch:1;
1294 u_int8_t reserved:8;
1295 } *t = (struct promise_timing*)&timing;
1297 t->iordy = 1; t->iordyp = 1;
1298 if (mode >= ATA_DMA) {
1299 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
1302 switch (ch->chiptype) {
1303 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
1306 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
1307 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
1308 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
1309 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
1310 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
1311 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
1312 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1316 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
1317 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
1318 case 0x0d30105a: /* Promise OEM ATA 100 */
1321 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
1322 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
1323 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
1324 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
1325 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
1326 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
1327 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
1328 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1329 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1333 pci_write_config(device_get_parent(ch->dev), 0x60 + (devno<<2), timing, 4);
1337 hpt_timing(struct ata_channel *ch, int devno, int mode)
1339 device_t parent = device_get_parent(ch->dev);
1342 if (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07) {
1343 switch (mode) { /* HPT374 */
1344 case ATA_PIO0: timing = 0x0ac1f48a; break;
1345 case ATA_PIO1: timing = 0x0ac1f465; break;
1346 case ATA_PIO2: timing = 0x0a81f454; break;
1347 case ATA_PIO3: timing = 0x0a81f443; break;
1348 case ATA_PIO4: timing = 0x0a81f442; break;
1349 case ATA_WDMA2: timing = 0x22808242; break;
1350 case ATA_UDMA2: timing = 0x120c8242; break;
1351 case ATA_UDMA4: timing = 0x12ac8242; break;
1352 case ATA_UDMA5: timing = 0x12848242; break;
1353 case ATA_UDMA6: timing = 0x12808242; break;
1354 default: timing = 0x0d029d5e;
1357 else if ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x05) ||
1358 (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01)) {
1359 switch (mode) { /* HPT372 */
1360 case ATA_PIO0: timing = 0x0d029d5e; break;
1361 case ATA_PIO1: timing = 0x0d029d26; break;
1362 case ATA_PIO2: timing = 0x0c829ca6; break;
1363 case ATA_PIO3: timing = 0x0c829c84; break;
1364 case ATA_PIO4: timing = 0x0c829c62; break;
1365 case ATA_WDMA2: timing = 0x2c829262; break;
1366 case ATA_UDMA2: timing = 0x1c91dc62; break;
1367 case ATA_UDMA4: timing = 0x1c8ddc62; break;
1368 case ATA_UDMA5: timing = 0x1c6ddc62; break;
1369 case ATA_UDMA6: timing = 0x1c81dc62; break;
1370 default: timing = 0x0d029d5e;
1373 else if (ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x03) {
1374 switch (mode) { /* HPT370 */
1375 case ATA_PIO0: timing = 0x06914e57; break;
1376 case ATA_PIO1: timing = 0x06914e43; break;
1377 case ATA_PIO2: timing = 0x06514e33; break;
1378 case ATA_PIO3: timing = 0x06514e22; break;
1379 case ATA_PIO4: timing = 0x06514e21; break;
1380 case ATA_WDMA2: timing = 0x26514e21; break;
1381 case ATA_UDMA2: timing = 0x16494e31; break;
1382 case ATA_UDMA4: timing = 0x16454e31; break;
1383 case ATA_UDMA5: timing = 0x16454e31; break;
1384 default: timing = 0x06514e57;
1386 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1388 else { /* HPT36[68] */
1389 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
1390 case 0x85: /* 25Mhz */
1392 case ATA_PIO0: timing = 0x40d08585; break;
1393 case ATA_PIO1: timing = 0x40d08572; break;
1394 case ATA_PIO2: timing = 0x40ca8542; break;
1395 case ATA_PIO3: timing = 0x40ca8532; break;
1396 case ATA_PIO4: timing = 0x40ca8521; break;
1397 case ATA_WDMA2: timing = 0x20ca8521; break;
1398 case ATA_UDMA2: timing = 0x10cf8521; break;
1399 case ATA_UDMA4: timing = 0x10c98521; break;
1400 default: timing = 0x01208585;
1404 case 0xa7: /* 33MHz */
1406 case ATA_PIO0: timing = 0x40d0a7aa; break;
1407 case ATA_PIO1: timing = 0x40d0a7a3; break;
1408 case ATA_PIO2: timing = 0x40d0a753; break;
1409 case ATA_PIO3: timing = 0x40c8a742; break;
1410 case ATA_PIO4: timing = 0x40c8a731; break;
1411 case ATA_WDMA2: timing = 0x20c8a731; break;
1412 case ATA_UDMA2: timing = 0x10caa731; break;
1413 case ATA_UDMA4: timing = 0x10c9a731; break;
1414 default: timing = 0x0120a7a7;
1417 case 0xd9: /* 40Mhz */
1419 case ATA_PIO0: timing = 0x4018d9d9; break;
1420 case ATA_PIO1: timing = 0x4010d9c7; break;
1421 case ATA_PIO2: timing = 0x4010d997; break;
1422 case ATA_PIO3: timing = 0x4010d974; break;
1423 case ATA_PIO4: timing = 0x4008d963; break;
1424 case ATA_WDMA2: timing = 0x2008d943; break;
1425 case ATA_UDMA2: timing = 0x100bd943; break;
1426 case ATA_UDMA4: timing = 0x100fd943; break;
1427 default: timing = 0x0120d9d9;
1431 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1435 hpt_cable80(struct ata_channel *ch)
1437 device_t parent = device_get_parent(ch->dev);
1438 u_int8_t reg, val, res;
1440 if (ch->chiptype == 0x00081103 && pci_get_function(parent) == 1) {
1441 reg = ch->unit ? 0x57 : 0x53;
1442 val = pci_read_config(parent, reg, 1);
1443 pci_write_config(parent, reg, val | 0x80, 1);
1447 val = pci_read_config(parent, reg, 1);
1448 pci_write_config(parent, reg, val & 0xfe, 1);
1450 res = pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x01 : 0x02);
1451 pci_write_config(parent, reg, val, 1);