2 * Copyright (c) 1997,1998 Maxim Bolotin and Oleg Sharoiko.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * $FreeBSD: src/sys/dev/cs/if_csreg.h,v 1.3.2.1 2001/01/25 20:13:48 imp Exp $
31 * $DragonFly: src/sys/dev/netif/cs/if_csreg.h,v 1.2 2003/06/17 04:28:23 dillon Exp $
34 #define CS_89x0_IO_PORTS 0x0020
36 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
37 /* offset 2h -> Model/Product Number */
38 /* offset 3h -> Chip Revision Number */
40 #define PP_ISAIOB 0x0020 /* IO base address */
41 #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
42 #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
43 #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
44 #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
45 #define PP_ISASOF 0x0026 /* ISA DMA offset */
46 #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
47 #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
48 #define PP_CS8920_ISAMemB 0x0348 /* Memory base */
50 /* EEPROM data and command registers */
51 #define PP_EECMD 0x0040 /* NVR Interface Command register */
52 #define PP_EEData 0x0042 /* NVR Interface Data Register */
53 #define PP_DebugReg 0x0044 /* Debug Register */
55 #define PP_RxCFG 0x0102 /* Rx Bus config */
56 #define PP_RxCTL 0x0104 /* Receive Control Register */
57 #define PP_TxCFG 0x0106 /* Transmit Config Register */
58 #define PP_TxCMD 0x0108 /* Transmit Command Register */
59 #define PP_BufCFG 0x010A /* Bus configuration Register */
60 #define PP_LineCTL 0x0112 /* Line Config Register */
61 #define PP_SelfCTL 0x0114 /* Self Command Register */
62 #define PP_BusCTL 0x0116 /* ISA bus control Register */
63 #define PP_TestCTL 0x0118 /* Test Register */
64 #define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */
66 #define PP_ISQ 0x0120 /* Interrupt Status */
67 #define PP_RxEvent 0x0124 /* Rx Event Register */
68 #define PP_TxEvent 0x0128 /* Tx Event Register */
69 #define PP_BufEvent 0x012C /* Bus Event Register */
70 #define PP_RxMiss 0x0130 /* Receive Miss Count */
71 #define PP_TxCol 0x0132 /* Transmit Collision Count */
72 #define PP_LineST 0x0134 /* Line State Register */
73 #define PP_SelfST 0x0136 /* Self State register */
74 #define PP_BusST 0x0138 /* Bus Status */
75 #define PP_TDR 0x013C /* Time Domain Reflectometry */
76 #define PP_AutoNegST 0x013E /* Auto Neg Status */
77 #define PP_TxCommand 0x0144 /* Tx Command */
78 #define PP_TxLength 0x0146 /* Tx Length */
79 #define PP_LAF 0x0150 /* Hash Table */
80 #define PP_IA 0x0158 /* Physical Address Register */
82 #define PP_RxStatus 0x0400 /* Receive start of frame */
83 #define PP_RxLength 0x0402 /* Receive Length of frame */
84 #define PP_RxFrame 0x0404 /* Receive frame pointer */
85 #define PP_TxFrame 0x0A00 /* Transmit frame pointer */
88 * Primary I/O Base Address. If no I/O base is supplied by the user, then this
89 * can be used as the default I/O base to access the PacketPage Area.
91 #define DEFAULTIOBASE 0x0300
92 #define FIRST_IO 0x020C /* First I/O port to check */
93 #define LAST_IO 0x037C /* Last I/O port to check (+10h) */
94 #define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */
95 #define ADD_SIG 0x3000 /* Expected ID signature */
97 #define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */
99 #define PRODUCT_ID_ADD 0x0002 /* Address of product ID */
101 /* Mask to find out the types of registers */
102 #define REG_TYPE_MASK 0x001F
104 /* Eeprom Commands */
105 #define ERSE_WR_ENBL 0x00F0
106 #define ERSE_WR_DISABLE 0x0000
108 /* Defines Control/Config register quintuplet numbers */
109 #define RX_BUF_CFG 0x0003
110 #define RX_CONTROL 0x0005
111 #define TX_CFG 0x0007
112 #define TX_COMMAND 0x0009
113 #define BUF_CFG 0x000B
114 #define LINE_CONTROL 0x0013
115 #define SELF_CONTROL 0x0015
116 #define BUS_CONTROL 0x0017
117 #define TEST_CONTROL 0x0019
119 /* Defines Status/Count registers quintuplet numbers */
120 #define RX_EVENT 0x0004
121 #define TX_EVENT 0x0008
122 #define BUF_EVENT 0x000C
123 #define RX_MISS_COUNT 0x0010
124 #define TX_COL_COUNT 0x0012
125 #define LINE_STATUS 0x0014
126 #define SELF_STATUS 0x0016
127 #define BUS_STATUS 0x0018
131 * PP_RxCFG - Receive Configuration and Interrupt Mask
132 * bit definition - Read/write
134 #define SKIP_1 0x0040
135 #define RX_STREAM_ENBL 0x0080
136 #define RX_OK_ENBL 0x0100
137 #define RX_DMA_ONLY 0x0200
138 #define AUTO_RX_DMA 0x0400
139 #define BUFFER_CRC 0x0800
140 #define RX_CRC_ERROR_ENBL 0x1000
141 #define RX_RUNT_ENBL 0x2000
142 #define RX_EXTRA_DATA_ENBL 0x4000
144 /* PP_RxCTL - Receive Control bit definition - Read/write */
145 #define RX_IA_HASH_ACCEPT 0x0040
146 #define RX_PROM_ACCEPT 0x0080
147 #define RX_OK_ACCEPT 0x0100
148 #define RX_MULTCAST_ACCEPT 0x0200
149 #define RX_IA_ACCEPT 0x0400
150 #define RX_BROADCAST_ACCEPT 0x0800
151 #define RX_BAD_CRC_ACCEPT 0x1000
152 #define RX_RUNT_ACCEPT 0x2000
153 #define RX_EXTRA_DATA_ACCEPT 0x4000
154 #define RX_ALL_ACCEPT (RX_PROM_ACCEPT | RX_BAD_CRC_ACCEPT | \
155 RX_RUNT_ACCEPT | RX_EXTRA_DATA_ACCEPT)
157 * Default receive mode - individually addressed, broadcast, and error free
159 #define RX_DEF_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT)
162 * PP_TxCFG - Transmit Configuration Interrupt Mask
163 * bit definition - Read/write
165 #define TX_LOST_CRS_ENBL 0x0040
166 #define TX_SQE_ERROR_ENBL 0x0080
167 #define TX_OK_ENBL 0x0100
168 #define TX_LATE_COL_ENBL 0x0200
169 #define TX_JBR_ENBL 0x0400
170 #define TX_ANY_COL_ENBL 0x0800
171 #define TX_16_COL_ENBL 0x8000
174 * PP_TxCMD - Transmit Command bit definition - Read-only
176 #define TX_START_4_BYTES 0x0000
177 #define TX_START_64_BYTES 0x0040
178 #define TX_START_128_BYTES 0x0080
179 #define TX_START_ALL_BYTES 0x00C0
180 #define TX_FORCE 0x0100
181 #define TX_ONE_COL 0x0200
182 #define TX_TWO_PART_DEFF_DISABLE 0x0400
183 #define TX_NO_CRC 0x1000
184 #define TX_RUNT 0x2000
187 * PP_BufCFG - Buffer Configuration Interrupt Mask
188 * bit definition - Read/write
190 #define GENERATE_SW_INTERRUPT 0x0040
191 #define RX_DMA_ENBL 0x0080
192 #define READY_FOR_TX_ENBL 0x0100
193 #define TX_UNDERRUN_ENBL 0x0200
194 #define RX_MISS_ENBL 0x0400
195 #define RX_128_BYTE_ENBL 0x0800
196 #define TX_COL_COUNT_OVRFLOW_ENBL 0x1000
197 #define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
198 #define RX_DEST_MATCH_ENBL 0x8000
201 * PP_LineCTL - Line Control bit definition - Read/write
203 #define SERIAL_RX_ON 0x0040
204 #define SERIAL_TX_ON 0x0080
205 #define AUI_ONLY 0x0100
206 #define AUTO_AUI_10BASET 0x0200
207 #define MODIFIED_BACKOFF 0x0800
208 #define NO_AUTO_POLARITY 0x1000
209 #define TWO_PART_DEFDIS 0x2000
210 #define LOW_RX_SQUELCH 0x4000
213 * PP_SelfCTL - Software Self Control bit definition - Read/write
215 #define POWER_ON_RESET 0x0040
216 #define SW_STOP 0x0100
217 #define SLEEP_ON 0x0200
218 #define AUTO_WAKEUP 0x0400
219 #define HCB0_ENBL 0x1000
220 #define HCB1_ENBL 0x2000
225 * PP_BusCTL - ISA Bus Control bit definition - Read/write
227 #define RESET_RX_DMA 0x0040
228 #define MEMORY_ON 0x0400
229 #define DMA_BURST_MODE 0x0800
230 #define IO_CHANNEL_READY_ON 0x1000
231 #define RX_DMA_SIZE_64Ks 0x2000
232 #define ENABLE_IRQ 0x8000
235 * PP_TestCTL - Test Control bit definition - Read/write
237 #define LINK_OFF 0x0080
238 #define ENDEC_LOOPBACK 0x0200
239 #define AUI_LOOPBACK 0x0400
240 #define BACKOFF_OFF 0x0800
241 #define FAST_TEST 0x8000
244 * PP_RxEvent - Receive Event Bit definition - Read-only
246 #define RX_IA_HASHED 0x0040
247 #define RX_DRIBBLE 0x0080
249 #define RX_HASHED 0x0200
251 #define RX_BROADCAST 0x0800
252 #define RX_CRC_ERROR 0x1000
253 #define RX_RUNT 0x2000
254 #define RX_EXTRA_DATA 0x4000
256 #define HASH_INDEX_MASK 0x0FC00
259 * PP_TxEvent - Transmit Event Bit definition - Read-only
261 #define TX_LOST_CRS 0x0040
262 #define TX_SQE_ERROR 0x0080
264 #define TX_LATE_COL 0x0200
265 #define TX_JBR 0x0400
266 #define TX_16_COL 0x8000
267 #define TX_SEND_OK_BITS (TX_OK | TX_LOST_CRS)
268 #define TX_COL_COUNT_MASK 0x7800
271 * PP_BufEvent - Buffer Event Bit definition - Read-only
273 #define SW_INTERRUPT 0x0040
274 #define RX_DMA 0x0080
275 #define READY_FOR_TX 0x0100
276 #define TX_UNDERRUN 0x0200
277 #define RX_MISS 0x0400
278 #define RX_128_BYTE 0x0800
279 #define TX_COL_OVRFLW 0x1000
280 #define RX_MISS_OVRFLW 0x2000
281 #define RX_DEST_MATCH 0x8000
284 * PP_LineST - Ethernet Line Status bit definition - Read-only
286 #define LINK_OK 0x0080
287 #define AUI_ON 0x0100
288 #define TENBASET_ON 0x0200
289 #define POLARITY_OK 0x1000
290 #define CRS_OK 0x4000
293 * PP_SelfST - Chip Software Status bit definition
295 #define ACTIVE_33V 0x0040
296 #define INIT_DONE 0x0080
297 #define SI_BUSY 0x0100
298 #define EEPROM_PRESENT 0x0200
299 #define EEPROM_OK 0x0400
300 #define EL_PRESENT 0x0800
301 #define EE_SIZE_64 0x1000
304 * PP_BusST - ISA Bus Status bit definition
306 #define TX_BID_ERROR 0x0080
307 #define READY_FOR_TX_NOW 0x0100
310 * PP_AutoNegCTL - Auto Negotiation Control bit definition
312 #define RE_NEG_NOW 0x0040
313 #define ALLOW_FDX 0x0080
314 #define AUTO_NEG_ENABLE 0x0100
315 #define NLP_ENABLE 0x0200
316 #define FORCE_FDX 0x8000
317 #define AUTO_NEG_BITS (FORCE_FDX | NLP_ENABLE | AUTO_NEG_ENABLE)
318 #define AUTO_NEG_MASK (FORCE_FDX | NLP_ENABLE | AUTO_NEG_ENABLE | \
319 ALLOW_FDX | RE_NEG_NOW)
322 * PP_AutoNegST - Auto Negotiation Status bit definition
324 #define AUTO_NEG_BUSY 0x0080
325 #define FLP_LINK 0x0100
326 #define FLP_LINK_GOOD 0x0800
327 #define LINK_FAULT 0x1000
328 #define HDX_ACTIVE 0x4000
329 #define FDX_ACTIVE 0x8000
332 * The following block defines the ISQ event types
334 #define ISQ_RECEIVER_EVENT 0x04
335 #define ISQ_TRANSMITTER_EVENT 0x08
336 #define ISQ_BUFFER_EVENT 0x0c
337 #define ISQ_RX_MISS_EVENT 0x10
338 #define ISQ_TX_COL_EVENT 0x12
340 #define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */
341 #define ISQ_HIST 16 /* small history buffer */
342 #define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */
344 #define TXRXBUFSIZE 0x0600
345 #define RXDMABUFSIZE 0x8000
346 #define RXDMASIZE 0x4000
347 #define TXRX_LENGTH_MASK 0x07FF
349 /* rx options bits */
350 #define RCV_WITH_RXON 1 /* Set SerRx ON */
351 #define RCV_COUNTS 2 /* Use Framecnt1 */
352 #define RCV_PONG 4 /* Pong respondent */
353 #define RCV_DONG 8 /* Dong operation */
354 #define RCV_POLLING 0x10 /* Poll RxEvent */
355 #define RCV_ISQ 0x20 /* Use ISQ, int */
356 #define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */
357 #define RCV_DMA 0x200 /* Set RxDMA only */
358 #define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */
359 #define RCV_FIXED_DATA 0x800 /* Every frame same */
360 #define RCV_IO 0x1000 /* Use ISA IO only */
361 #define RCV_MEMORY 0x2000 /* Use ISA Memory */
363 #define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */
364 #define PKT_START PP_TxFrame /* Start of packet RAM */
366 #define RX_FRAME_PORT 0x0000
367 #define TX_FRAME_PORT RX_FRAME_PORT
368 #define TX_CMD_PORT 0x0004
369 #define TX_CS8900_NOW 0x0000 /* Tx packet after 5 bytes copied */
370 #define TX_CS8900_AFTER_381 0x0020 /* Tx packet after 381 bytes copied */
371 #define TX_CS8900_AFTER_ALL 0x0060 /* Tx packet after all bytes copied */
372 #define TX_CS8920_NOW 0x0000 /* Tx packet after 5 bytes copied */
373 #define TX_CS8920_AFTER_381 0x0040 /* Tx packet after 381 bytes copied */
374 #define TX_CS8920_AFTER_1021 0x0080 /* Tx packet after1021 bytes copied */
375 #define TX_CS8920_AFTER_ALL 0x00C0 /* Tx packet after all bytes copied */
376 #define TX_LEN_PORT 0x0006
377 #define ISQ_PORT 0x0008
378 #define ADD_PORT 0x000A
379 #define DATA_PORT 0x000C
381 #define EEPROM_WRITE_EN 0x00F0
382 #define EEPROM_WRITE_DIS 0x0000
383 #define EEPROM_WRITE_CMD 0x0100
384 #define EEPROM_READ_CMD 0x0200
387 * Description of header of each packet in receive area of memory
389 #define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */
390 #define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */
391 #define RBUF_LEN_LOW 2 /* Length of received data - low byte */
392 #define RBUF_LEN_HI 3 /* Length of received data - high byte */
393 #define RBUF_HEAD_LEN 4 /* Length of this header */
395 #define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */
396 #define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */
401 /* use these values for debugging bios scan */
402 #define BIOS_START_SEG 0x00000
403 #define BIOS_OFFSET_INC 0x0010
405 #define BIOS_START_SEG 0x0c000
406 #define BIOS_OFFSET_INC 0x0200
409 #define BIOS_LAST_OFFSET 0x0fc00
412 * Byte offsets into the EEPROM configuration buffer
414 #define ISA_CNF_OFFSET 0x6
415 #define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8) /* 8900 eeprom */
416 #define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8) /* 8920 eeprom */
419 * the assumption here is that the bits in the eeprom are generally
420 * in the same position as those in the autonegctl register.
421 * Of course the IMM bit is not in that register so it must be
424 #define EE_FORCE_FDX 0x8000
425 #define EE_NLP_ENABLE 0x0200
426 #define EE_AUTO_NEG_ENABLE 0x0100
427 #define EE_ALLOW_FDX 0x0080
428 #define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX | EE_NLP_ENABLE | \
429 EE_AUTO_NEG_ENABLE | EE_ALLOW_FDX)
431 #define IMM_BIT 0x0040 /* ignore missing media */
433 #define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2)
434 #define A_CNF_MEDIA 0x0007
435 #define A_CNF_10B_T 0x0001
436 #define A_CNF_AUI 0x0002
437 #define A_CNF_10B_2 0x0004
438 #define A_CNF_MEDIA_TYPE 0x0060
439 #define A_CNF_MEDIA_AUTO 0x0000
440 #define A_CNF_MEDIA_10B_T 0x0020
441 #define A_CNF_MEDIA_AUI 0x0040
442 #define A_CNF_MEDIA_10B_2 0x0060
443 #define A_CNF_DC_DC_POLARITY 0x0080
444 #define A_CNF_NO_AUTO_POLARITY 0x2000
445 #define A_CNF_LOW_RX_SQUELCH 0x4000
446 #define A_CNF_EXTND_10B_2 0x8000
448 #define PACKET_PAGE_OFFSET 0x8
451 * Bit definitions for the ISA configuration word from the EEPROM
453 #define INT_NO_MASK 0x000F
454 #define DMA_NO_MASK 0x0070
455 #define ISA_DMA_SIZE 0x0200
456 #define ISA_AUTO_RxDMA 0x0400
457 #define ISA_RxDMA 0x0800
458 #define DMA_BURST 0x1000
459 #define STREAM_TRANSFER 0x2000
460 #define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA)
462 /* DMA controller registers */
463 #define DMA_BASE 0x00 /* DMA controller base */
464 #define DMA_BASE_2 0x0C0 /* DMA controller base */
466 #define DMA_STAT 0x0D0 /* DMA controller status register */
467 #define DMA_MASK 0x0D4 /* DMA controller mask register */
468 #define DMA_MODE 0x0D6 /* DMA controller mode register */
469 #define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */
472 #define DMA_DISABLE 0x04 /* Disable channel n */
473 #define DMA_ENABLE 0x00 /* Enable channel n */
474 /* Demand transfers, incr. address, auto init, writes, ch. n */
475 #define DMA_RX_MODE 0x14
476 /* Demand transfers, incr. address, auto init, reads, ch. n */
477 #define DMA_TX_MODE 0x18
479 #define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */
481 #define CS8900 0x0000
482 #define CS8920 0x4000
483 #define CS8920M 0x6000
484 #define REVISON_BITS 0x1F00
485 #define EEVER_NUMBER 0x12
486 #define CHKSUM_LEN 0x14
487 #define CHKSUM_VAL 0x0000
488 #define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */
489 #define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */
490 #define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */
491 #define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */
492 #define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */
494 #define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */
496 #define PNP_ADD_PORT 0x0279
497 #define PNP_WRITE_PORT 0x0A79
499 #define GET_PNP_ISA_STRUCT 0x40
500 #define PNP_ISA_STRUCT_LEN 0x06
501 #define PNP_CSN_CNT_OFF 0x01
502 #define PNP_RD_PORT_OFF 0x02
503 #define PNP_FUNCTION_OK 0x00
504 #define PNP_WAKE 0x03
505 #define PNP_RSRC_DATA 0x04
506 #define PNP_RSRC_READY 0x01
507 #define PNP_STATUS 0x05
508 #define PNP_ACTIVATE 0x30
509 #define PNP_CNF_IO_H 0x60
510 #define PNP_CNF_IO_L 0x61
511 #define PNP_CNF_INT 0x70
512 #define PNP_CNF_DMA 0x74
513 #define PNP_CNF_MEM 0x48
518 #define CS_DUPLEX_AUTO 0
519 #define CS_DUPLEX_FULL 1
520 #define CS_DUPLEX_HALF 2
525 #define cs_readreg(iobase, portno) \
526 (outw((iobase) + ADD_PORT, (portno)), \
527 inw((iobase) + DATA_PORT))
528 #define cs_writereg(iobase, portno, value) \
529 (outw((iobase) + ADD_PORT, (portno)), \
530 outw((iobase) + DATA_PORT, (value)))
531 #define cs_readword(iobase, portno) \
532 (inw((iobase) + (portno)))
533 #define cs_writeword(iobase, portno, value) \
534 (outw((iobase) + (portno), (value)))
536 #define reset_chip(nic_addr) \
537 cs_writereg(nic_addr, PP_SelfCTL, cs_readreg(ioaddr, PP_SelfCTL) | POWER_ON_RESET), \
540 #define cs_duplex_full(sc) \
541 (cs_writereg(sc->nic_addr, PP_AutoNegCTL, FORCE_FDX))
543 #define cs_duplex_half(sc) \
544 (cs_writereg(sc->nic_addr, PP_AutoNegCTL, NLP_ENABLE))