2 * Copyright (c) 1996 - 2001 John Hay.
3 * Copyright (c) 1996 SDL Communications, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the author nor the names of any co-contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * $FreeBSD: src/sys/dev/sr/if_sr.c,v 1.48.2.1 2002/06/17 15:10:58 jhay Exp $
31 * $DragonFly: src/sys/dev/netif/sr/if_sr.c,v 1.2 2003/06/17 04:28:31 dillon Exp $
35 * Programming assumptions and other issues.
37 * Only a 16K window will be used.
39 * The descriptors of a DMA channel will fit in a 16K memory window.
41 * The buffers of a transmit DMA channel will fit in a 16K memory window.
43 * When interface is going up, handshaking is set and it is only cleared
44 * when the interface is down'ed.
46 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
47 * internal/external clock, etc.....
51 #include "opt_netgraph.h"
53 #include <dev/sr/if_sr.h>
56 #include <sys/param.h>
57 #include <sys/systm.h>
58 #include <sys/kernel.h>
59 #include <sys/malloc.h>
61 #include <sys/sockio.h>
62 #include <sys/socket.h>
64 #include <machine/bus.h>
65 #include <machine/resource.h>
66 #include <machine/bus_pio.h>
67 #include <machine/bus_memio.h>
72 #include <sys/syslog.h>
74 #include <net/if_sppp.h>
79 #include <machine/md_var.h>
81 #include <dev/ic/hd64570.h>
82 #include <dev/sr/if_srregs.h>
85 #include <netgraph/ng_message.h>
86 #include <netgraph/netgraph.h>
88 /* #define USE_MODEMCK */
95 #define PPP_HEADER_LEN 4
98 static int next_sc_unit = 0;
101 static int sr_watcher = 0;
103 #endif /* NETGRAPH */
106 * Define the software interface for the card... There is one for
107 * every channel (port).
111 struct sppp ifsppp; /* PPP service w/in system */
112 #endif /* NETGRAPH */
113 struct sr_hardc *hc; /* card-level information */
115 int unit; /* With regard to all sr devices */
116 int subunit; /* With regard to this card */
119 u_int txdesc; /* DPRAM offset */
120 u_int txstart;/* DPRAM offset */
121 u_int txend; /* DPRAM offset */
122 u_int txtail; /* # of 1st free gran */
123 u_int txmax; /* # of free grans */
124 u_int txeda; /* err descr addr */
125 } block[SR_TX_BLOCKS];
127 char xmit_busy; /* Transmitter is busy */
128 char txb_inuse; /* # of tx grans in use */
129 u_int txb_new; /* ndx to new buffer */
130 u_int txb_next_tx; /* ndx to next gran rdy tx */
132 u_int rxdesc; /* DPRAM offset */
133 u_int rxstart; /* DPRAM offset */
134 u_int rxend; /* DPRAM offset */
135 u_int rxhind; /* ndx to the hd of rx bufrs */
136 u_int rxmax; /* # of avail grans */
138 u_int clk_cfg; /* Clock configuration */
140 int scachan; /* channel # on card */
142 int running; /* something is attached so we are running */
143 int dcd; /* do we have dcd? */
144 /* ---netgraph bits --- */
145 char nodename[NG_NODELEN + 1]; /* store our node name */
146 int datahooks; /* number of data hooks attached */
147 node_p node; /* netgraph node */
148 hook_p hook; /* data hook */
150 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */
151 struct ifqueue xmitq; /* transmit queue */
152 int flags; /* state */
153 #define SCF_RUNNING 0x01 /* board is active */
154 #define SCF_OACTIVE 0x02 /* output is active */
155 int out_dog; /* watchdog cycles output count-down */
156 #if ( __FreeBSD__ >= 3 )
157 struct callout_handle handle; /* timeout(9) handle */
159 u_long inbytes, outbytes; /* stats */
160 u_long lastinbytes, lastoutbytes; /* a second ago */
161 u_long inrate, outrate; /* highest rate seen */
162 u_long inlast; /* last input N secs ago */
163 u_long out_deficit; /* output since last input */
164 u_long oerrors, ierrors[6];
165 u_long opackets, ipackets;
166 #endif /* NETGRAPH */
170 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */
171 #define QUITE_A_WHILE 300 /* 5 MINUTES */
172 #define LOTS_OF_PACKETS 100
173 #endif /* NETGRAPH */
176 * Baud Rate table for Sync Mode.
177 * Each entry consists of 3 elements:
178 * Baud Rate (x100) , TMC, BR
180 * Baud Rate = FCLK / TMC / 2^BR
181 * Baud table for Crystal freq. of 9.8304 Mhz
185 int target; /* target rate/100 */
186 int tmc_reg; /* TMC register value */
187 int br_reg; /* BR (BaudRateClk) selector */
189 /* Baudx100 TMC BR */
210 int sr_test_speed[] = {
216 SR_MCR_ETC0, /* ISA channel 0 */
217 SR_MCR_ETC1, /* ISA channel 1 */
218 SR_FECR_ETC0, /* PCI channel 0 */
219 SR_FECR_ETC1 /* PCI channel 1 */
223 devclass_t sr_devclass;
225 MODULE_DEPEND(if_sr, sppp, 1, 1, 1);
227 MODULE_DEPEND(ng_sync_sr, netgraph, 1, 1, 1);
230 static void srintr(void *arg);
231 static void sr_xmit(struct sr_softc *sc);
233 static void srstart(struct ifnet *ifp);
234 static int srioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
235 static void srwatchdog(struct ifnet *ifp);
237 static void srstart(struct sr_softc *sc);
238 static void srwatchdog(struct sr_softc *sc);
239 #endif /* NETGRAPH */
240 static int sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat);
241 static void sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len);
242 static void sr_eat_packet(struct sr_softc *sc, int single);
243 static void sr_get_packets(struct sr_softc *sc);
245 static void sr_up(struct sr_softc *sc);
246 static void sr_down(struct sr_softc *sc);
247 static void src_init(struct sr_hardc *hc);
248 static void sr_init_sca(struct sr_hardc *hc);
249 static void sr_init_msci(struct sr_softc *sc);
250 static void sr_init_rx_dmac(struct sr_softc *sc);
251 static void sr_init_tx_dmac(struct sr_softc *sc);
252 static void sr_dmac_intr(struct sr_hardc *hc, u_char isr);
253 static void sr_msci_intr(struct sr_hardc *hc, u_char isr);
254 static void sr_timer_intr(struct sr_hardc *hc, u_char isr);
257 static void sr_modemck(void *x);
260 static void sr_modemck(struct sr_softc *x);
261 #endif /* NETGRAPH */
264 static void ngsr_watchdog_frame(void * arg);
265 static void ngsr_init(void* ignored);
267 static ng_constructor_t ngsr_constructor;
268 static ng_rcvmsg_t ngsr_rcvmsg;
269 static ng_shutdown_t ngsr_rmnode;
270 static ng_newhook_t ngsr_newhook;
271 /*static ng_findhook_t ngsr_findhook; */
272 static ng_connect_t ngsr_connect;
273 static ng_rcvdata_t ngsr_rcvdata;
274 static ng_disconnect_t ngsr_disconnect;
276 static struct ng_type typestruct = {
292 static int ngsr_done_init = 0;
293 #endif /* NETGRAPH */
296 * Register the ports on the adapter.
297 * Fill in the info for each port.
299 * Attach each port to sppp and bpf.
303 sr_attach(device_t device)
312 #endif /* NETGRAPH */
313 int unit; /* index: channel w/in card */
315 hc = (struct sr_hardc *)device_get_softc(device);
316 MALLOC(sc, struct sr_softc *,
317 hc->numports * sizeof(struct sr_softc),
318 M_DEVBUF, M_WAITOK | M_ZERO);
324 * Get the TX clock direction and configuration. The default is a
325 * single external clock which is used by RX and TX.
327 switch(hc->cardtype) {
329 flags = device_get_flags(device);
331 if (sr_test_speed[0] > 0)
332 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
335 if (flags & SR_FLAGS_0_CLK_MSK)
337 (flags & SR_FLAGS_0_CLK_MSK)
338 >> SR_FLAGS_CLK_SHFT;
340 if (hc->numports == 2)
342 if (sr_test_speed[1] > 0)
343 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
346 if (flags & SR_FLAGS_1_CLK_MSK)
347 hc->sc[1].clk_cfg = (flags & SR_FLAGS_1_CLK_MSK)
348 >> (SR_FLAGS_CLK_SHFT +
349 SR_FLAGS_CLK_CHAN_SHFT);
352 fecrp = (u_int *)(hc->sca_base + SR_FECR);
354 for (pndx = 0; pndx < hc->numports; pndx++, sc++) {
357 intf_sw = fecr & SR_FECR_ID1 >> SR_FE_ID1_SHFT;
361 intf_sw = fecr & SR_FECR_ID0 >> SR_FE_ID0_SHFT;
365 if (sr_test_speed[pndx] > 0)
366 sc->clk_cfg = SR_FLAGS_INT_CLK;
378 sc->clk_cfg = SR_FLAGS_EXT_SEP_CLK;
382 sc->clk_cfg = SR_FLAGS_EXT_CLK;
391 * Report Card configuration information before we start configuring
392 * each channel on the card...
394 printf("src%d: %uK RAM (%d mempages) @ %08x-%08x, %u ports.\n",
395 hc->cunit, hc->memsize / 1024, hc->mempages,
396 (u_int)hc->mem_start, (u_int)hc->mem_end, hc->numports);
401 if (BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
402 INTR_TYPE_NET, srintr, hc, &hc->intr_cookie) != 0)
406 * Now configure each port on the card.
408 for (unit = 0; unit < hc->numports; sc++, unit++) {
411 sc->unit = next_sc_unit;
413 sc->scachan = unit % NCHAN;
419 printf("sr%d: Adapter %d, port %d.\n",
420 sc->unit, hc->cunit, sc->subunit);
423 ifp = &sc->ifsppp.pp_if;
425 ifp->if_unit = sc->unit;
427 ifp->if_mtu = PP_MTU;
428 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
429 ifp->if_ioctl = srioctl;
430 ifp->if_start = srstart;
431 ifp->if_watchdog = srwatchdog;
433 sc->ifsppp.pp_flags = PP_KEEPALIVE;
434 sppp_attach((struct ifnet *)&sc->ifsppp);
437 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
440 * we have found a node, make sure our 'type' is availabe.
442 if (ngsr_done_init == 0) ngsr_init(NULL);
443 if (ng_make_node_common(&typestruct, &sc->node) != 0)
445 sc->node->private = sc;
446 callout_handle_init(&sc->handle);
447 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
448 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
449 sprintf(sc->nodename, "%s%d", NG_SR_NODE_TYPE, sc->unit);
450 if (ng_name_node(sc->node, sc->nodename)) {
456 #endif /* NETGRAPH */
460 SRC_SET_OFF(hc->iobase);
465 sr_deallocate_resources(device);
470 sr_detach(device_t device)
472 device_t parent = device_get_parent(device);
473 struct sr_hardc *hc = device_get_softc(device);
475 if (hc->intr_cookie != NULL) {
476 if (BUS_TEARDOWN_INTR(parent, device,
477 hc->res_irq, hc->intr_cookie) != 0) {
478 printf("intr teardown failed.. continuing\n");
480 hc->intr_cookie = NULL;
483 /* XXX Stop the DMA. */
486 * deallocate any system resources we may have
487 * allocated on behalf of this driver.
489 FREE(hc->sc, M_DEVBUF);
491 hc->mem_start = NULL;
492 return (sr_deallocate_resources(device));
496 sr_allocate_ioport(device_t device, int rid, u_long size)
498 struct sr_hardc *hc = device_get_softc(device);
500 hc->rid_ioport = rid;
501 hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT,
502 &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE);
503 if (hc->res_ioport == NULL) {
509 sr_deallocate_resources(device);
514 sr_allocate_irq(device_t device, int rid, u_long size)
516 struct sr_hardc *hc = device_get_softc(device);
519 hc->res_irq = bus_alloc_resource(device, SYS_RES_IRQ,
520 &hc->rid_irq, 0ul, ~0ul, 1, RF_SHAREABLE|RF_ACTIVE);
521 if (hc->res_irq == NULL) {
527 sr_deallocate_resources(device);
532 sr_allocate_memory(device_t device, int rid, u_long size)
534 struct sr_hardc *hc = device_get_softc(device);
536 hc->rid_memory = rid;
537 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
538 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
539 if (hc->res_memory == NULL) {
545 sr_deallocate_resources(device);
550 sr_allocate_plx_memory(device_t device, int rid, u_long size)
552 struct sr_hardc *hc = device_get_softc(device);
554 hc->rid_plx_memory = rid;
555 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
556 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
557 if (hc->res_plx_memory == NULL) {
563 sr_deallocate_resources(device);
568 sr_deallocate_resources(device_t device)
570 struct sr_hardc *hc = device_get_softc(device);
572 if (hc->res_irq != 0) {
573 bus_deactivate_resource(device, SYS_RES_IRQ,
574 hc->rid_irq, hc->res_irq);
575 bus_release_resource(device, SYS_RES_IRQ,
576 hc->rid_irq, hc->res_irq);
579 if (hc->res_ioport != 0) {
580 bus_deactivate_resource(device, SYS_RES_IOPORT,
581 hc->rid_ioport, hc->res_ioport);
582 bus_release_resource(device, SYS_RES_IOPORT,
583 hc->rid_ioport, hc->res_ioport);
586 if (hc->res_memory != 0) {
587 bus_deactivate_resource(device, SYS_RES_MEMORY,
588 hc->rid_memory, hc->res_memory);
589 bus_release_resource(device, SYS_RES_MEMORY,
590 hc->rid_memory, hc->res_memory);
593 if (hc->res_plx_memory != 0) {
594 bus_deactivate_resource(device, SYS_RES_MEMORY,
595 hc->rid_plx_memory, hc->res_plx_memory);
596 bus_release_resource(device, SYS_RES_MEMORY,
597 hc->rid_plx_memory, hc->res_plx_memory);
598 hc->res_plx_memory = 0;
604 * N2 Interrupt Service Routine
606 * First figure out which SCA gave the interrupt.
608 * See if there is other interrupts pending.
609 * Repeat until there no interrupts remain.
614 struct sr_hardc *hc = (struct sr_hardc *)arg;
615 sca_regs *sca = hc->sca; /* MSCI register tree */
616 u_char isr0, isr1, isr2; /* interrupt statii captured */
619 printf("sr: srintr_hc(hc=%08x)\n", hc);
623 * Since multiple interfaces may share this interrupt, we must loop
624 * until no interrupts are still pending service.
628 * Read all three interrupt status registers from the N2
631 isr0 = SRC_GET8(hc->sca_base, sca->isr0);
632 isr1 = SRC_GET8(hc->sca_base, sca->isr1);
633 isr2 = SRC_GET8(hc->sca_base, sca->isr2);
636 * If all three registers returned 0, we've finished
637 * processing interrupts from this device, so we can quit
640 if ((isr0 | isr1 | isr2) == 0)
644 printf("src%d: srintr_hc isr0 %x, isr1 %x, isr2 %x\n",
646 unit, isr0, isr1, isr2);
648 hc->cunit, isr0, isr1, isr2);
649 #endif /* NETGRAPH */
653 * Now we can dispatch the interrupts. Since we don't expect
654 * either MSCI or timer interrupts, we'll test for DMA
655 * interrupts first...
657 if (isr1) /* DMA-initiated interrupt */
658 sr_dmac_intr(hc, isr1);
660 if (isr0) /* serial part IRQ? */
661 sr_msci_intr(hc, isr0);
663 if (isr2) /* timer-initiated interrupt */
664 sr_timer_intr(hc, isr2);
669 * This will only start the transmitter. It is assumed that the data
671 * It is normally called from srstart() or sr_dmac_intr().
674 sr_xmit(struct sr_softc *sc)
676 u_short cda_value; /* starting descriptor */
677 u_short eda_value; /* ending descriptor */
680 struct ifnet *ifp; /* O/S Network Services */
681 #endif /* NETGRAPH */
682 dmac_channel *dmac; /* DMA channel registers */
685 printf("sr: sr_xmit( sc=%08x)\n", sc);
690 ifp = &sc->ifsppp.pp_if;
691 #endif /* NETGRAPH */
692 dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
695 * Get the starting and ending addresses of the chain to be
696 * transmitted and pass these on to the DMA engine on-chip.
698 cda_value = sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart;
699 cda_value &= 0x00ffff;
700 eda_value = sc->block[sc->txb_next_tx].txeda + hc->mem_pstart;
701 eda_value &= 0x00ffff;
703 SRC_PUT16(hc->sca_base, dmac->cda, cda_value);
704 SRC_PUT16(hc->sca_base, dmac->eda, eda_value);
707 * Now we'll let the DMA status register know about this change
709 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
711 sc->xmit_busy = 1; /* mark transmitter busy */
714 printf("sr%d: XMIT cda=%04x, eda=%4x, rcda=%08lx\n",
715 sc->unit, cda_value, eda_value,
716 sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart);
719 sc->txb_next_tx++; /* update next transmit seq# */
721 if (sc->txb_next_tx == SR_TX_BLOCKS) /* handle wrap... */
726 * Finally, we'll set a timout (which will start srwatchdog())
727 * within the O/S network services layer...
729 ifp->if_timer = 2; /* Value in seconds. */
732 * Don't time out for a while.
734 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/
735 #endif /* NETGRAPH */
739 * This function will be called from the upper level when a user add a
740 * packet to be send, and from the interrupt handler after a finished
743 * NOTE: it should run at spl_imp().
745 * This function only place the data in the oncard buffers. It does not
746 * start the transmition. sr_xmit() does that.
748 * Transmitter idle state is indicated by the IFF_OACTIVE flag.
749 * The function that clears that should ensure that the transmitter
750 * and its DMA is in a "good" idle state.
754 srstart(struct ifnet *ifp)
756 struct sr_softc *sc; /* channel control structure */
759 srstart(struct sr_softc *sc)
761 #endif /* NETGRAPH */
762 struct sr_hardc *hc; /* card control/config block */
763 int len; /* total length of a packet */
764 int pkts; /* packets placed in DPRAM */
765 int tlen; /* working length of pkt */
767 struct mbuf *mtx; /* message buffer from O/S */
768 u_char *txdata; /* buffer address in DPRAM */
769 sca_descriptor *txdesc; /* working descriptor pointr */
770 struct buf_block *blkp;
774 printf("sr: srstart( ifp=%08x)\n", ifp);
777 if ((ifp->if_flags & IFF_RUNNING) == 0)
779 #endif /* NETGRAPH */
782 * It is OK to set the memory window outside the loop because all tx
783 * buffers and descriptors are assumed to be in the same 16K window.
786 SRC_SET_ON(hc->iobase);
787 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
791 * Loop to place packets into DPRAM.
793 * We stay in this loop until there is nothing in
794 * the TX queue left or the tx buffers are full.
799 * See if we have space for more packets.
801 if (sc->txb_inuse == SR_TX_BLOCKS) { /* out of space? */
803 ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */
805 /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */
806 #endif /* NETGRAPH */
809 SRC_SET_OFF(hc->iobase);
812 printf("sr%d.srstart: sc->txb_inuse=%d; DPRAM full...\n",
813 sc->unit, sc->txb_inuse);
818 * OK, the card can take more traffic. Let's see if there's any
819 * pending from the system...
822 * The architecture of the networking interface doesn't
823 * actually call us like 'write()', providing an address. We get
824 * started, a lot like a disk strategy routine, and we actually call
825 * back out to the system to get traffic to send...
828 * If we were gonna run through another layer, we would use a
829 * dispatch table to select the service we're getting a packet
833 mtx = sppp_dequeue(ifp);
835 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
837 IF_DEQUEUE(&sc->xmitq, mtx);
839 #endif /* NETGRAPH */
842 SRC_SET_OFF(hc->iobase);
846 * OK, we got a packet from the network services of the O/S. Now we
847 * can move it into the DPRAM (under control of the descriptors) and
851 i = 0; /* counts # of granules used */
853 blkp = &sc->block[sc->txb_new]; /* address of free granule */
854 txdesc = (sca_descriptor *)
855 (hc->mem_start + (blkp->txdesc & hc->winmsk));
857 txdata = (u_char *)(hc->mem_start
858 + (blkp->txstart & hc->winmsk));
861 * Now we'll try to install as many packets as possible into the
862 * card's DP RAM buffers.
864 for (;;) { /* perform actual copy of packet */
865 len = mtx->m_pkthdr.len; /* length of message */
868 printf("sr%d.srstart: mbuf @ %08lx, %d bytes\n",
877 #endif /* NETGRAPH */
880 * We can perform a straight copy because the tranmit
881 * buffers won't wrap.
883 m_copydata(mtx, 0, len, txdata);
886 * Now we know how big the message is gonna be. We must now
887 * construct the descriptors to drive this message out...
890 while (tlen > SR_BUF_SIZ) { /* loop for full granules */
891 txdesc->stat = 0; /* reset bits */
892 txdesc->len = SR_BUF_SIZ; /* size of granule */
895 txdesc++; /* move to next dscr */
896 txdata += SR_BUF_SIZ; /* adjust data addr */
901 * This section handles the setting of the final piece of a
904 txdesc->stat = SCA_DESC_EOM;
909 * prepare for subsequent packets (if any)
912 txdata += SR_BUF_SIZ; /* next mem granule */
913 i++; /* count of granules */
916 * OK, we've now placed the message into the DPRAM where it
917 * can be transmitted. We'll now release the message memory
918 * and update the statistics...
922 ++sc->ifsppp.pp_if.if_opackets;
925 #endif /* NETGRAPH */
928 * Check if we have space for another packet. XXX This is
929 * hardcoded. A packet can't be larger than 3 buffers (3 x
932 if ((i + 3) >= blkp->txmax) { /* enough remains? */
934 printf("sr%d.srstart: i=%d (%d pkts); card full.\n",
940 * We'll pull the next message to be sent (if any)
943 mtx = sppp_dequeue(ifp);
945 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
947 IF_DEQUEUE(&sc->xmitq, mtx);
949 #endif /* NETGRAPH */
950 if (!mtx) { /* no message? We're done! */
952 printf("sr%d.srstart: pending=0, pkts=%d\n",
959 blkp->txtail = i; /* record next free granule */
962 * Mark the last descriptor, so that the SCA know where to stop.
964 txdesc--; /* back up to last descriptor in list */
965 txdesc->stat |= SCA_DESC_EOT; /* mark as end of list */
968 * Now we'll reset the transmit granule's descriptor address so we
969 * can record this in the structure and fire it off w/ the DMA
970 * processor of the serial chip...
972 txdesc = (sca_descriptor *)blkp->txdesc;
973 blkp->txeda = (u_short)((u_int)&txdesc[i]);
975 sc->txb_inuse++; /* update inuse status */
976 sc->txb_new++; /* new traffic wuz added */
978 if (sc->txb_new == SR_TX_BLOCKS)
982 * If the tranmitter wasn't marked as "busy" we will force it to be
985 if (sc->xmit_busy == 0) {
988 printf("sr%d.srstart: called sr_xmit()\n", sc->unit);
996 * Handle ioctl's at the device level, though we *will* call up
1000 static int bug_splats[] = {0, 0, 0, 0, 0, 0, 0, 0};
1004 srioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1006 int s, error, was_up, should_be_up;
1007 struct sr_softc *sc = ifp->if_softc;
1010 printf("sr%d: srioctl(ifp=%08x, cmd=%08x, data=%08x)\n",
1011 ifp->if_unit, ifp, cmd, data);
1014 was_up = ifp->if_flags & IFF_RUNNING;
1016 error = sppp_ioctl(ifp, cmd, data);
1019 printf("sr%d: ioctl: ifsppp.pp_flags = %08x, if_flags %08x.\n",
1020 ifp->if_unit, ((struct sppp *)ifp)->pp_flags, ifp->if_flags);
1026 if ((cmd != SIOCSIFFLAGS) && (cmd != SIOCSIFADDR)) {
1028 if (bug_splats[sc->unit]++ < 2) {
1029 printf("sr(%d).if_addrlist = %08x\n",
1030 sc->unit, ifp->if_addrlist);
1031 printf("sr(%d).if_bpf = %08x\n",
1032 sc->unit, ifp->if_bpf);
1033 printf("sr(%d).if_init = %08x\n",
1034 sc->unit, ifp->if_init);
1035 printf("sr(%d).if_output = %08x\n",
1036 sc->unit, ifp->if_output);
1037 printf("sr(%d).if_start = %08x\n",
1038 sc->unit, ifp->if_start);
1039 printf("sr(%d).if_done = %08x\n",
1040 sc->unit, ifp->if_done);
1041 printf("sr(%d).if_ioctl = %08x\n",
1042 sc->unit, ifp->if_ioctl);
1043 printf("sr(%d).if_reset = %08x\n",
1044 sc->unit, ifp->if_reset);
1045 printf("sr(%d).if_watchdog = %08x\n",
1046 sc->unit, ifp->if_watchdog);
1053 should_be_up = ifp->if_flags & IFF_RUNNING;
1055 if (!was_up && should_be_up) {
1057 * Interface should be up -- start it.
1063 * XXX Clear the IFF_UP flag so that the link will only go
1064 * up after sppp lcp and ipcp negotiation.
1066 /* ifp->if_flags &= ~IFF_UP; */
1067 } else if (was_up && !should_be_up) {
1069 * Interface should be down -- stop it.
1077 #endif /* NETGRAPH */
1080 * This is to catch lost tx interrupts.
1084 srwatchdog(struct ifnet *ifp)
1086 srwatchdog(struct sr_softc *sc)
1087 #endif /* NETGRAPH */
1089 int got_st0, got_st1, got_st3, got_dsr;
1091 struct sr_softc *sc = ifp->if_softc;
1092 #endif /* NETGRAPH */
1093 struct sr_hardc *hc = sc->hc;
1094 msci_channel *msci = &hc->sca->msci[sc->scachan];
1095 dmac_channel *dmac = &sc->hc->sca->dmac[sc->scachan];
1099 printf("srwatchdog(unit=%d)\n", unit);
1101 printf("srwatchdog(unit=%d)\n", sc->unit);
1102 #endif /* NETGRAPH */
1106 if (!(ifp->if_flags & IFF_RUNNING))
1109 ifp->if_oerrors++; /* update output error count */
1110 #else /* NETGRAPH */
1111 sc->oerrors++; /* update output error count */
1112 #endif /* NETGRAPH */
1114 got_st0 = SRC_GET8(hc->sca_base, msci->st0);
1115 got_st1 = SRC_GET8(hc->sca_base, msci->st1);
1116 got_st3 = SRC_GET8(hc->sca_base, msci->st3);
1117 got_dsr = SRC_GET8(hc->sca_base, dmac->dsr);
1121 if (ifp->if_flags & IFF_DEBUG)
1123 printf("sr%d: transmit failed, "
1124 #else /* NETGRAPH */
1125 printf("sr%d: transmit failed, "
1126 #endif /* NETGRAPH */
1127 "ST0 %02x, ST1 %02x, ST3 %02x, DSR %02x.\n",
1129 got_st0, got_st1, got_st3, got_dsr);
1131 if (SRC_GET8(hc->sca_base, msci->st1) & SCA_ST1_UDRN) {
1132 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXABORT);
1133 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1134 SRC_PUT8(hc->sca_base, msci->st1, SCA_ST1_UDRN);
1138 ifp->if_flags &= ~IFF_OACTIVE;
1140 /*ifp->if_flags &= ~IFF_OACTIVE; */
1141 #endif /* NETGRAPH */
1143 if (sc->txb_inuse && --sc->txb_inuse)
1147 srstart(ifp); /* restart transmitter */
1149 srstart(sc); /* restart transmitter */
1150 #endif /* NETGRAPH */
1154 sr_up(struct sr_softc *sc)
1157 struct sr_hardc *hc = sc->hc;
1158 sca_regs *sca = hc->sca;
1159 msci_channel *msci = &sca->msci[sc->scachan];
1162 printf("sr_up(sc=%08x)\n", sc);
1166 * Enable transmitter and receiver. Raise DTR and RTS. Enable
1169 * XXX What about using AUTO mode in msci->md0 ???
1171 SRC_PUT8(hc->sca_base, msci->ctl,
1172 SRC_GET8(hc->sca_base, msci->ctl) & ~SCA_CTL_RTS);
1174 if (sc->scachan == 0)
1175 switch (hc->cardtype) {
1177 outb(hc->iobase + SR_MCR,
1178 (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR0));
1181 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1182 *fecrp &= ~SR_FECR_DTR0;
1186 switch (hc->cardtype) {
1188 outb(hc->iobase + SR_MCR,
1189 (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR1));
1192 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1193 *fecrp &= ~SR_FECR_DTR1;
1197 if (sc->scachan == 0) {
1198 SRC_PUT8(hc->sca_base, sca->ier0,
1199 SRC_GET8(hc->sca_base, sca->ier0) | 0x000F);
1200 SRC_PUT8(hc->sca_base, sca->ier1,
1201 SRC_GET8(hc->sca_base, sca->ier1) | 0x000F);
1203 SRC_PUT8(hc->sca_base, sca->ier0,
1204 SRC_GET8(hc->sca_base, sca->ier0) | 0x00F0);
1205 SRC_PUT8(hc->sca_base, sca->ier1,
1206 SRC_GET8(hc->sca_base, sca->ier1) | 0x00F0);
1209 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXENABLE);
1210 inb(hc->iobase); /* XXX slow it down a bit. */
1211 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1215 if (sr_watcher == 0)
1218 #else /* NETGRAPH */
1219 untimeout(ngsr_watchdog_frame, sc, sc->handle);
1220 sc->handle = timeout(ngsr_watchdog_frame, sc, hz);
1222 #endif /* NETGRAPH */
1226 sr_down(struct sr_softc *sc)
1229 struct sr_hardc *hc = sc->hc;
1230 sca_regs *sca = hc->sca;
1231 msci_channel *msci = &sca->msci[sc->scachan];
1234 printf("sr_down(sc=%08x)\n", sc);
1237 untimeout(ngsr_watchdog_frame, sc, sc->handle);
1239 #endif /* NETGRAPH */
1242 * Disable transmitter and receiver. Lower DTR and RTS. Disable
1245 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXDISABLE);
1246 inb(hc->iobase); /* XXX slow it down a bit. */
1247 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXDISABLE);
1249 SRC_PUT8(hc->sca_base, msci->ctl,
1250 SRC_GET8(hc->sca_base, msci->ctl) | SCA_CTL_RTS);
1252 if (sc->scachan == 0)
1253 switch (hc->cardtype) {
1255 outb(hc->iobase + SR_MCR,
1256 (inb(hc->iobase + SR_MCR) | SR_MCR_DTR0));
1259 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1260 *fecrp |= SR_FECR_DTR0;
1264 switch (hc->cardtype) {
1266 outb(hc->iobase + SR_MCR,
1267 (inb(hc->iobase + SR_MCR) | SR_MCR_DTR1));
1270 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1271 *fecrp |= SR_FECR_DTR1;
1275 if (sc->scachan == 0) {
1276 SRC_PUT8(hc->sca_base, sca->ier0,
1277 SRC_GET8(hc->sca_base, sca->ier0) & ~0x0F);
1278 SRC_PUT8(hc->sca_base, sca->ier1,
1279 SRC_GET8(hc->sca_base, sca->ier1) & ~0x0F);
1281 SRC_PUT8(hc->sca_base, sca->ier0,
1282 SRC_GET8(hc->sca_base, sca->ier0) & ~0xF0);
1283 SRC_PUT8(hc->sca_base, sca->ier1,
1284 SRC_GET8(hc->sca_base, sca->ier1) & ~0xF0);
1289 * Initialize the card, allocate memory for the sr_softc structures
1290 * and fill in the pointers.
1293 src_init(struct sr_hardc *hc)
1295 struct sr_softc *sc = hc->sc;
1303 printf("src_init(hc=%08x)\n", hc);
1306 chanmem = hc->memsize / hc->numports;
1309 for (x = 0; x < hc->numports; x++, sc++) {
1312 for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1313 sc->block[blk].txdesc = next;
1314 bufmem = (16 * 1024) / SR_TX_BLOCKS;
1315 descneeded = bufmem / SR_BUF_SIZ;
1317 sc->block[blk].txstart = sc->block[blk].txdesc
1318 + ((((descneeded * sizeof(sca_descriptor))
1322 sc->block[blk].txend = next + bufmem;
1323 sc->block[blk].txmax =
1324 (sc->block[blk].txend - sc->block[blk].txstart)
1329 printf("sr%d: blk %d: txdesc %08x, txstart %08x\n",
1331 sc->block[blk].txdesc, sc->block[blk].txstart);
1336 bufmem = chanmem - (bufmem * SR_TX_BLOCKS);
1337 descneeded = bufmem / SR_BUF_SIZ;
1338 sc->rxstart = sc->rxdesc +
1339 ((((descneeded * sizeof(sca_descriptor)) /
1340 SR_BUF_SIZ) + 1) * SR_BUF_SIZ);
1341 sc->rxend = next + bufmem;
1342 sc->rxmax = (sc->rxend - sc->rxstart) / SR_BUF_SIZ;
1348 * The things done here are channel independent.
1350 * Configure the sca waitstates.
1351 * Configure the global interrupt registers.
1352 * Enable master dma enable.
1355 sr_init_sca(struct sr_hardc *hc)
1357 sca_regs *sca = hc->sca;
1360 printf("sr_init_sca(hc=%08x)\n", hc);
1364 * Do the wait registers. Set everything to 0 wait states.
1366 SRC_PUT8(hc->sca_base, sca->pabr0, 0);
1367 SRC_PUT8(hc->sca_base, sca->pabr1, 0);
1368 SRC_PUT8(hc->sca_base, sca->wcrl, 0);
1369 SRC_PUT8(hc->sca_base, sca->wcrm, 0);
1370 SRC_PUT8(hc->sca_base, sca->wcrh, 0);
1373 * Configure the interrupt registers. Most are cleared until the
1374 * interface is configured.
1376 SRC_PUT8(hc->sca_base, sca->ier0, 0x00); /* MSCI interrupts. */
1377 SRC_PUT8(hc->sca_base, sca->ier1, 0x00); /* DMAC interrupts */
1378 SRC_PUT8(hc->sca_base, sca->ier2, 0x00); /* TIMER interrupts. */
1379 SRC_PUT8(hc->sca_base, sca->itcr, 0x00); /* Use ivr and no intr
1381 SRC_PUT8(hc->sca_base, sca->ivr, 0x40); /* Interrupt vector. */
1382 SRC_PUT8(hc->sca_base, sca->imvr, 0x40);
1385 * Configure the timers. XXX Later
1389 * Set the DMA channel priority to rotate between all four channels.
1391 * Enable all dma channels.
1393 SRC_PUT8(hc->sca_base, sca->pcr, SCA_PCR_PR2);
1394 SRC_PUT8(hc->sca_base, sca->dmer, SCA_DMER_EN);
1398 * Configure the msci
1400 * NOTE: The serial port configuration is hardcoded at the moment.
1403 sr_init_msci(struct sr_softc *sc)
1405 int portndx; /* on-board port number */
1406 u_int mcr_v; /* contents of modem control */
1407 u_int *fecrp; /* pointer for PCI's MCR i/o */
1408 struct sr_hardc *hc = sc->hc;
1409 msci_channel *msci = &hc->sca->msci[sc->scachan];
1410 #ifdef N2_TEST_SPEED
1411 int br_v; /* contents for BR divisor */
1412 int etcndx; /* index into ETC table */
1413 int fifo_v, gotspeed; /* final tabled speed found */
1414 int tmc_v; /* timer control register */
1415 int wanted; /* speed (bitrate) wanted... */
1416 struct rate_line *rtp;
1419 portndx = sc->scachan;
1422 printf("sr: sr_init_msci( sc=%08x)\n", sc);
1425 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RESET);
1426 SRC_PUT8(hc->sca_base, msci->md0, SCA_MD0_CRC_1 |
1428 SCA_MD0_CRC_ENABLE |
1430 SRC_PUT8(hc->sca_base, msci->md1, SCA_MD1_NOADDRCHK);
1431 SRC_PUT8(hc->sca_base, msci->md2, SCA_MD2_DUPLEX | SCA_MD2_NRZ);
1434 * According to the manual I should give a reset after changing the
1437 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXRESET);
1438 SRC_PUT8(hc->sca_base, msci->ctl, SCA_CTL_IDLPAT |
1443 * XXX Later we will have to support different clock settings.
1445 switch (sc->clk_cfg) {
1448 printf("sr%: clk_cfg=%08x, selected default clock.\n",
1449 portndx, sc->clk_cfg);
1452 case SR_FLAGS_EXT_CLK:
1454 * For now all interfaces are programmed to use the RX clock
1459 printf("sr%d: External Clock Selected.\n", portndx);
1462 SRC_PUT8(hc->sca_base, msci->rxs,
1463 SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1464 SRC_PUT8(hc->sca_base, msci->txs,
1465 SCA_TXS_CLK_RX | SCA_TXS_DIV1);
1468 case SR_FLAGS_EXT_SEP_CLK:
1470 printf("sr%d: Split Clocking Selected.\n", portndx);
1473 SRC_PUT8(hc->sca_base, msci->rxs,
1474 SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1475 SRC_PUT8(hc->sca_base, msci->txs,
1476 SCA_TXS_CLK_TXC | SCA_TXS_DIV1);
1479 case SR_FLAGS_INT_CLK:
1481 printf("sr%d: Internal Clocking selected.\n", portndx);
1485 * XXX I do need some code to set the baud rate here!
1487 #ifdef N2_TEST_SPEED
1488 switch (hc->cardtype) {
1490 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1496 mcr_v = inb(hc->iobase + SR_MCR);
1500 fifo_v = 0x10; /* stolen from Linux version */
1503 * search for appropriate speed in table, don't calc it:
1505 wanted = sr_test_speed[portndx];
1506 rtp = &n2_rates[0]; /* point to first table item */
1508 while ((rtp->target > 0) /* search table for speed */
1509 &&(rtp->target != wanted))
1513 * We've searched the table for a matching speed. If we've
1514 * found the correct rate line, we'll get the pre-calc'd
1515 * values for the TMC and baud rate divisor for subsequent
1518 if (rtp->target > 0) { /* use table-provided values */
1520 tmc_v = rtp->tmc_reg;
1522 } else { /* otherwise assume 1MBit comm rate */
1529 * Now we mask in the enable clock output for the MCR:
1531 mcr_v |= etc0vals[etcndx + portndx];
1534 * Now we'll program the registers with these speed- related
1537 SRC_PUT8(hc->sca_base, msci->tmc, tmc_v);
1538 SRC_PUT8(hc->sca_base, msci->trc0, fifo_v);
1539 SRC_PUT8(hc->sca_base, msci->rxs, SCA_RXS_CLK_INT + br_v);
1540 SRC_PUT8(hc->sca_base, msci->txs, SCA_TXS_CLK_INT + br_v);
1542 switch (hc->cardtype) {
1548 outb(hc->iobase + SR_MCR, mcr_v);
1552 if (wanted != gotspeed)
1553 printf("sr%d: Speed wanted=%d, found=%d\n",
1556 printf("sr%d: Internal Clock %dx100 BPS, tmc=%d, div=%d\n",
1557 portndx, gotspeed, tmc_v, br_v);
1560 SRC_PUT8(hc->sca_base, msci->rxs,
1561 SCA_RXS_CLK_INT | SCA_RXS_DIV1);
1562 SRC_PUT8(hc->sca_base, msci->txs,
1563 SCA_TXS_CLK_INT | SCA_TXS_DIV1);
1565 SRC_PUT8(hc->sca_base, msci->tmc, 5);
1568 switch (hc->cardtype) {
1570 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1571 *fecrp |= SR_FECR_ETC0;
1575 mcr_v = inb(hc->iobase + SR_MCR);
1576 mcr_v |= SR_MCR_ETC0;
1577 outb(hc->iobase + SR_MCR, mcr_v);
1580 switch (hc->cardtype) {
1582 mcr_v = inb(hc->iobase + SR_MCR);
1583 mcr_v |= SR_MCR_ETC1;
1584 outb(hc->iobase + SR_MCR, mcr_v);
1587 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1588 *fecrp |= SR_FECR_ETC1;
1595 * XXX Disable all interrupts for now. I think if you are using the
1596 * dmac you don't use these interrupts.
1598 SRC_PUT8(hc->sca_base, msci->ie0, 0);
1599 SRC_PUT8(hc->sca_base, msci->ie1, 0x0C);
1600 SRC_PUT8(hc->sca_base, msci->ie2, 0);
1601 SRC_PUT8(hc->sca_base, msci->fie, 0);
1603 SRC_PUT8(hc->sca_base, msci->sa0, 0);
1604 SRC_PUT8(hc->sca_base, msci->sa1, 0);
1606 SRC_PUT8(hc->sca_base, msci->idl, 0x7E); /* set flags value */
1608 SRC_PUT8(hc->sca_base, msci->rrc, 0x0E);
1609 SRC_PUT8(hc->sca_base, msci->trc0, 0x10);
1610 SRC_PUT8(hc->sca_base, msci->trc1, 0x1F);
1614 * Configure the rx dma controller.
1617 sr_init_rx_dmac(struct sr_softc *sc)
1619 struct sr_hardc *hc;
1621 sca_descriptor *rxd;
1622 u_int cda_v, sarb_v, rxbuf, rxda, rxda_d;
1625 printf("sr_init_rx_dmac(sc=%08x)\n", sc);
1629 dmac = &hc->sca->dmac[DMAC_RXCH(sc->scachan)];
1632 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1635 * This phase initializes the contents of the descriptor table
1636 * needed to construct a circular buffer...
1638 rxd = (sca_descriptor *)(hc->mem_start + (sc->rxdesc & hc->winmsk));
1639 rxda_d = (u_int) hc->mem_start - (sc->rxdesc & ~hc->winmsk);
1641 for (rxbuf = sc->rxstart;
1643 rxbuf += SR_BUF_SIZ, rxd++) {
1645 * construct the circular chain...
1647 rxda = (u_int) & rxd[1] - rxda_d + hc->mem_pstart;
1648 rxd->cp = (u_short)(rxda & 0xffff);
1651 * set the on-card buffer address...
1653 rxd->bp = (u_short)((rxbuf + hc->mem_pstart) & 0xffff);
1654 rxd->bpb = (u_char)(((rxbuf + hc->mem_pstart) >> 16) & 0xff);
1656 rxd->len = 0; /* bytes resident w/in granule */
1657 rxd->stat = 0xff; /* The sca write here when finished */
1661 * heal the chain so that the last entry points to the first...
1664 rxd->cp = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1667 * reset the reception handler's index...
1672 * We'll now configure the receiver's DMA logic...
1674 SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA transfer */
1675 SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1677 /* XXX maybe also SCA_DMR_CNTE */
1678 SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1679 SRC_PUT16(hc->sca_base, dmac->bfl, SR_BUF_SIZ);
1681 cda_v = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1682 sarb_v = (u_char)(((sc->rxdesc + hc->mem_pstart) >> 16) & 0xff);
1684 SRC_PUT16(hc->sca_base, dmac->cda, cda_v);
1685 SRC_PUT8(hc->sca_base, dmac->sarb, sarb_v);
1687 rxd = (sca_descriptor *)sc->rxstart;
1689 SRC_PUT16(hc->sca_base, dmac->eda,
1690 (u_short)((u_int) & rxd[sc->rxmax - 1] & 0xffff));
1692 SRC_PUT8(hc->sca_base, dmac->dir, 0xF0);
1695 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE); /* Enable DMA */
1699 * Configure the TX DMA descriptors.
1700 * Initialize the needed values and chain the descriptors.
1703 sr_init_tx_dmac(struct sr_softc *sc)
1706 u_int txbuf, txda, txda_d;
1707 struct sr_hardc *hc;
1708 sca_descriptor *txd;
1710 struct buf_block *blkp;
1715 printf("sr_init_tx_dmac(sc=%08x)\n", sc);
1719 dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
1722 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
1725 * Initialize the array of descriptors for transmission
1727 for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1728 blkp = &sc->block[blk];
1729 txd = (sca_descriptor *)(hc->mem_start
1730 + (blkp->txdesc & hc->winmsk));
1731 txda_d = (u_int) hc->mem_start
1732 - (blkp->txdesc & ~hc->winmsk);
1735 txbuf = blkp->txstart;
1736 for (; txbuf < blkp->txend; txbuf += SR_BUF_SIZ, txd++) {
1737 txda = (u_int) & txd[1] - txda_d + hc->mem_pstart;
1738 txd->cp = (u_short)(txda & 0xffff);
1740 txd->bp = (u_short)((txbuf + hc->mem_pstart)
1742 txd->bpb = (u_char)(((txbuf + hc->mem_pstart) >> 16)
1750 txd->cp = (u_short)((blkp->txdesc + hc->mem_pstart)
1753 blkp->txtail = (u_int)txd - (u_int)hc->mem_start;
1756 SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA */
1757 SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1758 SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1759 SRC_PUT8(hc->sca_base, dmac->dir,
1760 SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF);
1762 sarb_v = (sc->block[0].txdesc + hc->mem_pstart) >> 16;
1765 SRC_PUT8(hc->sca_base, dmac->sarb, (u_char) sarb_v);
1769 * Look through the descriptors to see if there is a complete packet
1770 * available. Stop if we get to where the sca is busy.
1772 * Return the length and status of the packet.
1773 * Return nonzero if there is a packet available.
1776 * It seems that we get the interrupt a bit early. The updateing of
1777 * descriptor values is not always completed when this is called.
1780 sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat)
1782 int granules; /* count of granules in pkt */
1784 struct sr_hardc *hc;
1785 sca_descriptor *rxdesc; /* current descriptor */
1786 sca_descriptor *endp; /* ending descriptor */
1787 sca_descriptor *cda; /* starting descriptor */
1789 hc = sc->hc; /* get card's information */
1792 * set up starting descriptor by pulling that info from the DMA half
1795 wki = DMAC_RXCH(sc->scachan);
1796 wko = SRC_GET16(hc->sca_base, hc->sca->dmac[wki].cda);
1798 cda = (sca_descriptor *)(hc->mem_start + (wko & hc->winmsk));
1801 printf("sr_packet_avail(): wki=%d, wko=%04x, cda=%08x\n",
1806 * open the appropriate memory window and set our expectations...
1809 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1810 SRC_SET_ON(hc->iobase);
1812 rxdesc = (sca_descriptor *)
1813 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1815 rxdesc = &rxdesc[sc->rxhind];
1816 endp = &endp[sc->rxmax];
1818 *len = 0; /* reset result total length */
1819 granules = 0; /* reset count of granules */
1822 * This loop will scan descriptors, but it *will* puke up if we wrap
1823 * around to our starting point...
1825 while (rxdesc != cda) {
1826 *len += rxdesc->len; /* increment result length */
1830 * If we hit a valid packet's completion we'll know we've
1831 * got a live one, and that we can deliver the packet.
1832 * Since we're only allowed to report a packet available,
1833 * somebody else does that...
1835 if (rxdesc->stat & SCA_DESC_EOM) { /* End Of Message */
1836 *rxstat = rxdesc->stat; /* return closing */
1838 printf("sr%d: PKT AVAIL len %d, %x, bufs %u.\n",
1839 sc->unit, *len, *rxstat, granules);
1841 return 1; /* indicate success */
1844 * OK, this packet take up multiple granules. Move on to
1845 * the next descriptor so we can consider it...
1849 if (rxdesc == endp) /* recognize & act on wrap point */
1850 rxdesc = (sca_descriptor *)
1851 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1855 * Nothing found in the DPRAM. Let the caller know...
1864 * Copy a packet from the on card memory into a provided mbuf.
1865 * Take into account that buffers wrap and that a packet may
1866 * be larger than a buffer.
1869 sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len)
1871 struct sr_hardc *hc;
1872 sca_descriptor *rxdesc;
1879 printf("sr_copy_rxbuf(m=%08x,sc=%08x,len=%d)\n",
1885 rxdata = sc->rxstart + (sc->rxhind * SR_BUF_SIZ);
1886 rxmax = sc->rxstart + (sc->rxmax * SR_BUF_SIZ);
1888 rxdesc = (sca_descriptor *)
1889 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1890 rxdesc = &rxdesc[sc->rxhind];
1893 * Using the count of bytes in the received packet, we decrement it
1894 * for each granule (controller by an SCA descriptor) to control the
1899 * tlen gets the length of *this* granule... ...which is
1900 * then copied to the target buffer.
1902 tlen = (len < SR_BUF_SIZ) ? len : SR_BUF_SIZ;
1905 SRC_SET_MEM(hc->iobase, rxdata);
1907 bcopy(hc->mem_start + (rxdata & hc->winmsk),
1908 mtod(m, caddr_t) +off,
1915 * now, return to the descriptor's window in DPRAM and reset
1916 * the descriptor we've just suctioned...
1919 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1922 rxdesc->stat = 0xff;
1925 * Move on to the next granule. If we've any remaining
1926 * bytes to process we'll just continue in our loop...
1928 rxdata += SR_BUF_SIZ;
1931 if (rxdata == rxmax) { /* handle the wrap point */
1932 rxdata = sc->rxstart;
1933 rxdesc = (sca_descriptor *)
1934 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1940 * If single is set, just eat a packet. Otherwise eat everything up to
1941 * where cda points. Update pointers to point to the next packet.
1943 * This handles "flushing" of a packet as received...
1945 * If the "single" parameter is zero, all pending reeceive traffic will
1946 * be flushed out of existence. A non-zero value will only drop the
1947 * *next* (currently) pending packet...
1950 sr_eat_packet(struct sr_softc *sc, int single)
1952 struct sr_hardc *hc;
1953 sca_descriptor *rxdesc; /* current descriptor being eval'd */
1954 sca_descriptor *endp; /* last descriptor in chain */
1955 sca_descriptor *cda; /* current start point */
1956 u_int loopcnt = 0; /* count of packets flushed ??? */
1957 u_char stat; /* captured status byte from descr */
1960 cda = (sca_descriptor *)(hc->mem_start +
1961 (SRC_GET16(hc->sca_base,
1962 hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda) &
1966 * loop until desc->stat == (0xff || EOM) Clear the status and
1967 * length in the descriptor. Increment the descriptor.
1970 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1972 rxdesc = (sca_descriptor *)
1973 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1975 rxdesc = &rxdesc[sc->rxhind];
1976 endp = &endp[sc->rxmax];
1979 * allow loop, but abort it if we wrap completely...
1981 while (rxdesc != cda) {
1984 if (loopcnt > sc->rxmax) {
1985 printf("sr%d: eat pkt %d loop, cda %x, "
1986 "rxdesc %x, stat %x.\n",
1987 sc->unit, loopcnt, (u_int) cda, (u_int) rxdesc,
1991 stat = rxdesc->stat;
1994 rxdesc->stat = 0xff;
1999 if (rxdesc == endp) {
2000 rxdesc = (sca_descriptor *)
2001 (hc->mem_start + (sc->rxdesc & hc->winmsk));
2004 if (single && (stat == SCA_DESC_EOM))
2009 * Update the eda to the previous descriptor.
2011 rxdesc = (sca_descriptor *)sc->rxdesc;
2012 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2) % sc->rxmax];
2014 SRC_PUT16(hc->sca_base,
2015 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2016 (u_short)((u_int)(rxdesc + hc->mem_pstart) & 0xffff));
2020 * While there is packets available in the rx buffer, read them out
2021 * into mbufs and ship them off.
2024 sr_get_packets(struct sr_softc *sc)
2026 u_char rxstat; /* acquired status byte */
2028 int pkts; /* count of packets found */
2029 int rxndx; /* rcv buffer index */
2030 int tries; /* settling time counter */
2031 u_int len; /* length of pending packet */
2032 struct sr_hardc *hc; /* card-level information */
2033 sca_descriptor *rxdesc; /* descriptor in memory */
2035 struct ifnet *ifp; /* network intf ctl table */
2036 #endif /* NETGRAPH */
2037 struct mbuf *m = NULL; /* message buffer */
2040 printf("sr_get_packets(sc=%08x)\n", sc);
2045 ifp = &sc->ifsppp.pp_if;
2046 #endif /* NETGRAPH */
2049 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2050 SRC_SET_ON(hc->iobase); /* enable shared memory */
2052 pkts = 0; /* reset count of found packets */
2055 * for each complete packet in the receiving pool, process each
2058 while (sr_packet_avail(sc, &len, &rxstat)) { /* packet pending? */
2060 * I have seen situations where we got the interrupt but the
2061 * status value wasn't deposited. This code should allow
2062 * the status byte's value to settle...
2067 while ((rxstat == 0x00ff)
2069 sr_packet_avail(sc, &len, &rxstat);
2072 printf("sr_packet_avail() returned len=%d, rxstat=%02ux\n",
2080 #endif /* NETGRAPH */
2083 * OK, we've settled the incoming message status. We can now
2086 if (((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
2088 printf("sr%d: sr_get_packet() rxstat=%02x, len=%d\n",
2089 sc->unit, rxstat, len);
2092 MGETHDR(m, M_DONTWAIT, MT_DATA);
2095 * eat (flush) packet if get mbuf fail!!
2097 sr_eat_packet(sc, 1);
2101 * construct control information for pass-off
2104 m->m_pkthdr.rcvif = ifp;
2106 m->m_pkthdr.rcvif = NULL;
2107 #endif /* NETGRAPH */
2108 m->m_pkthdr.len = m->m_len = len;
2110 MCLGET(m, M_DONTWAIT);
2111 if ((m->m_flags & M_EXT) == 0) {
2113 * We couldn't get a big enough
2114 * message packet, so we'll send the
2115 * packet to /dev/null...
2118 sr_eat_packet(sc, 1);
2123 * OK, we've got a good message buffer. Now we can
2124 * copy the received message into it
2126 sr_copy_rxbuf(m, sc, len); /* copy from DPRAM */
2137 printf("sr%d: rcvd=%02x%02x%02x%02x%02x%02x\n",
2139 bp[0], bp[1], bp[2],
2140 bp[4], bp[5], bp[6]);
2146 #else /* NETGRAPH */
2151 bp = mtod(m,u_char *);
2152 printf("sr%d: rd=%02x:%02x:%02x:%02x:%02x:%02x",
2154 bp[0], bp[1], bp[2],
2155 bp[4], bp[5], bp[6]);
2156 printf(":%02x:%02x:%02x:%02x:%02x:%02x\n",
2157 bp[6], bp[7], bp[8],
2158 bp[9], bp[10], bp[11]);
2161 ng_queue_data(sc->hook, m, NULL);
2163 #endif /* NETGRAPH */
2165 * Update the eda to the previous descriptor.
2167 i = (len + SR_BUF_SIZ - 1) / SR_BUF_SIZ;
2168 sc->rxhind = (sc->rxhind + i) % sc->rxmax;
2170 rxdesc = (sca_descriptor *)sc->rxdesc;
2171 rxndx = (sc->rxhind + sc->rxmax - 2) % sc->rxmax;
2172 rxdesc = &rxdesc[rxndx];
2174 SRC_PUT16(hc->sca_base,
2175 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2176 (u_short)((u_int)(rxdesc + hc->mem_pstart)
2180 int got_st3, got_cda, got_eda;
2183 while ((rxstat == 0xff) && --tries)
2184 sr_packet_avail(sc, &len, &rxstat);
2187 * It look like we get an interrupt early
2188 * sometimes and then the status is not
2191 if (tries && (tries != 5))
2195 * This chunk of code handles the error packets.
2196 * We'll log them for posterity...
2198 sr_eat_packet(sc, 1);
2204 #endif /* NETGRAPH */
2206 got_st3 = SRC_GET8(hc->sca_base,
2207 hc->sca->msci[sc->scachan].st3);
2208 got_cda = SRC_GET16(hc->sca_base,
2209 hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda);
2210 got_eda = SRC_GET16(hc->sca_base,
2211 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda);
2214 printf("sr%d: Receive error chan %d, "
2215 "stat %02x, msci st3 %02x,"
2216 "rxhind %d, cda %04x, eda %04x.\n",
2217 sc->unit, sc->scachan, rxstat,
2218 got_st3, sc->rxhind, got_cda, got_eda);
2224 printf("sr%d: sr_get_packets() found %d packet(s)\n",
2229 SRC_SET_OFF(hc->iobase);
2233 * All DMA interrupts come here.
2235 * Each channel has two interrupts.
2236 * Interrupt A for errors and Interrupt B for normal stuff like end
2237 * of transmit or receive dmas.
2240 sr_dmac_intr(struct sr_hardc *hc, u_char isr1)
2242 u_char dsr; /* contents of DMA Stat Reg */
2243 u_char dotxstart; /* enables for tranmit part */
2244 int mch; /* channel being processed */
2245 struct sr_softc *sc; /* channel's softc structure */
2246 sca_regs *sca = hc->sca;
2247 dmac_channel *dmac; /* dma structure of chip */
2250 printf("sr_dmac_intr(hc=%08x,isr1=%04x)\n", hc, isr1);
2253 mch = 0; /* assume chan0 on card */
2254 dotxstart = isr1; /* copy for xmitter starts */
2257 * Shortcut if there is no interrupts for dma channel 0 or 1.
2258 * Skip processing for channel 0 if no incoming hit
2260 if ((isr1 & 0x0F) == 0) {
2268 * Transmit channel - DMA Status Register Evaluation
2271 dmac = &sca->dmac[DMAC_TXCH(mch)];
2274 * get the DMA Status Register contents and write
2275 * back to reset interrupt...
2277 dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2278 SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2281 * Check for (& process) a Counter overflow
2283 if (dsr & SCA_DSR_COF) {
2284 printf("sr%d: TX DMA Counter overflow, "
2285 "txpacket no %lu.\n",
2287 sc->unit, sc->ifsppp.pp_if.if_opackets);
2288 sc->ifsppp.pp_if.if_oerrors++;
2290 sc->unit, sc->opackets);
2292 #endif /* NETGRAPH */
2295 * Check for (& process) a Buffer overflow
2297 if (dsr & SCA_DSR_BOF) {
2298 printf("sr%d: TX DMA Buffer overflow, "
2299 "txpacket no %lu, dsr %02x, "
2300 "cda %04x, eda %04x.\n",
2302 sc->unit, sc->ifsppp.pp_if.if_opackets,
2304 sc->unit, sc->opackets,
2305 #endif /* NETGRAPH */
2307 SRC_GET16(hc->sca_base, dmac->cda),
2308 SRC_GET16(hc->sca_base, dmac->eda));
2310 sc->ifsppp.pp_if.if_oerrors++;
2313 #endif /* NETGRAPH */
2316 * Check for (& process) an End of Transfer (OK)
2318 if (dsr & SCA_DSR_EOT) {
2320 * This should be the most common case.
2322 * Clear the IFF_OACTIVE flag.
2324 * Call srstart to start a new transmit if
2325 * there is data to transmit.
2328 printf("sr%d: TX Completed OK\n", sc->unit);
2332 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE;
2333 sc->ifsppp.pp_if.if_timer = 0;
2335 /* XXX may need to mark tx inactive? */
2337 sc->out_dog = DOG_HOLDOFF;
2338 #endif /* NETGRAPH */
2340 if (sc->txb_inuse && --sc->txb_inuse)
2345 * Receive channel processing of DMA Status Register
2348 dmac = &sca->dmac[DMAC_RXCH(mch)];
2350 dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2351 SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2354 * End of frame processing (MSG OK?)
2356 if (dsr & SCA_DSR_EOM) {
2361 tt = sc->ifsppp.pp_if.if_ipackets;
2362 #else /* NETGRAPH */
2364 #endif /* NETGRAPH */
2371 if (tt == sc->ifsppp.pp_if.if_ipackets)
2372 #else /* NETGRAPH */
2373 if (tt == sc->ipackets)
2374 #endif /* NETGRAPH */
2376 sca_descriptor *rxdesc;
2379 printf("SR: RXINTR isr1 %x, dsr %x, "
2380 "no data %d pkts, orxind %d.\n",
2381 dotxstart, dsr, tt, ind);
2382 printf("SR: rxdesc %x, rxstart %x, "
2383 "rxend %x, rxhind %d, "
2385 sc->rxdesc, sc->rxstart,
2386 sc->rxend, sc->rxhind,
2388 printf("SR: cda %x, eda %x.\n",
2389 SRC_GET16(hc->sca_base, dmac->cda),
2390 SRC_GET16(hc->sca_base, dmac->eda));
2393 SRC_SET_ON(hc->iobase);
2394 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2396 rxdesc = (sca_descriptor *)
2398 (sc->rxdesc & hc->winmsk));
2399 rxdesc = &rxdesc[sc->rxhind];
2401 for (i = 0; i < 3; i++, rxdesc++)
2402 printf("SR: rxdesc->stat %x, "
2408 SRC_SET_OFF(hc->iobase);
2413 * Check for Counter overflow
2415 if (dsr & SCA_DSR_COF) {
2416 printf("sr%d: RX DMA Counter overflow, "
2419 sc->unit, sc->ifsppp.pp_if.if_ipackets);
2420 sc->ifsppp.pp_if.if_ierrors++;
2421 #else /* NETGRAPH */
2422 sc->unit, sc->ipackets);
2424 #endif /* NETGRAPH */
2427 * Check for Buffer overflow
2429 if (dsr & SCA_DSR_BOF) {
2430 printf("sr%d: RX DMA Buffer overflow, "
2431 "rxpkts %lu, rxind %d, "
2432 "cda %x, eda %x, dsr %x.\n",
2434 sc->unit, sc->ifsppp.pp_if.if_ipackets,
2435 #else /* NETGRAPH */
2436 sc->unit, sc->ipackets,
2437 #endif /* NETGRAPH */
2439 SRC_GET16(hc->sca_base, dmac->cda),
2440 SRC_GET16(hc->sca_base, dmac->eda),
2444 * Make sure we eat as many as possible.
2445 * Then get the system running again.
2448 SRC_SET_ON(hc->iobase);
2450 sr_eat_packet(sc, 0);
2452 sc->ifsppp.pp_if.if_ierrors++;
2453 #else /* NETGRAPH */
2455 #endif /* NETGRAPH */
2457 SRC_PUT8(hc->sca_base,
2461 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
2464 printf("sr%d: RX DMA Buffer overflow, "
2465 "rxpkts %lu, rxind %d, "
2466 "cda %x, eda %x, dsr %x. After\n",
2470 #else /* NETGRAPH */
2471 sc->ifsppp.pp_if.if_ipackets,
2472 #endif /* NETGRAPH */
2474 SRC_GET16(hc->sca_base, dmac->cda),
2475 SRC_GET16(hc->sca_base, dmac->eda),
2476 SRC_GET8(hc->sca_base, dmac->dsr));
2480 SRC_SET_OFF(hc->iobase);
2485 if (dsr & SCA_DSR_EOT) {
2487 * If this happen, it means that we are
2488 * receiving faster than what the processor
2491 * XXX We should enable the dma again.
2493 printf("sr%d: RX End of xfer, rxpkts %lu.\n",
2496 sc->ifsppp.pp_if.if_ipackets);
2497 sc->ifsppp.pp_if.if_ierrors++;
2501 #endif /* NETGRAPH */
2504 isr1 >>= 4; /* process next half of ISR */
2505 mch++; /* and move to next channel */
2506 } while ((mch < NCHAN) && isr1); /* loop for each chn */
2509 * Now that we have done all the urgent things, see if we can fill
2510 * the transmit buffers.
2512 for (mch = 0; mch < NCHAN; mch++) {
2513 if (dotxstart & 0x0C) { /* TX initiation enabled? */
2516 srstart(&sc->ifsppp.pp_if);
2519 #endif /* NETGRAPH */
2521 dotxstart >>= 4;/* shift for next channel */
2527 * Perform timeout on an FR channel
2529 * Establish a periodic check of open N2 ports; If
2530 * a port is open/active, its DCD state is checked
2531 * and a loss of DCD is recognized (and eventually
2535 sr_modemck(void *arg)
2538 int card; /* card index in table */
2539 int cards; /* card list index */
2540 int mch; /* channel on card */
2541 u_char dcd_v; /* Data Carrier Detect */
2542 u_char got_st0; /* contents of ST0 */
2543 u_char got_st1; /* contents of ST1 */
2544 u_char got_st2; /* contents of ST2 */
2545 u_char got_st3; /* contents of ST3 */
2546 struct sr_hardc *hc; /* card's configuration */
2547 struct sr_hardc *Card[16];/* up to 16 cards in system */
2548 struct sr_softc *sc; /* channel's softc structure */
2549 struct ifnet *ifp; /* interface control table */
2550 msci_channel *msci; /* regs specific to channel */
2555 if (sr_opens == 0) { /* count of "up" channels */
2556 sr_watcher = 0; /* indicate no watcher */
2562 sr_watcher = 1; /* mark that we're online */
2565 * Now we'll need a list of cards to process. Since we can handle
2566 * both ISA and PCI cards (and I didn't think of making this logic
2567 * global YET) we'll generate a single table of card table
2572 for (card = 0; card < NSR; card++) {
2573 hc = &sr_hardc[card];
2575 if (hc->sc == (void *)0)
2589 * OK, we've got work we can do. Let's do it... (Please note that
2590 * this code _only_ deals w/ ISA cards)
2592 for (card = 0; card < cards; card++) {
2593 hc = Card[card];/* get card table */
2595 for (mch = 0; mch < hc->numports; mch++) {
2598 ifp = &sc->ifsppp.pp_if;
2601 * if this channel isn't "up", skip it
2603 if ((ifp->if_flags & IFF_UP) == 0)
2607 * OK, now we can go looking at this channel's
2608 * actual register contents...
2610 msci = &hc->sca->msci[sc->scachan];
2613 * OK, now we'll look into the actual status of this
2616 * I suck in more registers than strictly needed
2618 got_st0 = SRC_GET8(hc->sca_base, msci->st0);
2619 got_st1 = SRC_GET8(hc->sca_base, msci->st1);
2620 got_st2 = SRC_GET8(hc->sca_base, msci->st2);
2621 got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2624 * We want to see if the DCD signal is up (DCD is
2627 dcd_v = (got_st3 & SCA_ST3_DCD) == 0;
2630 printf("sr%d: DCD lost\n", sc->unit);
2635 * OK, now set up for the next modem signal checking pass...
2637 timeout(sr_modemck, NULL, hz);
2642 #else /* NETGRAPH */
2644 * If a port is open/active, it's DCD state is checked
2645 * and a loss of DCD is recognized (and eventually processed?).
2648 sr_modemck(struct sr_softc *sc )
2651 u_char got_st3; /* contents of ST3 */
2652 struct sr_hardc *hc = sc->hc; /* card's configuration */
2653 msci_channel *msci; /* regs specific to channel */
2658 if (sc->running == 0)
2661 * OK, now we can go looking at this channel's register contents...
2663 msci = &hc->sca->msci[sc->scachan];
2664 got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2667 * We want to see if the DCD signal is up (DCD is true if zero)
2669 sc->dcd = (got_st3 & SCA_ST3_DCD) == 0;
2673 #endif /* NETGRAPH */
2675 sr_msci_intr(struct sr_hardc *hc, u_char isr0)
2677 printf("src%d: SRINTR: MSCI\n", hc->cunit);
2681 sr_timer_intr(struct sr_hardc *hc, u_char isr2)
2683 printf("src%d: SRINTR: TIMER\n", hc->cunit);
2687 /*****************************************
2688 * Device timeout/watchdog routine.
2689 * called once per second.
2690 * checks to see that if activity was expected, that it hapenned.
2691 * At present we only look to see if expected output was completed.
2694 ngsr_watchdog_frame(void * arg)
2696 struct sr_softc * sc = arg;
2700 if (sc->running == 0)
2701 return; /* if we are not running let timeouts die */
2703 * calculate the apparent throughputs
2707 speed = sc->inbytes - sc->lastinbytes;
2708 sc->lastinbytes = sc->inbytes;
2709 if ( sc->inrate < speed )
2711 speed = sc->outbytes - sc->lastoutbytes;
2712 sc->lastoutbytes = sc->outbytes;
2713 if ( sc->outrate < speed )
2714 sc->outrate = speed;
2718 if ((sc->inlast > QUITE_A_WHILE)
2719 && (sc->out_deficit > LOTS_OF_PACKETS)) {
2720 log(LOG_ERR, "sr%d: No response from remote end\n", sc->unit);
2724 sc->inlast = sc->out_deficit = 0;
2726 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2727 if (sc->out_dog == 0) {
2728 log(LOG_ERR, "sr%d: Transmit failure.. no clock?\n",
2737 sc->inlast = sc->out_deficit = 0;
2742 sr_modemck(sc); /* update the DCD status */
2743 sc->handle = timeout(ngsr_watchdog_frame, sc, hz);
2746 /***********************************************************************
2747 * This section contains the methods for the Netgraph interface
2748 ***********************************************************************/
2750 * It is not possible or allowable to create a node of this type.
2751 * If the hardware exists, it will already have created it.
2754 ngsr_constructor(node_p *nodep)
2760 * give our ok for a hook to be added...
2761 * If we are not running this should kick the device into life.
2762 * The hook's private info points to our stash of info about that
2766 ngsr_newhook(node_p node, hook_p hook, const char *name)
2768 struct sr_softc * sc = node->private;
2771 * check if it's our friend the debug hook
2773 if (strcmp(name, NG_SR_HOOK_DEBUG) == 0) {
2774 hook->private = NULL; /* paranoid */
2775 sc->debug_hook = hook;
2780 * Check for raw mode hook.
2782 if (strcmp(name, NG_SR_HOOK_RAW) != 0) {
2793 * incoming messages.
2794 * Just respond to the generic TEXT_STATUS message
2797 ngsr_rcvmsg(node_p node,
2798 struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp)
2800 struct sr_softc * sc;
2804 switch (msg->header.typecookie) {
2808 case NGM_GENERIC_COOKIE:
2809 switch(msg->header.cmd) {
2810 case NGM_TEXT_STATUS: {
2813 int resplen = sizeof(struct ng_mesg) + 512;
2814 MALLOC(*resp, struct ng_mesg *, resplen,
2815 M_NETGRAPH, M_NOWAIT | M_ZERO);
2816 if (*resp == NULL) {
2820 arg = (*resp)->data;
2823 * Put in the throughput information.
2825 pos = sprintf(arg, "%ld bytes in, %ld bytes out\n"
2826 "highest rate seen: %ld B/S in, %ld B/S out\n",
2827 sc->inbytes, sc->outbytes,
2828 sc->inrate, sc->outrate);
2829 pos += sprintf(arg + pos,
2830 "%ld output errors\n",
2832 pos += sprintf(arg + pos,
2833 "ierrors = %ld, %ld, %ld, %ld, %ld, %ld\n",
2841 (*resp)->header.version = NG_VERSION;
2842 (*resp)->header.arglen = strlen(arg) + 1;
2843 (*resp)->header.token = msg->header.token;
2844 (*resp)->header.typecookie = NG_SR_COOKIE;
2845 (*resp)->header.cmd = msg->header.cmd;
2846 strncpy((*resp)->header.cmdstr, "status",
2859 free(msg, M_NETGRAPH);
2864 * get data from another node and transmit it to the correct channel
2867 ngsr_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
2871 struct sr_softc * sc = hook->node->private;
2872 struct ifqueue *xmitq_p;
2875 * data doesn't come in from just anywhere (e.g control hook)
2877 if ( hook->private == NULL) {
2883 * Now queue the data for when it can be sent
2885 if (meta && meta->priority > 0) {
2886 xmitq_p = (&sc->xmitq_hipri);
2888 xmitq_p = (&sc->xmitq);
2891 if (IF_QFULL(xmitq_p)) {
2897 IF_ENQUEUE(xmitq_p, m);
2904 * It was an error case.
2905 * check if we need to free the mbuf, and then return the error
2907 NG_FREE_DATA(m, meta);
2912 * do local shutdown processing..
2913 * this node will refuse to go away, unless the hardware says to..
2914 * don't unref the node, or remove our name. just clear our links up.
2917 ngsr_rmnode(node_p node)
2919 struct sr_softc * sc = node->private;
2923 node->flags &= ~NG_INVALID; /* bounce back to life */
2927 /* already linked */
2929 ngsr_connect(hook_p hook)
2931 /* be really amiable and just say "YUP that's OK by me! " */
2936 * notify on hook disconnection (destruction)
2938 * Invalidate the private data associated with this dlci.
2939 * For this type, removal of the last link resets tries to destroy the node.
2940 * As the device still exists, the shutdown method will not actually
2941 * destroy the node, but reset the device and leave it 'fresh' :)
2943 * The node removal code will remove all references except that owned by the
2947 ngsr_disconnect(hook_p hook)
2949 struct sr_softc * sc = hook->node->private;
2952 * If it's the data hook, then free resources etc.
2954 if (hook->private) {
2957 if (sc->datahooks == 0)
2961 sc->debug_hook = NULL;
2967 * called during bootup
2968 * or LKM loading to put this type into the list of known modules
2971 ngsr_init(void *ignored)
2973 if (ng_newtype(&typestruct))
2974 printf("ngsr install failed\n");
2977 #endif /* NETGRAPH */
2980 ********************************* END ************************************