2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/dev/tx/if_tx.c,v 1.61.2.1 2002/10/29 01:43:49 semenu Exp $
27 * $DragonFly: src/sys/dev/netif/tx/if_tx.c,v 1.2 2003/06/17 04:28:32 dillon Exp $
31 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie)
33 * These cards are based on SMC83c17x (EPIC) chip and one of the various
34 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on
35 * card model. All cards support 10baseT/UTP and 100baseTX half- and full-
36 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also
37 * supports fibre optics.
39 * Thanks are going to Steve Bauer and Jason Wright.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/sockio.h>
46 #include <sys/malloc.h>
47 #include <sys/kernel.h>
48 #include <sys/socket.h>
49 #include <sys/queue.h>
52 #include <net/if_arp.h>
53 #include <net/ethernet.h>
54 #include <net/if_dl.h>
55 #include <net/if_media.h>
59 #include <net/if_vlan_var.h>
61 #include <vm/vm.h> /* for vtophys */
62 #include <vm/pmap.h> /* for vtophys */
63 #include <machine/bus_memio.h>
64 #include <machine/bus_pio.h>
65 #include <machine/bus.h>
66 #include <machine/resource.h>
67 #include <machine/clock.h> /* for DELAY */
71 #include <pci/pcireg.h>
72 #include <pci/pcivar.h>
74 #include <dev/mii/mii.h>
75 #include <dev/mii/miivar.h>
76 #include <dev/mii/miidevs.h>
78 #include <dev/mii/lxtphyreg.h>
80 #include "miibus_if.h"
82 #include <dev/tx/if_txreg.h>
83 #include <dev/tx/if_txvar.h>
85 MODULE_DEPEND(tx, miibus, 1, 1, 1);
87 static int epic_ifioctl(register struct ifnet *, u_long, caddr_t);
88 static void epic_intr(void *);
89 static void epic_tx_underrun(epic_softc_t *);
90 static int epic_common_attach(epic_softc_t *);
91 static void epic_ifstart(struct ifnet *);
92 static void epic_ifwatchdog(struct ifnet *);
93 static void epic_stats_update(epic_softc_t *);
94 static int epic_init(epic_softc_t *);
95 static void epic_stop(epic_softc_t *);
96 static void epic_rx_done(epic_softc_t *);
97 static void epic_tx_done(epic_softc_t *);
98 static int epic_init_rings(epic_softc_t *);
99 static void epic_free_rings(epic_softc_t *);
100 static void epic_stop_activity(epic_softc_t *);
101 static int epic_queue_last_packet(epic_softc_t *);
102 static void epic_start_activity(epic_softc_t *);
103 static void epic_set_rx_mode(epic_softc_t *);
104 static void epic_set_tx_mode(epic_softc_t *);
105 static void epic_set_mc_table(epic_softc_t *);
106 static u_int8_t epic_calchash(caddr_t);
107 static int epic_read_eeprom(epic_softc_t *,u_int16_t);
108 static void epic_output_eepromw(epic_softc_t *, u_int16_t);
109 static u_int16_t epic_input_eepromw(epic_softc_t *);
110 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t);
111 static void epic_write_eepromreg(epic_softc_t *,u_int8_t);
112 static u_int8_t epic_read_eepromreg(epic_softc_t *);
114 static int epic_read_phy_reg(epic_softc_t *, int, int);
115 static void epic_write_phy_reg(epic_softc_t *, int, int, int);
117 static int epic_miibus_readreg(device_t, int, int);
118 static int epic_miibus_writereg(device_t, int, int, int);
119 static void epic_miibus_statchg(device_t);
120 static void epic_miibus_mediainit(device_t);
122 static int epic_ifmedia_upd(struct ifnet *);
123 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *);
125 static int epic_probe(device_t);
126 static int epic_attach(device_t);
127 static void epic_shutdown(device_t);
128 static int epic_detach(device_t);
129 static struct epic_type *epic_devtype(device_t);
131 static device_method_t epic_methods[] = {
132 /* Device interface */
133 DEVMETHOD(device_probe, epic_probe),
134 DEVMETHOD(device_attach, epic_attach),
135 DEVMETHOD(device_detach, epic_detach),
136 DEVMETHOD(device_shutdown, epic_shutdown),
139 DEVMETHOD(miibus_readreg, epic_miibus_readreg),
140 DEVMETHOD(miibus_writereg, epic_miibus_writereg),
141 DEVMETHOD(miibus_statchg, epic_miibus_statchg),
142 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit),
147 static driver_t epic_driver = {
153 static devclass_t epic_devclass;
155 DRIVER_MODULE(if_tx, pci, epic_driver, epic_devclass, 0, 0);
156 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0);
158 static struct epic_type epic_devs[] = {
159 { SMC_VENDORID, SMC_DEVICEID_83C170,
160 "SMC EtherPower II 10/100" },
170 t = epic_devtype(dev);
173 device_set_desc(dev, t->name);
180 static struct epic_type *
188 while(t->name != NULL) {
189 if ((pci_get_vendor(dev) == t->ven_id) &&
190 (pci_get_device(dev) == t->dev_id)) {
198 #if defined(EPIC_USEIOSPACE)
199 #define EPIC_RES SYS_RES_IOPORT
200 #define EPIC_RID PCIR_BASEIO
202 #define EPIC_RES SYS_RES_MEMORY
203 #define EPIC_RID PCIR_BASEMEM
207 * Attach routine: map registers, allocate softc, rings and descriptors.
208 * Reset to known state.
222 sc = device_get_softc(dev);
223 unit = device_get_unit(dev);
225 /* Preinitialize softc structure */
226 bzero(sc, sizeof(epic_softc_t));
230 /* Fill ifnet structure */
235 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST;
236 ifp->if_ioctl = epic_ifioctl;
237 ifp->if_output = ether_output;
238 ifp->if_start = epic_ifstart;
239 ifp->if_watchdog = epic_ifwatchdog;
240 ifp->if_init = (if_init_f_t*)epic_init;
242 ifp->if_baudrate = 10000000;
243 ifp->if_snd.ifq_maxlen = TX_RING_SIZE - 1;
245 /* Enable ports, memory and busmastering */
246 command = pci_read_config(dev, PCIR_COMMAND, 4);
247 command |= PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
248 pci_write_config(dev, PCIR_COMMAND, command, 4);
249 command = pci_read_config(dev, PCIR_COMMAND, 4);
251 #if defined(EPIC_USEIOSPACE)
252 if ((command & PCIM_CMD_PORTEN) == 0) {
253 device_printf(dev, "failed to enable I/O mapping!\n");
258 if ((command & PCIM_CMD_MEMEN) == 0) {
259 device_printf(dev, "failed to enable memory mapping!\n");
266 sc->res = bus_alloc_resource(dev, EPIC_RES, &rid, 0, ~0, 1,
269 if (sc->res == NULL) {
270 device_printf(dev, "couldn't map ports/memory\n");
275 sc->sc_st = rman_get_bustag(sc->res);
276 sc->sc_sh = rman_get_bushandle(sc->res);
278 /* Allocate interrupt */
280 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
281 RF_SHAREABLE | RF_ACTIVE);
283 if (sc->irq == NULL) {
284 device_printf(dev, "couldn't map interrupt\n");
285 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
290 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
291 epic_intr, sc, &sc->sc_ih);
294 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
295 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
296 device_printf(dev, "couldn't set up irq\n");
300 /* Do OS independent part, including chip wakeup and reset */
301 error = epic_common_attach(sc);
303 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
304 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
305 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
310 /* Do ifmedia setup */
311 if (mii_phy_probe(dev, &sc->miibus,
312 epic_ifmedia_upd, epic_ifmedia_sts)) {
313 device_printf(dev, "ERROR! MII without any PHY!?\n");
314 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
315 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
316 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
321 /* Display ethernet address ,... */
322 device_printf(dev, "address %6D,", sc->sc_macaddr, ":");
324 /* board type and ... */
326 for(i=0x2c;i<0x32;i++) {
327 tmp = epic_read_eeprom(sc, i);
328 if (' ' == (u_int8_t)tmp) break;
329 printf("%c", (u_int8_t)tmp);
331 if (' ' == (u_int8_t)tmp) break;
332 printf("%c", (u_int8_t)tmp);
336 /* Attach to OS's managers */
337 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
338 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
339 callout_handle_init(&sc->stat_ch);
348 * Detach driver and free resources
360 sc = device_get_softc(dev);
361 ifp = &sc->arpcom.ac_if;
363 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
367 bus_generic_detach(dev);
368 device_delete_child(dev, sc->miibus);
370 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
371 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
372 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
374 free(sc->tx_flist, M_DEVBUF);
375 free(sc->tx_desc, M_DEVBUF);
376 free(sc->rx_desc, M_DEVBUF);
387 * Stop all chip I/O so that the kernel's probe routines don't
388 * get confused by errant DMAs when rebooting.
396 sc = device_get_softc(dev);
404 * This is if_ioctl handler.
407 epic_ifioctl(ifp, command, data)
412 epic_softc_t *sc = ifp->if_softc;
413 struct mii_data *mii;
414 struct ifreq *ifr = (struct ifreq *) data;
422 error = ether_ioctl(ifp, command, data);
425 if (ifp->if_mtu == ifr->ifr_mtu)
428 /* XXX Though the datasheet doesn't imply any
429 * limitations on RX and TX sizes beside max 64Kb
430 * DMA transfer, seems we can't send more then 1600
431 * data bytes per ethernet packet. (Transmitter hangs
432 * up if more data is sent)
434 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) {
435 ifp->if_mtu = ifr->ifr_mtu;
444 * If the interface is marked up and stopped, then start it.
445 * If it is marked down and running, then stop it.
447 if (ifp->if_flags & IFF_UP) {
448 if ((ifp->if_flags & IFF_RUNNING) == 0) {
453 if (ifp->if_flags & IFF_RUNNING) {
459 /* Handle IFF_PROMISC and IFF_ALLMULTI flags */
460 epic_stop_activity(sc);
461 epic_set_mc_table(sc);
462 epic_set_rx_mode(sc);
463 epic_start_activity(sc);
468 epic_set_mc_table(sc);
474 mii = device_get_softc(sc->miibus);
475 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
487 * OS-independed part of attach process. allocate memory for descriptors
488 * and frag lists, wake up chip, read MAC address and PHY identyfier.
489 * Return -1 on failure.
492 epic_common_attach(sc)
497 sc->tx_flist = malloc(sizeof(struct epic_frag_list)*TX_RING_SIZE,
498 M_DEVBUF, M_NOWAIT | M_ZERO);
499 sc->tx_desc = malloc(sizeof(struct epic_tx_desc)*TX_RING_SIZE,
500 M_DEVBUF, M_NOWAIT | M_ZERO);
501 sc->rx_desc = malloc(sizeof(struct epic_rx_desc)*RX_RING_SIZE,
502 M_DEVBUF, M_NOWAIT | M_ZERO);
504 if (sc->tx_flist == NULL || sc->tx_desc == NULL || sc->rx_desc == NULL){
505 device_printf(sc->dev, "failed to malloc memory\n");
506 if (sc->tx_flist) free(sc->tx_flist, M_DEVBUF);
507 if (sc->tx_desc) free(sc->tx_desc, M_DEVBUF);
508 if (sc->rx_desc) free(sc->rx_desc, M_DEVBUF);
512 /* Bring the chip out of low-power mode. */
513 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
516 /* Workaround for Application Note 7-15 */
517 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
519 /* Read mac address from EEPROM */
520 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
521 ((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i);
523 /* Set Non-Volatile Control Register from EEPROM */
524 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
527 sc->tx_threshold = TRANSMIT_THRESHOLD;
528 sc->txcon = TXCON_DEFAULT;
529 sc->miicfg = MIICFG_SMI_ENABLE;
530 sc->phyid = EPIC_UNKN_PHY;
534 sc->cardvend = pci_read_config(sc->dev, PCIR_SUBVEND_0, 2);
535 sc->cardid = pci_read_config(sc->dev, PCIR_SUBDEV_0, 2);
537 if (sc->cardvend != SMC_VENDORID)
538 device_printf(sc->dev, "unknown card vendor %04xh\n", sc->cardvend);
544 * This is if_start handler. It takes mbufs from if_snd queue
545 * and queue them for transmit, one by one, until TX ring become full
546 * or queue become empty.
552 epic_softc_t *sc = ifp->if_softc;
553 struct epic_tx_buffer *buf;
554 struct epic_tx_desc *desc;
555 struct epic_frag_list *flist;
557 register struct mbuf *m;
560 while (sc->pending_txs < TX_RING_SIZE) {
561 buf = sc->tx_buffer + sc->cur_tx;
562 desc = sc->tx_desc + sc->cur_tx;
563 flist = sc->tx_flist + sc->cur_tx;
565 /* Get next packet to send */
566 IF_DEQUEUE(&ifp->if_snd, m0);
568 /* If nothing to send, return */
569 if (NULL == m0) return;
571 /* Fill fragments list */
573 (NULL != m) && (i < EPIC_MAX_FRAGS);
574 m = m->m_next, i++) {
575 flist->frag[i].fraglen = m->m_len;
576 flist->frag[i].fragaddr = vtophys(mtod(m, caddr_t));
580 /* If packet was more than EPIC_MAX_FRAGS parts, */
581 /* recopy packet to new allocated mbuf cluster */
590 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
591 flist->frag[0].fraglen =
592 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
593 m->m_pkthdr.rcvif = ifp;
596 flist->frag[0].fragaddr = vtophys(mtod(m, caddr_t));
603 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
604 desc->control = 0x01;
606 max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
607 desc->status = 0x8000;
608 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED);
610 /* Set watchdog timer */
617 ifp->if_flags |= IFF_OACTIVE;
624 * Synopsis: Finish all received frames.
631 struct epic_rx_buffer *buf;
632 struct epic_rx_desc *desc;
634 struct ether_header *eh;
636 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) {
637 buf = sc->rx_buffer + sc->cur_rx;
638 desc = sc->rx_desc + sc->cur_rx;
640 /* Switch to next descriptor */
641 sc->cur_rx = (sc->cur_rx+1) & RX_RING_MASK;
644 * Check for RX errors. This should only happen if
645 * SAVE_ERRORED_PACKETS is set. RX errors generate
646 * RXE interrupt usually.
648 if ((desc->status & 1) == 0) {
649 sc->sc_if.if_ierrors++;
650 desc->status = 0x8000;
654 /* Save packet length and mbuf contained packet */
655 len = desc->rxlength - ETHER_CRC_LEN;
658 /* Try to get mbuf cluster */
659 EPIC_MGETCLUSTER(buf->mbuf);
660 if (NULL == buf->mbuf) {
662 desc->status = 0x8000;
663 sc->sc_if.if_ierrors++;
667 /* Point to new mbuf, and give descriptor to chip */
668 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
669 desc->status = 0x8000;
671 /* First mbuf in packet holds the ethernet and packet headers */
672 eh = mtod(m, struct ether_header *);
673 m->m_pkthdr.rcvif = &(sc->sc_if);
674 m->m_pkthdr.len = m->m_len = len;
676 /* Second mbuf holds packet ifself */
677 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header);
678 m->m_data += sizeof(struct ether_header);
680 /* Give mbuf to OS */
681 ether_input(&sc->sc_if, eh, m);
683 /* Successfuly received frame */
684 sc->sc_if.if_ipackets++;
691 * Synopsis: Do last phase of transmission. I.e. if desc is
692 * transmitted, decrease pending_txs counter, free mbuf contained
693 * packet, switch to next descriptor and repeat until no packets
694 * are pending or descriptor is not transmitted yet.
700 struct epic_tx_buffer *buf;
701 struct epic_tx_desc *desc;
704 while (sc->pending_txs > 0) {
705 buf = sc->tx_buffer + sc->dirty_tx;
706 desc = sc->tx_desc + sc->dirty_tx;
707 status = desc->status;
709 /* If packet is not transmitted, thou followed */
710 /* packets are not transmitted too */
711 if (status & 0x8000) break;
713 /* Packet is transmitted. Switch to next and */
716 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK;
720 /* Check for errors and collisions */
721 if (status & 0x0001) sc->sc_if.if_opackets++;
722 else sc->sc_if.if_oerrors++;
723 sc->sc_if.if_collisions += (status >> 8) & 0x1F;
724 #if defined(EPIC_DIAG)
725 if ((status & 0x1001) == 0x1001)
726 device_printf(sc->dev, "Tx ERROR: excessive coll. number\n");
730 if (sc->pending_txs < TX_RING_SIZE)
731 sc->sc_if.if_flags &= ~IFF_OACTIVE;
741 epic_softc_t * sc = (epic_softc_t *) arg;
744 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) {
745 CSR_WRITE_4(sc, INTSTAT, status);
747 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) {
749 if (status & (INTSTAT_RQE|INTSTAT_OVW)) {
750 #if defined(EPIC_DIAG)
751 if (status & INTSTAT_OVW)
752 device_printf(sc->dev, "RX buffer overflow\n");
753 if (status & INTSTAT_RQE)
754 device_printf(sc->dev, "RX FIFO overflow\n");
756 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0)
757 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED);
758 sc->sc_if.if_ierrors++;
762 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) {
764 if (sc->sc_if.if_snd.ifq_head != NULL)
765 epic_ifstart(&sc->sc_if);
768 /* Check for rare errors */
769 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
770 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) {
771 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
772 INTSTAT_APE|INTSTAT_DPE)) {
773 device_printf(sc->dev, "PCI fatal errors occured: %s%s%s%s\n",
774 (status&INTSTAT_PMA)?"PMA ":"",
775 (status&INTSTAT_PTA)?"PTA ":"",
776 (status&INTSTAT_APE)?"APE ":"",
777 (status&INTSTAT_DPE)?"DPE":""
786 if (status & INTSTAT_RXE) {
787 #if defined(EPIC_DIAG)
788 device_printf(sc->dev, "CRC/Alignment error\n");
790 sc->sc_if.if_ierrors++;
793 if (status & INTSTAT_TXU) {
794 epic_tx_underrun(sc);
795 sc->sc_if.if_oerrors++;
800 /* If no packets are pending, then no timeouts */
801 if (sc->pending_txs == 0) sc->sc_if.if_timer = 0;
807 * Handle the TX underrun error: increase the TX threshold
808 * and restart the transmitter.
814 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) {
815 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE;
816 #if defined(EPIC_DIAG)
817 device_printf(sc->dev, "Tx UNDERRUN: early TX disabled\n");
820 sc->tx_threshold += 0x40;
821 #if defined(EPIC_DIAG)
822 device_printf(sc->dev, "Tx UNDERRUN: TX threshold increased to %d\n",
827 /* We must set TXUGO to reset the stuck transmitter */
828 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO);
830 /* Update the TX threshold */
831 epic_stop_activity(sc);
832 epic_set_tx_mode(sc);
833 epic_start_activity(sc);
839 * Synopsis: This one is called if packets wasn't transmitted
840 * during timeout. Try to deallocate transmitted packets, and
841 * if success continue to work.
847 epic_softc_t *sc = ifp->if_softc;
852 device_printf(sc->dev, "device timeout %d packets\n", sc->pending_txs);
854 /* Try to finish queued packets */
857 /* If not successful */
858 if (sc->pending_txs > 0) {
860 ifp->if_oerrors+=sc->pending_txs;
862 /* Reinitialize board */
863 device_printf(sc->dev, "reinitialization\n");
868 device_printf(sc->dev, "seems we can continue normaly\n");
871 if (ifp->if_snd.ifq_head) epic_ifstart(ifp);
877 * Despite the name of this function, it doesn't update statistics, it only
878 * helps in autonegotiation process.
881 epic_stats_update(epic_softc_t * sc)
883 struct mii_data * mii;
888 mii = device_get_softc(sc->miibus);
891 sc->stat_ch = timeout((timeout_t *)epic_stats_update, sc, hz);
900 epic_ifmedia_upd(ifp)
904 struct mii_data *mii;
906 struct mii_softc *miisc;
910 mii = device_get_softc(sc->miibus);
911 ifm = &mii->mii_media;
912 media = ifm->ifm_cur->ifm_media;
914 /* Do not do anything if interface is not up */
915 if ((ifp->if_flags & IFF_UP) == 0)
919 * Lookup current selected PHY
921 if (IFM_INST(media) == sc->serinst) {
922 sc->phyid = EPIC_SERIAL;
925 /* If we're not selecting serial interface, select MII mode */
926 sc->miicfg &= ~MIICFG_SERIAL_ENABLE;
927 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
929 /* Default to unknown PHY */
930 sc->phyid = EPIC_UNKN_PHY;
932 /* Lookup selected PHY */
933 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
934 miisc = LIST_NEXT(miisc, mii_list)) {
935 if (IFM_INST(media) == miisc->mii_inst) {
941 /* Identify selected PHY */
943 int id1, id2, model, oui;
945 id1 = PHY_READ(sc->physc, MII_PHYIDR1);
946 id2 = PHY_READ(sc->physc, MII_PHYIDR2);
948 oui = MII_OUI(id1, id2);
949 model = MII_MODEL(id2);
951 case MII_OUI_QUALSEMI:
952 if (model == MII_MODEL_QUALSEMI_QS6612)
953 sc->phyid = EPIC_QS6612_PHY;
955 case MII_OUI_xxALTIMA:
956 if (model == MII_MODEL_xxALTIMA_AC101)
957 sc->phyid = EPIC_AC101_PHY;
959 case MII_OUI_xxLEVEL1:
960 if (model == MII_MODEL_xxLEVEL1_LXT970)
961 sc->phyid = EPIC_LXT970_PHY;
968 * Do PHY specific card setup
971 /* Call this, to isolate all not selected PHYs and
976 /* Do our own setup */
978 case EPIC_QS6612_PHY:
981 /* We have to powerup fiber tranceivers */
982 if (IFM_SUBTYPE(media) == IFM_100_FX)
983 sc->miicfg |= MIICFG_694_ENABLE;
985 sc->miicfg &= ~MIICFG_694_ENABLE;
986 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
989 case EPIC_LXT970_PHY:
990 /* We have to powerup fiber tranceivers */
991 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG);
992 if (IFM_SUBTYPE(media) == IFM_100_FX)
993 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0;
995 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
996 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg);
1000 /* Select serial PHY, (10base2/BNC usually) */
1001 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE;
1002 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1004 /* There is no driver to fill this */
1005 mii->mii_media_active = media;
1006 mii->mii_media_status = 0;
1008 /* We need to call this manualy as i wasn't called
1011 epic_miibus_statchg(sc->dev);
1015 device_printf(sc->dev, "ERROR! Unknown PHY selected\n");
1023 * Report current media status.
1026 epic_ifmedia_sts(ifp, ifmr)
1028 struct ifmediareq *ifmr;
1031 struct mii_data *mii;
1032 struct ifmedia *ifm;
1035 mii = device_get_softc(sc->miibus);
1036 ifm = &mii->mii_media;
1038 /* Nothing should be selected if interface is down */
1039 if ((ifp->if_flags & IFF_UP) == 0) {
1040 ifmr->ifm_active = IFM_NONE;
1041 ifmr->ifm_status = 0;
1046 /* Call underlying pollstat, if not serial PHY */
1047 if (sc->phyid != EPIC_SERIAL)
1050 /* Simply copy media info */
1051 ifmr->ifm_active = mii->mii_media_active;
1052 ifmr->ifm_status = mii->mii_media_status;
1058 * Callback routine, called on media change.
1061 epic_miibus_statchg(dev)
1065 struct mii_data *mii;
1068 sc = device_get_softc(dev);
1069 mii = device_get_softc(sc->miibus);
1070 media = mii->mii_media_active;
1072 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
1074 /* If we are in full-duplex mode or loopback operation,
1075 * we need to decouple receiver and transmitter.
1077 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP))
1078 sc->txcon |= TXCON_FULL_DUPLEX;
1080 /* On some cards we need manualy set fullduplex led */
1081 if (sc->cardid == SMC9432FTX ||
1082 sc->cardid == SMC9432FTX_SC) {
1083 if (IFM_OPTIONS(media) & IFM_FDX)
1084 sc->miicfg |= MIICFG_694_ENABLE;
1086 sc->miicfg &= ~MIICFG_694_ENABLE;
1088 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1091 /* Update baudrate */
1092 if (IFM_SUBTYPE(media) == IFM_100_TX ||
1093 IFM_SUBTYPE(media) == IFM_100_FX)
1094 sc->sc_if.if_baudrate = 100000000;
1096 sc->sc_if.if_baudrate = 10000000;
1098 epic_stop_activity(sc);
1099 epic_set_tx_mode(sc);
1100 epic_start_activity(sc);
1106 epic_miibus_mediainit(dev)
1110 struct mii_data *mii;
1111 struct ifmedia *ifm;
1114 sc = device_get_softc(dev);
1115 mii = device_get_softc(sc->miibus);
1116 ifm = &mii->mii_media;
1118 /* Add Serial Media Interface if present, this applies to
1121 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
1122 /* Store its instance */
1123 sc->serinst = mii->mii_instance++;
1125 /* Add as 10base2/BNC media */
1126 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst);
1127 ifmedia_add(ifm, media, 0, NULL);
1129 /* Report to user */
1130 device_printf(sc->dev, "serial PHY detected (10Base2/BNC)\n");
1137 * Reset chip, allocate rings, and update media.
1143 struct ifnet *ifp = &sc->sc_if;
1148 /* If interface is already running, then we need not do anything */
1149 if (ifp->if_flags & IFF_RUNNING) {
1154 /* Soft reset the chip (we have to power up card before) */
1155 CSR_WRITE_4(sc, GENCTL, 0);
1156 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1159 * Reset takes 15 pci ticks which depends on PCI bus speed.
1160 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec.
1165 CSR_WRITE_4(sc, GENCTL, 0);
1167 /* Workaround for Application Note 7-15 */
1168 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1170 /* Initialize rings */
1171 if (epic_init_rings(sc)) {
1172 device_printf(sc->dev, "failed to init rings\n");
1177 /* Give rings to EPIC */
1178 CSR_WRITE_4(sc, PRCDAR, vtophys(sc->rx_desc));
1179 CSR_WRITE_4(sc, PTCDAR, vtophys(sc->tx_desc));
1181 /* Put node address to EPIC */
1182 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)sc->sc_macaddr)[0]);
1183 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)sc->sc_macaddr)[1]);
1184 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)sc->sc_macaddr)[2]);
1186 /* Set tx mode, includeing transmit threshold */
1187 epic_set_tx_mode(sc);
1189 /* Compute and set RXCON. */
1190 epic_set_rx_mode(sc);
1192 /* Set multicast table */
1193 epic_set_mc_table(sc);
1195 /* Enable interrupts by setting the interrupt mask. */
1196 CSR_WRITE_4(sc, INTMASK,
1197 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */
1198 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU |
1201 /* Acknowledge all pending interrupts */
1202 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1204 /* Enable interrupts, set for PCI read multiple and etc */
1205 CSR_WRITE_4(sc, GENCTL,
1206 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE |
1207 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64);
1209 /* Mark interface running ... */
1210 if (ifp->if_flags & IFF_UP) ifp->if_flags |= IFF_RUNNING;
1211 else ifp->if_flags &= ~IFF_RUNNING;
1214 ifp->if_flags &= ~IFF_OACTIVE;
1216 /* Start Rx process */
1217 epic_start_activity(sc);
1219 /* Set appropriate media */
1220 epic_ifmedia_upd(ifp);
1222 sc->stat_ch = timeout((timeout_t *)epic_stats_update, sc, hz);
1230 * Synopsis: calculate and set Rx mode. Chip must be in idle state to
1234 epic_set_rx_mode(sc)
1237 u_int32_t flags = sc->sc_if.if_flags;
1238 u_int32_t rxcon = RXCON_DEFAULT;
1240 #if defined(EPIC_EARLY_RX)
1241 rxcon |= RXCON_EARLY_RX;
1244 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0;
1246 CSR_WRITE_4(sc, RXCON, rxcon);
1252 * Synopsis: Set transmit control register. Chip must be in idle state to
1256 epic_set_tx_mode(sc)
1259 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE)
1260 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold);
1262 CSR_WRITE_4(sc, TXCON, sc->txcon);
1266 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC
1267 * flags. (Note, that setting PROMISC bit in EPIC's RXCON will only touch
1268 * individual frames, multicast filter must be manually programmed)
1270 * Note: EPIC must be in idle state.
1273 epic_set_mc_table(sc)
1276 struct ifnet *ifp = &sc->sc_if;
1277 struct ifmultiaddr *ifma;
1278 u_int16_t filter[4];
1281 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1282 CSR_WRITE_4(sc, MC0, 0xFFFF);
1283 CSR_WRITE_4(sc, MC1, 0xFFFF);
1284 CSR_WRITE_4(sc, MC2, 0xFFFF);
1285 CSR_WRITE_4(sc, MC3, 0xFFFF);
1295 #if __FreeBSD_version < 500000
1296 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1298 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1300 if (ifma->ifma_addr->sa_family != AF_LINK)
1302 h = epic_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1303 filter[h >> 4] |= 1 << (h & 0xF);
1306 CSR_WRITE_4(sc, MC0, filter[0]);
1307 CSR_WRITE_4(sc, MC1, filter[1]);
1308 CSR_WRITE_4(sc, MC2, filter[2]);
1309 CSR_WRITE_4(sc, MC3, filter[3]);
1315 * Synopsis: calculate EPIC's hash of multicast address.
1321 u_int32_t crc, carry;
1325 /* Compute CRC for the address value. */
1326 crc = 0xFFFFFFFF; /* initial value */
1328 for (i = 0; i < 6; i++) {
1330 for (j = 0; j < 8; j++) {
1331 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
1335 crc = (crc ^ 0x04c11db6) | carry;
1339 return ((crc >> 26) & 0x3F);
1344 * Synopsis: Start receive process and transmit one, if they need.
1347 epic_start_activity(sc)
1350 /* Start rx process */
1351 CSR_WRITE_4(sc, COMMAND,
1352 COMMAND_RXQUEUED | COMMAND_START_RX |
1353 (sc->pending_txs?COMMAND_TXQUEUED:0));
1357 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional
1358 * packet needs to be queued to stop Tx DMA.
1361 epic_stop_activity(sc)
1366 /* Stop Tx and Rx DMA */
1367 CSR_WRITE_4(sc, COMMAND,
1368 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA);
1370 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX) */
1371 for (i=0; i<0x1000; i++) {
1372 status = CSR_READ_4(sc, INTSTAT) & (INTSTAT_TXIDLE | INTSTAT_RXIDLE);
1373 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE))
1378 /* Catch all finished packets */
1382 status = CSR_READ_4(sc, INTSTAT);
1384 if ((status & INTSTAT_RXIDLE) == 0)
1385 device_printf(sc->dev, "ERROR! Can't stop Rx DMA\n");
1387 if ((status & INTSTAT_TXIDLE) == 0)
1388 device_printf(sc->dev, "ERROR! Can't stop Tx DMA\n");
1391 * May need to queue one more packet if TQE, this is rare
1392 * but existing case.
1394 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE))
1395 (void) epic_queue_last_packet(sc);
1400 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until
1401 * a packet from current descriptor will be copied to internal RAM. We
1402 * compose a dummy packet here and queue it for transmission.
1404 * XXX the packet will then be actually sent over network...
1407 epic_queue_last_packet(sc)
1410 struct epic_tx_desc *desc;
1411 struct epic_frag_list *flist;
1412 struct epic_tx_buffer *buf;
1416 device_printf(sc->dev, "queue last packet\n");
1418 desc = sc->tx_desc + sc->cur_tx;
1419 flist = sc->tx_flist + sc->cur_tx;
1420 buf = sc->tx_buffer + sc->cur_tx;
1422 if ((desc->status & 0x8000) || (buf->mbuf != NULL))
1425 MGETHDR(m0, M_DONTWAIT, MT_DATA);
1430 m0->m_len = min(MHLEN, ETHER_MIN_LEN-ETHER_CRC_LEN);
1431 flist->frag[0].fraglen = m0->m_len;
1432 m0->m_pkthdr.len = m0->m_len;
1433 m0->m_pkthdr.rcvif = &sc->sc_if;
1434 bzero(mtod(m0,caddr_t), m0->m_len);
1436 /* Fill fragments list */
1437 flist->frag[0].fraglen = m0->m_len;
1438 flist->frag[0].fragaddr = vtophys(mtod(m0, caddr_t));
1439 flist->numfrags = 1;
1441 /* Fill in descriptor */
1444 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
1445 desc->control = 0x01;
1446 desc->txlength = max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
1447 desc->status = 0x8000;
1449 /* Launch transmition */
1450 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED);
1452 /* Wait Tx DMA to stop (for how long??? XXX) */
1453 for (i=0; i<1000; i++) {
1454 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE)
1459 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0)
1460 device_printf(sc->dev, "ERROR! can't stop Tx DMA (2)\n");
1468 * Synopsis: Shut down board and deallocates rings.
1478 sc->sc_if.if_timer = 0;
1480 untimeout((timeout_t *)epic_stats_update, sc, sc->stat_ch);
1482 /* Disable interrupts */
1483 CSR_WRITE_4(sc, INTMASK, 0);
1484 CSR_WRITE_4(sc, GENCTL, 0);
1486 /* Try to stop Rx and TX processes */
1487 epic_stop_activity(sc);
1490 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1493 /* Make chip go to bed */
1494 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN);
1496 /* Free memory allocated for rings */
1497 epic_free_rings(sc);
1499 /* Mark as stoped */
1500 sc->sc_if.if_flags &= ~IFF_RUNNING;
1507 * Synopsis: This function should free all memory allocated for rings.
1515 for (i=0; i<RX_RING_SIZE; i++) {
1516 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1517 struct epic_rx_desc *desc = sc->rx_desc + i;
1520 desc->buflength = 0;
1523 if (buf->mbuf) m_freem(buf->mbuf);
1527 for (i=0; i<TX_RING_SIZE; i++) {
1528 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1529 struct epic_tx_desc *desc = sc->tx_desc + i;
1532 desc->buflength = 0;
1535 if (buf->mbuf) m_freem(buf->mbuf);
1541 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them.
1542 * Point Tx descs to fragment lists. Check that all descs and fraglists
1543 * are bounded and aligned properly.
1551 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0;
1553 for (i = 0; i < RX_RING_SIZE; i++) {
1554 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1555 struct epic_rx_desc *desc = sc->rx_desc + i;
1557 desc->status = 0; /* Owned by driver */
1558 desc->next = vtophys(sc->rx_desc + ((i+1) & RX_RING_MASK));
1560 if ((desc->next & 3) ||
1561 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1562 epic_free_rings(sc);
1566 EPIC_MGETCLUSTER(buf->mbuf);
1567 if (NULL == buf->mbuf) {
1568 epic_free_rings(sc);
1571 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
1573 desc->buflength = MCLBYTES; /* Max RX buffer length */
1574 desc->status = 0x8000; /* Set owner bit to NIC */
1577 for (i = 0; i < TX_RING_SIZE; i++) {
1578 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1579 struct epic_tx_desc *desc = sc->tx_desc + i;
1582 desc->next = vtophys(sc->tx_desc + ((i+1) & TX_RING_MASK));
1584 if ((desc->next & 3) ||
1585 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1586 epic_free_rings(sc);
1591 desc->bufaddr = vtophys(sc->tx_flist + i);
1593 if ((desc->bufaddr & 3) ||
1594 ((desc->bufaddr & PAGE_MASK) + sizeof(struct epic_frag_list)) > PAGE_SIZE) {
1595 epic_free_rings(sc);
1604 * EEPROM operation functions
1607 epic_write_eepromreg(sc, val)
1613 CSR_WRITE_1(sc, EECTL, val);
1615 for (i=0; i<0xFF; i++)
1616 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0) break;
1622 epic_read_eepromreg(sc)
1625 return CSR_READ_1(sc, EECTL);
1629 epic_eeprom_clock(sc, val)
1633 epic_write_eepromreg(sc, val);
1634 epic_write_eepromreg(sc, (val | 0x4));
1635 epic_write_eepromreg(sc, val);
1637 return epic_read_eepromreg(sc);
1641 epic_output_eepromw(sc, val)
1647 for (i = 0xF; i >= 0; i--) {
1649 epic_eeprom_clock(sc, 0x0B);
1651 epic_eeprom_clock(sc, 0x03);
1656 epic_input_eepromw(sc)
1659 u_int16_t retval = 0;
1662 for (i = 0xF; i >= 0; i--) {
1663 if (epic_eeprom_clock(sc, 0x3) & 0x10)
1671 epic_read_eeprom(sc, loc)
1678 epic_write_eepromreg(sc, 3);
1680 if (epic_read_eepromreg(sc) & 0x40)
1681 read_cmd = (loc & 0x3F) | 0x180;
1683 read_cmd = (loc & 0xFF) | 0x600;
1685 epic_output_eepromw(sc, read_cmd);
1687 dataval = epic_input_eepromw(sc);
1689 epic_write_eepromreg(sc, 1);
1695 * Here goes MII read/write routines
1698 epic_read_phy_reg(sc, phy, reg)
1704 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1706 for (i = 0; i < 0x100; i++) {
1707 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0) break;
1711 return (CSR_READ_4(sc, MIIDATA));
1715 epic_write_phy_reg(sc, phy, reg, val)
1721 CSR_WRITE_4(sc, MIIDATA, val);
1722 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));
1724 for(i=0;i<0x100;i++) {
1725 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0) break;
1733 epic_miibus_readreg(dev, phy, reg)
1739 sc = device_get_softc(dev);
1741 return (PHY_READ_2(sc, phy, reg));
1745 epic_miibus_writereg(dev, phy, reg, data)
1751 sc = device_get_softc(dev);
1753 PHY_WRITE_2(sc, phy, reg, data);