sys/dev/drm/radeon/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/drmP.h>
  25 #include "radeon.h"
  26 #include "radeon_asic.h"
  27 #include "sid.h"
  28 #include "r600_dpm.h"
  29 #include "si_dpm.h"
  30 #include "atom.h"
  31 #include <linux/math64.h>
  32 #include <linux/seq_file.h>
  33
  34 #define MC_CG_ARB_FREQ_F0           0x0a
  35 #define MC_CG_ARB_FREQ_F1           0x0b
  36 #define MC_CG_ARB_FREQ_F2           0x0c
  37 #define MC_CG_ARB_FREQ_F3           0x0d
  38
  39 #define SMC_RAM_END                 0x20000
  40
  41 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  42
  43 static const struct si_cac_config_reg cac_weights_tahiti[] =
  44 {
  45         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
  46         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  47         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
  48         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
  49         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  50         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  51         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  52         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  53         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  54         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
  55         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  56         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
  57         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
  58         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
  59         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
  60         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  61         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  62         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
  63         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  64         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
  65         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
  66         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
  67         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  68         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  69         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  70         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  71         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  72         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  73         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  74         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  75         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
  76         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  77         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  78         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  79         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
  80         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  81         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  82         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
  83         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  84         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
  85         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  86         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  87         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  88         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  89         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  90         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  91         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  92         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  93         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  94         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  95         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  96         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  97         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  98         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  99         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 100         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 101         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 102         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 103         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 104         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 105         { 0xFFFFFFFF }
 106 };
 107
 108 static const struct si_cac_config_reg lcac_tahiti[] =
 109 {
 110         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 111         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 112         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 113         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 114         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 115         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 116         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 117         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 118         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 119         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 120         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 121         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 122         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 123         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 124         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 125         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 126         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 127         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 128         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 129         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 130         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 131         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 132         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 133         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 134         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 135         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 136         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 137         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 138         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 139         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 140         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 141         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 142         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 143         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 144         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 145         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 146         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 147         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 148         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 149         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 150         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 151         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 152         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 153         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 154         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 155         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 156         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 157         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 158         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 159         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 160         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 161         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 162         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 163         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 164         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 165         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 166         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 167         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 168         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 169         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 170         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 171         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 172         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 173         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 174         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 175         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 176         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 177         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 178         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 179         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 180         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 181         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 182         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 183         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 184         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 185         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 186         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 187         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 188         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 189         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 190         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 191         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 192         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 193         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 194         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 195         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 196         { 0xFFFFFFFF }
 197
 198 };
 199
 200 static const struct si_cac_config_reg cac_override_tahiti[] =
 201 {
 202         { 0xFFFFFFFF }
 203 };
 204
 205 static const struct si_powertune_data powertune_data_tahiti =
 206 {
 207         ((1 << 16) | 27027),
 208         6,
 209         0,
 210         4,
 211         95,
 212         {
 213                 0UL,
 214                 0UL,
 215                 4521550UL,
 216                 309631529UL,
 217                 -1270850L,
 218                 4513710L,
 219                 40
 220         },
 221         595000000UL,
 222         12,
 223         {
 224                 0,
 225                 0,
 226                 0,
 227                 0,
 228                 0,
 229                 0,
 230                 0,
 231                 0
 232         },
 233         true
 234 };
 235
 236 static const struct si_dte_data dte_data_tahiti =
 237 {
 238         { 1159409, 0, 0, 0, 0 },
 239         { 777, 0, 0, 0, 0 },
 240         2,
 241         54000,
 242         127000,
 243         25,
 244         2,
 245         10,
 246         13,
 247         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 248         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 249         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 250         85,
 251         false
 252 };
 253
 254 #if 0 /* unused */
 255 static const struct si_dte_data dte_data_tahiti_le =
 256 {
 257         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 258         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 259         0x5,
 260         0xAFC8,
 261         0x64,
 262         0x32,
 263         1,
 264         0,
 265         0x10,
 266         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 267         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 268         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 269         85,
 270         true
 271 };
 272 #endif
 273
 274 static const struct si_dte_data dte_data_tahiti_pro =
 275 {
 276         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 277         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 278         5,
 279         45000,
 280         100,
 281         0xA,
 282         1,
 283         0,
 284         0x10,
 285         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 286         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 287         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 288         90,
 289         true
 290 };
 291
 292 static const struct si_dte_data dte_data_new_zealand =
 293 {
 294         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 295         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 296         0x5,
 297         0xAFC8,
 298         0x69,
 299         0x32,
 300         1,
 301         0,
 302         0x10,
 303         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 304         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 305         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 306         85,
 307         true
 308 };
 309
 310 static const struct si_dte_data dte_data_aruba_pro =
 311 {
 312         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 313         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 314         5,
 315         45000,
 316         100,
 317         0xA,
 318         1,
 319         0,
 320         0x10,
 321         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 322         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 323         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 324         90,
 325         true
 326 };
 327
 328 static const struct si_dte_data dte_data_malta =
 329 {
 330         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 331         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 332         5,
 333         45000,
 334         100,
 335         0xA,
 336         1,
 337         0,
 338         0x10,
 339         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 340         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 341         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 342         90,
 343         true
 344 };
 345
 346 struct si_cac_config_reg cac_weights_pitcairn[] =
 347 {
 348         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 349         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 350         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 351         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 352         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 353         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 354         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 355         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 356         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 357         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 358         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 359         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 360         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 361         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 362         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 363         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 364         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 365         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 366         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 367         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 368         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 369         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 370         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 371         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 372         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 373         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 374         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 375         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 376         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 377         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 378         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 379         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 380         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 381         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 382         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 383         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 384         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 385         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 386         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 387         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 388         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 389         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 390         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 391         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 392         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 393         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 394         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 395         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 396         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 397         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 398         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 399         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 400         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 401         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 402         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 403         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 404         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 405         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 406         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 407         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 408         { 0xFFFFFFFF }
 409 };
 410
 411 static const struct si_cac_config_reg lcac_pitcairn[] =
 412 {
 413         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 414         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 415         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 416         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 417         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 418         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 419         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 420         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 421         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 422         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 423         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 424         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 425         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 426         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 427         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 428         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 429         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 430         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 431         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 432         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 433         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 434         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 435         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 436         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 437         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 438         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 439         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 440         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 441         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 442         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 443         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 444         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 445         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 446         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 447         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 448         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 449         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 450         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 451         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 452         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 453         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 454         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 455         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 456         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 457         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 458         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 459         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 460         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 461         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 462         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 463         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 464         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 465         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 466         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 467         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 468         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 469         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 470         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 471         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 472         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 473         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 474         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 475         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 476         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 477         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 478         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 479         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 480         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 481         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 482         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 483         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 484         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 485         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 486         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 487         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 488         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 489         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 490         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 491         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 492         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 493         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 494         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 495         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 496         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 497         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 498         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 499         { 0xFFFFFFFF }
 500 };
 501
 502 static const struct si_cac_config_reg cac_override_pitcairn[] =
 503 {
 504         { 0xFFFFFFFF }
 505 };
 506
 507 static const struct si_powertune_data powertune_data_pitcairn =
 508 {
 509         ((1 << 16) | 27027),
 510         5,
 511         0,
 512         6,
 513         100,
 514         {
 515                 51600000UL,
 516                 1800000UL,
 517                 7194395UL,
 518                 309631529UL,
 519                 -1270850L,
 520                 4513710L,
 521                 100
 522         },
 523         117830498UL,
 524         12,
 525         {
 526                 0,
 527                 0,
 528                 0,
 529                 0,
 530                 0,
 531                 0,
 532                 0,
 533                 0
 534         },
 535         true
 536 };
 537
 538 static const struct si_dte_data dte_data_pitcairn =
 539 {
 540         { 0, 0, 0, 0, 0 },
 541         { 0, 0, 0, 0, 0 },
 542         0,
 543         0,
 544         0,
 545         0,
 546         0,
 547         0,
 548         0,
 549         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 550         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 551         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 552         0,
 553         false
 554 };
 555
 556 static const struct si_dte_data dte_data_curacao_xt =
 557 {
 558         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 559         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 560         5,
 561         45000,
 562         100,
 563         0xA,
 564         1,
 565         0,
 566         0x10,
 567         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 568         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 569         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 570         90,
 571         true
 572 };
 573
 574 static const struct si_dte_data dte_data_curacao_pro =
 575 {
 576         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 577         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 578         5,
 579         45000,
 580         100,
 581         0xA,
 582         1,
 583         0,
 584         0x10,
 585         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 586         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 587         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 588         90,
 589         true
 590 };
 591
 592 static const struct si_dte_data dte_data_neptune_xt =
 593 {
 594         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 595         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 596         5,
 597         45000,
 598         100,
 599         0xA,
 600         1,
 601         0,
 602         0x10,
 603         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 604         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 605         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 606         90,
 607         true
 608 };
 609
 610 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 611 {
 612         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 613         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 614         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 615         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 616         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 617         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 618         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 619         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 620         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 621         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 622         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 623         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 624         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 625         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 626         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 627         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 628         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 629         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 630         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 631         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 632         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 633         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 634         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 635         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 636         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 637         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 638         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 639         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 640         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 641         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 642         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 643         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 644         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 645         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 646         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 647         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 648         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 649         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 650         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 651         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 652         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 653         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 654         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 655         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 656         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 657         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 658         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 659         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 660         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 661         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 662         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 663         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 664         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 665         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 666         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 667         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 668         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 669         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 670         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 671         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 672         { 0xFFFFFFFF }
 673 };
 674
 675 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 676 {
 677         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 678         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 679         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 680         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 681         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 682         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 683         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 684         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 685         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 686         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 687         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 688         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 689         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 690         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 691         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 692         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 693         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 694         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 695         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 696         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 697         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 698         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 699         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 700         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 701         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 702         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 703         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 704         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 705         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 706         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 707         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 708         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 709         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 710         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 711         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 712         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 713         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 714         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 715         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 716         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 717         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 718         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 719         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 720         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 721         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 722         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 723         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 724         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 725         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 726         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 727         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 728         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 729         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 730         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 731         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 732         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 733         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 734         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 735         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 736         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 737         { 0xFFFFFFFF }
 738 };
 739
 740 static const struct si_cac_config_reg cac_weights_heathrow[] =
 741 {
 742         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 743         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 744         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 745         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 746         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 747         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 748         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 749         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 750         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 751         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 752         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 753         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 754         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 755         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 756         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 757         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 758         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 759         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 760         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 761         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 762         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 763         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 764         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 765         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 766         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 767         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 768         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 769         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 770         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 771         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 772         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 773         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 774         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 775         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 776         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 777         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 778         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 779         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 780         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 781         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 782         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 783         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 784         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 785         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 786         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 787         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 788         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 789         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 790         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 791         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 792         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 793         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 794         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 795         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 796         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 797         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 798         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 799         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 800         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 801         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 802         { 0xFFFFFFFF }
 803 };
 804
 805 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 806 {
 807         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 808         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 809         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 810         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 811         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 812         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 813         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 814         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 815         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 816         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 817         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 818         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 819         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 820         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 821         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 822         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 823         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 824         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 825         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 826         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 827         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 828         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 829         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 830         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 831         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 832         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 833         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 834         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 835         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 836         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 837         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 838         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 839         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 840         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 841         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 842         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 843         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 844         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 845         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 846         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 847         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 848         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 849         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 850         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 851         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 852         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 853         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 854         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 855         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 856         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 857         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 858         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 859         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 860         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 861         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 862         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 863         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 864         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 865         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 866         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 867         { 0xFFFFFFFF }
 868 };
 869
 870 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 871 {
 872         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 873         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 874         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 875         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 876         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 877         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 878         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 879         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 880         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 881         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 882         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 883         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 884         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 885         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 886         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 887         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 888         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 889         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 890         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 891         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 892         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 893         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 894         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 895         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 896         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 897         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 898         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 899         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 900         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 901         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 902         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 903         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 904         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 905         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 906         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 907         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 908         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 909         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 910         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 911         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 912         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 913         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 914         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 915         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 916         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 917         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 918         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 919         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 920         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 921         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 922         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 923         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 924         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 925         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 926         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 927         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 928         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 929         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 930         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 931         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 932         { 0xFFFFFFFF }
 933 };
 934
 935 static const struct si_cac_config_reg lcac_cape_verde[] =
 936 {
 937         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 938         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 939         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 940         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 941         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 942         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 943         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 944         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 945         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 946         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 947         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 948         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 949         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 950         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 951         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 952         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 953         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 954         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 955         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 956         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 957         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 958         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 959         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 960         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 961         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 962         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 963         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 964         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 965         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 966         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 967         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 968         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 969         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 970         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 971         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 972         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 973         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 974         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 975         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 976         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 977         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 978         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 979         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 980         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 981         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 982         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 983         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 984         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 985         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 986         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 987         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 988         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 989         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 990         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 991         { 0xFFFFFFFF }
 992 };
 993
 994 static const struct si_cac_config_reg cac_override_cape_verde[] =
 995 {
 996         { 0xFFFFFFFF }
 997 };
 998
 999 static const struct si_powertune_data powertune_data_cape_verde =
1000 {
1001         ((1 << 16) | 0x6993),
1002         5,
1003         0,
1004         7,
1005         105,
1006         {
1007                 0UL,
1008                 0UL,
1009                 7194395UL,
1010                 309631529UL,
1011                 -1270850L,
1012                 4513710L,
1013                 100
1014         },
1015         117830498UL,
1016         12,
1017         {
1018                 0,
1019                 0,
1020                 0,
1021                 0,
1022                 0,
1023                 0,
1024                 0,
1025                 0
1026         },
1027         true
1028 };
1029
1030 static const struct si_dte_data dte_data_cape_verde =
1031 {
1032         { 0, 0, 0, 0, 0 },
1033         { 0, 0, 0, 0, 0 },
1034         0,
1035         0,
1036         0,
1037         0,
1038         0,
1039         0,
1040         0,
1041         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1042         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1043         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1044         0,
1045         false
1046 };
1047
1048 static const struct si_dte_data dte_data_venus_xtx =
1049 {
1050         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1051         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1052         5,
1053         55000,
1054         0x69,
1055         0xA,
1056         1,
1057         0,
1058         0x3,
1059         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1060         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1061         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1062         90,
1063         true
1064 };
1065
1066 static const struct si_dte_data dte_data_venus_xt =
1067 {
1068         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1069         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1070         5,
1071         55000,
1072         0x69,
1073         0xA,
1074         1,
1075         0,
1076         0x3,
1077         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1078         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1079         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1080         90,
1081         true
1082 };
1083
1084 static const struct si_dte_data dte_data_venus_pro =
1085 {
1086         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1087         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1088         5,
1089         55000,
1090         0x69,
1091         0xA,
1092         1,
1093         0,
1094         0x3,
1095         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1096         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1097         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1098         90,
1099         true
1100 };
1101
1102 struct si_cac_config_reg cac_weights_oland[] =
1103 {
1104         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1105         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1106         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1107         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1108         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1109         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1110         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1111         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1112         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1113         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1114         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1115         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1116         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1117         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1118         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1119         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1120         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1121         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1122         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1123         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1124         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1125         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1126         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1127         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1128         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1129         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1130         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1131         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1132         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1133         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1134         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1135         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1136         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1137         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1138         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1139         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1140         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1141         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1142         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1143         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1144         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1145         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1146         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1147         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1148         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1149         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1150         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1151         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1152         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1153         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1154         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1155         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1156         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1157         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1158         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1159         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1160         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1161         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1162         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1163         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1164         { 0xFFFFFFFF }
1165 };
1166
1167 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1168 {
1169         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1170         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1171         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1172         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1173         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1174         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1175         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1176         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1177         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1178         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1179         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1180         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1181         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1182         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1183         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1184         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1185         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1186         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1187         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1188         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1189         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1190         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1191         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1192         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1193         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1194         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1195         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1196         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1197         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1198         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1199         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1200         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1201         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1202         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1203         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1204         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1205         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1206         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1207         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1208         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1209         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1210         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1211         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1212         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1214         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1215         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1216         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1217         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1218         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1219         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1220         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1221         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1222         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1223         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1224         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1225         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1226         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1227         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1228         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1229         { 0xFFFFFFFF }
1230 };
1231
1232 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1233 {
1234         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1235         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1236         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1237         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1238         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1239         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1240         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1241         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1242         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1243         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1244         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1245         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1246         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1247         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1248         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1249         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1250         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1251         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1252         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1253         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1254         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1255         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1256         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1257         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1258         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1259         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1260         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1261         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1262         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1263         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1264         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1265         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1266         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1267         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1268         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1269         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1270         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1271         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1272         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1273         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1274         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1275         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1276         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1277         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1278         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1279         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1280         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1281         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1282         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1283         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1284         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1285         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1286         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1287         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1288         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1289         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1290         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1291         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1292         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1293         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1294         { 0xFFFFFFFF }
1295 };
1296
1297 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1298 {
1299         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1300         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1301         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1302         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1303         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1304         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1305         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1306         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1307         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1308         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1309         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1310         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1311         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1312         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1313         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1314         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1315         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1316         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1317         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1318         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1319         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1320         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1321         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1322         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1323         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1324         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1325         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1326         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1327         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1328         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1329         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1330         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1331         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1332         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1333         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1334         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1335         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1336         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1337         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1338         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1339         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1340         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1341         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1342         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1343         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1344         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1345         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1346         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1347         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1348         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1349         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1350         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1351         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1352         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1353         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1354         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1355         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1356         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1357         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1358         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1359         { 0xFFFFFFFF }
1360 };
1361
1362 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1363 {
1364         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1365         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1366         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1367         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1368         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1369         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1370         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1371         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1372         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1373         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1374         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1375         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1376         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1377         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1378         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1379         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1380         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1381         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1382         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1383         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1384         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1385         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1386         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1387         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1388         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1389         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1390         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1391         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1392         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1393         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1394         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1395         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1396         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1397         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1398         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1399         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1400         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1401         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1402         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1403         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1404         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1405         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1406         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1407         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1408         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1409         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1410         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1411         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1412         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1413         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1414         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1415         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1416         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1417         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1418         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1419         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1420         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1421         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1422         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1423         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1424         { 0xFFFFFFFF }
1425 };
1426
1427 static const struct si_cac_config_reg lcac_oland[] =
1428 {
1429         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1430         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1431         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1432         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1434         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1435         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1436         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1437         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1438         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1439         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1440         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1441         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1442         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1443         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1444         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1445         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1446         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1447         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1448         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1449         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1450         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1451         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1452         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1453         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1454         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1455         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1456         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1457         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1458         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1460         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1462         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1464         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1466         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1468         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1469         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1470         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1471         { 0xFFFFFFFF }
1472 };
1473
1474 static const struct si_cac_config_reg lcac_mars_pro[] =
1475 {
1476         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1477         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1479         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1480         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1481         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1483         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1484         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1485         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1486         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1487         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1488         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1489         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1490         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1491         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1492         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1493         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1494         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1495         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1496         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1497         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1499         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1500         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1501         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1502         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1503         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1504         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1505         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1506         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1507         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1508         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1509         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1510         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1511         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1513         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1515         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1516         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1517         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1518         { 0xFFFFFFFF }
1519 };
1520
1521 static const struct si_cac_config_reg cac_override_oland[] =
1522 {
1523         { 0xFFFFFFFF }
1524 };
1525
1526 static const struct si_powertune_data powertune_data_oland =
1527 {
1528         ((1 << 16) | 0x6993),
1529         5,
1530         0,
1531         7,
1532         105,
1533         {
1534                 0UL,
1535                 0UL,
1536                 7194395UL,
1537                 309631529UL,
1538                 -1270850L,
1539                 4513710L,
1540                 100
1541         },
1542         117830498UL,
1543         12,
1544         {
1545                 0,
1546                 0,
1547                 0,
1548                 0,
1549                 0,
1550                 0,
1551                 0,
1552                 0
1553         },
1554         true
1555 };
1556
1557 static const struct si_powertune_data powertune_data_mars_pro =
1558 {
1559         ((1 << 16) | 0x6993),
1560         5,
1561         0,
1562         7,
1563         105,
1564         {
1565                 0UL,
1566                 0UL,
1567                 7194395UL,
1568                 309631529UL,
1569                 -1270850L,
1570                 4513710L,
1571                 100
1572         },
1573         117830498UL,
1574         12,
1575         {
1576                 0,
1577                 0,
1578                 0,
1579                 0,
1580                 0,
1581                 0,
1582                 0,
1583                 0
1584         },
1585         true
1586 };
1587
1588 static const struct si_dte_data dte_data_oland =
1589 {
1590         { 0, 0, 0, 0, 0 },
1591         { 0, 0, 0, 0, 0 },
1592         0,
1593         0,
1594         0,
1595         0,
1596         0,
1597         0,
1598         0,
1599         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1600         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1601         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1602         0,
1603         false
1604 };
1605
1606 static const struct si_dte_data dte_data_mars_pro =
1607 {
1608         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1609         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1610         5,
1611         55000,
1612         105,
1613         0xA,
1614         1,
1615         0,
1616         0x10,
1617         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1618         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1619         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1620         90,
1621         true
1622 };
1623
1624 static const struct si_dte_data dte_data_sun_xt =
1625 {
1626         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1627         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1628         5,
1629         55000,
1630         105,
1631         0xA,
1632         1,
1633         0,
1634         0x10,
1635         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1636         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1637         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1638         90,
1639         true
1640 };
1641
1642
1643 static const struct si_cac_config_reg cac_weights_hainan[] =
1644 {
1645         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1646         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1647         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1648         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1649         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1650         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1651         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1652         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1653         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1654         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1655         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1656         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1657         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1658         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1659         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1660         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1661         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1662         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1663         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1664         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1665         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1666         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1667         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1668         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1669         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1670         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1671         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1672         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1673         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1674         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1675         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1676         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1677         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1678         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1679         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1680         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1681         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1682         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1683         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1684         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1685         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1686         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1687         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1688         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1689         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1690         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1691         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1692         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1693         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1694         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1695         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1696         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1697         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1698         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1699         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1700         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1701         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1702         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1703         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1704         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1705         { 0xFFFFFFFF }
1706 };
1707
1708 static const struct si_powertune_data powertune_data_hainan =
1709 {
1710         ((1 << 16) | 0x6993),
1711         5,
1712         0,
1713         9,
1714         105,
1715         {
1716                 0UL,
1717                 0UL,
1718                 7194395UL,
1719                 309631529UL,
1720                 -1270850L,
1721                 4513710L,
1722                 100
1723         },
1724         117830498UL,
1725         12,
1726         {
1727                 0,
1728                 0,
1729                 0,
1730                 0,
1731                 0,
1732                 0,
1733                 0,
1734                 0
1735         },
1736         true
1737 };
1738
1739 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1740 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1741 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1742 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1743
1744 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
1745
1746 static int si_populate_voltage_value(struct radeon_device *rdev,
1747                                      const struct atom_voltage_table *table,
1748                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1749 static int si_get_std_voltage_value(struct radeon_device *rdev,
1750                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1751                                     u16 *std_voltage);
1752 static int si_write_smc_soft_register(struct radeon_device *rdev,
1753                                       u16 reg_offset, u32 value);
1754 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1755                                          struct rv7xx_pl *pl,
1756                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1757 static int si_calculate_sclk_params(struct radeon_device *rdev,
1758                                     u32 engine_clock,
1759                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1760
1761 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1762 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1763
1764 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1765 {
1766         struct si_power_info *pi = rdev->pm.dpm.priv;
1767
1768         return pi;
1769 }
1770
1771 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1772                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1773 {
1774         s64 kt, kv, leakage_w, i_leakage, vddc;
1775         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1776         s64 tmp;
1777
1778         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1779         vddc = div64_s64(drm_int2fixp(v), 1000);
1780         temperature = div64_s64(drm_int2fixp(t), 1000);
1781
1782         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1783         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1784         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1785         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1786         t_ref = drm_int2fixp(coeff->t_ref);
1787
1788         tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1789         kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1790         kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1791         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1792
1793         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1794
1795         *leakage = drm_fixp2int(leakage_w * 1000);
1796 }
1797
1798 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1799                                              const struct ni_leakage_coeffients *coeff,
1800                                              u16 v,
1801                                              s32 t,
1802                                              u32 i_leakage,
1803                                              u32 *leakage)
1804 {
1805         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1806 }
1807
1808 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1809                                                const u32 fixed_kt, u16 v,
1810                                                u32 ileakage, u32 *leakage)
1811 {
1812         s64 kt, kv, leakage_w, i_leakage, vddc;
1813
1814         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1815         vddc = div64_s64(drm_int2fixp(v), 1000);
1816
1817         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1818         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1819                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1820
1821         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1822
1823         *leakage = drm_fixp2int(leakage_w * 1000);
1824 }
1825
1826 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1827                                        const struct ni_leakage_coeffients *coeff,
1828                                        const u32 fixed_kt,
1829                                        u16 v,
1830                                        u32 i_leakage,
1831                                        u32 *leakage)
1832 {
1833         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1834 }
1835
1836
1837 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1838                                    struct si_dte_data *dte_data)
1839 {
1840         u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1841         u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1842         u32 k = dte_data->k;
1843         u32 t_max = dte_data->max_t;
1844         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1845         u32 t_0 = dte_data->t0;
1846         u32 i;
1847
1848         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1849                 dte_data->tdep_count = 3;
1850
1851                 for (i = 0; i < k; i++) {
1852                         dte_data->r[i] =
1853                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1854                                 (p_limit2  * (u32)100);
1855                 }
1856
1857                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1858
1859                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1860                         dte_data->tdep_r[i] = dte_data->r[4];
1861                 }
1862         } else {
1863                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1864         }
1865 }
1866
1867 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1868 {
1869         struct ni_power_info *ni_pi = ni_get_pi(rdev);
1870         struct si_power_info *si_pi = si_get_pi(rdev);
1871         bool update_dte_from_pl2 = false;
1872
1873         if (rdev->family == CHIP_TAHITI) {
1874                 si_pi->cac_weights = cac_weights_tahiti;
1875                 si_pi->lcac_config = lcac_tahiti;
1876                 si_pi->cac_override = cac_override_tahiti;
1877                 si_pi->powertune_data = &powertune_data_tahiti;
1878                 si_pi->dte_data = dte_data_tahiti;
1879
1880                 switch (rdev->pdev->device) {
1881                 case 0x6798:
1882                         si_pi->dte_data.enable_dte_by_default = true;
1883                         break;
1884                 case 0x6799:
1885                         si_pi->dte_data = dte_data_new_zealand;
1886                         break;
1887                 case 0x6790:
1888                 case 0x6791:
1889                 case 0x6792:
1890                 case 0x679E:
1891                         si_pi->dte_data = dte_data_aruba_pro;
1892                         update_dte_from_pl2 = true;
1893                         break;
1894                 case 0x679B:
1895                         si_pi->dte_data = dte_data_malta;
1896                         update_dte_from_pl2 = true;
1897                         break;
1898                 case 0x679A:
1899                         si_pi->dte_data = dte_data_tahiti_pro;
1900                         update_dte_from_pl2 = true;
1901                         break;
1902                 default:
1903                         if (si_pi->dte_data.enable_dte_by_default == true)
1904                                 DRM_ERROR("DTE is not enabled!\n");
1905                         break;
1906                 }
1907         } else if (rdev->family == CHIP_PITCAIRN) {
1908                 switch (rdev->pdev->device) {
1909                 case 0x6810:
1910                 case 0x6818:
1911                         si_pi->cac_weights = cac_weights_pitcairn;
1912                         si_pi->lcac_config = lcac_pitcairn;
1913                         si_pi->cac_override = cac_override_pitcairn;
1914                         si_pi->powertune_data = &powertune_data_pitcairn;
1915                         si_pi->dte_data = dte_data_curacao_xt;
1916                         update_dte_from_pl2 = true;
1917                         break;
1918                 case 0x6819:
1919                 case 0x6811:
1920                         si_pi->cac_weights = cac_weights_pitcairn;
1921                         si_pi->lcac_config = lcac_pitcairn;
1922                         si_pi->cac_override = cac_override_pitcairn;
1923                         si_pi->powertune_data = &powertune_data_pitcairn;
1924                         si_pi->dte_data = dte_data_curacao_pro;
1925                         update_dte_from_pl2 = true;
1926                         break;
1927                 case 0x6800:
1928                 case 0x6806:
1929                         si_pi->cac_weights = cac_weights_pitcairn;
1930                         si_pi->lcac_config = lcac_pitcairn;
1931                         si_pi->cac_override = cac_override_pitcairn;
1932                         si_pi->powertune_data = &powertune_data_pitcairn;
1933                         si_pi->dte_data = dte_data_neptune_xt;
1934                         update_dte_from_pl2 = true;
1935                         break;
1936                 default:
1937                         si_pi->cac_weights = cac_weights_pitcairn;
1938                         si_pi->lcac_config = lcac_pitcairn;
1939                         si_pi->cac_override = cac_override_pitcairn;
1940                         si_pi->powertune_data = &powertune_data_pitcairn;
1941                         si_pi->dte_data = dte_data_pitcairn;
1942                         break;
1943                 }
1944         } else if (rdev->family == CHIP_VERDE) {
1945                 si_pi->lcac_config = lcac_cape_verde;
1946                 si_pi->cac_override = cac_override_cape_verde;
1947                 si_pi->powertune_data = &powertune_data_cape_verde;
1948
1949                 switch (rdev->pdev->device) {
1950                 case 0x683B:
1951                 case 0x683F:
1952                 case 0x6829:
1953                 case 0x6835:
1954                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1955                         si_pi->dte_data = dte_data_cape_verde;
1956                         break;
1957                 case 0x682C:
1958                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1959                         si_pi->dte_data = dte_data_sun_xt;
1960                         break;
1961                 case 0x6825:
1962                 case 0x6827:
1963                         si_pi->cac_weights = cac_weights_heathrow;
1964                         si_pi->dte_data = dte_data_cape_verde;
1965                         break;
1966                 case 0x6824:
1967                 case 0x682D:
1968                         si_pi->cac_weights = cac_weights_chelsea_xt;
1969                         si_pi->dte_data = dte_data_cape_verde;
1970                         break;
1971                 case 0x682F:
1972                         si_pi->cac_weights = cac_weights_chelsea_pro;
1973                         si_pi->dte_data = dte_data_cape_verde;
1974                         break;
1975                 case 0x6820:
1976                         si_pi->cac_weights = cac_weights_heathrow;
1977                         si_pi->dte_data = dte_data_venus_xtx;
1978                         break;
1979                 case 0x6821:
1980                         si_pi->cac_weights = cac_weights_heathrow;
1981                         si_pi->dte_data = dte_data_venus_xt;
1982                         break;
1983                 case 0x6823:
1984                 case 0x682B:
1985                 case 0x6822:
1986                 case 0x682A:
1987                         si_pi->cac_weights = cac_weights_chelsea_pro;
1988                         si_pi->dte_data = dte_data_venus_pro;
1989                         break;
1990                 default:
1991                         si_pi->cac_weights = cac_weights_cape_verde;
1992                         si_pi->dte_data = dte_data_cape_verde;
1993                         break;
1994                 }
1995         } else if (rdev->family == CHIP_OLAND) {
1996                 switch (rdev->pdev->device) {
1997                 case 0x6601:
1998                 case 0x6621:
1999                 case 0x6603:
2000                 case 0x6605:
2001                         si_pi->cac_weights = cac_weights_mars_pro;
2002                         si_pi->lcac_config = lcac_mars_pro;
2003                         si_pi->cac_override = cac_override_oland;
2004                         si_pi->powertune_data = &powertune_data_mars_pro;
2005                         si_pi->dte_data = dte_data_mars_pro;
2006                         update_dte_from_pl2 = true;
2007                         break;
2008                 case 0x6600:
2009                 case 0x6606:
2010                 case 0x6620:
2011                 case 0x6604:
2012                         si_pi->cac_weights = cac_weights_mars_xt;
2013                         si_pi->lcac_config = lcac_mars_pro;
2014                         si_pi->cac_override = cac_override_oland;
2015                         si_pi->powertune_data = &powertune_data_mars_pro;
2016                         si_pi->dte_data = dte_data_mars_pro;
2017                         update_dte_from_pl2 = true;
2018                         break;
2019                 case 0x6611:
2020                 case 0x6613:
2021                 case 0x6608:
2022                         si_pi->cac_weights = cac_weights_oland_pro;
2023                         si_pi->lcac_config = lcac_mars_pro;
2024                         si_pi->cac_override = cac_override_oland;
2025                         si_pi->powertune_data = &powertune_data_mars_pro;
2026                         si_pi->dte_data = dte_data_mars_pro;
2027                         update_dte_from_pl2 = true;
2028                         break;
2029                 case 0x6610:
2030                         si_pi->cac_weights = cac_weights_oland_xt;
2031                         si_pi->lcac_config = lcac_mars_pro;
2032                         si_pi->cac_override = cac_override_oland;
2033                         si_pi->powertune_data = &powertune_data_mars_pro;
2034                         si_pi->dte_data = dte_data_mars_pro;
2035                         update_dte_from_pl2 = true;
2036                         break;
2037                 default:
2038                         si_pi->cac_weights = cac_weights_oland;
2039                         si_pi->lcac_config = lcac_oland;
2040                         si_pi->cac_override = cac_override_oland;
2041                         si_pi->powertune_data = &powertune_data_oland;
2042                         si_pi->dte_data = dte_data_oland;
2043                         break;
2044                 }
2045         } else if (rdev->family == CHIP_HAINAN) {
2046                 si_pi->cac_weights = cac_weights_hainan;
2047                 si_pi->lcac_config = lcac_oland;
2048                 si_pi->cac_override = cac_override_oland;
2049                 si_pi->powertune_data = &powertune_data_hainan;
2050                 si_pi->dte_data = dte_data_sun_xt;
2051                 update_dte_from_pl2 = true;
2052         } else {
2053                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2054                 return;
2055         }
2056
2057         ni_pi->enable_power_containment = false;
2058         ni_pi->enable_cac = false;
2059         ni_pi->enable_sq_ramping = false;
2060         si_pi->enable_dte = false;
2061
2062         if (si_pi->powertune_data->enable_powertune_by_default) {
2063                 ni_pi->enable_power_containment= true;
2064                 ni_pi->enable_cac = true;
2065                 if (si_pi->dte_data.enable_dte_by_default) {
2066                         si_pi->enable_dte = true;
2067                         if (update_dte_from_pl2)
2068                                 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2069
2070                 }
2071                 ni_pi->enable_sq_ramping = true;
2072         }
2073
2074         ni_pi->driver_calculate_cac_leakage = true;
2075         ni_pi->cac_configuration_required = true;
2076
2077         if (ni_pi->cac_configuration_required) {
2078                 ni_pi->support_cac_long_term_average = true;
2079                 si_pi->dyn_powertune_data.l2_lta_window_size =
2080                         si_pi->powertune_data->l2_lta_window_size_default;
2081                 si_pi->dyn_powertune_data.lts_truncate =
2082                         si_pi->powertune_data->lts_truncate_default;
2083         } else {
2084                 ni_pi->support_cac_long_term_average = false;
2085                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2086                 si_pi->dyn_powertune_data.lts_truncate = 0;
2087         }
2088
2089         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2090 }
2091
2092 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2093 {
2094         return 1;
2095 }
2096
2097 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2098 {
2099         u32 xclk;
2100         u32 wintime;
2101         u32 cac_window;
2102         u32 cac_window_size;
2103
2104         xclk = radeon_get_xclk(rdev);
2105
2106         if (xclk == 0)
2107                 return 0;
2108
2109         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2110         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2111
2112         wintime = (cac_window_size * 100) / xclk;
2113
2114         return wintime;
2115 }
2116
2117 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2118 {
2119         return power_in_watts;
2120 }
2121
2122 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2123                                             bool adjust_polarity,
2124                                             u32 tdp_adjustment,
2125                                             u32 *tdp_limit,
2126                                             u32 *near_tdp_limit)
2127 {
2128         u32 adjustment_delta, max_tdp_limit;
2129
2130         if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2131                 return -EINVAL;
2132
2133         max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2134
2135         if (adjust_polarity) {
2136                 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2137                 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2138         } else {
2139                 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2140                 adjustment_delta  = rdev->pm.dpm.tdp_limit - *tdp_limit;
2141                 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2142                         *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2143                 else
2144                         *near_tdp_limit = 0;
2145         }
2146
2147         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2148                 return -EINVAL;
2149         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2150                 return -EINVAL;
2151
2152         return 0;
2153 }
2154
2155 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2156                                       struct radeon_ps *radeon_state)
2157 {
2158         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2159         struct si_power_info *si_pi = si_get_pi(rdev);
2160
2161         if (ni_pi->enable_power_containment) {
2162                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2163                 PP_SIslands_PAPMParameters *papm_parm;
2164                 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2165                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2166                 u32 tdp_limit;
2167                 u32 near_tdp_limit;
2168                 int ret;
2169
2170                 if (scaling_factor == 0)
2171                         return -EINVAL;
2172
2173                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2174
2175                 ret = si_calculate_adjusted_tdp_limits(rdev,
2176                                                        false, /* ??? */
2177                                                        rdev->pm.dpm.tdp_adjustment,
2178                                                        &tdp_limit,
2179                                                        &near_tdp_limit);
2180                 if (ret)
2181                         return ret;
2182
2183                 smc_table->dpm2Params.TDPLimit =
2184                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2185                 smc_table->dpm2Params.NearTDPLimit =
2186                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2187                 smc_table->dpm2Params.SafePowerLimit =
2188                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2189
2190                 ret = si_copy_bytes_to_smc(rdev,
2191                                            (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2192                                                  offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2193                                            (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2194                                            sizeof(u32) * 3,
2195                                            si_pi->sram_end);
2196                 if (ret)
2197                         return ret;
2198
2199                 if (si_pi->enable_ppm) {
2200                         papm_parm = &si_pi->papm_parm;
2201                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2202                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2203                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2204                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2205                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2206                         papm_parm->PlatformPowerLimit = 0xffffffff;
2207                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2208
2209                         ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2210                                                    (u8 *)papm_parm,
2211                                                    sizeof(PP_SIslands_PAPMParameters),
2212                                                    si_pi->sram_end);
2213                         if (ret)
2214                                 return ret;
2215                 }
2216         }
2217         return 0;
2218 }
2219
2220 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2221                                         struct radeon_ps *radeon_state)
2222 {
2223         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2224         struct si_power_info *si_pi = si_get_pi(rdev);
2225
2226         if (ni_pi->enable_power_containment) {
2227                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2228                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2229                 int ret;
2230
2231                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2232
2233                 smc_table->dpm2Params.NearTDPLimit =
2234                         cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2235                 smc_table->dpm2Params.SafePowerLimit =
2236                         cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2237
2238                 ret = si_copy_bytes_to_smc(rdev,
2239                                            (si_pi->state_table_start +
2240                                             offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2241                                             offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2242                                            (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2243                                            sizeof(u32) * 2,
2244                                            si_pi->sram_end);
2245                 if (ret)
2246                         return ret;
2247         }
2248
2249         return 0;
2250 }
2251
2252 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2253                                                const u16 prev_std_vddc,
2254                                                const u16 curr_std_vddc)
2255 {
2256         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2257         u64 prev_vddc = (u64)prev_std_vddc;
2258         u64 curr_vddc = (u64)curr_std_vddc;
2259         u64 pwr_efficiency_ratio, n, d;
2260
2261         if ((prev_vddc == 0) || (curr_vddc == 0))
2262                 return 0;
2263
2264         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2265         d = prev_vddc * prev_vddc;
2266         pwr_efficiency_ratio = div64_u64(n, d);
2267
2268         if (pwr_efficiency_ratio > (u64)0xFFFF)
2269                 return 0;
2270
2271         return (u16)pwr_efficiency_ratio;
2272 }
2273
2274 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2275                                             struct radeon_ps *radeon_state)
2276 {
2277         struct si_power_info *si_pi = si_get_pi(rdev);
2278
2279         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2280             radeon_state->vclk && radeon_state->dclk)
2281                 return true;
2282
2283         return false;
2284 }
2285
2286 static int si_populate_power_containment_values(struct radeon_device *rdev,
2287                                                 struct radeon_ps *radeon_state,
2288                                                 SISLANDS_SMC_SWSTATE *smc_state)
2289 {
2290         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2291         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2292         struct ni_ps *state = ni_get_ps(radeon_state);
2293         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2294         u32 prev_sclk;
2295         u32 max_sclk;
2296         u32 min_sclk;
2297         u16 prev_std_vddc;
2298         u16 curr_std_vddc;
2299         int i;
2300         u16 pwr_efficiency_ratio;
2301         u8 max_ps_percent;
2302         bool disable_uvd_power_tune;
2303         int ret;
2304
2305         if (ni_pi->enable_power_containment == false)
2306                 return 0;
2307
2308         if (state->performance_level_count == 0)
2309                 return -EINVAL;
2310
2311         if (smc_state->levelCount != state->performance_level_count)
2312                 return -EINVAL;
2313
2314         disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2315
2316         smc_state->levels[0].dpm2.MaxPS = 0;
2317         smc_state->levels[0].dpm2.NearTDPDec = 0;
2318         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2319         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2320         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2321
2322         for (i = 1; i < state->performance_level_count; i++) {
2323                 prev_sclk = state->performance_levels[i-1].sclk;
2324                 max_sclk  = state->performance_levels[i].sclk;
2325                 if (i == 1)
2326                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2327                 else
2328                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2329
2330                 if (prev_sclk > max_sclk)
2331                         return -EINVAL;
2332
2333                 if ((max_ps_percent == 0) ||
2334                     (prev_sclk == max_sclk) ||
2335                     disable_uvd_power_tune) {
2336                         min_sclk = max_sclk;
2337                 } else if (i == 1) {
2338                         min_sclk = prev_sclk;
2339                 } else {
2340                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2341                 }
2342
2343                 if (min_sclk < state->performance_levels[0].sclk)
2344                         min_sclk = state->performance_levels[0].sclk;
2345
2346                 if (min_sclk == 0)
2347                         return -EINVAL;
2348
2349                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2350                                                 state->performance_levels[i-1].vddc, &vddc);
2351                 if (ret)
2352                         return ret;
2353
2354                 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2355                 if (ret)
2356                         return ret;
2357
2358                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2359                                                 state->performance_levels[i].vddc, &vddc);
2360                 if (ret)
2361                         return ret;
2362
2363                 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2364                 if (ret)
2365                         return ret;
2366
2367                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2368                                                                            prev_std_vddc, curr_std_vddc);
2369
2370                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2371                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2372                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2373                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2374                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2375         }
2376
2377         return 0;
2378 }
2379
2380 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2381                                          struct radeon_ps *radeon_state,
2382                                          SISLANDS_SMC_SWSTATE *smc_state)
2383 {
2384         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2385         struct ni_ps *state = ni_get_ps(radeon_state);
2386         u32 sq_power_throttle, sq_power_throttle2;
2387         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2388         int i;
2389
2390         if (state->performance_level_count == 0)
2391                 return -EINVAL;
2392
2393         if (smc_state->levelCount != state->performance_level_count)
2394                 return -EINVAL;
2395
2396         if (rdev->pm.dpm.sq_ramping_threshold == 0)
2397                 return -EINVAL;
2398
2399         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2400                 enable_sq_ramping = false;
2401
2402         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2403                 enable_sq_ramping = false;
2404
2405         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2406                 enable_sq_ramping = false;
2407
2408         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2409                 enable_sq_ramping = false;
2410
2411         if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2412                 enable_sq_ramping = false;
2413
2414         for (i = 0; i < state->performance_level_count; i++) {
2415                 sq_power_throttle = 0;
2416                 sq_power_throttle2 = 0;
2417
2418                 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2419                     enable_sq_ramping) {
2420                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2421                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2422                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2423                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2424                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2425                 } else {
2426                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2427                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2428                 }
2429
2430                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2431                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2432         }
2433
2434         return 0;
2435 }
2436
2437 static int si_enable_power_containment(struct radeon_device *rdev,
2438                                        struct radeon_ps *radeon_new_state,
2439                                        bool enable)
2440 {
2441         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2442         PPSMC_Result smc_result;
2443         int ret = 0;
2444
2445         if (ni_pi->enable_power_containment) {
2446                 if (enable) {
2447                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2448                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2449                                 if (smc_result != PPSMC_Result_OK) {
2450                                         ret = -EINVAL;
2451                                         ni_pi->pc_enabled = false;
2452                                 } else {
2453                                         ni_pi->pc_enabled = true;
2454                                 }
2455                         }
2456                 } else {
2457                         smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2458                         if (smc_result != PPSMC_Result_OK)
2459                                 ret = -EINVAL;
2460                         ni_pi->pc_enabled = false;
2461                 }
2462         }
2463
2464         return ret;
2465 }
2466
2467 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2468 {
2469         struct si_power_info *si_pi = si_get_pi(rdev);
2470         int ret = 0;
2471         struct si_dte_data *dte_data = &si_pi->dte_data;
2472         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2473         u32 table_size;
2474         u8 tdep_count;
2475         u32 i;
2476
2477         if (dte_data == NULL)
2478                 si_pi->enable_dte = false;
2479
2480         if (si_pi->enable_dte == false)
2481                 return 0;
2482
2483         if (dte_data->k <= 0)
2484                 return -EINVAL;
2485
2486         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2487         if (dte_tables == NULL) {
2488                 si_pi->enable_dte = false;
2489                 return -ENOMEM;
2490         }
2491
2492         table_size = dte_data->k;
2493
2494         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2495                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2496
2497         tdep_count = dte_data->tdep_count;
2498         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2499                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2500
2501         dte_tables->K = cpu_to_be32(table_size);
2502         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2503         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2504         dte_tables->WindowSize = dte_data->window_size;
2505         dte_tables->temp_select = dte_data->temp_select;
2506         dte_tables->DTE_mode = dte_data->dte_mode;
2507         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2508
2509         if (tdep_count > 0)
2510                 table_size--;
2511
2512         for (i = 0; i < table_size; i++) {
2513                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2514                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2515         }
2516
2517         dte_tables->Tdep_count = tdep_count;
2518
2519         for (i = 0; i < (u32)tdep_count; i++) {
2520                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2521                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2522                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2523         }
2524
2525         ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2526                                    sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2527         kfree(dte_tables);
2528
2529         return ret;
2530 }
2531
2532 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2533                                           u16 *max, u16 *min)
2534 {
2535         struct si_power_info *si_pi = si_get_pi(rdev);
2536         struct radeon_cac_leakage_table *table =
2537                 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2538         u32 i;
2539         u32 v0_loadline;
2540
2541
2542         if (table == NULL)
2543                 return -EINVAL;
2544
2545         *max = 0;
2546         *min = 0xFFFF;
2547
2548         for (i = 0; i < table->count; i++) {
2549                 if (table->entries[i].vddc > *max)
2550                         *max = table->entries[i].vddc;
2551                 if (table->entries[i].vddc < *min)
2552                         *min = table->entries[i].vddc;
2553         }
2554
2555         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2556                 return -EINVAL;
2557
2558         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2559
2560         if (v0_loadline > 0xFFFFUL)
2561                 return -EINVAL;
2562
2563         *min = (u16)v0_loadline;
2564
2565         if ((*min > *max) || (*max == 0) || (*min == 0))
2566                 return -EINVAL;
2567
2568         return 0;
2569 }
2570
2571 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2572 {
2573         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2574                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2575 }
2576
2577 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2578                                      PP_SIslands_CacConfig *cac_tables,
2579                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2580                                      u16 t0, u16 t_step)
2581 {
2582         struct si_power_info *si_pi = si_get_pi(rdev);
2583         u32 leakage;
2584         unsigned int i, j;
2585         s32 t;
2586         u32 smc_leakage;
2587         u32 scaling_factor;
2588         u16 voltage;
2589
2590         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2591
2592         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2593                 t = (1000 * (i * t_step + t0));
2594
2595                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2596                         voltage = vddc_max - (vddc_step * j);
2597
2598                         si_calculate_leakage_for_v_and_t(rdev,
2599                                                          &si_pi->powertune_data->leakage_coefficients,
2600                                                          voltage,
2601                                                          t,
2602                                                          si_pi->dyn_powertune_data.cac_leakage,
2603                                                          &leakage);
2604
2605                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2606
2607                         if (smc_leakage > 0xFFFF)
2608                                 smc_leakage = 0xFFFF;
2609
2610                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2611                                 cpu_to_be16((u16)smc_leakage);
2612                 }
2613         }
2614         return 0;
2615 }
2616
2617 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2618                                             PP_SIslands_CacConfig *cac_tables,
2619                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2620 {
2621         struct si_power_info *si_pi = si_get_pi(rdev);
2622         u32 leakage;
2623         unsigned int i, j;
2624         u32 smc_leakage;
2625         u32 scaling_factor;
2626         u16 voltage;
2627
2628         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2629
2630         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2631                 voltage = vddc_max - (vddc_step * j);
2632
2633                 si_calculate_leakage_for_v(rdev,
2634                                            &si_pi->powertune_data->leakage_coefficients,
2635                                            si_pi->powertune_data->fixed_kt,
2636                                            voltage,
2637                                            si_pi->dyn_powertune_data.cac_leakage,
2638                                            &leakage);
2639
2640                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2641
2642                 if (smc_leakage > 0xFFFF)
2643                         smc_leakage = 0xFFFF;
2644
2645                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2646                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2647                                 cpu_to_be16((u16)smc_leakage);
2648         }
2649         return 0;
2650 }
2651
2652 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2653 {
2654         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2655         struct si_power_info *si_pi = si_get_pi(rdev);
2656         PP_SIslands_CacConfig *cac_tables = NULL;
2657         u16 vddc_max, vddc_min, vddc_step;
2658         u16 t0, t_step;
2659         u32 load_line_slope, reg;
2660         int ret = 0;
2661         u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2662
2663         if (ni_pi->enable_cac == false)
2664                 return 0;
2665
2666         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2667         if (!cac_tables)
2668                 return -ENOMEM;
2669
2670         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2671         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2672         WREG32(CG_CAC_CTRL, reg);
2673
2674         si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2675         si_pi->dyn_powertune_data.dc_pwr_value =
2676                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2677         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2678         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2679
2680         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2681
2682         ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2683         if (ret)
2684                 goto done_free;
2685
2686         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2687         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2688         t_step = 4;
2689         t0 = 60;
2690
2691         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2692                 ret = si_init_dte_leakage_table(rdev, cac_tables,
2693                                                 vddc_max, vddc_min, vddc_step,
2694                                                 t0, t_step);
2695         else
2696                 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2697                                                        vddc_max, vddc_min, vddc_step);
2698         if (ret)
2699                 goto done_free;
2700
2701         load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2702
2703         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2704         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2705         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2706         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2707         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2708         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2709         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2710         cac_tables->calculation_repeats = cpu_to_be32(2);
2711         cac_tables->dc_cac = cpu_to_be32(0);
2712         cac_tables->log2_PG_LKG_SCALE = 12;
2713         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2714         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2715         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2716
2717         ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2718                                    sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2719
2720         if (ret)
2721                 goto done_free;
2722
2723         ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2724
2725 done_free:
2726         if (ret) {
2727                 ni_pi->enable_cac = false;
2728                 ni_pi->enable_power_containment = false;
2729         }
2730
2731         kfree(cac_tables);
2732
2733         return 0;
2734 }
2735
2736 static int si_program_cac_config_registers(struct radeon_device *rdev,
2737                                            const struct si_cac_config_reg *cac_config_regs)
2738 {
2739         const struct si_cac_config_reg *config_regs = cac_config_regs;
2740         u32 data = 0, offset;
2741
2742         if (!config_regs)
2743                 return -EINVAL;
2744
2745         while (config_regs->offset != 0xFFFFFFFF) {
2746                 switch (config_regs->type) {
2747                 case SISLANDS_CACCONFIG_CGIND:
2748                         offset = SMC_CG_IND_START + config_regs->offset;
2749                         if (offset < SMC_CG_IND_END)
2750                                 data = RREG32_SMC(offset);
2751                         break;
2752                 default:
2753                         data = RREG32(config_regs->offset << 2);
2754                         break;
2755                 }
2756
2757                 data &= ~config_regs->mask;
2758                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2759
2760                 switch (config_regs->type) {
2761                 case SISLANDS_CACCONFIG_CGIND:
2762                         offset = SMC_CG_IND_START + config_regs->offset;
2763                         if (offset < SMC_CG_IND_END)
2764                                 WREG32_SMC(offset, data);
2765                         break;
2766                 default:
2767                         WREG32(config_regs->offset << 2, data);
2768                         break;
2769                 }
2770                 config_regs++;
2771         }
2772         return 0;
2773 }
2774
2775 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2776 {
2777         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2778         struct si_power_info *si_pi = si_get_pi(rdev);
2779         int ret;
2780
2781         if ((ni_pi->enable_cac == false) ||
2782             (ni_pi->cac_configuration_required == false))
2783                 return 0;
2784
2785         ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2786         if (ret)
2787                 return ret;
2788         ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2789         if (ret)
2790                 return ret;
2791         ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2792         if (ret)
2793                 return ret;
2794
2795         return 0;
2796 }
2797
2798 static int si_enable_smc_cac(struct radeon_device *rdev,
2799                              struct radeon_ps *radeon_new_state,
2800                              bool enable)
2801 {
2802         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2803         struct si_power_info *si_pi = si_get_pi(rdev);
2804         PPSMC_Result smc_result;
2805         int ret = 0;
2806
2807         if (ni_pi->enable_cac) {
2808                 if (enable) {
2809                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2810                                 if (ni_pi->support_cac_long_term_average) {
2811                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2812                                         if (smc_result != PPSMC_Result_OK)
2813                                                 ni_pi->support_cac_long_term_average = false;
2814                                 }
2815
2816                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2817                                 if (smc_result != PPSMC_Result_OK) {
2818                                         ret = -EINVAL;
2819                                         ni_pi->cac_enabled = false;
2820                                 } else {
2821                                         ni_pi->cac_enabled = true;
2822                                 }
2823
2824                                 if (si_pi->enable_dte) {
2825                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2826                                         if (smc_result != PPSMC_Result_OK)
2827                                                 ret = -EINVAL;
2828                                 }
2829                         }
2830                 } else if (ni_pi->cac_enabled) {
2831                         if (si_pi->enable_dte)
2832                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2833
2834                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2835
2836                         ni_pi->cac_enabled = false;
2837
2838                         if (ni_pi->support_cac_long_term_average)
2839                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2840                 }
2841         }
2842         return ret;
2843 }
2844
2845 static int si_init_smc_spll_table(struct radeon_device *rdev)
2846 {
2847         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2848         struct si_power_info *si_pi = si_get_pi(rdev);
2849         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2850         SISLANDS_SMC_SCLK_VALUE sclk_params;
2851         u32 fb_div, p_div;
2852         u32 clk_s, clk_v;
2853         u32 sclk = 0;
2854         int ret = 0;
2855         u32 tmp;
2856         int i;
2857
2858         if (si_pi->spll_table_start == 0)
2859                 return -EINVAL;
2860
2861         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2862         if (spll_table == NULL)
2863                 return -ENOMEM;
2864
2865         for (i = 0; i < 256; i++) {
2866                 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2867                 if (ret)
2868                         break;
2869
2870                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2871                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2872                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2873                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2874
2875                 fb_div &= ~0x00001FFF;
2876                 fb_div >>= 1;
2877                 clk_v >>= 6;
2878
2879                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2880                         ret = -EINVAL;
2881                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2882                         ret = -EINVAL;
2883                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2884                         ret = -EINVAL;
2885                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2886                         ret = -EINVAL;
2887
2888                 if (ret)
2889                         break;
2890
2891                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2892                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2893                 spll_table->freq[i] = cpu_to_be32(tmp);
2894
2895                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2896                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2897                 spll_table->ss[i] = cpu_to_be32(tmp);
2898
2899                 sclk += 512;
2900         }
2901
2902
2903         if (!ret)
2904                 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2905                                            (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2906                                            si_pi->sram_end);
2907
2908         if (ret)
2909                 ni_pi->enable_power_containment = false;
2910
2911         kfree(spll_table);
2912
2913         return ret;
2914 }
2915
2916 struct si_dpm_quirk {
2917         u32 chip_vendor;
2918         u32 chip_device;
2919         u32 subsys_vendor;
2920         u32 subsys_device;
2921         u32 max_sclk;
2922         u32 max_mclk;
2923 };
2924
2925 /* cards with dpm stability problems */
2926 static struct si_dpm_quirk si_dpm_quirk_list[] = {
2927         /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
2928         { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
2929         { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
2930         { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
2931         { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
2932         { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
2933         { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
2934         { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
2935         { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
2936         { 0, 0, 0, 0 },
2937 };
2938
2939 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev,
2940                                                    u16 vce_voltage)
2941 {
2942         u16 highest_leakage = 0;
2943         struct si_power_info *si_pi = si_get_pi(rdev);
2944         int i;
2945
2946         for (i = 0; i < si_pi->leakage_voltage.count; i++){
2947                 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
2948                         highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
2949         }
2950
2951         if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
2952                 return highest_leakage;
2953
2954         return vce_voltage;
2955 }
2956
2957 static int si_get_vce_clock_voltage(struct radeon_device *rdev,
2958                                     u32 evclk, u32 ecclk, u16 *voltage)
2959 {
2960         u32 i;
2961         int ret = -EINVAL;
2962         struct radeon_vce_clock_voltage_dependency_table *table =
2963                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2964
2965         if (((evclk == 0) && (ecclk == 0)) ||
2966             (table && (table->count == 0))) {
2967                 *voltage = 0;
2968                 return 0;
2969         }
2970
2971         for (i = 0; i < table->count; i++) {
2972                 if ((evclk <= table->entries[i].evclk) &&
2973                     (ecclk <= table->entries[i].ecclk)) {
2974                         *voltage = table->entries[i].v;
2975                         ret = 0;
2976                         break;
2977                 }
2978         }
2979
2980         /* if no match return the highest voltage */
2981         if (ret)
2982                 *voltage = table->entries[table->count - 1].v;
2983
2984         *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage);
2985
2986         return ret;
2987 }
2988
2989 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2990                                         struct radeon_ps *rps)
2991 {
2992         struct ni_ps *ps = ni_get_ps(rps);
2993         struct radeon_clock_and_voltage_limits *max_limits;
2994         bool disable_mclk_switching = false;
2995         bool disable_sclk_switching = false;
2996         u32 mclk, sclk;
2997         u16 vddc, vddci, min_vce_voltage = 0;
2998         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2999         u32 max_sclk = 0, max_mclk = 0;
3000         int i;
3001         struct si_dpm_quirk *p = si_dpm_quirk_list;
3002
3003         /* limit all SI kickers */
3004         if (rdev->family == CHIP_PITCAIRN) {
3005                 if ((rdev->pdev->revision == 0x81) ||
3006                     (rdev->pdev->device == 0x6810) ||
3007                     (rdev->pdev->device == 0x6811) ||
3008                     (rdev->pdev->device == 0x6816) ||
3009                     (rdev->pdev->device == 0x6817) ||
3010                     (rdev->pdev->device == 0x6806))
3011                         max_mclk = 120000;
3012         } else if (rdev->family == CHIP_VERDE) {
3013                 if ((rdev->pdev->revision == 0x81) ||
3014                     (rdev->pdev->revision == 0x83) ||
3015                     (rdev->pdev->revision == 0x87) ||
3016                     (rdev->pdev->device == 0x6820) ||
3017                     (rdev->pdev->device == 0x6821) ||
3018                     (rdev->pdev->device == 0x6822) ||
3019                     (rdev->pdev->device == 0x6823) ||
3020                     (rdev->pdev->device == 0x682A) ||
3021                     (rdev->pdev->device == 0x682B)) {
3022                         max_sclk = 75000;
3023                         max_mclk = 80000;
3024                 }
3025         } else if (rdev->family == CHIP_OLAND) {
3026                 if ((rdev->pdev->revision == 0xC7) ||
3027                     (rdev->pdev->revision == 0x80) ||
3028                     (rdev->pdev->revision == 0x81) ||
3029                     (rdev->pdev->revision == 0x83) ||
3030                     (rdev->pdev->device == 0x6604) ||
3031                     (rdev->pdev->device == 0x6605)) {
3032                         max_sclk = 75000;
3033                         max_mclk = 80000;
3034                 }
3035         } else if (rdev->family == CHIP_HAINAN) {
3036                 if ((rdev->pdev->revision == 0x81) ||
3037                     (rdev->pdev->revision == 0x83) ||
3038                     (rdev->pdev->revision == 0xC3) ||
3039                     (rdev->pdev->device == 0x6664) ||
3040                     (rdev->pdev->device == 0x6665) ||
3041                     (rdev->pdev->device == 0x6667)) {
3042                         max_sclk = 75000;
3043                         max_mclk = 80000;
3044                 }
3045         }
3046         /* Apply dpm quirks */
3047         while (p && p->chip_device != 0) {
3048                 if (rdev->pdev->vendor == p->chip_vendor &&
3049                     rdev->pdev->device == p->chip_device &&
3050                     rdev->pdev->subsystem_vendor == p->subsys_vendor &&
3051                     rdev->pdev->subsystem_device == p->subsys_device) {
3052                         max_sclk = p->max_sclk;
3053                         max_mclk = p->max_mclk;
3054                         break;
3055                 }
3056                 ++p;
3057         }
3058
3059         if (rps->vce_active) {
3060                 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
3061                 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
3062                 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,
3063                                          &min_vce_voltage);
3064         } else {
3065                 rps->evclk = 0;
3066                 rps->ecclk = 0;
3067         }
3068
3069         if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
3070             ni_dpm_vblank_too_short(rdev))
3071                 disable_mclk_switching = true;
3072
3073         if (rps->vclk || rps->dclk) {
3074                 disable_mclk_switching = true;
3075                 disable_sclk_switching = true;
3076         }
3077
3078         if (rdev->pm.dpm.ac_power)
3079                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3080         else
3081                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3082
3083         for (i = ps->performance_level_count - 2; i >= 0; i--) {
3084                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3085                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3086         }
3087         if (rdev->pm.dpm.ac_power == false) {
3088                 for (i = 0; i < ps->performance_level_count; i++) {
3089                         if (ps->performance_levels[i].mclk > max_limits->mclk)
3090                                 ps->performance_levels[i].mclk = max_limits->mclk;
3091                         if (ps->performance_levels[i].sclk > max_limits->sclk)
3092                                 ps->performance_levels[i].sclk = max_limits->sclk;
3093                         if (ps->performance_levels[i].vddc > max_limits->vddc)
3094                                 ps->performance_levels[i].vddc = max_limits->vddc;
3095                         if (ps->performance_levels[i].vddci > max_limits->vddci)
3096                                 ps->performance_levels[i].vddci = max_limits->vddci;
3097                 }
3098         }
3099
3100         /* limit clocks to max supported clocks based on voltage dependency tables */
3101         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3102                                                         &max_sclk_vddc);
3103         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3104                                                         &max_mclk_vddci);
3105         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3106                                                         &max_mclk_vddc);
3107
3108         for (i = 0; i < ps->performance_level_count; i++) {
3109                 if (max_sclk_vddc) {
3110                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
3111                                 ps->performance_levels[i].sclk = max_sclk_vddc;
3112                 }
3113                 if (max_mclk_vddci) {
3114                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
3115                                 ps->performance_levels[i].mclk = max_mclk_vddci;
3116                 }
3117                 if (max_mclk_vddc) {
3118                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
3119                                 ps->performance_levels[i].mclk = max_mclk_vddc;
3120                 }
3121                 if (max_mclk) {
3122                         if (ps->performance_levels[i].mclk > max_mclk)
3123                                 ps->performance_levels[i].mclk = max_mclk;
3124                 }
3125                 if (max_sclk) {
3126                         if (ps->performance_levels[i].sclk > max_sclk)
3127                                 ps->performance_levels[i].sclk = max_sclk;
3128                 }
3129         }
3130
3131         /* XXX validate the min clocks required for display */
3132
3133         if (disable_mclk_switching) {
3134                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3135                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3136         } else {
3137                 mclk = ps->performance_levels[0].mclk;
3138                 vddci = ps->performance_levels[0].vddci;
3139         }
3140
3141         if (disable_sclk_switching) {
3142                 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3143                 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3144         } else {
3145                 sclk = ps->performance_levels[0].sclk;
3146                 vddc = ps->performance_levels[0].vddc;
3147         }
3148
3149         if (rps->vce_active) {
3150                 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
3151                         sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
3152                 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
3153                         mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
3154         }
3155
3156         /* adjusted low state */
3157         ps->performance_levels[0].sclk = sclk;
3158         ps->performance_levels[0].mclk = mclk;
3159         ps->performance_levels[0].vddc = vddc;
3160         ps->performance_levels[0].vddci = vddci;
3161
3162         if (disable_sclk_switching) {
3163                 sclk = ps->performance_levels[0].sclk;
3164                 for (i = 1; i < ps->performance_level_count; i++) {
3165                         if (sclk < ps->performance_levels[i].sclk)
3166                                 sclk = ps->performance_levels[i].sclk;
3167                 }
3168                 for (i = 0; i < ps->performance_level_count; i++) {
3169                         ps->performance_levels[i].sclk = sclk;
3170                         ps->performance_levels[i].vddc = vddc;
3171                 }
3172         } else {
3173                 for (i = 1; i < ps->performance_level_count; i++) {
3174                         if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3175                                 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3176                         if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3177                                 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3178                 }
3179         }
3180
3181         if (disable_mclk_switching) {
3182                 mclk = ps->performance_levels[0].mclk;
3183                 for (i = 1; i < ps->performance_level_count; i++) {
3184                         if (mclk < ps->performance_levels[i].mclk)
3185                                 mclk = ps->performance_levels[i].mclk;
3186                 }
3187                 for (i = 0; i < ps->performance_level_count; i++) {
3188                         ps->performance_levels[i].mclk = mclk;
3189                         ps->performance_levels[i].vddci = vddci;
3190                 }
3191         } else {
3192                 for (i = 1; i < ps->performance_level_count; i++) {
3193                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3194                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3195                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3196                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3197                 }
3198         }
3199
3200         for (i = 0; i < ps->performance_level_count; i++)
3201                 btc_adjust_clock_combinations(rdev, max_limits,
3202                                               &ps->performance_levels[i]);
3203
3204         for (i = 0; i < ps->performance_level_count; i++) {
3205                 if (ps->performance_levels[i].vddc < min_vce_voltage)
3206                         ps->performance_levels[i].vddc = min_vce_voltage;
3207                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3208                                                    ps->performance_levels[i].sclk,
3209                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3210                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3211                                                    ps->performance_levels[i].mclk,
3212                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
3213                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3214                                                    ps->performance_levels[i].mclk,
3215                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3216                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3217                                                    rdev->clock.current_dispclk,
3218                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3219         }
3220
3221         for (i = 0; i < ps->performance_level_count; i++) {
3222                 btc_apply_voltage_delta_rules(rdev,
3223                                               max_limits->vddc, max_limits->vddci,
3224                                               &ps->performance_levels[i].vddc,
3225                                               &ps->performance_levels[i].vddci);
3226         }
3227
3228         ps->dc_compatible = true;
3229         for (i = 0; i < ps->performance_level_count; i++) {
3230                 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3231                         ps->dc_compatible = false;
3232         }
3233 }
3234
3235 #if 0
3236 static int si_read_smc_soft_register(struct radeon_device *rdev,
3237                                      u16 reg_offset, u32 *value)
3238 {
3239         struct si_power_info *si_pi = si_get_pi(rdev);
3240
3241         return si_read_smc_sram_dword(rdev,
3242                                       si_pi->soft_regs_start + reg_offset, value,
3243                                       si_pi->sram_end);
3244 }
3245 #endif
3246
3247 static int si_write_smc_soft_register(struct radeon_device *rdev,
3248                                       u16 reg_offset, u32 value)
3249 {
3250         struct si_power_info *si_pi = si_get_pi(rdev);
3251
3252         return si_write_smc_sram_dword(rdev,
3253                                        si_pi->soft_regs_start + reg_offset,
3254                                        value, si_pi->sram_end);
3255 }
3256
3257 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3258 {
3259         bool ret = false;
3260         u32 tmp, width, row, column, bank, density;
3261         bool is_memory_gddr5, is_special;
3262
3263         tmp = RREG32(MC_SEQ_MISC0);
3264         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3265         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3266                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3267
3268         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3269         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3270
3271         tmp = RREG32(MC_ARB_RAMCFG);
3272         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3273         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3274         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3275
3276         density = (1 << (row + column - 20 + bank)) * width;
3277
3278         if ((rdev->pdev->device == 0x6819) &&
3279             is_memory_gddr5 && is_special && (density == 0x400))
3280                 ret = true;
3281
3282         return ret;
3283 }
3284
3285 static void si_get_leakage_vddc(struct radeon_device *rdev)
3286 {
3287         struct si_power_info *si_pi = si_get_pi(rdev);
3288         u16 vddc, count = 0;
3289         int i, ret;
3290
3291         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3292                 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3293
3294                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3295                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3296                         si_pi->leakage_voltage.entries[count].leakage_index =
3297                                 SISLANDS_LEAKAGE_INDEX0 + i;
3298                         count++;
3299                 }
3300         }
3301         si_pi->leakage_voltage.count = count;
3302 }
3303
3304 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3305                                                      u32 index, u16 *leakage_voltage)
3306 {
3307         struct si_power_info *si_pi = si_get_pi(rdev);
3308         int i;
3309
3310         if (leakage_voltage == NULL)
3311                 return -EINVAL;
3312
3313         if ((index & 0xff00) != 0xff00)
3314                 return -EINVAL;
3315
3316         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3317                 return -EINVAL;
3318
3319         if (index < SISLANDS_LEAKAGE_INDEX0)
3320                 return -EINVAL;
3321
3322         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3323                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3324                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3325                         return 0;
3326                 }
3327         }
3328         return -EAGAIN;
3329 }
3330
3331 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3332 {
3333         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3334         bool want_thermal_protection;
3335         enum radeon_dpm_event_src dpm_event_src;
3336
3337         switch (sources) {
3338         case 0:
3339         default:
3340                 want_thermal_protection = false;
3341                 break;
3342         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3343                 want_thermal_protection = true;
3344                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3345                 break;
3346         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3347                 want_thermal_protection = true;
3348                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3349                 break;
3350         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3351               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3352                 want_thermal_protection = true;
3353                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3354                 break;
3355         }
3356
3357         if (want_thermal_protection) {
3358                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3359                 if (pi->thermal_protection)
3360                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3361         } else {
3362                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3363         }
3364 }
3365
3366 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3367                                            enum radeon_dpm_auto_throttle_src source,
3368                                            bool enable)
3369 {
3370         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3371
3372         if (enable) {
3373                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3374                         pi->active_auto_throttle_sources |= 1 << source;
3375                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3376                 }
3377         } else {
3378                 if (pi->active_auto_throttle_sources & (1 << source)) {
3379                         pi->active_auto_throttle_sources &= ~(1 << source);
3380                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3381                 }
3382         }
3383 }
3384
3385 static void si_start_dpm(struct radeon_device *rdev)
3386 {
3387         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3388 }
3389
3390 static void si_stop_dpm(struct radeon_device *rdev)
3391 {
3392         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3393 }
3394
3395 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3396 {
3397         if (enable)
3398                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3399         else
3400                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3401
3402 }
3403
3404 #if 0
3405 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3406                                                u32 thermal_level)
3407 {
3408         PPSMC_Result ret;
3409
3410         if (thermal_level == 0) {
3411                 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3412                 if (ret == PPSMC_Result_OK)
3413                         return 0;
3414                 else
3415                         return -EINVAL;
3416         }
3417         return 0;
3418 }
3419
3420 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3421 {
3422         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3423 }
3424 #endif
3425
3426 #if 0
3427 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3428 {
3429         if (ac_power)
3430                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3431                         0 : -EINVAL;
3432
3433         return 0;
3434 }
3435 #endif
3436
3437 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3438                                                       PPSMC_Msg msg, u32 parameter)
3439 {
3440         WREG32(SMC_SCRATCH0, parameter);
3441         return si_send_msg_to_smc(rdev, msg);
3442 }
3443
3444 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3445 {
3446         if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3447                 return -EINVAL;
3448
3449         return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3450                 0 : -EINVAL;
3451 }
3452
3453 int si_dpm_force_performance_level(struct radeon_device *rdev,
3454                                    enum radeon_dpm_forced_level level)
3455 {
3456         struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3457         struct ni_ps *ps = ni_get_ps(rps);
3458         u32 levels = ps->performance_level_count;
3459
3460         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3461                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3462                         return -EINVAL;
3463
3464                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3465                         return -EINVAL;
3466         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3467                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3468                         return -EINVAL;
3469
3470                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3471                         return -EINVAL;
3472         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3473                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3474                         return -EINVAL;
3475
3476                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3477                         return -EINVAL;
3478         }
3479
3480         rdev->pm.dpm.forced_level = level;
3481
3482         return 0;
3483 }
3484
3485 #if 0
3486 static int si_set_boot_state(struct radeon_device *rdev)
3487 {
3488         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3489                 0 : -EINVAL;
3490 }
3491 #endif
3492
3493 static int si_set_sw_state(struct radeon_device *rdev)
3494 {
3495         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3496                 0 : -EINVAL;
3497 }
3498
3499 static int si_halt_smc(struct radeon_device *rdev)
3500 {
3501         if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3502                 return -EINVAL;
3503
3504         return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3505                 0 : -EINVAL;
3506 }
3507
3508 static int si_resume_smc(struct radeon_device *rdev)
3509 {
3510         if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3511                 return -EINVAL;
3512
3513         return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3514                 0 : -EINVAL;
3515 }
3516
3517 static void si_dpm_start_smc(struct radeon_device *rdev)
3518 {
3519         si_program_jump_on_start(rdev);
3520         si_start_smc(rdev);
3521         si_start_smc_clock(rdev);
3522 }
3523
3524 static void si_dpm_stop_smc(struct radeon_device *rdev)
3525 {
3526         si_reset_smc(rdev);
3527         si_stop_smc_clock(rdev);
3528 }
3529
3530 static int si_process_firmware_header(struct radeon_device *rdev)
3531 {
3532         struct si_power_info *si_pi = si_get_pi(rdev);
3533         u32 tmp;
3534         int ret;
3535
3536         ret = si_read_smc_sram_dword(rdev,
3537                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3538                                      SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3539                                      &tmp, si_pi->sram_end);
3540         if (ret)
3541                 return ret;
3542
3543         si_pi->state_table_start = tmp;
3544
3545         ret = si_read_smc_sram_dword(rdev,
3546                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3547                                      SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3548                                      &tmp, si_pi->sram_end);
3549         if (ret)
3550                 return ret;
3551
3552         si_pi->soft_regs_start = tmp;
3553
3554         ret = si_read_smc_sram_dword(rdev,
3555                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3556                                      SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3557                                      &tmp, si_pi->sram_end);
3558         if (ret)
3559                 return ret;
3560
3561         si_pi->mc_reg_table_start = tmp;
3562
3563         ret = si_read_smc_sram_dword(rdev,
3564                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3565                                      SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3566                                      &tmp, si_pi->sram_end);
3567         if (ret)
3568                 return ret;
3569
3570         si_pi->fan_table_start = tmp;
3571
3572         ret = si_read_smc_sram_dword(rdev,
3573                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3574                                      SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3575                                      &tmp, si_pi->sram_end);
3576         if (ret)
3577                 return ret;
3578
3579         si_pi->arb_table_start = tmp;
3580
3581         ret = si_read_smc_sram_dword(rdev,
3582                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3583                                      SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3584                                      &tmp, si_pi->sram_end);
3585         if (ret)
3586                 return ret;
3587
3588         si_pi->cac_table_start = tmp;
3589
3590         ret = si_read_smc_sram_dword(rdev,
3591                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3592                                      SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3593                                      &tmp, si_pi->sram_end);
3594         if (ret)
3595                 return ret;
3596
3597         si_pi->dte_table_start = tmp;
3598
3599         ret = si_read_smc_sram_dword(rdev,
3600                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3601                                      SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3602                                      &tmp, si_pi->sram_end);
3603         if (ret)
3604                 return ret;
3605
3606         si_pi->spll_table_start = tmp;
3607
3608         ret = si_read_smc_sram_dword(rdev,
3609                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3610                                      SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3611                                      &tmp, si_pi->sram_end);
3612         if (ret)
3613                 return ret;
3614
3615         si_pi->papm_cfg_table_start = tmp;
3616
3617         return ret;
3618 }
3619
3620 static void si_read_clock_registers(struct radeon_device *rdev)
3621 {
3622         struct si_power_info *si_pi = si_get_pi(rdev);
3623
3624         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3625         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3626         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3627         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3628         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3629         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3630         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3631         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3632         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3633         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3634         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3635         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3636         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3637         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3638         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3639 }
3640
3641 static void si_enable_thermal_protection(struct radeon_device *rdev,
3642                                           bool enable)
3643 {
3644         if (enable)
3645                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3646         else
3647                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3648 }
3649
3650 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3651 {
3652         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3653 }
3654
3655 #if 0
3656 static int si_enter_ulp_state(struct radeon_device *rdev)
3657 {
3658         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3659
3660         udelay(25000);
3661
3662         return 0;
3663 }
3664
3665 static int si_exit_ulp_state(struct radeon_device *rdev)
3666 {
3667         int i;
3668
3669         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3670
3671         udelay(7000);
3672
3673         for (i = 0; i < rdev->usec_timeout; i++) {
3674                 if (RREG32(SMC_RESP_0) == 1)
3675                         break;
3676                 udelay(1000);
3677         }
3678
3679         return 0;
3680 }
3681 #endif
3682
3683 static int si_notify_smc_display_change(struct radeon_device *rdev,
3684                                      bool has_display)
3685 {
3686         PPSMC_Msg msg = has_display ?
3687                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3688
3689         return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3690                 0 : -EINVAL;
3691 }
3692
3693 static void si_program_response_times(struct radeon_device *rdev)
3694 {
3695         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3696         u32 vddc_dly, acpi_dly, vbi_dly;
3697         u32 reference_clock;
3698
3699         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3700
3701         voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3702         backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3703
3704         if (voltage_response_time == 0)
3705                 voltage_response_time = 1000;
3706
3707         acpi_delay_time = 15000;
3708         vbi_time_out = 100000;
3709
3710         reference_clock = radeon_get_xclk(rdev);
3711
3712         vddc_dly = (voltage_response_time  * reference_clock) / 100;
3713         acpi_dly = (acpi_delay_time * reference_clock) / 100;
3714         vbi_dly  = (vbi_time_out * reference_clock) / 100;
3715
3716         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
3717         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
3718         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3719         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3720 }
3721
3722 static void si_program_ds_registers(struct radeon_device *rdev)
3723 {
3724         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3725         u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3726
3727         if (eg_pi->sclk_deep_sleep) {
3728                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3729                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3730                          ~AUTOSCALE_ON_SS_CLEAR);
3731         }
3732 }
3733
3734 static void si_program_display_gap(struct radeon_device *rdev)
3735 {
3736         u32 tmp, pipe;
3737         int i;
3738
3739         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3740         if (rdev->pm.dpm.new_active_crtc_count > 0)
3741                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3742         else
3743                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3744
3745         if (rdev->pm.dpm.new_active_crtc_count > 1)
3746                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3747         else
3748                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3749
3750         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3751
3752         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3753         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3754
3755         if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3756             (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3757                 /* find the first active crtc */
3758                 for (i = 0; i < rdev->num_crtc; i++) {
3759                         if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3760                                 break;
3761                 }
3762                 if (i == rdev->num_crtc)
3763                         pipe = 0;
3764                 else
3765                         pipe = i;
3766
3767                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3768                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3769                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3770         }
3771
3772         /* Setting this to false forces the performance state to low if the crtcs are disabled.
3773          * This can be a problem on PowerXpress systems or if you want to use the card
3774          * for offscreen rendering or compute if there are no crtcs enabled.
3775          */
3776         si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3777 }
3778
3779 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3780 {
3781         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3782
3783         if (enable) {
3784                 if (pi->sclk_ss)
3785                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3786         } else {
3787                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3788                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3789         }
3790 }
3791
3792 static void si_setup_bsp(struct radeon_device *rdev)
3793 {
3794         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3795         u32 xclk = radeon_get_xclk(rdev);
3796
3797         r600_calculate_u_and_p(pi->asi,
3798                                xclk,
3799                                16,
3800                                &pi->bsp,
3801                                &pi->bsu);
3802
3803         r600_calculate_u_and_p(pi->pasi,
3804                                xclk,
3805                                16,
3806                                &pi->pbsp,
3807                                &pi->pbsu);
3808
3809
3810         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3811         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3812
3813         WREG32(CG_BSP, pi->dsp);
3814 }
3815
3816 static void si_program_git(struct radeon_device *rdev)
3817 {
3818         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3819 }
3820
3821 static void si_program_tp(struct radeon_device *rdev)
3822 {
3823         int i;
3824         enum r600_td td = R600_TD_DFLT;
3825
3826         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3827                 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3828
3829         if (td == R600_TD_AUTO)
3830                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3831         else
3832                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3833
3834         if (td == R600_TD_UP)
3835                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3836
3837         if (td == R600_TD_DOWN)
3838                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3839 }
3840
3841 static void si_program_tpp(struct radeon_device *rdev)
3842 {
3843         WREG32(CG_TPC, R600_TPC_DFLT);
3844 }
3845
3846 static void si_program_sstp(struct radeon_device *rdev)
3847 {
3848         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3849 }
3850
3851 static void si_enable_display_gap(struct radeon_device *rdev)
3852 {
3853         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3854
3855         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3856         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3857                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3858
3859         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3860         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3861                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3862         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3863 }
3864
3865 static void si_program_vc(struct radeon_device *rdev)
3866 {
3867         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3868
3869         WREG32(CG_FTV, pi->vrc);
3870 }
3871
3872 static void si_clear_vc(struct radeon_device *rdev)
3873 {
3874         WREG32(CG_FTV, 0);
3875 }
3876
3877 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3878 {
3879         u8 mc_para_index;
3880
3881         if (memory_clock < 10000)
3882                 mc_para_index = 0;
3883         else if (memory_clock >= 80000)
3884                 mc_para_index = 0x0f;
3885         else
3886                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3887         return mc_para_index;
3888 }
3889
3890 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3891 {
3892         u8 mc_para_index;
3893
3894         if (strobe_mode) {
3895                 if (memory_clock < 12500)
3896                         mc_para_index = 0x00;
3897                 else if (memory_clock > 47500)
3898                         mc_para_index = 0x0f;
3899                 else
3900                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
3901         } else {
3902                 if (memory_clock < 65000)
3903                         mc_para_index = 0x00;
3904                 else if (memory_clock > 135000)
3905                         mc_para_index = 0x0f;
3906                 else
3907                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
3908         }
3909         return mc_para_index;
3910 }
3911
3912 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3913 {
3914         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3915         bool strobe_mode = false;
3916         u8 result = 0;
3917
3918         if (mclk <= pi->mclk_strobe_mode_threshold)
3919                 strobe_mode = true;
3920
3921         if (pi->mem_gddr5)
3922                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3923         else
3924                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3925
3926         if (strobe_mode)
3927                 result |= SISLANDS_SMC_STROBE_ENABLE;
3928
3929         return result;
3930 }
3931
3932 static int si_upload_firmware(struct radeon_device *rdev)
3933 {
3934         struct si_power_info *si_pi = si_get_pi(rdev);
3935         int ret;
3936
3937         si_reset_smc(rdev);
3938         si_stop_smc_clock(rdev);
3939
3940         ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3941
3942         return ret;
3943 }
3944
3945 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3946                                               const struct atom_voltage_table *table,
3947                                               const struct radeon_phase_shedding_limits_table *limits)
3948 {
3949         u32 data, num_bits, num_levels;
3950
3951         if ((table == NULL) || (limits == NULL))
3952                 return false;
3953
3954         data = table->mask_low;
3955
3956         num_bits = hweight32(data);
3957
3958         if (num_bits == 0)
3959                 return false;
3960
3961         num_levels = (1 << num_bits);
3962
3963         if (table->count != num_levels)
3964                 return false;
3965
3966         if (limits->count != (num_levels - 1))
3967                 return false;
3968
3969         return true;
3970 }
3971
3972 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3973                                               u32 max_voltage_steps,
3974                                               struct atom_voltage_table *voltage_table)
3975 {
3976         unsigned int i, diff;
3977
3978         if (voltage_table->count <= max_voltage_steps)
3979                 return;
3980
3981         diff = voltage_table->count - max_voltage_steps;
3982
3983         for (i= 0; i < max_voltage_steps; i++)
3984                 voltage_table->entries[i] = voltage_table->entries[i + diff];
3985
3986         voltage_table->count = max_voltage_steps;
3987 }
3988
3989 static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3990                                      struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3991                                      struct atom_voltage_table *voltage_table)
3992 {
3993         u32 i;
3994
3995         if (voltage_dependency_table == NULL)
3996                 return -EINVAL;
3997
3998         voltage_table->mask_low = 0;
3999         voltage_table->phase_delay = 0;
4000
4001         voltage_table->count = voltage_dependency_table->count;
4002         for (i = 0; i < voltage_table->count; i++) {
4003                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4004                 voltage_table->entries[i].smio_low = 0;
4005         }
4006
4007         return 0;
4008 }
4009
4010 static int si_construct_voltage_tables(struct radeon_device *rdev)
4011 {
4012         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4013         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4014         struct si_power_info *si_pi = si_get_pi(rdev);
4015         int ret;
4016
4017         if (pi->voltage_control) {
4018                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4019                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4020                 if (ret)
4021                         return ret;
4022
4023                 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4024                         si_trim_voltage_table_to_fit_state_table(rdev,
4025                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4026                                                                  &eg_pi->vddc_voltage_table);
4027         } else if (si_pi->voltage_control_svi2) {
4028                 ret = si_get_svi2_voltage_table(rdev,
4029                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4030                                                 &eg_pi->vddc_voltage_table);
4031                 if (ret)
4032                         return ret;
4033         } else {
4034                 return -EINVAL;
4035         }
4036
4037         if (eg_pi->vddci_control) {
4038                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
4039                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4040                 if (ret)
4041                         return ret;
4042
4043                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4044                         si_trim_voltage_table_to_fit_state_table(rdev,
4045                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4046                                                                  &eg_pi->vddci_voltage_table);
4047         }
4048         if (si_pi->vddci_control_svi2) {
4049                 ret = si_get_svi2_voltage_table(rdev,
4050                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4051                                                 &eg_pi->vddci_voltage_table);
4052                 if (ret)
4053                         return ret;
4054         }
4055
4056         if (pi->mvdd_control) {
4057                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
4058                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4059
4060                 if (ret) {
4061                         pi->mvdd_control = false;
4062                         return ret;
4063                 }
4064
4065                 if (si_pi->mvdd_voltage_table.count == 0) {
4066                         pi->mvdd_control = false;
4067                         return -EINVAL;
4068                 }
4069
4070                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4071                         si_trim_voltage_table_to_fit_state_table(rdev,
4072                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4073                                                                  &si_pi->mvdd_voltage_table);
4074         }
4075
4076         if (si_pi->vddc_phase_shed_control) {
4077                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4078                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4079                 if (ret)
4080                         si_pi->vddc_phase_shed_control = false;
4081
4082                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4083                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4084                         si_pi->vddc_phase_shed_control = false;
4085         }
4086
4087         return 0;
4088 }
4089
4090 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
4091                                           const struct atom_voltage_table *voltage_table,
4092                                           SISLANDS_SMC_STATETABLE *table)
4093 {
4094         unsigned int i;
4095
4096         for (i = 0; i < voltage_table->count; i++)
4097                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4098 }
4099
4100 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
4101                                           SISLANDS_SMC_STATETABLE *table)
4102 {
4103         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4104         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4105         struct si_power_info *si_pi = si_get_pi(rdev);
4106         u8 i;
4107
4108         if (si_pi->voltage_control_svi2) {
4109                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4110                         si_pi->svc_gpio_id);
4111                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4112                         si_pi->svd_gpio_id);
4113                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4114                                            2);
4115         } else {
4116                 if (eg_pi->vddc_voltage_table.count) {
4117                         si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
4118                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4119                                 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4120
4121                         for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4122                                 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4123                                         table->maxVDDCIndexInPPTable = i;
4124                                         break;
4125                                 }
4126                         }
4127                 }
4128
4129                 if (eg_pi->vddci_voltage_table.count) {
4130                         si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4131
4132                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4133                                 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4134                 }
4135
4136
4137                 if (si_pi->mvdd_voltage_table.count) {
4138                         si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4139
4140                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4141                                 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4142                 }
4143
4144                 if (si_pi->vddc_phase_shed_control) {
4145                         if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4146                                                               &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4147                                 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4148
4149                                 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4150                                         cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4151
4152                                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4153                                                            (u32)si_pi->vddc_phase_shed_table.phase_delay);
4154                         } else {
4155                                 si_pi->vddc_phase_shed_control = false;
4156                         }
4157                 }
4158         }
4159
4160         return 0;
4161 }
4162
4163 static int si_populate_voltage_value(struct radeon_device *rdev,
4164                                      const struct atom_voltage_table *table,
4165                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4166 {
4167         unsigned int i;
4168
4169         for (i = 0; i < table->count; i++) {
4170                 if (value <= table->entries[i].value) {
4171                         voltage->index = (u8)i;
4172                         voltage->value = cpu_to_be16(table->entries[i].value);
4173                         break;
4174                 }
4175         }
4176
4177         if (i >= table->count)
4178                 return -EINVAL;
4179
4180         return 0;
4181 }
4182
4183 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4184                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4185 {
4186         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4187         struct si_power_info *si_pi = si_get_pi(rdev);
4188
4189         if (pi->mvdd_control) {
4190                 if (mclk <= pi->mvdd_split_frequency)
4191                         voltage->index = 0;
4192                 else
4193                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4194
4195                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4196         }
4197         return 0;
4198 }
4199
4200 static int si_get_std_voltage_value(struct radeon_device *rdev,
4201                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4202                                     u16 *std_voltage)
4203 {
4204         u16 v_index;
4205         bool voltage_found = false;
4206         *std_voltage = be16_to_cpu(voltage->value);
4207
4208         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4209                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4210                         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4211                                 return -EINVAL;
4212
4213                         for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4214                                 if (be16_to_cpu(voltage->value) ==
4215                                     (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4216                                         voltage_found = true;
4217                                         if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4218                                                 *std_voltage =
4219                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4220                                         else
4221                                                 *std_voltage =
4222                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4223                                         break;
4224                                 }
4225                         }
4226
4227                         if (!voltage_found) {
4228                                 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4229                                         if (be16_to_cpu(voltage->value) <=
4230                                             (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4231                                                 voltage_found = true;
4232                                                 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4233                                                         *std_voltage =
4234                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4235                                                 else
4236                                                         *std_voltage =
4237                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4238                                                 break;
4239                                         }
4240                                 }
4241                         }
4242                 } else {
4243                         if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4244                                 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4245                 }
4246         }
4247
4248         return 0;
4249 }
4250
4251 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4252                                          u16 value, u8 index,
4253                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4254 {
4255         voltage->index = index;
4256         voltage->value = cpu_to_be16(value);
4257
4258         return 0;
4259 }
4260
4261 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4262                                             const struct radeon_phase_shedding_limits_table *limits,
4263                                             u16 voltage, u32 sclk, u32 mclk,
4264                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4265 {
4266         unsigned int i;
4267
4268         for (i = 0; i < limits->count; i++) {
4269                 if ((voltage <= limits->entries[i].voltage) &&
4270                     (sclk <= limits->entries[i].sclk) &&
4271                     (mclk <= limits->entries[i].mclk))
4272                         break;
4273         }
4274
4275         smc_voltage->phase_settings = (u8)i;
4276
4277         return 0;
4278 }
4279
4280 static int si_init_arb_table_index(struct radeon_device *rdev)
4281 {
4282         struct si_power_info *si_pi = si_get_pi(rdev);
4283         u32 tmp;
4284         int ret;
4285
4286         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4287         if (ret)
4288                 return ret;
4289
4290         tmp &= 0x00FFFFFF;
4291         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4292
4293         return si_write_smc_sram_dword(rdev, si_pi->arb_table_start,  tmp, si_pi->sram_end);
4294 }
4295
4296 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4297 {
4298         return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4299 }
4300
4301 static int si_reset_to_default(struct radeon_device *rdev)
4302 {
4303         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4304                 0 : -EINVAL;
4305 }
4306
4307 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4308 {
4309         struct si_power_info *si_pi = si_get_pi(rdev);
4310         u32 tmp;
4311         int ret;
4312
4313         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4314                                      &tmp, si_pi->sram_end);
4315         if (ret)
4316                 return ret;
4317
4318         tmp = (tmp >> 24) & 0xff;
4319
4320         if (tmp == MC_CG_ARB_FREQ_F0)
4321                 return 0;
4322
4323         return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4324 }
4325
4326 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4327                                             u32 engine_clock)
4328 {
4329         u32 dram_rows;
4330         u32 dram_refresh_rate;
4331         u32 mc_arb_rfsh_rate;
4332         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4333
4334         if (tmp >= 4)
4335                 dram_rows = 16384;
4336         else
4337                 dram_rows = 1 << (tmp + 10);
4338
4339         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4340         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4341
4342         return mc_arb_rfsh_rate;
4343 }
4344
4345 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4346                                                 struct rv7xx_pl *pl,
4347                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4348 {
4349         u32 dram_timing;
4350         u32 dram_timing2;
4351         u32 burst_time;
4352
4353         arb_regs->mc_arb_rfsh_rate =
4354                 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4355
4356         radeon_atom_set_engine_dram_timings(rdev,
4357                                             pl->sclk,
4358                                             pl->mclk);
4359
4360         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4361         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4362         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4363
4364         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4365         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4366         arb_regs->mc_arb_burst_time = (u8)burst_time;
4367
4368         return 0;
4369 }
4370
4371 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4372                                                   struct radeon_ps *radeon_state,
4373                                                   unsigned int first_arb_set)
4374 {
4375         struct si_power_info *si_pi = si_get_pi(rdev);
4376         struct ni_ps *state = ni_get_ps(radeon_state);
4377         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4378         int i, ret = 0;
4379
4380         for (i = 0; i < state->performance_level_count; i++) {
4381                 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4382                 if (ret)
4383                         break;
4384                 ret = si_copy_bytes_to_smc(rdev,
4385                                            si_pi->arb_table_start +
4386                                            offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4387                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4388                                            (u8 *)&arb_regs,
4389                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4390                                            si_pi->sram_end);
4391                 if (ret)
4392                         break;
4393         }
4394
4395         return ret;
4396 }
4397
4398 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4399                                                struct radeon_ps *radeon_new_state)
4400 {
4401         return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4402                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4403 }
4404
4405 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4406                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4407 {
4408         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4409         struct si_power_info *si_pi = si_get_pi(rdev);
4410
4411         if (pi->mvdd_control)
4412                 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4413                                                  si_pi->mvdd_bootup_value, voltage);
4414
4415         return 0;
4416 }
4417
4418 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4419                                          struct radeon_ps *radeon_initial_state,
4420                                          SISLANDS_SMC_STATETABLE *table)
4421 {
4422         struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4423         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4424         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4425         struct si_power_info *si_pi = si_get_pi(rdev);
4426         u32 reg;
4427         int ret;
4428
4429         table->initialState.levels[0].mclk.vDLL_CNTL =
4430                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4431         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4432                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4433         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4434                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4435         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4436                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4437         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4438                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4439         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4440                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4441         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4442                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4443         table->initialState.levels[0].mclk.vMPLL_SS =
4444                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4445         table->initialState.levels[0].mclk.vMPLL_SS2 =
4446                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4447
4448         table->initialState.levels[0].mclk.mclk_value =
4449                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4450
4451         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4452                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4453         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4454                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4455         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4456                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4457         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4458                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4459         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4460                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4461         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4462                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4463
4464         table->initialState.levels[0].sclk.sclk_value =
4465                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4466
4467         table->initialState.levels[0].arbRefreshState =
4468                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4469
4470         table->initialState.levels[0].ACIndex = 0;
4471
4472         ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4473                                         initial_state->performance_levels[0].vddc,
4474                                         &table->initialState.levels[0].vddc);
4475
4476         if (!ret) {
4477                 u16 std_vddc;
4478
4479                 ret = si_get_std_voltage_value(rdev,
4480                                                &table->initialState.levels[0].vddc,
4481                                                &std_vddc);
4482                 if (!ret)
4483                         si_populate_std_voltage_value(rdev, std_vddc,
4484                                                       table->initialState.levels[0].vddc.index,
4485                                                       &table->initialState.levels[0].std_vddc);
4486         }
4487
4488         if (eg_pi->vddci_control)
4489                 si_populate_voltage_value(rdev,
4490                                           &eg_pi->vddci_voltage_table,
4491                                           initial_state->performance_levels[0].vddci,
4492                                           &table->initialState.levels[0].vddci);
4493
4494         if (si_pi->vddc_phase_shed_control)
4495                 si_populate_phase_shedding_value(rdev,
4496                                                  &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4497                                                  initial_state->performance_levels[0].vddc,
4498                                                  initial_state->performance_levels[0].sclk,
4499                                                  initial_state->performance_levels[0].mclk,
4500                                                  &table->initialState.levels[0].vddc);
4501
4502         si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4503
4504         reg = CG_R(0xffff) | CG_L(0);
4505         table->initialState.levels[0].aT = cpu_to_be32(reg);
4506
4507         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4508
4509         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4510
4511         if (pi->mem_gddr5) {
4512                 table->initialState.levels[0].strobeMode =
4513                         si_get_strobe_mode_settings(rdev,
4514                                                     initial_state->performance_levels[0].mclk);
4515
4516                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4517                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4518                 else
4519                         table->initialState.levels[0].mcFlags =  0;
4520         }
4521
4522         table->initialState.levelCount = 1;
4523
4524         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4525
4526         table->initialState.levels[0].dpm2.MaxPS = 0;
4527         table->initialState.levels[0].dpm2.NearTDPDec = 0;
4528         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4529         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4530         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4531
4532         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4533         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4534
4535         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4536         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4537
4538         return 0;
4539 }
4540
4541 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4542                                       SISLANDS_SMC_STATETABLE *table)
4543 {
4544         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4545         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4546         struct si_power_info *si_pi = si_get_pi(rdev);
4547         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4548         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4549         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4550         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4551         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4552         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4553         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4554         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4555         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4556         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4557         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4558         u32 reg;
4559         int ret;
4560
4561         table->ACPIState = table->initialState;
4562
4563         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4564
4565         if (pi->acpi_vddc) {
4566                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4567                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4568                 if (!ret) {
4569                         u16 std_vddc;
4570
4571                         ret = si_get_std_voltage_value(rdev,
4572                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4573                         if (!ret)
4574                                 si_populate_std_voltage_value(rdev, std_vddc,
4575                                                               table->ACPIState.levels[0].vddc.index,
4576                                                               &table->ACPIState.levels[0].std_vddc);
4577                 }
4578                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4579
4580                 if (si_pi->vddc_phase_shed_control) {
4581                         si_populate_phase_shedding_value(rdev,
4582                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4583                                                          pi->acpi_vddc,
4584                                                          0,
4585                                                          0,
4586                                                          &table->ACPIState.levels[0].vddc);
4587                 }
4588         } else {
4589                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4590                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4591                 if (!ret) {
4592                         u16 std_vddc;
4593
4594                         ret = si_get_std_voltage_value(rdev,
4595                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4596
4597                         if (!ret)
4598                                 si_populate_std_voltage_value(rdev, std_vddc,
4599                                                               table->ACPIState.levels[0].vddc.index,
4600                                                               &table->ACPIState.levels[0].std_vddc);
4601                 }
4602                 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4603                                                                                     si_pi->sys_pcie_mask,
4604                                                                                     si_pi->boot_pcie_gen,
4605                                                                                     RADEON_PCIE_GEN1);
4606
4607                 if (si_pi->vddc_phase_shed_control)
4608                         si_populate_phase_shedding_value(rdev,
4609                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4610                                                          pi->min_vddc_in_table,
4611                                                          0,
4612                                                          0,
4613                                                          &table->ACPIState.levels[0].vddc);
4614         }
4615
4616         if (pi->acpi_vddc) {
4617                 if (eg_pi->acpi_vddci)
4618                         si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4619                                                   eg_pi->acpi_vddci,
4620                                                   &table->ACPIState.levels[0].vddci);
4621         }
4622
4623         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4624         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4625
4626         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4627
4628         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4629         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4630
4631         table->ACPIState.levels[0].mclk.vDLL_CNTL =
4632                 cpu_to_be32(dll_cntl);
4633         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4634                 cpu_to_be32(mclk_pwrmgt_cntl);
4635         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4636                 cpu_to_be32(mpll_ad_func_cntl);
4637         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4638                 cpu_to_be32(mpll_dq_func_cntl);
4639         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4640                 cpu_to_be32(mpll_func_cntl);
4641         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4642                 cpu_to_be32(mpll_func_cntl_1);
4643         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4644                 cpu_to_be32(mpll_func_cntl_2);
4645         table->ACPIState.levels[0].mclk.vMPLL_SS =
4646                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4647         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4648                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4649
4650         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4651                 cpu_to_be32(spll_func_cntl);
4652         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4653                 cpu_to_be32(spll_func_cntl_2);
4654         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4655                 cpu_to_be32(spll_func_cntl_3);
4656         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4657                 cpu_to_be32(spll_func_cntl_4);
4658
4659         table->ACPIState.levels[0].mclk.mclk_value = 0;
4660         table->ACPIState.levels[0].sclk.sclk_value = 0;
4661
4662         si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4663
4664         if (eg_pi->dynamic_ac_timing)
4665                 table->ACPIState.levels[0].ACIndex = 0;
4666
4667         table->ACPIState.levels[0].dpm2.MaxPS = 0;
4668         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4669         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4670         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4671         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4672
4673         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4674         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4675
4676         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4677         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4678
4679         return 0;
4680 }
4681
4682 static int si_populate_ulv_state(struct radeon_device *rdev,
4683                                  SISLANDS_SMC_SWSTATE *state)
4684 {
4685         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4686         struct si_power_info *si_pi = si_get_pi(rdev);
4687         struct si_ulv_param *ulv = &si_pi->ulv;
4688         u32 sclk_in_sr = 1350; /* ??? */
4689         int ret;
4690
4691         ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4692                                             &state->levels[0]);
4693         if (!ret) {
4694                 if (eg_pi->sclk_deep_sleep) {
4695                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4696                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4697                         else
4698                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4699                 }
4700                 if (ulv->one_pcie_lane_in_ulv)
4701                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4702                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4703                 state->levels[0].ACIndex = 1;
4704                 state->levels[0].std_vddc = state->levels[0].vddc;
4705                 state->levelCount = 1;
4706
4707                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4708         }
4709
4710         return ret;
4711 }
4712
4713 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4714 {
4715         struct si_power_info *si_pi = si_get_pi(rdev);
4716         struct si_ulv_param *ulv = &si_pi->ulv;
4717         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4718         int ret;
4719
4720         ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4721                                                    &arb_regs);
4722         if (ret)
4723                 return ret;
4724
4725         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4726                                    ulv->volt_change_delay);
4727
4728         ret = si_copy_bytes_to_smc(rdev,
4729                                    si_pi->arb_table_start +
4730                                    offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4731                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4732                                    (u8 *)&arb_regs,
4733                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4734                                    si_pi->sram_end);
4735
4736         return ret;
4737 }
4738
4739 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4740 {
4741         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4742
4743         pi->mvdd_split_frequency = 30000;
4744 }
4745
4746 static int si_init_smc_table(struct radeon_device *rdev)
4747 {
4748         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4749         struct si_power_info *si_pi = si_get_pi(rdev);
4750         struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4751         const struct si_ulv_param *ulv = &si_pi->ulv;
4752         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
4753         int ret;
4754         u32 lane_width;
4755         u32 vr_hot_gpio;
4756
4757         si_populate_smc_voltage_tables(rdev, table);
4758
4759         switch (rdev->pm.int_thermal_type) {
4760         case THERMAL_TYPE_SI:
4761         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4762                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4763                 break;
4764         case THERMAL_TYPE_NONE:
4765                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4766                 break;
4767         default:
4768                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4769                 break;
4770         }
4771
4772         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4773                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4774
4775         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4776                 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4777                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4778         }
4779
4780         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4781                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4782
4783         if (pi->mem_gddr5)
4784                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4785
4786         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4787                 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4788
4789         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4790                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4791                 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4792                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4793                                            vr_hot_gpio);
4794         }
4795
4796         ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4797         if (ret)
4798                 return ret;
4799
4800         ret = si_populate_smc_acpi_state(rdev, table);
4801         if (ret)
4802                 return ret;
4803
4804         table->driverState = table->initialState;
4805
4806         ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4807                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
4808         if (ret)
4809                 return ret;
4810
4811         if (ulv->supported && ulv->pl.vddc) {
4812                 ret = si_populate_ulv_state(rdev, &table->ULVState);
4813                 if (ret)
4814                         return ret;
4815
4816                 ret = si_program_ulv_memory_timing_parameters(rdev);
4817                 if (ret)
4818                         return ret;
4819
4820                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4821                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4822
4823                 lane_width = radeon_get_pcie_lanes(rdev);
4824                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4825         } else {
4826                 table->ULVState = table->initialState;
4827         }
4828
4829         return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4830                                     (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4831                                     si_pi->sram_end);
4832 }
4833
4834 static int si_calculate_sclk_params(struct radeon_device *rdev,
4835                                     u32 engine_clock,
4836                                     SISLANDS_SMC_SCLK_VALUE *sclk)
4837 {
4838         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4839         struct si_power_info *si_pi = si_get_pi(rdev);
4840         struct atom_clock_dividers dividers;
4841         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4842         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4843         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4844         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4845         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4846         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4847         u64 tmp;
4848         u32 reference_clock = rdev->clock.spll.reference_freq;
4849         u32 reference_divider;
4850         u32 fbdiv;
4851         int ret;
4852
4853         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4854                                              engine_clock, false, &dividers);
4855         if (ret)
4856                 return ret;
4857
4858         reference_divider = 1 + dividers.ref_div;
4859
4860         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4861         do_div(tmp, reference_clock);
4862         fbdiv = (u32) tmp;
4863
4864         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4865         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4866         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4867
4868         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4869         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4870
4871         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4872         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4873         spll_func_cntl_3 |= SPLL_DITHEN;
4874
4875         if (pi->sclk_ss) {
4876                 struct radeon_atom_ss ss;
4877                 u32 vco_freq = engine_clock * dividers.post_div;
4878
4879                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4880                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4881                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4882                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4883
4884                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
4885                         cg_spll_spread_spectrum |= CLK_S(clk_s);
4886                         cg_spll_spread_spectrum |= SSEN;
4887
4888                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4889                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4890                 }
4891         }
4892
4893         sclk->sclk_value = engine_clock;
4894         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4895         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4896         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4897         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4898         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4899         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4900
4901         return 0;
4902 }
4903
4904 static int si_populate_sclk_value(struct radeon_device *rdev,
4905                                   u32 engine_clock,
4906                                   SISLANDS_SMC_SCLK_VALUE *sclk)
4907 {
4908         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4909         int ret;
4910
4911         ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4912         if (!ret) {
4913                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4914                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4915                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4916                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4917                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4918                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4919                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4920         }
4921
4922         return ret;
4923 }
4924
4925 static int si_populate_mclk_value(struct radeon_device *rdev,
4926                                   u32 engine_clock,
4927                                   u32 memory_clock,
4928                                   SISLANDS_SMC_MCLK_VALUE *mclk,
4929                                   bool strobe_mode,
4930                                   bool dll_state_on)
4931 {
4932         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4933         struct si_power_info *si_pi = si_get_pi(rdev);
4934         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
4935         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4936         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4937         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4938         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4939         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4940         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4941         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4942         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4943         struct atom_mpll_param mpll_param;
4944         int ret;
4945
4946         ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4947         if (ret)
4948                 return ret;
4949
4950         mpll_func_cntl &= ~BWCTRL_MASK;
4951         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4952
4953         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4954         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4955                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4956
4957         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4958         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4959
4960         if (pi->mem_gddr5) {
4961                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4962                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4963                         YCLK_POST_DIV(mpll_param.post_div);
4964         }
4965
4966         if (pi->mclk_ss) {
4967                 struct radeon_atom_ss ss;
4968                 u32 freq_nom;
4969                 u32 tmp;
4970                 u32 reference_clock = rdev->clock.mpll.reference_freq;
4971
4972                 if (pi->mem_gddr5)
4973                         freq_nom = memory_clock * 4;
4974                 else
4975                         freq_nom = memory_clock * 2;
4976
4977                 tmp = freq_nom / reference_clock;
4978                 tmp = tmp * tmp;
4979                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4980                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4981                         u32 clks = reference_clock * 5 / ss.rate;
4982                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4983
4984                         mpll_ss1 &= ~CLKV_MASK;
4985                         mpll_ss1 |= CLKV(clkv);
4986
4987                         mpll_ss2 &= ~CLKS_MASK;
4988                         mpll_ss2 |= CLKS(clks);
4989                 }
4990         }
4991
4992         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4993         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4994
4995         if (dll_state_on)
4996                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4997         else
4998                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4999
5000         mclk->mclk_value = cpu_to_be32(memory_clock);
5001         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5002         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5003         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5004         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5005         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5006         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5007         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5008         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5009         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5010
5011         return 0;
5012 }
5013
5014 static void si_populate_smc_sp(struct radeon_device *rdev,
5015                                struct radeon_ps *radeon_state,
5016                                SISLANDS_SMC_SWSTATE *smc_state)
5017 {
5018         struct ni_ps *ps = ni_get_ps(radeon_state);
5019         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5020         int i;
5021
5022         for (i = 0; i < ps->performance_level_count - 1; i++)
5023                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5024
5025         smc_state->levels[ps->performance_level_count - 1].bSP =
5026                 cpu_to_be32(pi->psp);
5027 }
5028
5029 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
5030                                          struct rv7xx_pl *pl,
5031                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5032 {
5033         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5034         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5035         struct si_power_info *si_pi = si_get_pi(rdev);
5036         int ret;
5037         bool dll_state_on;
5038         u16 std_vddc;
5039         bool gmc_pg = false;
5040
5041         if (eg_pi->pcie_performance_request &&
5042             (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
5043                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5044         else
5045                 level->gen2PCIE = (u8)pl->pcie_gen;
5046
5047         ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
5048         if (ret)
5049                 return ret;
5050
5051         level->mcFlags =  0;
5052
5053         if (pi->mclk_stutter_mode_threshold &&
5054             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5055             !eg_pi->uvd_enabled &&
5056             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5057             (rdev->pm.dpm.new_active_crtc_count <= 2)) {
5058                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5059
5060                 if (gmc_pg)
5061                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5062         }
5063
5064         if (pi->mem_gddr5) {
5065                 if (pl->mclk > pi->mclk_edc_enable_threshold)
5066                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5067
5068                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5069                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5070
5071                 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
5072
5073                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5074                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5075                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5076                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5077                         else
5078                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5079                 } else {
5080                         dll_state_on = false;
5081                 }
5082         } else {
5083                 level->strobeMode = si_get_strobe_mode_settings(rdev,
5084                                                                 pl->mclk);
5085
5086                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5087         }
5088
5089         ret = si_populate_mclk_value(rdev,
5090                                      pl->sclk,
5091                                      pl->mclk,
5092                                      &level->mclk,
5093                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5094         if (ret)
5095                 return ret;
5096
5097         ret = si_populate_voltage_value(rdev,
5098                                         &eg_pi->vddc_voltage_table,
5099                                         pl->vddc, &level->vddc);
5100         if (ret)
5101                 return ret;
5102
5103
5104         ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
5105         if (ret)
5106                 return ret;
5107
5108         ret = si_populate_std_voltage_value(rdev, std_vddc,
5109                                             level->vddc.index, &level->std_vddc);
5110         if (ret)
5111                 return ret;
5112
5113         if (eg_pi->vddci_control) {
5114                 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
5115                                                 pl->vddci, &level->vddci);
5116                 if (ret)
5117                         return ret;
5118         }
5119
5120         if (si_pi->vddc_phase_shed_control) {
5121                 ret = si_populate_phase_shedding_value(rdev,
5122                                                        &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5123                                                        pl->vddc,
5124                                                        pl->sclk,
5125                                                        pl->mclk,
5126                                                        &level->vddc);
5127                 if (ret)
5128                         return ret;
5129         }
5130
5131         level->MaxPoweredUpCU = si_pi->max_cu;
5132
5133         ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5134
5135         return ret;
5136 }
5137
5138 static int si_populate_smc_t(struct radeon_device *rdev,
5139                              struct radeon_ps *radeon_state,
5140                              SISLANDS_SMC_SWSTATE *smc_state)
5141 {
5142         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5143         struct ni_ps *state = ni_get_ps(radeon_state);
5144         u32 a_t;
5145         u32 t_l, t_h;
5146         u32 high_bsp;
5147         int i, ret;
5148
5149         if (state->performance_level_count >= 9)
5150                 return -EINVAL;
5151
5152         if (state->performance_level_count < 2) {
5153                 a_t = CG_R(0xffff) | CG_L(0);
5154                 smc_state->levels[0].aT = cpu_to_be32(a_t);
5155                 return 0;
5156         }
5157
5158         smc_state->levels[0].aT = cpu_to_be32(0);
5159
5160         for (i = 0; i <= state->performance_level_count - 2; i++) {
5161                 ret = r600_calculate_at(
5162                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5163                         100 * R600_AH_DFLT,
5164                         state->performance_levels[i + 1].sclk,
5165                         state->performance_levels[i].sclk,
5166                         &t_l,
5167                         &t_h);
5168
5169                 if (ret) {
5170                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5171                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5172                 }
5173
5174                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5175                 a_t |= CG_R(t_l * pi->bsp / 20000);
5176                 smc_state->levels[i].aT = cpu_to_be32(a_t);
5177
5178                 high_bsp = (i == state->performance_level_count - 2) ?
5179                         pi->pbsp : pi->bsp;
5180                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5181                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5182         }
5183
5184         return 0;
5185 }
5186
5187 static int si_disable_ulv(struct radeon_device *rdev)
5188 {
5189         struct si_power_info *si_pi = si_get_pi(rdev);
5190         struct si_ulv_param *ulv = &si_pi->ulv;
5191
5192         if (ulv->supported)
5193                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5194                         0 : -EINVAL;
5195
5196         return 0;
5197 }
5198
5199 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5200                                        struct radeon_ps *radeon_state)
5201 {
5202         const struct si_power_info *si_pi = si_get_pi(rdev);
5203         const struct si_ulv_param *ulv = &si_pi->ulv;
5204         const struct ni_ps *state = ni_get_ps(radeon_state);
5205         int i;
5206
5207         if (state->performance_levels[0].mclk != ulv->pl.mclk)
5208                 return false;
5209
5210         /* XXX validate against display requirements! */
5211
5212         for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5213                 if (rdev->clock.current_dispclk <=
5214                     rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5215                         if (ulv->pl.vddc <
5216                             rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5217                                 return false;
5218                 }
5219         }
5220
5221         if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5222                 return false;
5223
5224         return true;
5225 }
5226
5227 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5228                                                        struct radeon_ps *radeon_new_state)
5229 {
5230         const struct si_power_info *si_pi = si_get_pi(rdev);
5231         const struct si_ulv_param *ulv = &si_pi->ulv;
5232
5233         if (ulv->supported) {
5234                 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5235                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5236                                 0 : -EINVAL;
5237         }
5238         return 0;
5239 }
5240
5241 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5242                                          struct radeon_ps *radeon_state,
5243                                          SISLANDS_SMC_SWSTATE *smc_state)
5244 {
5245         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5246         struct ni_power_info *ni_pi = ni_get_pi(rdev);
5247         struct si_power_info *si_pi = si_get_pi(rdev);
5248         struct ni_ps *state = ni_get_ps(radeon_state);
5249         int i, ret;
5250         u32 threshold;
5251         u32 sclk_in_sr = 1350; /* ??? */
5252
5253         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5254                 return -EINVAL;
5255
5256         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5257
5258         if (radeon_state->vclk && radeon_state->dclk) {
5259                 eg_pi->uvd_enabled = true;
5260                 if (eg_pi->smu_uvd_hs)
5261                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5262         } else {
5263                 eg_pi->uvd_enabled = false;
5264         }
5265
5266         if (state->dc_compatible)
5267                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5268
5269         smc_state->levelCount = 0;
5270         for (i = 0; i < state->performance_level_count; i++) {
5271                 if (eg_pi->sclk_deep_sleep) {
5272                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5273                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5274                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5275                                 else
5276                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5277                         }
5278                 }
5279
5280                 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5281                                                     &smc_state->levels[i]);
5282                 smc_state->levels[i].arbRefreshState =
5283                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5284
5285                 if (ret)
5286                         return ret;
5287
5288                 if (ni_pi->enable_power_containment)
5289                         smc_state->levels[i].displayWatermark =
5290                                 (state->performance_levels[i].sclk < threshold) ?
5291                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5292                 else
5293                         smc_state->levels[i].displayWatermark = (i < 2) ?
5294                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5295
5296                 if (eg_pi->dynamic_ac_timing)
5297                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5298                 else
5299                         smc_state->levels[i].ACIndex = 0;
5300
5301                 smc_state->levelCount++;
5302         }
5303
5304         si_write_smc_soft_register(rdev,
5305                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5306                                    threshold / 512);
5307
5308         si_populate_smc_sp(rdev, radeon_state, smc_state);
5309
5310         ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5311         if (ret)
5312                 ni_pi->enable_power_containment = false;
5313
5314         ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5315         if (ret)
5316                 ni_pi->enable_sq_ramping = false;
5317
5318         return si_populate_smc_t(rdev, radeon_state, smc_state);
5319 }
5320
5321 static int si_upload_sw_state(struct radeon_device *rdev,
5322                               struct radeon_ps *radeon_new_state)
5323 {
5324         struct si_power_info *si_pi = si_get_pi(rdev);
5325         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5326         int ret;
5327         u32 address = si_pi->state_table_start +
5328                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5329         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5330                 ((new_state->performance_level_count - 1) *
5331                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5332         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5333
5334         memset(smc_state, 0, state_size);
5335
5336         ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5337         if (ret)
5338                 return ret;
5339
5340         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5341                                    state_size, si_pi->sram_end);
5342
5343         return ret;
5344 }
5345
5346 static int si_upload_ulv_state(struct radeon_device *rdev)
5347 {
5348         struct si_power_info *si_pi = si_get_pi(rdev);
5349         struct si_ulv_param *ulv = &si_pi->ulv;
5350         int ret = 0;
5351
5352         if (ulv->supported && ulv->pl.vddc) {
5353                 u32 address = si_pi->state_table_start +
5354                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5355                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5356                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5357
5358                 memset(smc_state, 0, state_size);
5359
5360                 ret = si_populate_ulv_state(rdev, smc_state);
5361                 if (!ret)
5362                         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5363                                                    state_size, si_pi->sram_end);
5364         }
5365
5366         return ret;
5367 }
5368
5369 static int si_upload_smc_data(struct radeon_device *rdev)
5370 {
5371         struct radeon_crtc *radeon_crtc = NULL;
5372         int i;
5373
5374         if (rdev->pm.dpm.new_active_crtc_count == 0)
5375                 return 0;
5376
5377         for (i = 0; i < rdev->num_crtc; i++) {
5378                 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5379                         radeon_crtc = rdev->mode_info.crtcs[i];
5380                         break;
5381                 }
5382         }
5383
5384         if (radeon_crtc == NULL)
5385                 return 0;
5386
5387         if (radeon_crtc->line_time <= 0)
5388                 return 0;
5389
5390         if (si_write_smc_soft_register(rdev,
5391                                        SI_SMC_SOFT_REGISTER_crtc_index,
5392                                        radeon_crtc->crtc_id) != PPSMC_Result_OK)
5393                 return 0;
5394
5395         if (si_write_smc_soft_register(rdev,
5396                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5397                                        radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5398                 return 0;
5399
5400         if (si_write_smc_soft_register(rdev,
5401                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5402                                        radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5403                 return 0;
5404
5405         return 0;
5406 }
5407
5408 static int si_set_mc_special_registers(struct radeon_device *rdev,
5409                                        struct si_mc_reg_table *table)
5410 {
5411         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5412         u8 i, j, k;
5413         u32 temp_reg;
5414
5415         for (i = 0, j = table->last; i < table->last; i++) {
5416                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5417                         return -EINVAL;
5418                 switch (table->mc_reg_address[i].s1 << 2) {
5419                 case MC_SEQ_MISC1:
5420                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5421                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5422                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5423                         for (k = 0; k < table->num_entries; k++)
5424                                 table->mc_reg_table_entry[k].mc_data[j] =
5425                                         ((temp_reg & 0xffff0000)) |
5426                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5427                         j++;
5428                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5429                                 return -EINVAL;
5430
5431                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5432                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5433                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5434                         for (k = 0; k < table->num_entries; k++) {
5435                                 table->mc_reg_table_entry[k].mc_data[j] =
5436                                         (temp_reg & 0xffff0000) |
5437                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5438                                 if (!pi->mem_gddr5)
5439                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5440                         }
5441                         j++;
5442                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5443                                 return -EINVAL;
5444
5445                         if (!pi->mem_gddr5) {
5446                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5447                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5448                                 for (k = 0; k < table->num_entries; k++)
5449                                         table->mc_reg_table_entry[k].mc_data[j] =
5450                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5451                                 j++;
5452                                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5453                                         return -EINVAL;
5454                         }
5455                         break;
5456                 case MC_SEQ_RESERVE_M:
5457                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5458                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5459                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5460                         for(k = 0; k < table->num_entries; k++)
5461                                 table->mc_reg_table_entry[k].mc_data[j] =
5462                                         (temp_reg & 0xffff0000) |
5463                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5464                         j++;
5465                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5466                                 return -EINVAL;
5467                         break;
5468                 default:
5469                         break;
5470                 }
5471         }
5472
5473         table->last = j;
5474
5475         return 0;
5476 }
5477
5478 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5479 {
5480         bool result = true;
5481
5482         switch (in_reg) {
5483         case  MC_SEQ_RAS_TIMING >> 2:
5484                 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5485                 break;
5486         case MC_SEQ_CAS_TIMING >> 2:
5487                 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5488                 break;
5489         case MC_SEQ_MISC_TIMING >> 2:
5490                 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5491                 break;
5492         case MC_SEQ_MISC_TIMING2 >> 2:
5493                 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5494                 break;
5495         case MC_SEQ_RD_CTL_D0 >> 2:
5496                 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5497                 break;
5498         case MC_SEQ_RD_CTL_D1 >> 2:
5499                 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5500                 break;
5501         case MC_SEQ_WR_CTL_D0 >> 2:
5502                 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5503                 break;
5504         case MC_SEQ_WR_CTL_D1 >> 2:
5505                 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5506                 break;
5507         case MC_PMG_CMD_EMRS >> 2:
5508                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5509                 break;
5510         case MC_PMG_CMD_MRS >> 2:
5511                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5512                 break;
5513         case MC_PMG_CMD_MRS1 >> 2:
5514                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5515                 break;
5516         case MC_SEQ_PMG_TIMING >> 2:
5517                 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5518                 break;
5519         case MC_PMG_CMD_MRS2 >> 2:
5520                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5521                 break;
5522         case MC_SEQ_WR_CTL_2 >> 2:
5523                 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5524                 break;
5525         default:
5526                 result = false;
5527                 break;
5528         }
5529
5530         return result;
5531 }
5532
5533 static void si_set_valid_flag(struct si_mc_reg_table *table)
5534 {
5535         u8 i, j;
5536
5537         for (i = 0; i < table->last; i++) {
5538                 for (j = 1; j < table->num_entries; j++) {
5539                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5540                                 table->valid_flag |= 1 << i;
5541                                 break;
5542                         }
5543                 }
5544         }
5545 }
5546
5547 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5548 {
5549         u32 i;
5550         u16 address;
5551
5552         for (i = 0; i < table->last; i++)
5553                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5554                         address : table->mc_reg_address[i].s1;
5555
5556 }
5557
5558 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5559                                       struct si_mc_reg_table *si_table)
5560 {
5561         u8 i, j;
5562
5563         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5564                 return -EINVAL;
5565         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5566                 return -EINVAL;
5567
5568         for (i = 0; i < table->last; i++)
5569                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5570         si_table->last = table->last;
5571
5572         for (i = 0; i < table->num_entries; i++) {
5573                 si_table->mc_reg_table_entry[i].mclk_max =
5574                         table->mc_reg_table_entry[i].mclk_max;
5575                 for (j = 0; j < table->last; j++) {
5576                         si_table->mc_reg_table_entry[i].mc_data[j] =
5577                                 table->mc_reg_table_entry[i].mc_data[j];
5578                 }
5579         }
5580         si_table->num_entries = table->num_entries;
5581
5582         return 0;
5583 }
5584
5585 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5586 {
5587         struct si_power_info *si_pi = si_get_pi(rdev);
5588         struct atom_mc_reg_table *table;
5589         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5590         u8 module_index = rv770_get_memory_module_index(rdev);
5591         int ret;
5592
5593         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5594         if (!table)
5595                 return -ENOMEM;
5596
5597         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5598         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5599         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5600         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5601         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5602         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5603         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5604         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5605         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5606         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5607         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5608         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5609         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5610         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5611
5612         ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5613         if (ret)
5614                 goto init_mc_done;
5615
5616         ret = si_copy_vbios_mc_reg_table(table, si_table);
5617         if (ret)
5618                 goto init_mc_done;
5619
5620         si_set_s0_mc_reg_index(si_table);
5621
5622         ret = si_set_mc_special_registers(rdev, si_table);
5623         if (ret)
5624                 goto init_mc_done;
5625
5626         si_set_valid_flag(si_table);
5627
5628 init_mc_done:
5629         kfree(table);
5630
5631         return ret;
5632
5633 }
5634
5635 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5636                                          SMC_SIslands_MCRegisters *mc_reg_table)
5637 {
5638         struct si_power_info *si_pi = si_get_pi(rdev);
5639         u32 i, j;
5640
5641         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5642                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5643                         if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5644                                 break;
5645                         mc_reg_table->address[i].s0 =
5646                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5647                         mc_reg_table->address[i].s1 =
5648                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5649                         i++;
5650                 }
5651         }
5652         mc_reg_table->last = (u8)i;
5653 }
5654
5655 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5656                                     SMC_SIslands_MCRegisterSet *data,
5657                                     u32 num_entries, u32 valid_flag)
5658 {
5659         u32 i, j;
5660
5661         for(i = 0, j = 0; j < num_entries; j++) {
5662                 if (valid_flag & (1 << j)) {
5663                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
5664                         i++;
5665                 }
5666         }
5667 }
5668
5669 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5670                                                  struct rv7xx_pl *pl,
5671                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5672 {
5673         struct si_power_info *si_pi = si_get_pi(rdev);
5674         u32 i = 0;
5675
5676         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5677                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5678                         break;
5679         }
5680
5681         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5682                 --i;
5683
5684         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5685                                 mc_reg_table_data, si_pi->mc_reg_table.last,
5686                                 si_pi->mc_reg_table.valid_flag);
5687 }
5688
5689 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5690                                            struct radeon_ps *radeon_state,
5691                                            SMC_SIslands_MCRegisters *mc_reg_table)
5692 {
5693         struct ni_ps *state = ni_get_ps(radeon_state);
5694         int i;
5695
5696         for (i = 0; i < state->performance_level_count; i++) {
5697                 si_convert_mc_reg_table_entry_to_smc(rdev,
5698                                                      &state->performance_levels[i],
5699                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5700         }
5701 }
5702
5703 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5704                                     struct radeon_ps *radeon_boot_state)
5705 {
5706         struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5707         struct si_power_info *si_pi = si_get_pi(rdev);
5708         struct si_ulv_param *ulv = &si_pi->ulv;
5709         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5710
5711         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5712
5713         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5714
5715         si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5716
5717         si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5718                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5719
5720         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5721                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5722                                 si_pi->mc_reg_table.last,
5723                                 si_pi->mc_reg_table.valid_flag);
5724
5725         if (ulv->supported && ulv->pl.vddc != 0)
5726                 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5727                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5728         else
5729                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5730                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5731                                         si_pi->mc_reg_table.last,
5732                                         si_pi->mc_reg_table.valid_flag);
5733
5734         si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5735
5736         return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5737                                     (u8 *)smc_mc_reg_table,
5738                                     sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5739 }
5740
5741 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5742                                   struct radeon_ps *radeon_new_state)
5743 {
5744         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5745         struct si_power_info *si_pi = si_get_pi(rdev);
5746         u32 address = si_pi->mc_reg_table_start +
5747                 offsetof(SMC_SIslands_MCRegisters,
5748                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5749         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5750
5751         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5752
5753         si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5754
5755
5756         return si_copy_bytes_to_smc(rdev, address,
5757                                     (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5758                                     sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5759                                     si_pi->sram_end);
5760
5761 }
5762
5763 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5764 {
5765         if (enable)
5766                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5767         else
5768                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5769 }
5770
5771 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5772                                                       struct radeon_ps *radeon_state)
5773 {
5774         struct ni_ps *state = ni_get_ps(radeon_state);
5775         int i;
5776         u16 pcie_speed, max_speed = 0;
5777
5778         for (i = 0; i < state->performance_level_count; i++) {
5779                 pcie_speed = state->performance_levels[i].pcie_gen;
5780                 if (max_speed < pcie_speed)
5781                         max_speed = pcie_speed;
5782         }
5783         return max_speed;
5784 }
5785
5786 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5787 {
5788         u32 speed_cntl;
5789
5790         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5791         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5792
5793         return (u16)speed_cntl;
5794 }
5795
5796 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5797                                                              struct radeon_ps *radeon_new_state,
5798                                                              struct radeon_ps *radeon_current_state)
5799 {
5800         struct si_power_info *si_pi = si_get_pi(rdev);
5801         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5802         enum radeon_pcie_gen current_link_speed;
5803
5804         if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5805                 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5806         else
5807                 current_link_speed = si_pi->force_pcie_gen;
5808
5809         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5810         si_pi->pspp_notify_required = false;
5811         if (target_link_speed > current_link_speed) {
5812                 switch (target_link_speed) {
5813 #if defined(CONFIG_ACPI)
5814                 case RADEON_PCIE_GEN3:
5815                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5816                                 break;
5817                         si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5818                         if (current_link_speed == RADEON_PCIE_GEN2)
5819                                 break;
5820                 case RADEON_PCIE_GEN2:
5821                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5822                                 break;
5823 #endif
5824                 default:
5825                         si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5826                         break;
5827                 }
5828         } else {
5829                 if (target_link_speed < current_link_speed)
5830                         si_pi->pspp_notify_required = true;
5831         }
5832 }
5833
5834 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5835                                                            struct radeon_ps *radeon_new_state,
5836                                                            struct radeon_ps *radeon_current_state)
5837 {
5838         struct si_power_info *si_pi = si_get_pi(rdev);
5839         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5840         u8 request;
5841
5842         if (si_pi->pspp_notify_required) {
5843                 if (target_link_speed == RADEON_PCIE_GEN3)
5844                         request = PCIE_PERF_REQ_PECI_GEN3;
5845                 else if (target_link_speed == RADEON_PCIE_GEN2)
5846                         request = PCIE_PERF_REQ_PECI_GEN2;
5847                 else
5848                         request = PCIE_PERF_REQ_PECI_GEN1;
5849
5850                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5851                     (si_get_current_pcie_speed(rdev) > 0))
5852                         return;
5853
5854 #if defined(CONFIG_ACPI)
5855                 radeon_acpi_pcie_performance_request(rdev, request, false);
5856 #endif
5857         }
5858 }
5859
5860 #if 0
5861 static int si_ds_request(struct radeon_device *rdev,
5862                          bool ds_status_on, u32 count_write)
5863 {
5864         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5865
5866         if (eg_pi->sclk_deep_sleep) {
5867                 if (ds_status_on)
5868                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5869                                 PPSMC_Result_OK) ?
5870                                 0 : -EINVAL;
5871                 else
5872                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5873                                 PPSMC_Result_OK) ? 0 : -EINVAL;
5874         }
5875         return 0;
5876 }
5877 #endif
5878
5879 static void si_set_max_cu_value(struct radeon_device *rdev)
5880 {
5881         struct si_power_info *si_pi = si_get_pi(rdev);
5882
5883         if (rdev->family == CHIP_VERDE) {
5884                 switch (rdev->pdev->device) {
5885                 case 0x6820:
5886                 case 0x6825:
5887                 case 0x6821:
5888                 case 0x6823:
5889                 case 0x6827:
5890                         si_pi->max_cu = 10;
5891                         break;
5892                 case 0x682D:
5893                 case 0x6824:
5894                 case 0x682F:
5895                 case 0x6826:
5896                         si_pi->max_cu = 8;
5897                         break;
5898                 case 0x6828:
5899                 case 0x6830:
5900                 case 0x6831:
5901                 case 0x6838:
5902                 case 0x6839:
5903                 case 0x683D:
5904                         si_pi->max_cu = 10;
5905                         break;
5906                 case 0x683B:
5907                 case 0x683F:
5908                 case 0x6829:
5909                         si_pi->max_cu = 8;
5910                         break;
5911                 default:
5912                         si_pi->max_cu = 0;
5913                         break;
5914                 }
5915         } else {
5916                 si_pi->max_cu = 0;
5917         }
5918 }
5919
5920 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5921                                                              struct radeon_clock_voltage_dependency_table *table)
5922 {
5923         u32 i;
5924         int j;
5925         u16 leakage_voltage;
5926
5927         if (table) {
5928                 for (i = 0; i < table->count; i++) {
5929                         switch (si_get_leakage_voltage_from_leakage_index(rdev,
5930                                                                           table->entries[i].v,
5931                                                                           &leakage_voltage)) {
5932                         case 0:
5933                                 table->entries[i].v = leakage_voltage;
5934                                 break;
5935                         case -EAGAIN:
5936                                 return -EINVAL;
5937                         case -EINVAL:
5938                         default:
5939                                 break;
5940                         }
5941                 }
5942
5943                 for (j = (table->count - 2); j >= 0; j--) {
5944                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5945                                 table->entries[j].v : table->entries[j + 1].v;
5946                 }
5947         }
5948         return 0;
5949 }
5950
5951 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5952 {
5953         int ret = 0;
5954
5955         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5956                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5957         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5958                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5959         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5960                                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5961         return ret;
5962 }
5963
5964 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5965                                           struct radeon_ps *radeon_new_state,
5966                                           struct radeon_ps *radeon_current_state)
5967 {
5968         u32 lane_width;
5969         u32 new_lane_width =
5970                 ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
5971         u32 current_lane_width =
5972                 ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
5973
5974         if (new_lane_width != current_lane_width) {
5975                 radeon_set_pcie_lanes(rdev, new_lane_width);
5976                 lane_width = radeon_get_pcie_lanes(rdev);
5977                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5978         }
5979 }
5980
5981 static void si_set_vce_clock(struct radeon_device *rdev,
5982                              struct radeon_ps *new_rps,
5983                              struct radeon_ps *old_rps)
5984 {
5985         if ((old_rps->evclk != new_rps->evclk) ||
5986             (old_rps->ecclk != new_rps->ecclk)) {
5987                 /* turn the clocks on when encoding, off otherwise */
5988                 if (new_rps->evclk || new_rps->ecclk)
5989                         vce_v1_0_enable_mgcg(rdev, false);
5990                 else
5991                         vce_v1_0_enable_mgcg(rdev, true);
5992                 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk);
5993         }
5994 }
5995
5996 void si_dpm_setup_asic(struct radeon_device *rdev)
5997 {
5998         int r;
5999
6000         r = si_mc_load_microcode(rdev);
6001         if (r)
6002                 DRM_ERROR("Failed to load MC firmware!\n");
6003         rv770_get_memory_type(rdev);
6004         si_read_clock_registers(rdev);
6005         si_enable_acpi_power_management(rdev);
6006 }
6007
6008 static int si_thermal_enable_alert(struct radeon_device *rdev,
6009                                    bool enable)
6010 {
6011         u32 thermal_int = RREG32(CG_THERMAL_INT);
6012
6013         if (enable) {
6014                 PPSMC_Result result;
6015
6016                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6017                 WREG32(CG_THERMAL_INT, thermal_int);
6018                 rdev->irq.dpm_thermal = false;
6019                 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
6020                 if (result != PPSMC_Result_OK) {
6021                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6022                         return -EINVAL;
6023                 }
6024         } else {
6025                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6026                 WREG32(CG_THERMAL_INT, thermal_int);
6027                 rdev->irq.dpm_thermal = true;
6028         }
6029
6030         return 0;
6031 }
6032
6033 static int si_thermal_set_temperature_range(struct radeon_device *rdev,
6034                                             int min_temp, int max_temp)
6035 {
6036         int low_temp = 0 * 1000;
6037         int high_temp = 255 * 1000;
6038
6039         if (low_temp < min_temp)
6040                 low_temp = min_temp;
6041         if (high_temp > max_temp)
6042                 high_temp = max_temp;
6043         if (high_temp < low_temp) {
6044                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6045                 return -EINVAL;
6046         }
6047
6048         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6049         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6050         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6051
6052         rdev->pm.dpm.thermal.min_temp = low_temp;
6053         rdev->pm.dpm.thermal.max_temp = high_temp;
6054
6055         return 0;
6056 }
6057
6058 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
6059 {
6060         struct si_power_info *si_pi = si_get_pi(rdev);
6061         u32 tmp;
6062
6063         if (si_pi->fan_ctrl_is_in_default_mode) {
6064                 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6065                 si_pi->fan_ctrl_default_mode = tmp;
6066                 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6067                 si_pi->t_min = tmp;
6068                 si_pi->fan_ctrl_is_in_default_mode = false;
6069         }
6070
6071         tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6072         tmp |= TMIN(0);
6073         WREG32(CG_FDO_CTRL2, tmp);
6074
6075         tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6076         tmp |= FDO_PWM_MODE(mode);
6077         WREG32(CG_FDO_CTRL2, tmp);
6078 }
6079
6080 static int si_thermal_setup_fan_table(struct radeon_device *rdev)
6081 {
6082         struct si_power_info *si_pi = si_get_pi(rdev);
6083         PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6084         u32 duty100;
6085         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6086         u16 fdo_min, slope1, slope2;
6087         u32 reference_clock, tmp;
6088         int ret;
6089         u64 tmp64;
6090
6091         if (!si_pi->fan_table_start) {
6092                 rdev->pm.dpm.fan.ucode_fan_control = false;
6093                 return 0;
6094         }
6095
6096         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6097
6098         if (duty100 == 0) {
6099                 rdev->pm.dpm.fan.ucode_fan_control = false;
6100                 return 0;
6101         }
6102
6103         tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
6104         do_div(tmp64, 10000);
6105         fdo_min = (u16)tmp64;
6106
6107         t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
6108         t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
6109
6110         pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
6111         pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
6112
6113         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6114         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6115
6116         fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
6117         fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
6118         fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
6119
6120         fan_table.slope1 = cpu_to_be16(slope1);
6121         fan_table.slope2 = cpu_to_be16(slope2);
6122
6123         fan_table.fdo_min = cpu_to_be16(fdo_min);
6124
6125         fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
6126
6127         fan_table.hys_up = cpu_to_be16(1);
6128
6129         fan_table.hys_slope = cpu_to_be16(1);
6130
6131         fan_table.temp_resp_lim = cpu_to_be16(5);
6132
6133         reference_clock = radeon_get_xclk(rdev);
6134
6135         fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
6136                                                 reference_clock) / 1600);
6137
6138         fan_table.fdo_max = cpu_to_be16((u16)duty100);
6139
6140         tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6141         fan_table.temp_src = (uint8_t)tmp;
6142
6143         ret = si_copy_bytes_to_smc(rdev,
6144                                    si_pi->fan_table_start,
6145                                    (u8 *)(&fan_table),
6146                                    sizeof(fan_table),
6147                                    si_pi->sram_end);
6148
6149         if (ret) {
6150                 DRM_ERROR("Failed to load fan table to the SMC.");
6151                 rdev->pm.dpm.fan.ucode_fan_control = false;
6152         }
6153
6154         return 0;
6155 }
6156
6157 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6158 {
6159         struct si_power_info *si_pi = si_get_pi(rdev);
6160         PPSMC_Result ret;
6161
6162         ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6163         if (ret == PPSMC_Result_OK) {
6164                 si_pi->fan_is_controlled_by_smc = true;
6165                 return 0;
6166         } else {
6167                 return -EINVAL;
6168         }
6169 }
6170
6171 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6172 {
6173         struct si_power_info *si_pi = si_get_pi(rdev);
6174         PPSMC_Result ret;
6175
6176         ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6177
6178         if (ret == PPSMC_Result_OK) {
6179                 si_pi->fan_is_controlled_by_smc = false;
6180                 return 0;
6181         } else {
6182                 return -EINVAL;
6183         }
6184 }
6185
6186 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6187                                       u32 *speed)
6188 {
6189         u32 duty, duty100;
6190         u64 tmp64;
6191
6192         if (rdev->pm.no_fan)
6193                 return -ENOENT;
6194
6195         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6196         duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6197
6198         if (duty100 == 0)
6199                 return -EINVAL;
6200
6201         tmp64 = (u64)duty * 100;
6202         do_div(tmp64, duty100);
6203         *speed = (u32)tmp64;
6204
6205         if (*speed > 100)
6206                 *speed = 100;
6207
6208         return 0;
6209 }
6210
6211 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6212                                       u32 speed)
6213 {
6214         struct si_power_info *si_pi = si_get_pi(rdev);
6215         u32 tmp;
6216         u32 duty, duty100;
6217         u64 tmp64;
6218
6219         if (rdev->pm.no_fan)
6220                 return -ENOENT;
6221
6222         if (si_pi->fan_is_controlled_by_smc)
6223                 return -EINVAL;
6224
6225         if (speed > 100)
6226                 return -EINVAL;
6227
6228         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6229
6230         if (duty100 == 0)
6231                 return -EINVAL;
6232
6233         tmp64 = (u64)speed * duty100;
6234         do_div(tmp64, 100);
6235         duty = (u32)tmp64;
6236
6237         tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6238         tmp |= FDO_STATIC_DUTY(duty);
6239         WREG32(CG_FDO_CTRL0, tmp);
6240
6241         return 0;
6242 }
6243
6244 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
6245 {
6246         if (mode) {
6247                 /* stop auto-manage */
6248                 if (rdev->pm.dpm.fan.ucode_fan_control)
6249                         si_fan_ctrl_stop_smc_fan_control(rdev);
6250                 si_fan_ctrl_set_static_mode(rdev, mode);
6251         } else {
6252                 /* restart auto-manage */
6253                 if (rdev->pm.dpm.fan.ucode_fan_control)
6254                         si_thermal_start_smc_fan_control(rdev);
6255                 else
6256                         si_fan_ctrl_set_default_mode(rdev);
6257         }
6258 }
6259
6260 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
6261 {
6262         struct si_power_info *si_pi = si_get_pi(rdev);
6263         u32 tmp;
6264
6265         if (si_pi->fan_is_controlled_by_smc)
6266                 return 0;
6267
6268         tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6269         return (tmp >> FDO_PWM_MODE_SHIFT);
6270 }
6271
6272 #if 0
6273 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6274                                          u32 *speed)
6275 {
6276         u32 tach_period;
6277         u32 xclk = radeon_get_xclk(rdev);
6278
6279         if (rdev->pm.no_fan)
6280                 return -ENOENT;
6281
6282         if (rdev->pm.fan_pulses_per_revolution == 0)
6283                 return -ENOENT;
6284
6285         tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6286         if (tach_period == 0)
6287                 return -ENOENT;
6288
6289         *speed = 60 * xclk * 10000 / tach_period;
6290
6291         return 0;
6292 }
6293
6294 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6295                                          u32 speed)
6296 {
6297         u32 tach_period, tmp;
6298         u32 xclk = radeon_get_xclk(rdev);
6299
6300         if (rdev->pm.no_fan)
6301                 return -ENOENT;
6302
6303         if (rdev->pm.fan_pulses_per_revolution == 0)
6304                 return -ENOENT;
6305
6306         if ((speed < rdev->pm.fan_min_rpm) ||
6307             (speed > rdev->pm.fan_max_rpm))
6308                 return -EINVAL;
6309
6310         if (rdev->pm.dpm.fan.ucode_fan_control)
6311                 si_fan_ctrl_stop_smc_fan_control(rdev);
6312
6313         tach_period = 60 * xclk * 10000 / (8 * speed);
6314         tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6315         tmp |= TARGET_PERIOD(tach_period);
6316         WREG32(CG_TACH_CTRL, tmp);
6317
6318         si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6319
6320         return 0;
6321 }
6322 #endif
6323
6324 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6325 {
6326         struct si_power_info *si_pi = si_get_pi(rdev);
6327         u32 tmp;
6328
6329         if (!si_pi->fan_ctrl_is_in_default_mode) {
6330                 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6331                 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6332                 WREG32(CG_FDO_CTRL2, tmp);
6333
6334                 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6335                 tmp |= TMIN(si_pi->t_min);
6336                 WREG32(CG_FDO_CTRL2, tmp);
6337                 si_pi->fan_ctrl_is_in_default_mode = true;
6338         }
6339 }
6340
6341 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6342 {
6343         if (rdev->pm.dpm.fan.ucode_fan_control) {
6344                 si_fan_ctrl_start_smc_fan_control(rdev);
6345                 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6346         }
6347 }
6348
6349 static void si_thermal_initialize(struct radeon_device *rdev)
6350 {
6351         u32 tmp;
6352
6353         if (rdev->pm.fan_pulses_per_revolution) {
6354                 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6355                 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6356                 WREG32(CG_TACH_CTRL, tmp);
6357         }
6358
6359         tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6360         tmp |= TACH_PWM_RESP_RATE(0x28);
6361         WREG32(CG_FDO_CTRL2, tmp);
6362 }
6363
6364 static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6365 {
6366         int ret;
6367
6368         si_thermal_initialize(rdev);
6369         ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6370         if (ret)
6371                 return ret;
6372         ret = si_thermal_enable_alert(rdev, true);
6373         if (ret)
6374                 return ret;
6375         if (rdev->pm.dpm.fan.ucode_fan_control) {
6376                 ret = si_halt_smc(rdev);
6377                 if (ret)
6378                         return ret;
6379                 ret = si_thermal_setup_fan_table(rdev);
6380                 if (ret)
6381                         return ret;
6382                 ret = si_resume_smc(rdev);
6383                 if (ret)
6384                         return ret;
6385                 si_thermal_start_smc_fan_control(rdev);
6386         }
6387
6388         return 0;
6389 }
6390
6391 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6392 {
6393         if (!rdev->pm.no_fan) {
6394                 si_fan_ctrl_set_default_mode(rdev);
6395                 si_fan_ctrl_stop_smc_fan_control(rdev);
6396         }
6397 }
6398
6399 int si_dpm_enable(struct radeon_device *rdev)
6400 {
6401         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6402         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6403         struct si_power_info *si_pi = si_get_pi(rdev);
6404         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6405         int ret;
6406
6407         if (si_is_smc_running(rdev))
6408                 return -EINVAL;
6409         if (pi->voltage_control || si_pi->voltage_control_svi2)
6410                 si_enable_voltage_control(rdev, true);
6411         if (pi->mvdd_control)
6412                 si_get_mvdd_configuration(rdev);
6413         if (pi->voltage_control || si_pi->voltage_control_svi2) {
6414                 ret = si_construct_voltage_tables(rdev);
6415                 if (ret) {
6416                         DRM_ERROR("si_construct_voltage_tables failed\n");
6417                         return ret;
6418                 }
6419         }
6420         if (eg_pi->dynamic_ac_timing) {
6421                 ret = si_initialize_mc_reg_table(rdev);
6422                 if (ret)
6423                         eg_pi->dynamic_ac_timing = false;
6424         }
6425         if (pi->dynamic_ss)
6426                 si_enable_spread_spectrum(rdev, true);
6427         if (pi->thermal_protection)
6428                 si_enable_thermal_protection(rdev, true);
6429         si_setup_bsp(rdev);
6430         si_program_git(rdev);
6431         si_program_tp(rdev);
6432         si_program_tpp(rdev);
6433         si_program_sstp(rdev);
6434         si_enable_display_gap(rdev);
6435         si_program_vc(rdev);
6436         ret = si_upload_firmware(rdev);
6437         if (ret) {
6438                 DRM_ERROR("si_upload_firmware failed\n");
6439                 return ret;
6440         }
6441         ret = si_process_firmware_header(rdev);
6442         if (ret) {
6443                 DRM_ERROR("si_process_firmware_header failed\n");
6444                 return ret;
6445         }
6446         ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6447         if (ret) {
6448                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6449                 return ret;
6450         }
6451         ret = si_init_smc_table(rdev);
6452         if (ret) {
6453                 DRM_ERROR("si_init_smc_table failed\n");
6454                 return ret;
6455         }
6456         ret = si_init_smc_spll_table(rdev);
6457         if (ret) {
6458                 DRM_ERROR("si_init_smc_spll_table failed\n");
6459                 return ret;
6460         }
6461         ret = si_init_arb_table_index(rdev);
6462         if (ret) {
6463                 DRM_ERROR("si_init_arb_table_index failed\n");
6464                 return ret;
6465         }
6466         if (eg_pi->dynamic_ac_timing) {
6467                 ret = si_populate_mc_reg_table(rdev, boot_ps);
6468                 if (ret) {
6469                         DRM_ERROR("si_populate_mc_reg_table failed\n");
6470                         return ret;
6471                 }
6472         }
6473         ret = si_initialize_smc_cac_tables(rdev);
6474         if (ret) {
6475                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6476                 return ret;
6477         }
6478         ret = si_initialize_hardware_cac_manager(rdev);
6479         if (ret) {
6480                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6481                 return ret;
6482         }
6483         ret = si_initialize_smc_dte_tables(rdev);
6484         if (ret) {
6485                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6486                 return ret;
6487         }
6488         ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6489         if (ret) {
6490                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6491                 return ret;
6492         }
6493         ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6494         if (ret) {
6495                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6496                 return ret;
6497         }
6498         si_program_response_times(rdev);
6499         si_program_ds_registers(rdev);
6500         si_dpm_start_smc(rdev);
6501         ret = si_notify_smc_display_change(rdev, false);
6502         if (ret) {
6503                 DRM_ERROR("si_notify_smc_display_change failed\n");
6504                 return ret;
6505         }
6506         si_enable_sclk_control(rdev, true);
6507         si_start_dpm(rdev);
6508
6509         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6510
6511         si_thermal_start_thermal_controller(rdev);
6512
6513         ni_update_current_ps(rdev, boot_ps);
6514
6515         return 0;
6516 }
6517
6518 static int si_set_temperature_range(struct radeon_device *rdev)
6519 {
6520         int ret;
6521
6522         ret = si_thermal_enable_alert(rdev, false);
6523         if (ret)
6524                 return ret;
6525         ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6526         if (ret)
6527                 return ret;
6528         ret = si_thermal_enable_alert(rdev, true);
6529         if (ret)
6530                 return ret;
6531
6532         return ret;
6533 }
6534
6535 int si_dpm_late_enable(struct radeon_device *rdev)
6536 {
6537         int ret;
6538
6539         ret = si_set_temperature_range(rdev);
6540         if (ret)
6541                 return ret;
6542
6543         return ret;
6544 }
6545
6546 void si_dpm_disable(struct radeon_device *rdev)
6547 {
6548         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6549         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6550
6551         if (!si_is_smc_running(rdev))
6552                 return;
6553         si_thermal_stop_thermal_controller(rdev);
6554         si_disable_ulv(rdev);
6555         si_clear_vc(rdev);
6556         if (pi->thermal_protection)
6557                 si_enable_thermal_protection(rdev, false);
6558         si_enable_power_containment(rdev, boot_ps, false);
6559         si_enable_smc_cac(rdev, boot_ps, false);
6560         si_enable_spread_spectrum(rdev, false);
6561         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6562         si_stop_dpm(rdev);
6563         si_reset_to_default(rdev);
6564         si_dpm_stop_smc(rdev);
6565         si_force_switch_to_arb_f0(rdev);
6566
6567         ni_update_current_ps(rdev, boot_ps);
6568 }
6569
6570 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6571 {
6572         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6573         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6574         struct radeon_ps *new_ps = &requested_ps;
6575
6576         ni_update_requested_ps(rdev, new_ps);
6577
6578         si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6579
6580         return 0;
6581 }
6582
6583 static int si_power_control_set_level(struct radeon_device *rdev)
6584 {
6585         struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6586         int ret;
6587
6588         ret = si_restrict_performance_levels_before_switch(rdev);
6589         if (ret)
6590                 return ret;
6591         ret = si_halt_smc(rdev);
6592         if (ret)
6593                 return ret;
6594         ret = si_populate_smc_tdp_limits(rdev, new_ps);
6595         if (ret)
6596                 return ret;
6597         ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6598         if (ret)
6599                 return ret;
6600         ret = si_resume_smc(rdev);
6601         if (ret)
6602                 return ret;
6603         ret = si_set_sw_state(rdev);
6604         if (ret)
6605                 return ret;
6606         return 0;
6607 }
6608
6609 int si_dpm_set_power_state(struct radeon_device *rdev)
6610 {
6611         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6612         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6613         struct radeon_ps *old_ps = &eg_pi->current_rps;
6614         int ret;
6615
6616         ret = si_disable_ulv(rdev);
6617         if (ret) {
6618                 DRM_ERROR("si_disable_ulv failed\n");
6619                 return ret;
6620         }
6621         ret = si_restrict_performance_levels_before_switch(rdev);
6622         if (ret) {
6623                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6624                 return ret;
6625         }
6626         if (eg_pi->pcie_performance_request)
6627                 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6628         ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6629         ret = si_enable_power_containment(rdev, new_ps, false);
6630         if (ret) {
6631                 DRM_ERROR("si_enable_power_containment failed\n");
6632                 return ret;
6633         }
6634         ret = si_enable_smc_cac(rdev, new_ps, false);
6635         if (ret) {
6636                 DRM_ERROR("si_enable_smc_cac failed\n");
6637                 return ret;
6638         }
6639         ret = si_halt_smc(rdev);
6640         if (ret) {
6641                 DRM_ERROR("si_halt_smc failed\n");
6642                 return ret;
6643         }
6644         ret = si_upload_sw_state(rdev, new_ps);
6645         if (ret) {
6646                 DRM_ERROR("si_upload_sw_state failed\n");
6647                 return ret;
6648         }
6649         ret = si_upload_smc_data(rdev);
6650         if (ret) {
6651                 DRM_ERROR("si_upload_smc_data failed\n");
6652                 return ret;
6653         }
6654         ret = si_upload_ulv_state(rdev);
6655         if (ret) {
6656                 DRM_ERROR("si_upload_ulv_state failed\n");
6657                 return ret;
6658         }
6659         if (eg_pi->dynamic_ac_timing) {
6660                 ret = si_upload_mc_reg_table(rdev, new_ps);
6661                 if (ret) {
6662                         DRM_ERROR("si_upload_mc_reg_table failed\n");
6663                         return ret;
6664                 }
6665         }
6666         ret = si_program_memory_timing_parameters(rdev, new_ps);
6667         if (ret) {
6668                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6669                 return ret;
6670         }
6671         si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6672
6673         ret = si_resume_smc(rdev);
6674         if (ret) {
6675                 DRM_ERROR("si_resume_smc failed\n");
6676                 return ret;
6677         }
6678         ret = si_set_sw_state(rdev);
6679         if (ret) {
6680                 DRM_ERROR("si_set_sw_state failed\n");
6681                 return ret;
6682         }
6683         ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6684         si_set_vce_clock(rdev, new_ps, old_ps);
6685         if (eg_pi->pcie_performance_request)
6686                 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6687         ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6688         if (ret) {
6689                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6690                 return ret;
6691         }
6692         ret = si_enable_smc_cac(rdev, new_ps, true);
6693         if (ret) {
6694                 DRM_ERROR("si_enable_smc_cac failed\n");
6695                 return ret;
6696         }
6697         ret = si_enable_power_containment(rdev, new_ps, true);
6698         if (ret) {
6699                 DRM_ERROR("si_enable_power_containment failed\n");
6700                 return ret;
6701         }
6702
6703         ret = si_power_control_set_level(rdev);
6704         if (ret) {
6705                 DRM_ERROR("si_power_control_set_level failed\n");
6706                 return ret;
6707         }
6708
6709         return 0;
6710 }
6711
6712 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6713 {
6714         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6715         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6716
6717         ni_update_current_ps(rdev, new_ps);
6718 }
6719
6720 #if 0
6721 void si_dpm_reset_asic(struct radeon_device *rdev)
6722 {
6723         si_restrict_performance_levels_before_switch(rdev);
6724         si_disable_ulv(rdev);
6725         si_set_boot_state(rdev);
6726 }
6727 #endif
6728
6729 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6730 {
6731         si_program_display_gap(rdev);
6732 }
6733
6734 union power_info {
6735         struct _ATOM_POWERPLAY_INFO info;
6736         struct _ATOM_POWERPLAY_INFO_V2 info_2;
6737         struct _ATOM_POWERPLAY_INFO_V3 info_3;
6738         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6739         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6740         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6741 };
6742
6743 union pplib_clock_info {
6744         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6745         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6746         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6747         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6748         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6749 };
6750
6751 union pplib_power_state {
6752         struct _ATOM_PPLIB_STATE v1;
6753         struct _ATOM_PPLIB_STATE_V2 v2;
6754 };
6755
6756 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6757                                           struct radeon_ps *rps,
6758                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6759                                           u8 table_rev)
6760 {
6761         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6762         rps->class = le16_to_cpu(non_clock_info->usClassification);
6763         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6764
6765         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6766                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6767                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6768         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6769                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6770                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6771         } else {
6772                 rps->vclk = 0;
6773                 rps->dclk = 0;
6774         }
6775
6776         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6777                 rdev->pm.dpm.boot_ps = rps;
6778         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6779                 rdev->pm.dpm.uvd_ps = rps;
6780 }
6781
6782 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6783                                       struct radeon_ps *rps, int index,
6784                                       union pplib_clock_info *clock_info)
6785 {
6786         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6787         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6788         struct si_power_info *si_pi = si_get_pi(rdev);
6789         struct ni_ps *ps = ni_get_ps(rps);
6790         u16 leakage_voltage;
6791         struct rv7xx_pl *pl = &ps->performance_levels[index];
6792         int ret;
6793
6794         ps->performance_level_count = index + 1;
6795
6796         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6797         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6798         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6799         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6800
6801         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6802         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6803         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6804         pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6805                                                  si_pi->sys_pcie_mask,
6806                                                  si_pi->boot_pcie_gen,
6807                                                  clock_info->si.ucPCIEGen);
6808
6809         /* patch up vddc if necessary */
6810         ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6811                                                         &leakage_voltage);
6812         if (ret == 0)
6813                 pl->vddc = leakage_voltage;
6814
6815         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6816                 pi->acpi_vddc = pl->vddc;
6817                 eg_pi->acpi_vddci = pl->vddci;
6818                 si_pi->acpi_pcie_gen = pl->pcie_gen;
6819         }
6820
6821         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6822             index == 0) {
6823                 /* XXX disable for A0 tahiti */
6824                 si_pi->ulv.supported = false;
6825                 si_pi->ulv.pl = *pl;
6826                 si_pi->ulv.one_pcie_lane_in_ulv = false;
6827                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6828                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6829                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6830         }
6831
6832         if (pi->min_vddc_in_table > pl->vddc)
6833                 pi->min_vddc_in_table = pl->vddc;
6834
6835         if (pi->max_vddc_in_table < pl->vddc)
6836                 pi->max_vddc_in_table = pl->vddc;
6837
6838         /* patch up boot state */
6839         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6840                 u16 vddc, vddci, mvdd;
6841                 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6842                 pl->mclk = rdev->clock.default_mclk;
6843                 pl->sclk = rdev->clock.default_sclk;
6844                 pl->vddc = vddc;
6845                 pl->vddci = vddci;
6846                 si_pi->mvdd_bootup_value = mvdd;
6847         }
6848
6849         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6850             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6851                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6852                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6853                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6854                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6855         }
6856 }
6857
6858 static int si_parse_power_table(struct radeon_device *rdev)
6859 {
6860         struct radeon_mode_info *mode_info = &rdev->mode_info;
6861         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6862         union pplib_power_state *power_state;
6863         int i, j, k, non_clock_array_index, clock_array_index;
6864         union pplib_clock_info *clock_info;
6865         struct _StateArray *state_array;
6866         struct _ClockInfoArray *clock_info_array;
6867         struct _NonClockInfoArray *non_clock_info_array;
6868         union power_info *power_info;
6869         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6870         u16 data_offset;
6871         u8 frev, crev;
6872         u8 *power_state_offset;
6873         struct ni_ps *ps;
6874
6875         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6876                                    &frev, &crev, &data_offset))
6877                 return -EINVAL;
6878         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6879
6880         state_array = (struct _StateArray *)
6881                 (mode_info->atom_context->bios + data_offset +
6882                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
6883         clock_info_array = (struct _ClockInfoArray *)
6884                 (mode_info->atom_context->bios + data_offset +
6885                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6886         non_clock_info_array = (struct _NonClockInfoArray *)
6887                 (mode_info->atom_context->bios + data_offset +
6888                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6889
6890         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6891                                   state_array->ucNumEntries, GFP_KERNEL);
6892         if (!rdev->pm.dpm.ps)
6893                 return -ENOMEM;
6894         power_state_offset = (u8 *)state_array->states;
6895         for (i = 0; i < state_array->ucNumEntries; i++) {
6896                 u8 *idx;
6897                 power_state = (union pplib_power_state *)power_state_offset;
6898                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6899                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6900                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
6901                 if (!rdev->pm.power_state[i].clock_info)
6902                         return -EINVAL;
6903                 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6904                 if (ps == NULL) {
6905                         kfree(rdev->pm.dpm.ps);
6906                         return -ENOMEM;
6907                 }
6908                 rdev->pm.dpm.ps[i].ps_priv = ps;
6909                 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6910                                               non_clock_info,
6911                                               non_clock_info_array->ucEntrySize);
6912                 k = 0;
6913                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6914                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6915                         clock_array_index = idx[j];
6916                         if (clock_array_index >= clock_info_array->ucNumEntries)
6917                                 continue;
6918                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6919                                 break;
6920                         clock_info = (union pplib_clock_info *)
6921                                 ((u8 *)&clock_info_array->clockInfo[0] +
6922                                  (clock_array_index * clock_info_array->ucEntrySize));
6923                         si_parse_pplib_clock_info(rdev,
6924                                                   &rdev->pm.dpm.ps[i], k,
6925                                                   clock_info);
6926                         k++;
6927                 }
6928                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6929         }
6930         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6931
6932         /* fill in the vce power states */
6933         for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
6934                 u32 sclk, mclk;
6935                 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
6936                 clock_info = (union pplib_clock_info *)
6937                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6938                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6939                 sclk |= clock_info->si.ucEngineClockHigh << 16;
6940                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6941                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
6942                 rdev->pm.dpm.vce_states[i].sclk = sclk;
6943                 rdev->pm.dpm.vce_states[i].mclk = mclk;
6944         }
6945
6946         return 0;
6947 }
6948
6949 int si_dpm_init(struct radeon_device *rdev)
6950 {
6951         struct rv7xx_power_info *pi;
6952         struct evergreen_power_info *eg_pi;
6953         struct ni_power_info *ni_pi;
6954         struct si_power_info *si_pi;
6955         struct atom_clock_dividers dividers;
6956         int ret;
6957         u32 mask;
6958
6959         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6960         if (si_pi == NULL)
6961                 return -ENOMEM;
6962         rdev->pm.dpm.priv = si_pi;
6963         ni_pi = &si_pi->ni;
6964         eg_pi = &ni_pi->eg;
6965         pi = &eg_pi->rv7xx;
6966
6967         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6968         if (ret)
6969                 si_pi->sys_pcie_mask = 0;
6970         else
6971                 si_pi->sys_pcie_mask = mask;
6972         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6973         si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6974
6975         si_set_max_cu_value(rdev);
6976
6977         rv770_get_max_vddc(rdev);
6978         si_get_leakage_vddc(rdev);
6979         si_patch_dependency_tables_based_on_leakage(rdev);
6980
6981         pi->acpi_vddc = 0;
6982         eg_pi->acpi_vddci = 0;
6983         pi->min_vddc_in_table = 0;
6984         pi->max_vddc_in_table = 0;
6985
6986         ret = r600_get_platform_caps(rdev);
6987         if (ret)
6988                 return ret;
6989
6990         ret = r600_parse_extended_power_table(rdev);
6991         if (ret)
6992                 return ret;
6993
6994         ret = si_parse_power_table(rdev);
6995         if (ret)
6996                 return ret;
6997
6998         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6999                 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
7000         if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7001                 r600_free_extended_power_table(rdev);
7002                 return -ENOMEM;
7003         }
7004         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7005         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7006         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7007         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7008         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7009         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7010         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7011         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7012         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7013
7014         if (rdev->pm.dpm.voltage_response_time == 0)
7015                 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7016         if (rdev->pm.dpm.backbias_response_time == 0)
7017                 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7018
7019         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
7020                                              0, false, &dividers);
7021         if (ret)
7022                 pi->ref_div = dividers.ref_div + 1;
7023         else
7024                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7025
7026         eg_pi->smu_uvd_hs = false;
7027
7028         pi->mclk_strobe_mode_threshold = 40000;
7029         if (si_is_special_1gb_platform(rdev))
7030                 pi->mclk_stutter_mode_threshold = 0;
7031         else
7032                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7033         pi->mclk_edc_enable_threshold = 40000;
7034         eg_pi->mclk_edc_wr_enable_threshold = 40000;
7035
7036         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7037
7038         pi->voltage_control =
7039                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7040                                             VOLTAGE_OBJ_GPIO_LUT);
7041         if (!pi->voltage_control) {
7042                 si_pi->voltage_control_svi2 =
7043                         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7044                                                     VOLTAGE_OBJ_SVID2);
7045                 if (si_pi->voltage_control_svi2)
7046                         radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7047                                                   &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7048         }
7049
7050         pi->mvdd_control =
7051                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7052                                             VOLTAGE_OBJ_GPIO_LUT);
7053
7054         eg_pi->vddci_control =
7055                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7056                                             VOLTAGE_OBJ_GPIO_LUT);
7057         if (!eg_pi->vddci_control)
7058                 si_pi->vddci_control_svi2 =
7059                         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7060                                                     VOLTAGE_OBJ_SVID2);
7061
7062         si_pi->vddc_phase_shed_control =
7063                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7064                                             VOLTAGE_OBJ_PHASE_LUT);
7065
7066         rv770_get_engine_memory_ss(rdev);
7067
7068         pi->asi = RV770_ASI_DFLT;
7069         pi->pasi = CYPRESS_HASI_DFLT;
7070         pi->vrc = SISLANDS_VRC_DFLT;
7071
7072         pi->gfx_clock_gating = true;
7073
7074         eg_pi->sclk_deep_sleep = true;
7075         si_pi->sclk_deep_sleep_above_low = false;
7076
7077         if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7078                 pi->thermal_protection = true;
7079         else
7080                 pi->thermal_protection = false;
7081
7082         eg_pi->dynamic_ac_timing = true;
7083
7084         eg_pi->light_sleep = true;
7085 #if defined(CONFIG_ACPI)
7086         eg_pi->pcie_performance_request =
7087                 radeon_acpi_is_pcie_performance_request_supported(rdev);
7088 #else
7089         eg_pi->pcie_performance_request = false;
7090 #endif
7091
7092         si_pi->sram_end = SMC_RAM_END;
7093
7094         rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7095         rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7096         rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7097         rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7098         rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7099         rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7100         rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7101
7102         si_initialize_powertune_defaults(rdev);
7103
7104         /* make sure dc limits are valid */
7105         if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7106             (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7107                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7108                         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7109
7110         si_pi->fan_ctrl_is_in_default_mode = true;
7111
7112         return 0;
7113 }
7114
7115 void si_dpm_fini(struct radeon_device *rdev)
7116 {
7117         int i;
7118
7119         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
7120                 kfree(rdev->pm.dpm.ps[i].ps_priv);
7121         }
7122         kfree(rdev->pm.dpm.ps);
7123         kfree(rdev->pm.dpm.priv);
7124         kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7125         r600_free_extended_power_table(rdev);
7126 }
7127
7128 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
7129                                                     struct seq_file *m)
7130 {
7131         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7132         struct radeon_ps *rps = &eg_pi->current_rps;
7133         struct ni_ps *ps = ni_get_ps(rps);
7134         struct rv7xx_pl *pl;
7135         u32 current_index =
7136                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7137                 CURRENT_STATE_INDEX_SHIFT;
7138
7139         if (current_index >= ps->performance_level_count) {
7140                 seq_printf(m, "invalid dpm profile %d\n", current_index);
7141         } else {
7142                 pl = &ps->performance_levels[current_index];
7143                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7144                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7145                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7146         }
7147 }
7148
7149 u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
7150 {
7151         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7152         struct radeon_ps *rps = &eg_pi->current_rps;
7153         struct ni_ps *ps = ni_get_ps(rps);
7154         struct rv7xx_pl *pl;
7155         u32 current_index =
7156                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7157                 CURRENT_STATE_INDEX_SHIFT;
7158
7159         if (current_index >= ps->performance_level_count) {
7160                 return 0;
7161         } else {
7162                 pl = &ps->performance_levels[current_index];
7163                 return pl->sclk;
7164         }
7165 }
7166
7167 u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
7168 {
7169         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7170         struct radeon_ps *rps = &eg_pi->current_rps;
7171         struct ni_ps *ps = ni_get_ps(rps);
7172         struct rv7xx_pl *pl;
7173         u32 current_index =
7174                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7175                 CURRENT_STATE_INDEX_SHIFT;
7176
7177         if (current_index >= ps->performance_level_count) {
7178                 return 0;
7179         } else {
7180                 pl = &ps->performance_levels[current_index];
7181                 return pl->mclk;
7182         }
7183 }