2 * Copyright (c) 1995, David Greenman
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/ed/if_ed.c,v 1.224 2003/12/08 07:54:12 obrien Exp $
28 * $DragonFly: src/sys/dev/netif/ed/if_ed.c,v 1.18 2005/01/23 20:21:31 joerg Exp $
32 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
33 * adapters. By David Greenman, 29-April-1993
35 * Currently supports the Western Digital/SMC 8003 and 8013 series,
36 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
37 * and a variety of similar clones.
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/sockio.h>
47 #include <sys/kernel.h>
48 #include <sys/socket.h>
49 #include <sys/syslog.h>
51 #include <sys/module.h>
54 #include <machine/bus.h>
56 #include <machine/resource.h>
58 #include <net/ethernet.h>
60 #include <net/if_arp.h>
61 #include <net/if_dl.h>
62 #include <net/if_mib.h>
63 #include <net/if_media.h>
66 #include <dev/netif/mii_layer/mii.h>
67 #include <dev/netif/mii_layer/miivar.h>
72 #include <net/bridge/bridge.h>
74 #include <machine/md_var.h>
79 devclass_t ed_devclass;
81 static void ed_init (void *);
82 static int ed_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
83 static void ed_start (struct ifnet *);
84 static void ed_reset (struct ifnet *);
85 static void ed_watchdog (struct ifnet *);
87 static void ed_tick (void *);
90 static void ds_getmcaf (struct ed_softc *, u_int32_t *);
92 static void ed_get_packet (struct ed_softc *, char *, /* u_short */ int);
94 static __inline void ed_rint (struct ed_softc *);
95 static __inline void ed_xmit (struct ed_softc *);
96 static __inline char * ed_ring_copy (struct ed_softc *, char *, char *,
98 static void ed_hpp_set_physical_link (struct ed_softc *);
99 static void ed_hpp_readmem (struct ed_softc *, int, unsigned char *,
101 static void ed_hpp_writemem (struct ed_softc *, unsigned char *,
102 /* u_short */ int, /* u_short */ int);
103 static u_short ed_hpp_write_mbufs (struct ed_softc *, struct mbuf *,
106 static u_short ed_pio_write_mbufs (struct ed_softc *, struct mbuf *,
109 static void ed_setrcr (struct ed_softc *);
111 static uint32_t ds_mchash (const uint8_t *);
113 DECLARE_DUMMY_MODULE(if_ed);
116 * Interrupt conversion table for WD/SMC ASIC/83C584
118 static unsigned short ed_intr_val[] = {
130 * Interrupt conversion table for 83C790
132 static unsigned short ed_790_intr_val[] = {
144 * Interrupt conversion table for the HP PC LAN+
147 static unsigned short ed_hpp_intr_val[] = {
167 * Generic probe routine for testing for the existance of a DS8390.
168 * Must be called after the NIC has just been reset. This routine
169 * works by looking at certain register values that are guaranteed
170 * to be initialized a certain way after power-up or reset. Seems
171 * not to currently work on the 83C690.
175 * Register reset bits set bits
176 * Command Register (CR) TXP, STA RD2, STP
177 * Interrupt Status (ISR) RST
178 * Interrupt Mask (IMR) All bits
179 * Data Control (DCR) LAS
180 * Transmit Config. (TCR) LB1, LB0
182 * We only look at the CR and ISR registers, however, because looking at
183 * the others would require changing register pages (which would be
184 * intrusive if this isn't an 8390).
186 * Return 1 if 8390 was found, 0 if not.
190 ed_probe_generic8390(sc)
193 if ((ed_nic_inb(sc, ED_P0_CR) &
194 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
195 (ED_CR_RD2 | ED_CR_STP))
197 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
204 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
207 ed_probe_WD80x3_generic(dev, flags, intr_vals)
210 unsigned short *intr_vals[];
212 struct ed_softc *sc = device_get_softc(dev);
215 u_int memsize, maddr;
216 u_char iptr, isa16bit, sum, totalsum;
217 u_long conf_maddr, conf_msize, irq, junk;
219 sc->chip_type = ED_CHIP_TYPE_DP8390;
221 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
222 totalsum = ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER;
223 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_POW);
227 totalsum = ED_WD_ROM_CHECKSUM_TOTAL;
230 * Attempt to do a checksum over the station address PROM. If it
231 * fails, it's probably not a SMC/WD board. There is a problem with
232 * this, though: some clone WD boards don't pass the checksum test.
233 * Danpex boards for one.
235 for (sum = 0, i = 0; i < 8; ++i)
236 sum += ed_asic_inb(sc, ED_WD_PROM + i);
238 if (sum != totalsum) {
241 * Checksum is invalid. This often happens with cheap WD8003E
242 * clones. In this case, the checksum byte (the eighth byte)
243 * seems to always be zero.
245 if (ed_asic_inb(sc, ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
246 ed_asic_inb(sc, ED_WD_PROM + 7) != 0)
249 /* reset card to force it into a known state. */
250 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER)
251 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
253 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST);
256 ed_asic_outb(sc, ED_WD_MSR, ed_asic_inb(sc, ED_WD_MSR) & ~ED_WD_MSR_RST);
257 /* wait in the case this card is reading its EEROM */
260 sc->vendor = ED_VENDOR_WD_SMC;
261 sc->type = ed_asic_inb(sc, ED_WD_CARD_ID);
264 * Set initial values for width/size.
269 case ED_TYPE_WD8003S:
270 sc->type_str = "WD8003S";
272 case ED_TYPE_WD8003E:
273 sc->type_str = "WD8003E";
275 case ED_TYPE_WD8003EB:
276 sc->type_str = "WD8003EB";
278 case ED_TYPE_WD8003W:
279 sc->type_str = "WD8003W";
281 case ED_TYPE_WD8013EBT:
282 sc->type_str = "WD8013EBT";
286 case ED_TYPE_WD8013W:
287 sc->type_str = "WD8013W";
291 case ED_TYPE_WD8013EP: /* also WD8003EP */
292 if (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) {
295 sc->type_str = "WD8013EP";
297 sc->type_str = "WD8003EP";
300 case ED_TYPE_WD8013WC:
301 sc->type_str = "WD8013WC";
305 case ED_TYPE_WD8013EBP:
306 sc->type_str = "WD8013EBP";
310 case ED_TYPE_WD8013EPC:
311 sc->type_str = "WD8013EPC";
315 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
316 case ED_TYPE_SMC8216T:
317 if (sc->type == ED_TYPE_SMC8216C) {
318 sc->type_str = "SMC8216/SMC8216C";
320 sc->type_str = "SMC8216T";
323 ed_asic_outb(sc, ED_WD790_HWR,
324 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
325 switch (ed_asic_inb(sc, ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
326 case ED_WD790_RAR_SZ64:
329 case ED_WD790_RAR_SZ32:
332 case ED_WD790_RAR_SZ16:
335 case ED_WD790_RAR_SZ8:
336 /* 8216 has 16K shared mem -- 8416 has 8K */
337 if (sc->type == ED_TYPE_SMC8216C) {
338 sc->type_str = "SMC8416C/SMC8416BT";
340 sc->type_str = "SMC8416T";
345 ed_asic_outb(sc, ED_WD790_HWR,
346 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
349 sc->chip_type = ED_CHIP_TYPE_WD790;
351 case ED_TYPE_TOSHIBA1:
352 sc->type_str = "Toshiba1";
356 case ED_TYPE_TOSHIBA4:
357 sc->type_str = "Toshiba4";
367 * Make some adjustments to initial values depending on what is found
370 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
371 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
372 && ((ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
377 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
378 &conf_maddr, &conf_msize);
383 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
384 sc->type, sc->type_str, isa16bit, memsize, conf_msize);
385 for (i = 0; i < 8; i++)
386 printf("%x -> %x\n", i, ed_asic_inb(sc, i));
390 * Allow the user to override the autoconfiguration
393 memsize = conf_msize;
396 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
397 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n",
398 maddr, maddr + memsize);
403 * (note that if the user specifies both of the following flags that
404 * '8bit' mode intentionally has precedence)
406 if (flags & ED_FLAGS_FORCE_16BIT_MODE)
408 if (flags & ED_FLAGS_FORCE_8BIT_MODE)
412 * If possible, get the assigned interrupt number from the card and
415 if ((sc->type & ED_WD_SOFTCONFIG) &&
416 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
419 * Assemble together the encoded interrupt number.
421 iptr = (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_IR2) |
422 ((ed_asic_inb(sc, ED_WD_IRR) &
423 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
426 * If no interrupt specified (or "?"), use what the board tells us.
428 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
430 if (error && intr_vals[0] != NULL) {
431 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
432 intr_vals[0][iptr], 1);
438 * Enable the interrupt.
440 ed_asic_outb(sc, ED_WD_IRR,
441 ed_asic_inb(sc, ED_WD_IRR) | ED_WD_IRR_IEN);
443 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
444 ed_asic_outb(sc, ED_WD790_HWR,
445 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
446 iptr = (((ed_asic_inb(sc, ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
447 (ed_asic_inb(sc, ED_WD790_GCR) &
448 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
449 ed_asic_outb(sc, ED_WD790_HWR,
450 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
453 * If no interrupt specified (or "?"), use what the board tells us.
455 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
457 if (error && intr_vals[1] != NULL) {
458 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
459 intr_vals[1][iptr], 1);
467 ed_asic_outb(sc, ED_WD790_ICR,
468 ed_asic_inb(sc, ED_WD790_ICR) | ED_WD790_ICR_EIL);
470 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
473 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n",
477 sc->isa16bit = isa16bit;
480 error = ed_alloc_memory(dev, 0, memsize);
482 printf("*** ed_alloc_memory() failed! (%d)\n", error);
485 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
488 * allocate one xmit buffer if < 16k, two buffers otherwise
490 if ((memsize < 16384) ||
491 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
496 sc->tx_page_start = ED_WD_PAGE_OFFSET;
497 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
498 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
499 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
500 sc->mem_size = memsize;
501 sc->mem_end = sc->mem_start + memsize;
504 * Get station address from on-board ROM
506 for (i = 0; i < ETHER_ADDR_LEN; ++i)
507 sc->arpcom.ac_enaddr[i] = ed_asic_inb(sc, ED_WD_PROM + i);
510 * Set upper address bits and 8/16 bit access to shared memory.
513 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
514 sc->wd_laar_proto = ed_asic_inb(sc, ED_WD_LAAR);
516 sc->wd_laar_proto = ED_WD_LAAR_L16EN |
517 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
520 * Enable 16bit access
522 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto |
525 if (((sc->type & ED_WD_SOFTCONFIG) ||
526 (sc->type == ED_TYPE_TOSHIBA1) ||
527 (sc->type == ED_TYPE_TOSHIBA4) ||
528 (sc->type == ED_TYPE_WD8013EBT)) &&
529 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
530 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
532 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto);
537 * Set address and enable interface shared memory.
539 if (sc->chip_type != ED_CHIP_TYPE_WD790) {
540 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
541 ed_asic_outb(sc, ED_WD_MSR + 1,
542 ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
543 ed_asic_outb(sc, ED_WD_MSR + 2,
544 ((kvtop(sc->mem_start) >> 16) & 0x0f));
545 ed_asic_outb(sc, ED_WD_MSR,
546 ED_WD_MSR_MENB | ED_WD_MSR_POW);
548 ed_asic_outb(sc, ED_WD_MSR,
549 ((kvtop(sc->mem_start) >> 13) &
550 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
552 sc->cr_proto = ED_CR_RD2;
554 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
555 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH));
556 ed_asic_outb(sc, ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
557 ((kvtop(sc->mem_start) >> 11) & 0x40) |
558 (ed_asic_inb(sc, ED_WD790_RAR) & 0xb0));
559 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
564 printf("starting memory performance test at 0x%x, size %d...\n",
565 sc->mem_start, memsize*16384);
566 for (i = 0; i < 16384; i++)
567 bzero(sc->mem_start, memsize);
568 printf("***DONE***\n");
572 * Now zero memory and verify that it is clear
574 bzero(sc->mem_start, memsize);
576 for (i = 0; i < memsize; ++i) {
577 if (sc->mem_start[i]) {
578 device_printf(dev, "failed to clear shared memory at %llx - check configuration\n",
579 (long long)kvtop(sc->mem_start + i));
582 * Disable 16 bit access to shared memory
585 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
586 ed_asic_outb(sc, ED_WD_MSR, 0x00);
588 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
596 * Disable 16bit access to shared memory - we leave it
597 * disabled so that 1) machines reboot properly when the board
598 * is set 16 bit mode and there are conflicting 8bit
599 * devices/ROMS in the same 128k address space as this boards
600 * shared memory. and 2) so that other 8 bit devices with
601 * shared memory can be used in this 128k region, too.
604 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
605 ed_asic_outb(sc, ED_WD_MSR, 0x00);
607 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
614 ed_probe_WD80x3(dev, port_rid, flags)
619 struct ed_softc *sc = device_get_softc(dev);
621 static unsigned short *intr_vals[] = {ed_intr_val, ed_790_intr_val};
623 error = ed_alloc_port(dev, port_rid, ED_WD_IO_PORTS);
627 sc->asic_offset = ED_WD_ASIC_OFFSET;
628 sc->nic_offset = ED_WD_NIC_OFFSET;
630 return ed_probe_WD80x3_generic(dev, flags, intr_vals);
634 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
637 ed_probe_3Com(dev, port_rid, flags)
642 struct ed_softc *sc = device_get_softc(dev);
647 u_long conf_maddr, conf_msize, irq, junk;
649 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS);
653 sc->asic_offset = ED_3COM_ASIC_OFFSET;
654 sc->nic_offset = ED_3COM_NIC_OFFSET;
657 * Verify that the kernel configured I/O address matches the board
660 switch (ed_asic_inb(sc, ED_3COM_BCFR)) {
661 case ED_3COM_BCFR_300:
662 if (rman_get_start(sc->port_res) != 0x300)
665 case ED_3COM_BCFR_310:
666 if (rman_get_start(sc->port_res) != 0x310)
669 case ED_3COM_BCFR_330:
670 if (rman_get_start(sc->port_res) != 0x330)
673 case ED_3COM_BCFR_350:
674 if (rman_get_start(sc->port_res) != 0x350)
677 case ED_3COM_BCFR_250:
678 if (rman_get_start(sc->port_res) != 0x250)
681 case ED_3COM_BCFR_280:
682 if (rman_get_start(sc->port_res) != 0x280)
685 case ED_3COM_BCFR_2A0:
686 if (rman_get_start(sc->port_res) != 0x2a0)
689 case ED_3COM_BCFR_2E0:
690 if (rman_get_start(sc->port_res) != 0x2e0)
697 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
698 &conf_maddr, &conf_msize);
703 * Verify that the kernel shared memory address matches the board
704 * configured address.
706 switch (ed_asic_inb(sc, ED_3COM_PCFR)) {
707 case ED_3COM_PCFR_DC000:
708 if (conf_maddr != 0xdc000)
711 case ED_3COM_PCFR_D8000:
712 if (conf_maddr != 0xd8000)
715 case ED_3COM_PCFR_CC000:
716 if (conf_maddr != 0xcc000)
719 case ED_3COM_PCFR_C8000:
720 if (conf_maddr != 0xc8000)
729 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
730 * sequence because it'll lock up if the cable isn't connected if we
733 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
736 * Wait for a while, then un-reset it
741 * The 3Com ASIC defaults to rather strange settings for the CR after
742 * a reset - it's important to set it again after the following outb
743 * (this is done when we map the PROM below).
745 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
748 * Wait a bit for the NIC to recover from the reset
752 sc->vendor = ED_VENDOR_3COM;
753 sc->type_str = "3c503";
755 sc->cr_proto = ED_CR_RD2;
758 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
764 * Get station address from on-board ROM
768 * First, map ethernet address PROM over the top of where the NIC
769 * registers normally appear.
771 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
773 for (i = 0; i < ETHER_ADDR_LEN; ++i)
774 sc->arpcom.ac_enaddr[i] = ed_nic_inb(sc, i);
777 * Unmap PROM - select NIC registers. The proper setting of the
778 * tranceiver is set in ed_init so that the attach code is given a
779 * chance to set the default based on a compile-time config option
781 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
784 * Determine if this is an 8bit or 16bit board
788 * select page 0 registers
790 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
793 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
796 ed_nic_outb(sc, ED_P0_DCR, 0);
799 * select page 2 registers
801 ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
804 * The 3c503 forces the WTS bit to a one if this is a 16bit board
806 if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS)
812 * select page 0 registers
814 ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
816 error = ed_alloc_memory(dev, 0, memsize);
820 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
821 sc->mem_size = memsize;
822 sc->mem_end = sc->mem_start + memsize;
825 * We have an entire 8k window to put the transmit buffers on the
826 * 16bit boards. But since the 16bit 3c503's shared memory is only
827 * fast enough to overlap the loading of one full-size packet, trying
828 * to load more than 2 buffers can actually leave the transmitter idle
829 * during the load. So 2 seems the best value. (Although a mix of
830 * variable-sized packets might change this assumption. Nonetheless,
831 * we optimize for linear transfers of same-size packets.)
834 if (flags & ED_FLAGS_NO_MULTI_BUFFERING)
839 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
840 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
841 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
842 ED_3COM_RX_PAGE_OFFSET_16BIT;
843 sc->mem_ring = sc->mem_start;
846 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
847 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
848 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
849 ED_3COM_TX_PAGE_OFFSET_8BIT;
850 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
853 sc->isa16bit = isa16bit;
856 * Initialize GA page start/stop registers. Probably only needed if
857 * doing DMA, but what the hell.
859 ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start);
860 ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop);
863 * Set IRQ. 3c503 only allows a choice of irq 2-5.
865 error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk);
872 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
875 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
878 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
881 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
884 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n",
890 * Initialize GA configuration register. Set bank and enable shared
893 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
897 * Initialize "Vector Pointer" registers. These gawd-awful things are
898 * compared to 20 bits of the address on ISA, and if they match, the
899 * shared memory is disabled. We set them to 0xffff0...allegedly the
902 ed_asic_outb(sc, ED_3COM_VPTR2, 0xff);
903 ed_asic_outb(sc, ED_3COM_VPTR1, 0xff);
904 ed_asic_outb(sc, ED_3COM_VPTR0, 0x00);
907 * Zero memory and verify that it is clear
909 bzero(sc->mem_start, memsize);
911 for (i = 0; i < memsize; ++i)
912 if (sc->mem_start[i]) {
913 device_printf(dev, "failed to clear shared memory at %llx - check configuration\n",
914 (unsigned long long)kvtop(sc->mem_start + i));
921 * Probe and vendor-specific initialization routine for SIC boards
924 ed_probe_SIC(dev, port_rid, flags)
929 struct ed_softc *sc = device_get_softc(dev);
933 u_long conf_maddr, conf_msize;
936 error = ed_alloc_port(dev, 0, ED_SIC_IO_PORTS);
940 sc->asic_offset = ED_SIC_ASIC_OFFSET;
941 sc->nic_offset = ED_SIC_NIC_OFFSET;
943 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
944 &conf_maddr, &conf_msize);
950 memsize = conf_msize;
952 error = ed_alloc_memory(dev, 0, memsize);
956 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
957 sc->mem_size = memsize;
959 /* Reset card to force it into a known state. */
960 ed_asic_outb(sc, 0, 0x00);
964 * Here we check the card ROM, if the checksum passes, and the
965 * type code and ethernet address check out, then we know we have
968 ed_asic_outb(sc, 0, 0x81);
971 sum = sc->mem_start[6];
972 for (i = 0; i < ETHER_ADDR_LEN; i++) {
973 sum ^= (sc->arpcom.ac_enaddr[i] = sc->mem_start[i]);
976 device_printf(dev, "ed_probe_sic: got address %6D\n",
977 sc->arpcom.ac_enaddr, ":");
982 if ((sc->arpcom.ac_enaddr[0] | sc->arpcom.ac_enaddr[1] |
983 sc->arpcom.ac_enaddr[2]) == 0) {
987 sc->vendor = ED_VENDOR_SIC;
988 sc->type_str = "SIC";
993 * SIC RAM page 0x0000-0x3fff(or 0x7fff)
995 ed_asic_outb(sc, 0, 0x80);
999 * Now zero memory and verify that it is clear
1001 bzero(sc->mem_start, sc->mem_size);
1003 for (i = 0; i < sc->mem_size; i++) {
1004 if (sc->mem_start[i]) {
1005 device_printf(dev, "failed to clear shared memory "
1006 "at %llx - check configuration\n",
1007 (long long)kvtop(sc->mem_start + i));
1014 sc->mem_end = sc->mem_start + sc->mem_size;
1017 * allocate one xmit buffer if < 16k, two buffers otherwise
1019 if ((sc->mem_size < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
1024 sc->tx_page_start = 0;
1026 sc->rec_page_start = sc->tx_page_start + ED_TXBUF_SIZE * sc->txb_cnt;
1027 sc->rec_page_stop = sc->tx_page_start + sc->mem_size / ED_PAGE_SIZE;
1029 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1035 * Probe and vendor-specific initialization routine for NE1000/2000 boards
1038 ed_probe_Novell_generic(dev, flags)
1042 struct ed_softc *sc = device_get_softc(dev);
1044 u_char romdata[16], tmp;
1045 static char test_pattern[32] = "THIS is A memory TEST pattern";
1046 char test_buffer[32];
1048 /* XXX - do Novell-specific probe here */
1050 /* Reset the board */
1051 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1052 ed_asic_outb(sc, ED_NOVELL_RESET, 0);
1055 tmp = ed_asic_inb(sc, ED_NOVELL_RESET);
1058 * I don't know if this is necessary; probably cruft leftover from
1059 * Clarkson packet driver code. Doesn't do a thing on the boards I've
1060 * tested. -DG [note that an outb(0x84, 0) seems to work here, and is
1061 * non-invasive...but some boards don't seem to reset and I don't have
1062 * complete documentation on what the 'right' thing to do is...so we
1063 * do the invasive thing for now. Yuck.]
1065 ed_asic_outb(sc, ED_NOVELL_RESET, tmp);
1069 * This is needed because some NE clones apparently don't reset the
1070 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
1071 * - this makes the probe invasive! ...Done against my better
1074 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
1078 /* Make sure that we really have an 8390 based board */
1079 if (!ed_probe_generic8390(sc))
1082 sc->vendor = ED_VENDOR_NOVELL;
1084 sc->cr_proto = ED_CR_RD2;
1087 * Test the ability to read and write to the NIC memory. This has the
1088 * side affect of determining if this is an NE1000 or an NE2000.
1092 * This prevents packets from being stored in the NIC memory when the
1093 * readmem routine turns on the start bit in the CR.
1095 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1097 /* Temporarily initialize DCR for byte operations */
1098 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1100 ed_nic_outb(sc, ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
1101 ed_nic_outb(sc, ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
1106 * Write a test pattern in byte mode. If this fails, then there
1107 * probably isn't any memory at 8k - which likely means that the board
1110 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
1111 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
1113 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1114 sc->type = ED_TYPE_NE1000;
1115 sc->type_str = "NE1000";
1118 /* neither an NE1000 nor a Linksys - try NE2000 */
1119 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
1120 ed_nic_outb(sc, ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
1121 ed_nic_outb(sc, ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1126 * Write a test pattern in word mode. If this also fails, then
1127 * we don't know what this board is.
1129 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1130 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1131 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1132 sc->type = ED_TYPE_NE2000;
1133 sc->type_str = "NE2000";
1140 /* 8k of memory plus an additional 8k if 16bit */
1141 memsize = 8192 + sc->isa16bit * 8192;
1143 #if 0 /* probably not useful - NE boards only come two ways */
1144 /* allow kernel config file overrides */
1145 if (isa_dev->id_msize)
1146 memsize = isa_dev->id_msize;
1149 sc->mem_size = memsize;
1151 /* NIC memory doesn't start at zero on an NE board */
1152 /* The start address is tied to the bus width */
1153 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1154 sc->mem_end = sc->mem_start + memsize;
1155 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1157 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1158 int x, i, mstart = 0, msize = 0;
1159 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1161 for (i = 0; i < ED_PAGE_SIZE; i++)
1164 /* Clear all the memory. */
1165 for (x = 1; x < 256; x++)
1166 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1168 /* Search for the start of RAM. */
1169 for (x = 1; x < 256; x++) {
1170 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1171 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1172 for (i = 0; i < ED_PAGE_SIZE; i++)
1174 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1175 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1176 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1177 mstart = x * ED_PAGE_SIZE;
1178 msize = ED_PAGE_SIZE;
1185 device_printf(dev, "Cannot find start of RAM.\n");
1188 /* Search for the start of RAM. */
1189 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1190 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1191 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1192 for (i = 0; i < ED_PAGE_SIZE; i++)
1194 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1195 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1196 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1197 msize += ED_PAGE_SIZE;
1207 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x);
1210 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize);
1212 sc->mem_size = msize;
1213 sc->mem_start = (caddr_t) mstart;
1214 sc->mem_end = (caddr_t) (msize + mstart);
1215 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1219 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1222 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1227 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1228 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1230 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1232 ed_pio_readmem(sc, 0, romdata, 16);
1233 for (n = 0; n < ETHER_ADDR_LEN; n++)
1234 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1236 if ((ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) &&
1237 (sc->arpcom.ac_enaddr[2] == 0x86)) {
1238 sc->type_str = "Gateway AT";
1241 /* clear any pending interrupts that might have occurred above */
1242 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1248 ed_probe_Novell(dev, port_rid, flags)
1253 struct ed_softc *sc = device_get_softc(dev);
1256 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS);
1260 sc->asic_offset = ED_NOVELL_ASIC_OFFSET;
1261 sc->nic_offset = ED_NOVELL_NIC_OFFSET;
1263 return ed_probe_Novell_generic(dev, flags);
1266 #define ED_HPP_TEST_SIZE 16
1269 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1270 * (HP Part nos: 27247B and 27252A).
1272 * The card has an asic wrapper around a DS8390 core. The asic handles
1273 * host accesses and offers both standard register IO and memory mapped
1274 * IO. Memory mapped I/O allows better performance at the expense of greater
1275 * chance of an incompatibility with existing ISA cards.
1277 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1278 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1279 * don't allow 32 bit accesses; these are indicated by a bit in the software
1280 * ID register (see if_edreg.h).
1282 * Other caveats are: we should read the MAC address only when the card
1285 * For more information; please consult the CRYNWR packet driver.
1287 * The AUI port is turned on using the "link2" option on the ifconfig
1291 ed_probe_HP_pclanp(dev, port_rid, flags)
1296 struct ed_softc *sc = device_get_softc(dev);
1298 int n; /* temp var */
1299 int memsize; /* mem on board */
1300 u_char checksum; /* checksum of board address */
1301 u_char irq; /* board configured IRQ */
1302 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1303 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1304 u_long conf_maddr, conf_msize, conf_irq, junk;
1306 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS);
1310 /* Fill in basic information */
1311 sc->asic_offset = ED_HPP_ASIC_OFFSET;
1312 sc->nic_offset = ED_HPP_NIC_OFFSET;
1314 sc->chip_type = ED_CHIP_TYPE_DP8390;
1315 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1318 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1321 if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) ||
1322 (ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) ||
1323 ((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) ||
1324 (ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53))
1328 * Read the MAC address and verify checksum on the address.
1331 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1332 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1333 checksum += (sc->arpcom.ac_enaddr[n] =
1334 ed_asic_inb(sc, ED_HPP_MAC_ADDR + n));
1336 checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1338 if (checksum != 0xFF)
1342 * Verify that the software model number is 0.
1345 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_ID);
1346 if (((sc->hpp_id = ed_asic_inw(sc, ED_HPP_PAGE_4)) &
1347 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1351 * Read in and save the current options configured on card.
1354 sc->hpp_options = ed_asic_inw(sc, ED_HPP_OPTION);
1356 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1357 ED_HPP_OPTION_CHIP_RESET |
1358 ED_HPP_OPTION_ENABLE_IRQ);
1361 * Reset the chip. This requires writing to the option register
1362 * so take care to preserve the other bits.
1365 ed_asic_outw(sc, ED_HPP_OPTION,
1366 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1367 ED_HPP_OPTION_CHIP_RESET)));
1369 DELAY(5000); /* wait for chip reset to complete */
1371 ed_asic_outw(sc, ED_HPP_OPTION,
1372 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1373 ED_HPP_OPTION_CHIP_RESET |
1374 ED_HPP_OPTION_ENABLE_IRQ)));
1378 if (!(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST))
1379 return ENXIO; /* reset did not complete */
1382 * Read out configuration information.
1385 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1387 irq = ed_asic_inb(sc, ED_HPP_HW_IRQ);
1390 * Check for impossible IRQ.
1393 if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0])))
1397 * If the kernel IRQ was specified with a '?' use the cards idea
1398 * of the IRQ. If the kernel IRQ was explicitly specified, it
1399 * should match that of the hardware.
1401 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
1404 bus_set_resource(dev, SYS_RES_IRQ, 0,
1405 ed_hpp_intr_val[irq], 1);
1407 if (conf_irq != ed_hpp_intr_val[irq])
1412 * Fill in softconfig info.
1415 sc->vendor = ED_VENDOR_HP;
1416 sc->type = ED_TYPE_HP_PCLANPLUS;
1417 sc->type_str = "HP-PCLAN+";
1419 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1420 sc->mem_start = 0; /* we use offsets inside the card RAM */
1422 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1425 * The board has 32KB of memory. Is there a way to determine
1426 * this programmatically?
1432 * Check if memory mapping of the I/O registers possible.
1435 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1440 * determine the memory address from the board.
1443 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1444 mem_addr = (ed_asic_inw(sc, ED_HPP_HW_MEM_MAP) << 8);
1447 * Check that the kernel specified start of memory and
1448 * hardware's idea of it match.
1450 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
1451 &conf_maddr, &conf_msize);
1455 if (mem_addr != conf_maddr)
1458 error = ed_alloc_memory(dev, 0, memsize);
1462 sc->hpp_mem_start = rman_get_virtual(sc->mem_res);
1466 * Fill in the rest of the soft config structure.
1470 * The transmit page index.
1473 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1475 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING)
1481 * Memory description
1484 sc->mem_size = memsize;
1485 sc->mem_ring = sc->mem_start +
1486 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1487 sc->mem_end = sc->mem_start + sc->mem_size;
1490 * Receive area starts after the transmit area and
1491 * continues till the end of memory.
1494 sc->rec_page_start = sc->tx_page_start +
1495 (sc->txb_cnt * ED_TXBUF_SIZE);
1496 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1499 sc->cr_proto = 0; /* value works */
1502 * Set the wrap registers for string I/O reads.
1505 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1506 ed_asic_outw(sc, ED_HPP_HW_WRAP,
1507 ((sc->rec_page_start / ED_PAGE_SIZE) |
1508 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1511 * Reset the register page to normal operation.
1514 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1517 * Verify that we can read/write from adapter memory.
1518 * Create test pattern.
1521 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1523 test_pattern[n] = (n*n) ^ ~n;
1526 #undef ED_HPP_TEST_SIZE
1529 * Check that the memory is accessible thru the I/O ports.
1530 * Write out the contents of "test_pattern", read back
1531 * into "test_buffer" and compare the two for any
1535 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1537 ed_hpp_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1538 sizeof(test_pattern));
1539 ed_hpp_readmem(sc, (n * ED_PAGE_SIZE),
1540 test_buffer, sizeof(test_pattern));
1542 if (bcmp(test_pattern, test_buffer,
1543 sizeof(test_pattern)))
1552 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1556 ed_hpp_set_physical_link(struct ed_softc *sc)
1558 struct ifnet *ifp = &sc->arpcom.ac_if;
1561 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1562 lan_page = ed_asic_inw(sc, ED_HPP_PAGE_0);
1564 if (ifp->if_flags & IFF_ALTPHYS) {
1570 lan_page |= ED_HPP_LAN_AUI;
1572 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1573 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1579 * Use the ThinLan interface
1582 lan_page &= ~ED_HPP_LAN_AUI;
1584 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1585 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1590 * Wait for the lan card to re-initialize itself
1593 DELAY(150000); /* wait 150 ms */
1596 * Restore normal pages.
1599 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1604 * Allocate a port resource with the given resource id.
1607 ed_alloc_port(dev, rid, size)
1612 struct ed_softc *sc = device_get_softc(dev);
1613 struct resource *res;
1615 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1616 0ul, ~0ul, size, RF_ACTIVE);
1620 sc->port_used = size;
1628 * Allocate a memory resource with the given resource id.
1631 ed_alloc_memory(dev, rid, size)
1636 struct ed_softc *sc = device_get_softc(dev);
1637 struct resource *res;
1639 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1640 0ul, ~0ul, size, RF_ACTIVE);
1644 sc->mem_used = size;
1652 * Allocate an irq resource with the given resource id.
1655 ed_alloc_irq(dev, rid, flags)
1660 struct ed_softc *sc = device_get_softc(dev);
1661 struct resource *res;
1663 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
1664 0ul, ~0ul, 1, (RF_ACTIVE | flags));
1675 * Release all resources
1678 ed_release_resources(dev)
1681 struct ed_softc *sc = device_get_softc(dev);
1684 bus_deactivate_resource(dev, SYS_RES_IOPORT,
1685 sc->port_rid, sc->port_res);
1686 bus_release_resource(dev, SYS_RES_IOPORT,
1687 sc->port_rid, sc->port_res);
1691 bus_deactivate_resource(dev, SYS_RES_MEMORY,
1692 sc->mem_rid, sc->mem_res);
1693 bus_release_resource(dev, SYS_RES_MEMORY,
1694 sc->mem_rid, sc->mem_res);
1698 bus_deactivate_resource(dev, SYS_RES_IRQ,
1699 sc->irq_rid, sc->irq_res);
1700 bus_release_resource(dev, SYS_RES_IRQ,
1701 sc->irq_rid, sc->irq_res);
1707 * Install interface into kernel networking data structures
1710 ed_attach(device_t dev)
1712 struct ed_softc *sc = device_get_softc(dev);
1713 struct ifnet *ifp = &sc->arpcom.ac_if;
1715 callout_init(&sc->ed_timer);
1717 * Set interface to stopped condition (reset)
1722 * Initialize ifnet structure
1725 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1726 ifp->if_mtu = ETHERMTU;
1727 ifp->if_start = ed_start;
1728 ifp->if_ioctl = ed_ioctl;
1729 ifp->if_watchdog = ed_watchdog;
1730 ifp->if_init = ed_init;
1731 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1732 ifp->if_linkmib = &sc->mibdata;
1733 ifp->if_linkmiblen = sizeof sc->mibdata;
1734 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1736 * XXX - should do a better job.
1738 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1739 sc->mibdata.dot3StatsEtherChipSet =
1740 DOT3CHIPSET(dot3VendorWesternDigital,
1741 dot3ChipSetWesternDigital83C790);
1743 sc->mibdata.dot3StatsEtherChipSet =
1744 DOT3CHIPSET(dot3VendorNational,
1745 dot3ChipSetNational8390);
1746 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
1749 * Set default state for ALTPHYS flag (used to disable the
1750 * tranceiver for AUI operation), based on compile-time
1753 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER)
1754 ifp->if_flags |= IFF_ALTPHYS;
1757 * Attach the interface
1759 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
1761 /* device attach does transition from UNCONFIGURED to IDLE state */
1763 if (sc->type_str && (*sc->type_str != 0))
1764 printf("type %s ", sc->type_str);
1766 printf("type unknown (0x%x) ", sc->type);
1768 if (sc->vendor == ED_VENDOR_HP)
1769 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
1770 "16-bit" : "32-bit",
1771 sc->hpp_mem_start ? "memory mapped" : "regular");
1773 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
1775 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
1776 (sc->vendor == ED_VENDOR_HP)) &&
1777 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : "");
1789 struct ed_softc *sc = ifp->if_softc;
1797 * Stop interface and re-initialize.
1806 * Take interface offline.
1810 struct ed_softc *sc;
1814 #ifndef ED_NO_MIIBUS
1815 callout_stop(&sc->ed_timer);
1820 * Stop everything on the interface, and select page 0 registers.
1822 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1825 * Wait for interface to enter stopped state, but limit # of checks to
1826 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1827 * just in case it's an old one.
1829 if (sc->chip_type != ED_CHIP_TYPE_AX88190)
1830 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1834 * Device timeout/watchdog routine. Entered if the device neglects to
1835 * generate an interrupt after a transmit has been started on it.
1841 struct ed_softc *sc = ifp->if_softc;
1845 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname);
1851 #ifndef ED_NO_MIIBUS
1856 struct ed_softc *sc = arg;
1857 struct mii_data *mii;
1863 if (sc->miibus != NULL) {
1864 mii = device_get_softc(sc->miibus);
1867 callout_reset(&sc->ed_timer, hz, ed_tick, sc);
1873 * Initialize device.
1879 struct ed_softc *sc = xsc;
1880 struct ifnet *ifp = &sc->arpcom.ac_if;
1886 /* address not known */
1887 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */
1891 * Initialize the NIC in the exact order outlined in the NS manual.
1892 * This init procedure is "mandatory"...don't change what or when
1897 /* reset transmitter flags */
1903 sc->txb_next_tx = 0;
1905 /* This variable is used below - don't move this assignment */
1906 sc->next_packet = sc->rec_page_start + 1;
1909 * Set interface for page 0, Remote DMA complete, Stopped
1911 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1916 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1917 * order=80x86, word-wide DMA xfers,
1919 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1923 * Same as above, but byte-wide DMA xfers
1925 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1929 * Clear Remote Byte Count Registers
1931 ed_nic_outb(sc, ED_P0_RBCR0, 0);
1932 ed_nic_outb(sc, ED_P0_RBCR1, 0);
1935 * For the moment, don't store incoming packets in memory.
1937 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1940 * Place NIC in internal loopback mode
1942 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0);
1945 * Initialize transmit/receive (ring-buffer) Page Start
1947 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start);
1948 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start);
1949 /* Set lower bits of byte addressable framing to 0 */
1950 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1951 ed_nic_outb(sc, 0x09, 0);
1954 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1956 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop);
1957 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start);
1960 * Clear all interrupts. A '1' in each bit position clears the
1961 * corresponding flag.
1963 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1966 * Enable the following interrupts: receive/transmit complete,
1967 * receive/transmit error, and Receiver OverWrite.
1969 * Counter overflow and Remote DMA complete are *not* enabled.
1971 ed_nic_outb(sc, ED_P0_IMR,
1972 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1975 * Program Command Register for page 1
1977 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1980 * Copy out our station address
1982 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1983 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]);
1986 * Set Current Page pointer to next_packet (initialized above)
1988 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet);
1991 * Program Receiver Configuration Register and multicast filter. CR is
1992 * set to page 0 on return.
1997 * Take interface out of loopback
1999 ed_nic_outb(sc, ED_P0_TCR, 0);
2002 * If this is a 3Com board, the tranceiver must be software enabled
2003 * (there is no settable hardware default).
2005 if (sc->vendor == ED_VENDOR_3COM) {
2006 if (ifp->if_flags & IFF_ALTPHYS) {
2007 ed_asic_outb(sc, ED_3COM_CR, 0);
2009 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
2013 #ifndef ED_NO_MIIBUS
2014 if (sc->miibus != NULL) {
2015 struct mii_data *mii;
2016 mii = device_get_softc(sc->miibus);
2021 * Set 'running' flag, and clear output active flag.
2023 ifp->if_flags |= IFF_RUNNING;
2024 ifp->if_flags &= ~IFF_OACTIVE;
2027 * ...and attempt to start output
2031 #ifndef ED_NO_MIIBUS
2032 callout_reset(&sc->ed_timer, hz, ed_tick, sc);
2038 * This routine actually starts the transmission on the interface
2040 static __inline void
2042 struct ed_softc *sc;
2044 struct ifnet *ifp = (struct ifnet *)sc;
2049 len = sc->txb_len[sc->txb_next_tx];
2052 * Set NIC for page 0 register access
2054 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2057 * Set TX buffer start page
2059 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start +
2060 sc->txb_next_tx * ED_TXBUF_SIZE);
2065 ed_nic_outb(sc, ED_P0_TBCR0, len);
2066 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8);
2069 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
2071 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
2075 * Point to next transmit buffer slot and wrap if necessary.
2078 if (sc->txb_next_tx == sc->txb_cnt)
2079 sc->txb_next_tx = 0;
2082 * Set a timer just in case we never hear from the board again
2088 * Start output on interface.
2089 * We make two assumptions here:
2090 * 1) that the current priority is set to splimp _before_ this code
2091 * is called *and* is returned to the appropriate priority after
2093 * 2) that the IFF_OACTIVE flag is checked before this code is called
2094 * (i.e. that the output part of the interface is idle)
2100 struct ed_softc *sc = ifp->if_softc;
2101 struct mbuf *m0, *m;
2106 printf("ed_start(%p) GONE\n",ifp);
2112 * First, see if there are buffered packets and an idle transmitter -
2113 * should never happen at this point.
2115 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
2116 printf("ed: packets buffered, but transmitter idle\n");
2121 * See if there is room to put another packet in the buffer.
2123 if (sc->txb_inuse == sc->txb_cnt) {
2126 * No room. Indicate this to the outside world and exit.
2128 ifp->if_flags |= IFF_OACTIVE;
2131 IF_DEQUEUE(&ifp->if_snd, m);
2135 * We are using the !OACTIVE flag to indicate to the outside
2136 * world that we can accept an additional packet rather than
2137 * that the transmitter is _actually_ active. Indeed, the
2138 * transmitter may be active, but if we haven't filled all the
2139 * buffers with data then we still want to accept more.
2141 ifp->if_flags &= ~IFF_OACTIVE;
2146 * Copy the mbuf chain into the transmit buffer
2151 /* txb_new points to next open buffer slot */
2152 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2154 if (sc->mem_shared) {
2157 * Special case setup for 16 bit boards...
2160 switch (sc->vendor) {
2163 * For 16bit 3Com boards (which have 16k of
2164 * memory), we have the xmit buffers in a
2165 * different page of memory ('page 0') - so
2168 case ED_VENDOR_3COM:
2169 ed_asic_outb(sc, ED_3COM_GACFR,
2170 ED_3COM_GACFR_RSEL);
2174 * Enable 16bit access to shared memory on
2177 case ED_VENDOR_WD_SMC:
2178 ed_asic_outb(sc, ED_WD_LAAR,
2179 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2180 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2181 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
2186 for (len = 0; m != 0; m = m->m_next) {
2187 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2193 * Restore previous shared memory access
2196 switch (sc->vendor) {
2197 case ED_VENDOR_3COM:
2198 ed_asic_outb(sc, ED_3COM_GACFR,
2199 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2201 case ED_VENDOR_WD_SMC:
2202 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2203 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2205 ed_asic_outb(sc, ED_WD_LAAR,
2206 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2211 len = ed_pio_write_mbufs(sc, m, (int)buffer);
2218 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2223 * Point to next buffer slot and wrap if necessary.
2226 if (sc->txb_new == sc->txb_cnt)
2229 if (sc->xmit_busy == 0)
2237 * Loop back to the top to possibly buffer more packets
2243 * Ethernet interface receiver interrupt.
2245 static __inline void
2247 struct ed_softc *sc;
2249 struct ifnet *ifp = &sc->arpcom.ac_if;
2252 struct ed_ring packet_hdr;
2259 * Set NIC to page 1 registers to get 'current' pointer
2261 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2264 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2265 * i.e. it points to where new data has been buffered. The 'CURR'
2266 * (current) register points to the logical end of the ring-buffer -
2267 * i.e. it points to where additional new data will be added. We loop
2268 * here until the logical beginning equals the logical end (or in
2269 * other words, until the ring-buffer is empty).
2271 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) {
2273 /* get pointer to this buffer's header structure */
2274 packet_ptr = sc->mem_ring +
2275 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2278 * The byte count includes a 4 byte header that was added by
2282 packet_hdr = *(struct ed_ring *) packet_ptr;
2284 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2285 sizeof(packet_hdr));
2286 len = packet_hdr.count;
2287 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2288 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2290 * Length is a wild value. There's a good chance that
2291 * this was caused by the NIC being old and buggy.
2292 * The bug is that the length low byte is duplicated in
2293 * the high byte. Try to recalculate the length based on
2294 * the pointer to the next packet.
2297 * NOTE: sc->next_packet is pointing at the current packet.
2299 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2300 if (packet_hdr.next_packet >= sc->next_packet) {
2301 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2303 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2304 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2307 * because buffers are aligned on 256-byte boundary,
2308 * the length computed above is off by 256 in almost
2309 * all cases. Fix it...
2313 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2314 + sizeof(struct ed_ring)))
2315 sc->mibdata.dot3StatsFrameTooLongs++;
2318 * Be fairly liberal about what we allow as a "reasonable" length
2319 * so that a [crufty] packet will make it to BPF (and can thus
2320 * be analyzed). Note that all that is really important is that
2321 * we have a length that will fit into one mbuf cluster or less;
2322 * the upper layer protocols can then figure out the length from
2323 * their own length field(s).
2324 * But make sure that we have at least a full ethernet header
2325 * or we would be unable to call ether_input() later.
2327 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) &&
2328 (len <= MCLBYTES) &&
2329 (packet_hdr.next_packet >= sc->rec_page_start) &&
2330 (packet_hdr.next_packet < sc->rec_page_stop)) {
2334 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2335 len - sizeof(struct ed_ring));
2339 * Really BAD. The ring pointers are corrupted.
2342 "%s: NIC memory corrupt - invalid packet length %d\n",
2343 ifp->if_xname, len);
2350 * Update next packet pointer
2352 sc->next_packet = packet_hdr.next_packet;
2355 * Update NIC boundry pointer - being careful to keep it one
2356 * buffer behind. (as recommended by NS databook)
2358 boundry = sc->next_packet - 1;
2359 if (boundry < sc->rec_page_start)
2360 boundry = sc->rec_page_stop - 1;
2363 * Set NIC to page 0 registers to update boundry register
2365 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2367 ed_nic_outb(sc, ED_P0_BNRY, boundry);
2370 * Set NIC to page 1 registers before looping to top (prepare
2371 * to get 'CURR' current pointer)
2373 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2378 * Ethernet interface interrupt processor
2384 struct ed_softc *sc = (struct ed_softc*) arg;
2385 struct ifnet *ifp = (struct ifnet *)sc;
2392 * Set NIC to page 0 registers
2394 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2397 * loop until there are no more new interrupts. When the card
2398 * goes away, the hardware will read back 0xff. Looking at
2399 * the interrupts, it would appear that 0xff is impossible,
2400 * or at least extremely unlikely.
2402 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) {
2405 * reset all the bits that we are 'acknowledging' by writing a
2406 * '1' to each bit position that was set (writing a '1'
2409 ed_nic_outb(sc, ED_P0_ISR, isr);
2412 * XXX workaround for AX88190
2413 * We limit this to 5000 iterations. At 1us per inb/outb,
2414 * this translates to about 15ms, which should be plenty
2415 * of time, and also gives protection in the card eject
2418 if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
2419 count = 5000; /* 15ms */
2420 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) {
2421 ed_nic_outb(sc, ED_P0_ISR,0);
2422 ed_nic_outb(sc, ED_P0_ISR,isr);
2429 * Handle transmitter interrupts. Handle these first because
2430 * the receiver will reset the board under some conditions.
2432 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2433 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f;
2436 * Check for transmit error. If a TX completed with an
2437 * error, we end up throwing the packet away. Really
2438 * the only error that is possible is excessive
2439 * collisions, and in this case it is best to allow
2440 * the automatic mechanisms of TCP to backoff the
2441 * flow. Of course, with UDP we're screwed, but this
2442 * is expected when a network is heavily loaded.
2444 (void) ed_nic_inb(sc, ED_P0_TSR);
2445 if (isr & ED_ISR_TXE) {
2449 * Excessive collisions (16)
2451 tsr = ed_nic_inb(sc, ED_P0_TSR);
2452 if ((tsr & ED_TSR_ABT)
2453 && (collisions == 0)) {
2456 * When collisions total 16, the
2457 * P0_NCR will indicate 0, and the
2461 sc->mibdata.dot3StatsExcessiveCollisions++;
2462 sc->mibdata.dot3StatsCollFrequencies[15]++;
2464 if (tsr & ED_TSR_OWC)
2465 sc->mibdata.dot3StatsLateCollisions++;
2466 if (tsr & ED_TSR_CDH)
2467 sc->mibdata.dot3StatsSQETestErrors++;
2468 if (tsr & ED_TSR_CRS)
2469 sc->mibdata.dot3StatsCarrierSenseErrors++;
2470 if (tsr & ED_TSR_FU)
2471 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2474 * update output errors counter
2480 * Update total number of successfully
2481 * transmitted packets.
2487 * reset tx busy and output active flags
2490 ifp->if_flags &= ~IFF_OACTIVE;
2493 * clear watchdog timer
2498 * Add in total number of collisions on last
2501 ifp->if_collisions += collisions;
2502 switch(collisions) {
2507 sc->mibdata.dot3StatsSingleCollisionFrames++;
2508 sc->mibdata.dot3StatsCollFrequencies[0]++;
2511 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2513 dot3StatsCollFrequencies[collisions-1]
2519 * Decrement buffer in-use count if not zero (can only
2520 * be zero if a transmitter interrupt occured while
2521 * not actually transmitting). If data is ready to
2522 * transmit, start it transmitting, otherwise defer
2523 * until after handling receiver
2525 if (sc->txb_inuse && --sc->txb_inuse)
2530 * Handle receiver interrupts
2532 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2535 * Overwrite warning. In order to make sure that a
2536 * lockup of the local DMA hasn't occurred, we reset
2537 * and re-init the NIC. The NSC manual suggests only a
2538 * partial reset/re-init is necessary - but some chips
2539 * seem to want more. The DMA lockup has been seen
2540 * only with early rev chips - Methinks this bug was
2541 * fixed in later revs. -DG
2543 if (isr & ED_ISR_OVW) {
2547 "%s: warning - receiver ring buffer overrun\n",
2552 * Stop/reset/re-init NIC
2558 * Receiver Error. One or more of: CRC error,
2559 * frame alignment error FIFO overrun, or
2562 if (isr & ED_ISR_RXE) {
2564 rsr = ed_nic_inb(sc, ED_P0_RSR);
2565 if (rsr & ED_RSR_CRC)
2566 sc->mibdata.dot3StatsFCSErrors++;
2567 if (rsr & ED_RSR_FAE)
2568 sc->mibdata.dot3StatsAlignmentErrors++;
2569 if (rsr & ED_RSR_FO)
2570 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2573 if_printf("receive error %x\n",
2574 ed_nic_inb(sc, ED_P0_RSR));
2579 * Go get the packet(s) XXX - Doing this on an
2580 * error is dubious because there shouldn't be
2581 * any data to get (we've configured the
2582 * interface to not accept packets with
2587 * Enable 16bit access to shared memory first
2591 (sc->vendor == ED_VENDOR_WD_SMC)) {
2593 ed_asic_outb(sc, ED_WD_LAAR,
2594 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2595 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2596 ed_asic_outb(sc, ED_WD_MSR,
2602 /* disable 16bit access */
2604 (sc->vendor == ED_VENDOR_WD_SMC)) {
2606 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2607 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2609 ed_asic_outb(sc, ED_WD_LAAR,
2610 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2616 * If it looks like the transmitter can take more data,
2617 * attempt to start output on the interface. This is done
2618 * after handling the receiver to give the receiver priority.
2620 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2624 * return NIC CR to standard state: page 0, remote DMA
2625 * complete, start (toggling the TXP bit off, even if was just
2626 * set in the transmit routine, is *okay* - it is 'edge'
2627 * triggered from low to high)
2629 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2632 * If the Network Talley Counters overflow, read them to reset
2633 * them. It appears that old 8390's won't clear the ISR flag
2634 * otherwise - resulting in an infinite loop.
2636 if (isr & ED_ISR_CNT) {
2637 (void) ed_nic_inb(sc, ED_P0_CNTR0);
2638 (void) ed_nic_inb(sc, ED_P0_CNTR1);
2639 (void) ed_nic_inb(sc, ED_P0_CNTR2);
2645 * Process an ioctl request. This code needs some work - it looks
2649 ed_ioctl(ifp, command, data, cr)
2655 struct ed_softc *sc = ifp->if_softc;
2656 #ifndef ED_NO_MIIBUS
2657 struct ifreq *ifr = (struct ifreq *)data;
2658 struct mii_data *mii;
2662 if (sc == NULL || sc->gone) {
2663 ifp->if_flags &= ~IFF_RUNNING;
2673 error = ether_ioctl(ifp, command, data);
2679 * If the interface is marked up and stopped, then start it.
2680 * If it is marked down and running, then stop it.
2682 if (ifp->if_flags & IFF_UP) {
2683 if ((ifp->if_flags & IFF_RUNNING) == 0)
2686 if (ifp->if_flags & IFF_RUNNING) {
2688 ifp->if_flags &= ~IFF_RUNNING;
2693 * Promiscuous flag may have changed, so reprogram the RCR.
2698 * An unfortunate hack to provide the (required) software
2699 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2700 * disables the tranceiver if set.
2702 if (sc->vendor == ED_VENDOR_3COM) {
2703 if (ifp->if_flags & IFF_ALTPHYS) {
2704 ed_asic_outb(sc, ED_3COM_CR, 0);
2706 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
2708 } else if (sc->vendor == ED_VENDOR_HP)
2709 ed_hpp_set_physical_link(sc);
2715 * Multicast list has changed; set the hardware filter
2722 #ifndef ED_NO_MIIBUS
2725 if (sc->miibus == NULL) {
2729 mii = device_get_softc(sc->miibus);
2730 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2742 * Given a source and destination address, copy 'amount' of a packet from
2743 * the ring buffer into a linear destination buffer. Takes into account
2746 static __inline char *
2747 ed_ring_copy(sc, src, dst, amount)
2748 struct ed_softc *sc;
2755 /* does copy wrap to lower addr in ring buffer? */
2756 if (src + amount > sc->mem_end) {
2757 tmp_amount = sc->mem_end - src;
2759 /* copy amount up to end of NIC memory */
2761 bcopy(src, dst, tmp_amount);
2763 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2765 amount -= tmp_amount;
2770 bcopy(src, dst, amount);
2772 ed_pio_readmem(sc, (int)src, dst, amount);
2774 return (src + amount);
2778 * Retreive packet from shared memory and send to the next level up via
2782 ed_get_packet(sc, buf, len)
2783 struct ed_softc *sc;
2787 struct ifnet *ifp = &sc->arpcom.ac_if;
2788 struct ether_header *eh;
2791 /* Allocate a header mbuf */
2792 MGETHDR(m, MB_DONTWAIT, MT_DATA);
2795 m->m_pkthdr.rcvif = ifp;
2796 m->m_pkthdr.len = m->m_len = len;
2799 * We always put the received packet in a single buffer -
2800 * either with just an mbuf header or in a cluster attached
2801 * to the header. The +2 is to compensate for the alignment
2804 if ((len + 2) > MHLEN) {
2805 /* Attach an mbuf cluster */
2806 MCLGET(m, MB_DONTWAIT);
2808 /* Insist on getting a cluster */
2809 if ((m->m_flags & M_EXT) == 0) {
2816 * The +2 is to longword align the start of the real packet.
2817 * This is important for NFS.
2820 eh = mtod(m, struct ether_header *);
2823 * Don't read in the entire packet if we know we're going to drop it
2824 * and no bpf is active.
2826 if (!ifp->if_bpf && BDG_ACTIVE( (ifp) ) ) {
2829 ed_ring_copy(sc, buf, (char *)eh, ETHER_HDR_LEN);
2830 bif = bridge_in_ptr(ifp, eh) ;
2831 if (bif == BDG_DROP) {
2835 if (len > ETHER_HDR_LEN)
2836 ed_ring_copy(sc, buf + ETHER_HDR_LEN,
2837 (char *)(eh + 1), len - ETHER_HDR_LEN);
2840 * Get packet, including link layer address, from interface.
2842 ed_ring_copy(sc, buf, (char *)eh, len);
2844 m->m_pkthdr.len = m->m_len = len;
2846 (*ifp->if_input)(ifp, m);
2850 * Supporting routines
2854 * Given a NIC memory source address and a host memory destination
2855 * address, copy 'amount' from NIC to host using Programmed I/O.
2856 * The 'amount' is rounded up to a word - okay as long as mbufs
2858 * This routine is currently Novell-specific.
2861 ed_pio_readmem(sc, src, dst, amount)
2862 struct ed_softc *sc;
2865 unsigned short amount;
2867 /* HP PC Lan+ cards need special handling */
2868 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2869 ed_hpp_readmem(sc, src, dst, amount);
2873 /* Regular Novell cards */
2874 /* select page 0 registers */
2875 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2877 /* round up to a word */
2881 /* set up DMA byte count */
2882 ed_nic_outb(sc, ED_P0_RBCR0, amount);
2883 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8);
2885 /* set up source address in NIC mem */
2886 ed_nic_outb(sc, ED_P0_RSAR0, src);
2887 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8);
2889 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2892 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2);
2894 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount);
2899 * Stripped down routine for writing a linear buffer to NIC memory.
2900 * Only used in the probe routine to test the memory. 'len' must
2904 ed_pio_writemem(sc, src, dst, len)
2905 struct ed_softc *sc;
2910 int maxwait = 200; /* about 240us */
2912 /* select page 0 registers */
2913 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2915 /* reset remote DMA complete flag */
2916 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2918 /* set up DMA byte count */
2919 ed_nic_outb(sc, ED_P0_RBCR0, len);
2920 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8);
2922 /* set up destination address in NIC mem */
2923 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2924 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2926 /* set remote DMA write */
2927 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2930 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2);
2932 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len);
2936 * Wait for remote DMA complete. This is necessary because on the
2937 * transmit side, data is handled internally by the NIC in bursts and
2938 * we can't start another remote DMA until this one completes. Not
2939 * waiting causes really bad things to happen - like the NIC
2940 * irrecoverably jamming the ISA bus.
2942 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2946 * Write an mbuf chain to the destination NIC memory address using
2950 ed_pio_write_mbufs(sc, m, dst)
2951 struct ed_softc *sc;
2955 struct ifnet *ifp = (struct ifnet *)sc;
2956 unsigned short total_len, dma_len;
2958 int maxwait = 200; /* about 240us */
2960 /* HP PC Lan+ cards need special handling */
2961 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2962 return ed_hpp_write_mbufs(sc, m, dst);
2965 /* Regular Novell cards */
2966 /* First, count up the total number of bytes to copy */
2967 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2968 total_len += mp->m_len;
2970 dma_len = total_len;
2971 if (sc->isa16bit && (dma_len & 1))
2974 /* select page 0 registers */
2975 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2977 /* reset remote DMA complete flag */
2978 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2980 /* set up DMA byte count */
2981 ed_nic_outb(sc, ED_P0_RBCR0, dma_len);
2982 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8);
2984 /* set up destination address in NIC mem */
2985 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2986 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2988 /* set remote DMA write */
2989 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2992 * Transfer the mbuf chain to the NIC memory.
2993 * 16-bit cards require that data be transferred as words, and only words.
2994 * So that case requires some extra code to patch over odd-length mbufs.
2997 if (!sc->isa16bit) {
2998 /* NE1000s are easy */
3001 ed_asic_outsb(sc, ED_NOVELL_DATA,
3002 m->m_data, m->m_len);
3007 /* NE2000s are a pain */
3008 unsigned char *data;
3010 unsigned char savebyte[2];
3017 data = mtod(m, caddr_t);
3018 /* finish the last word */
3020 savebyte[1] = *data;
3021 ed_asic_outw(sc, ED_NOVELL_DATA,
3022 *(u_short *)savebyte);
3027 /* output contiguous words */
3029 ed_asic_outsw(sc, ED_NOVELL_DATA,
3034 /* save last byte, if necessary */
3036 savebyte[0] = *data;
3042 /* spit last byte */
3044 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte);
3049 * Wait for remote DMA complete. This is necessary because on the
3050 * transmit side, data is handled internally by the NIC in bursts and
3051 * we can't start another remote DMA until this one completes. Not
3052 * waiting causes really bad things to happen - like the NIC
3053 * irrecoverably jamming the ISA bus.
3055 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
3058 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n",
3067 * Support routines to handle the HP PC Lan+ card.
3071 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
3076 ed_hpp_readmem(sc, src, dst, amount)
3077 struct ed_softc *sc;
3080 unsigned short amount;
3083 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3086 /* Program the source address in RAM */
3087 ed_asic_outw(sc, ED_HPP_PAGE_2, src);
3090 * The HP PC Lan+ card supports word reads as well as
3091 * a memory mapped i/o port that is aliased to every
3092 * even address on the board.
3095 if (sc->hpp_mem_start) {
3097 /* Enable memory mapped access. */
3098 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3099 ~(ED_HPP_OPTION_MEM_DISABLE |
3100 ED_HPP_OPTION_BOOT_ROM_ENB));
3102 if (use_32bit_access && (amount > 3)) {
3103 u_int32_t *dl = (u_int32_t *) dst;
3104 volatile u_int32_t *const sl =
3105 (u_int32_t *) sc->hpp_mem_start;
3106 u_int32_t *const fence = dl + (amount >> 2);
3108 /* Copy out NIC data. We could probably write this
3109 as a `movsl'. The currently generated code is lousy.
3115 dst += (amount & ~3);
3120 /* Finish off any words left, as a series of short reads */
3122 u_short *d = (u_short *) dst;
3123 volatile u_short *const s =
3124 (u_short *) sc->hpp_mem_start;
3125 u_short *const fence = d + (amount >> 1);
3127 /* Copy out NIC data. */
3132 dst += (amount & ~1);
3137 * read in a byte; however we need to always read 16 bits
3138 * at a time or the hardware gets into a funny state
3142 /* need to read in a short and copy LSB */
3143 volatile u_short *const s =
3144 (volatile u_short *) sc->hpp_mem_start;
3149 /* Restore Boot ROM access. */
3151 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3155 /* Read in data using the I/O port */
3156 if (use_32bit_access && (amount > 3)) {
3157 ed_asic_insl(sc, ED_HPP_PAGE_4, dst, amount >> 2);
3158 dst += (amount & ~3);
3162 ed_asic_insw(sc, ED_HPP_PAGE_4, dst, amount >> 1);
3163 dst += (amount & ~1);
3166 if (amount == 1) { /* read in a short and keep the LSB */
3167 *dst = ed_asic_inw(sc, ED_HPP_PAGE_4) & 0xFF;
3173 * HP PC Lan+: Write to NIC memory, using either PIO or memory mapped
3175 * Only used in the probe routine to test the memory. 'len' must
3179 ed_hpp_writemem(sc, src, dst, len)
3180 struct ed_softc *sc;
3185 /* reset remote DMA complete flag */
3186 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3188 /* program the write address in RAM */
3189 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3191 if (sc->hpp_mem_start) {
3192 u_short *s = (u_short *) src;
3193 volatile u_short *d = (u_short *) sc->hpp_mem_start;
3194 u_short *const fence = s + (len >> 1);
3197 * Enable memory mapped access.
3200 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3201 ~(ED_HPP_OPTION_MEM_DISABLE |
3202 ED_HPP_OPTION_BOOT_ROM_ENB));
3205 * Copy to NIC memory.
3212 * Restore Boot ROM access.
3215 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3218 /* write data using I/O writes */
3219 ed_asic_outsw(sc, ED_HPP_PAGE_4, src, len / 2);
3224 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3225 * outsw() or via the memory mapped interface to the same register.
3226 * Writes have to be in word units; byte accesses won't work and may cause
3227 * the NIC to behave weirdly. Long word accesses are permitted if the ASIC
3232 ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3235 unsigned short total_len;
3236 unsigned char savebyte[2];
3237 volatile u_short * const d =
3238 (volatile u_short *) sc->hpp_mem_start;
3239 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3241 /* select page 0 registers */
3242 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3244 /* reset remote DMA complete flag */
3245 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3247 /* program the write address in RAM */
3248 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3250 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3251 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3252 ~(ED_HPP_OPTION_MEM_DISABLE |
3253 ED_HPP_OPTION_BOOT_ROM_ENB));
3258 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3260 total_len += (len = m->m_len);
3262 caddr_t data = mtod(m, caddr_t);
3263 /* finish the last word of the previous mbuf */
3265 savebyte[1] = *data;
3266 *d = *((u_short *) savebyte);
3267 data++; len--; wantbyte = 0;
3269 /* output contiguous words */
3270 if ((len > 3) && (use_32bit_accesses)) {
3271 volatile u_int32_t *const dl =
3272 (volatile u_int32_t *) d;
3273 u_int32_t *sl = (u_int32_t *) data;
3274 u_int32_t *fence = sl + (len >> 2);
3282 /* finish off remain 16 bit writes */
3284 u_short *s = (u_short *) data;
3285 u_short *fence = s + (len >> 1);
3293 /* save last byte if needed */
3294 if ((wantbyte = (len == 1)) != 0)
3295 savebyte[0] = *data;
3297 m = m->m_next; /* to next mbuf */
3299 if (wantbyte) /* write last byte */
3300 *d = *((u_short *) savebyte);
3302 /* use programmed I/O */
3304 total_len += (len = m->m_len);
3306 caddr_t data = mtod(m, caddr_t);
3307 /* finish the last word of the previous mbuf */
3309 savebyte[1] = *data;
3310 ed_asic_outw(sc, ED_HPP_PAGE_4,
3311 *((u_short *)savebyte));
3316 /* output contiguous words */
3317 if ((len > 3) && use_32bit_accesses) {
3318 ed_asic_outsl(sc, ED_HPP_PAGE_4,
3323 /* finish off remaining 16 bit accesses */
3325 ed_asic_outsw(sc, ED_HPP_PAGE_4,
3330 if ((wantbyte = (len == 1)) != 0)
3331 savebyte[0] = *data;
3336 if (wantbyte) /* spit last byte */
3337 ed_asic_outw(sc, ED_HPP_PAGE_4, *(u_short *)savebyte);
3341 if (sc->hpp_mem_start) /* turn off memory mapped i/o */
3342 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3347 #ifndef ED_NO_MIIBUS
3349 * MII bus support routines.
3352 ed_miibus_readreg(dev, phy, reg)
3356 struct ed_softc *sc;
3360 sc = device_get_softc(dev);
3366 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3367 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3368 (*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS);
3369 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3370 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3372 failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS);
3373 val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS);
3374 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3377 return (failed ? 0 : val);
3381 ed_miibus_writereg(dev, phy, reg, data)
3385 struct ed_softc *sc;
3389 sc = device_get_softc(dev);
3395 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3396 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3397 (*sc->mii_writebits)(sc, ED_MII_WRITEOP, ED_MII_OP_BITS);
3398 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3399 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3400 (*sc->mii_writebits)(sc, ED_MII_TURNAROUND, ED_MII_TURNAROUND_BITS);
3401 (*sc->mii_writebits)(sc, data, ED_MII_DATA_BITS);
3402 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3411 struct ed_softc *sc;
3412 struct mii_data *mii;
3415 if (sc->gone || sc->miibus == NULL)
3418 mii = device_get_softc(sc->miibus);
3419 return mii_mediachg(mii);
3423 ed_ifmedia_sts(ifp, ifmr)
3425 struct ifmediareq *ifmr;
3427 struct ed_softc *sc;
3428 struct mii_data *mii;
3431 if (sc->gone || sc->miibus == NULL)
3434 mii = device_get_softc(sc->miibus);
3436 ifmr->ifm_active = mii->mii_media_active;
3437 ifmr->ifm_status = mii->mii_media_status;
3441 ed_child_detached(dev, child)
3445 struct ed_softc *sc;
3447 sc = device_get_softc(dev);
3448 if (child == sc->miibus)
3455 struct ed_softc *sc;
3457 struct ifnet *ifp = (struct ifnet *)sc;
3461 /* Bit 6 in AX88190 RCR register must be set. */
3462 if (sc->chip_type == ED_CHIP_TYPE_AX88190)
3467 /* set page 1 registers */
3468 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
3470 if (ifp->if_flags & IFF_PROMISC) {
3473 * Reconfigure the multicast filter.
3475 for (i = 0; i < 8; i++)
3476 ed_nic_outb(sc, ED_P1_MAR(i), 0xff);
3479 * And turn on promiscuous mode. Also enable reception of
3480 * runts and packets with CRC & alignment errors.
3482 /* Set page 0 registers */
3483 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3485 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
3486 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1);
3488 /* set up multicast addresses and filter modes */
3489 if (ifp->if_flags & IFF_MULTICAST) {
3492 if (ifp->if_flags & IFF_ALLMULTI) {
3493 mcaf[0] = 0xffffffff;
3494 mcaf[1] = 0xffffffff;
3496 ds_getmcaf(sc, mcaf);
3499 * Set multicast filter on chip.
3501 for (i = 0; i < 8; i++)
3502 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]);
3504 /* Set page 0 registers */
3505 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3507 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1);
3511 * Initialize multicast address hashing registers to
3512 * not accept multicasts.
3514 for (i = 0; i < 8; ++i)
3515 ed_nic_outb(sc, ED_P1_MAR(i), 0x00);
3517 /* Set page 0 registers */
3518 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3520 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1);
3527 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3531 * Compute crc for ethernet address
3535 const uint8_t *addr;
3537 #define ED_POLYNOMIAL 0x04c11db6
3538 uint32_t crc = 0xffffffff;
3539 int carry, idx, bit;
3542 for (idx = 6; --idx >= 0;) {
3543 for (data = *addr++, bit = 8; --bit >= 0; data >>=1 ) {
3544 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01);
3547 crc = (crc ^ ED_POLYNOMIAL) | carry;
3555 * Compute the multicast address filter from the
3556 * list of multicast addresses we need to listen to.
3559 ds_getmcaf(sc, mcaf)
3560 struct ed_softc *sc;
3564 u_char *af = (u_char *) mcaf;
3565 struct ifmultiaddr *ifma;
3570 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma;
3571 ifma = ifma->ifma_link.le_next) {
3572 if (ifma->ifma_addr->sa_family != AF_LINK)
3574 index = ds_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr))
3576 af[index >> 3] |= 1 << (index & 7);