2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/dev/tx/if_tx.c,v 1.61.2.1 2002/10/29 01:43:49 semenu Exp $
27 * $DragonFly: src/sys/dev/netif/tx/if_tx.c,v 1.4 2003/08/07 21:17:06 dillon Exp $
31 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie)
33 * These cards are based on SMC83c17x (EPIC) chip and one of the various
34 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on
35 * card model. All cards support 10baseT/UTP and 100baseTX half- and full-
36 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also
37 * supports fibre optics.
39 * Thanks are going to Steve Bauer and Jason Wright.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/sockio.h>
46 #include <sys/malloc.h>
47 #include <sys/kernel.h>
48 #include <sys/socket.h>
49 #include <sys/queue.h>
52 #include <net/if_arp.h>
53 #include <net/ethernet.h>
54 #include <net/if_dl.h>
55 #include <net/if_media.h>
59 #include <net/vlan/if_vlan_var.h>
61 #include <vm/vm.h> /* for vtophys */
62 #include <vm/pmap.h> /* for vtophys */
63 #include <machine/bus_memio.h>
64 #include <machine/bus_pio.h>
65 #include <machine/bus.h>
66 #include <machine/resource.h>
67 #include <machine/clock.h> /* for DELAY */
71 #include <bus/pci/pcireg.h>
72 #include <bus/pci/pcivar.h>
74 #include "../mii_layer/mii.h"
75 #include "../mii_layer/miivar.h"
76 #include "../mii_layer/miidevs.h"
77 #include "../mii_layer/lxtphyreg.h"
79 #include "miibus_if.h"
84 MODULE_DEPEND(tx, miibus, 1, 1, 1);
86 static int epic_ifioctl(struct ifnet *, u_long, caddr_t);
87 static void epic_intr(void *);
88 static void epic_tx_underrun(epic_softc_t *);
89 static int epic_common_attach(epic_softc_t *);
90 static void epic_ifstart(struct ifnet *);
91 static void epic_ifwatchdog(struct ifnet *);
92 static void epic_stats_update(epic_softc_t *);
93 static int epic_init(epic_softc_t *);
94 static void epic_stop(epic_softc_t *);
95 static void epic_rx_done(epic_softc_t *);
96 static void epic_tx_done(epic_softc_t *);
97 static int epic_init_rings(epic_softc_t *);
98 static void epic_free_rings(epic_softc_t *);
99 static void epic_stop_activity(epic_softc_t *);
100 static int epic_queue_last_packet(epic_softc_t *);
101 static void epic_start_activity(epic_softc_t *);
102 static void epic_set_rx_mode(epic_softc_t *);
103 static void epic_set_tx_mode(epic_softc_t *);
104 static void epic_set_mc_table(epic_softc_t *);
105 static u_int8_t epic_calchash(caddr_t);
106 static int epic_read_eeprom(epic_softc_t *,u_int16_t);
107 static void epic_output_eepromw(epic_softc_t *, u_int16_t);
108 static u_int16_t epic_input_eepromw(epic_softc_t *);
109 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t);
110 static void epic_write_eepromreg(epic_softc_t *,u_int8_t);
111 static u_int8_t epic_read_eepromreg(epic_softc_t *);
113 static int epic_read_phy_reg(epic_softc_t *, int, int);
114 static void epic_write_phy_reg(epic_softc_t *, int, int, int);
116 static int epic_miibus_readreg(device_t, int, int);
117 static int epic_miibus_writereg(device_t, int, int, int);
118 static void epic_miibus_statchg(device_t);
119 static void epic_miibus_mediainit(device_t);
121 static int epic_ifmedia_upd(struct ifnet *);
122 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *);
124 static int epic_probe(device_t);
125 static int epic_attach(device_t);
126 static void epic_shutdown(device_t);
127 static int epic_detach(device_t);
128 static struct epic_type *epic_devtype(device_t);
130 static device_method_t epic_methods[] = {
131 /* Device interface */
132 DEVMETHOD(device_probe, epic_probe),
133 DEVMETHOD(device_attach, epic_attach),
134 DEVMETHOD(device_detach, epic_detach),
135 DEVMETHOD(device_shutdown, epic_shutdown),
138 DEVMETHOD(miibus_readreg, epic_miibus_readreg),
139 DEVMETHOD(miibus_writereg, epic_miibus_writereg),
140 DEVMETHOD(miibus_statchg, epic_miibus_statchg),
141 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit),
146 static driver_t epic_driver = {
152 static devclass_t epic_devclass;
154 DRIVER_MODULE(if_tx, pci, epic_driver, epic_devclass, 0, 0);
155 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0);
157 static struct epic_type epic_devs[] = {
158 { SMC_VENDORID, SMC_DEVICEID_83C170,
159 "SMC EtherPower II 10/100" },
169 t = epic_devtype(dev);
172 device_set_desc(dev, t->name);
179 static struct epic_type *
187 while(t->name != NULL) {
188 if ((pci_get_vendor(dev) == t->ven_id) &&
189 (pci_get_device(dev) == t->dev_id)) {
197 #if defined(EPIC_USEIOSPACE)
198 #define EPIC_RES SYS_RES_IOPORT
199 #define EPIC_RID PCIR_BASEIO
201 #define EPIC_RES SYS_RES_MEMORY
202 #define EPIC_RID PCIR_BASEMEM
206 * Attach routine: map registers, allocate softc, rings and descriptors.
207 * Reset to known state.
221 sc = device_get_softc(dev);
222 unit = device_get_unit(dev);
224 /* Preinitialize softc structure */
225 bzero(sc, sizeof(epic_softc_t));
229 /* Fill ifnet structure */
234 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST;
235 ifp->if_ioctl = epic_ifioctl;
236 ifp->if_output = ether_output;
237 ifp->if_start = epic_ifstart;
238 ifp->if_watchdog = epic_ifwatchdog;
239 ifp->if_init = (if_init_f_t*)epic_init;
241 ifp->if_baudrate = 10000000;
242 ifp->if_snd.ifq_maxlen = TX_RING_SIZE - 1;
244 /* Enable ports, memory and busmastering */
245 command = pci_read_config(dev, PCIR_COMMAND, 4);
246 command |= PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
247 pci_write_config(dev, PCIR_COMMAND, command, 4);
248 command = pci_read_config(dev, PCIR_COMMAND, 4);
250 #if defined(EPIC_USEIOSPACE)
251 if ((command & PCIM_CMD_PORTEN) == 0) {
252 device_printf(dev, "failed to enable I/O mapping!\n");
257 if ((command & PCIM_CMD_MEMEN) == 0) {
258 device_printf(dev, "failed to enable memory mapping!\n");
265 sc->res = bus_alloc_resource(dev, EPIC_RES, &rid, 0, ~0, 1,
268 if (sc->res == NULL) {
269 device_printf(dev, "couldn't map ports/memory\n");
274 sc->sc_st = rman_get_bustag(sc->res);
275 sc->sc_sh = rman_get_bushandle(sc->res);
277 /* Allocate interrupt */
279 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
280 RF_SHAREABLE | RF_ACTIVE);
282 if (sc->irq == NULL) {
283 device_printf(dev, "couldn't map interrupt\n");
284 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
289 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
290 epic_intr, sc, &sc->sc_ih);
293 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
294 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
295 device_printf(dev, "couldn't set up irq\n");
299 /* Do OS independent part, including chip wakeup and reset */
300 error = epic_common_attach(sc);
302 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
303 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
304 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
309 /* Do ifmedia setup */
310 if (mii_phy_probe(dev, &sc->miibus,
311 epic_ifmedia_upd, epic_ifmedia_sts)) {
312 device_printf(dev, "ERROR! MII without any PHY!?\n");
313 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
314 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
315 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
320 /* Display ethernet address ,... */
321 device_printf(dev, "address %6D,", sc->sc_macaddr, ":");
323 /* board type and ... */
325 for(i=0x2c;i<0x32;i++) {
326 tmp = epic_read_eeprom(sc, i);
327 if (' ' == (u_int8_t)tmp) break;
328 printf("%c", (u_int8_t)tmp);
330 if (' ' == (u_int8_t)tmp) break;
331 printf("%c", (u_int8_t)tmp);
335 /* Attach to OS's managers */
336 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
337 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
338 callout_handle_init(&sc->stat_ch);
347 * Detach driver and free resources
359 sc = device_get_softc(dev);
360 ifp = &sc->arpcom.ac_if;
362 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
366 bus_generic_detach(dev);
367 device_delete_child(dev, sc->miibus);
369 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
370 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
371 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
373 free(sc->tx_flist, M_DEVBUF);
374 free(sc->tx_desc, M_DEVBUF);
375 free(sc->rx_desc, M_DEVBUF);
386 * Stop all chip I/O so that the kernel's probe routines don't
387 * get confused by errant DMAs when rebooting.
395 sc = device_get_softc(dev);
403 * This is if_ioctl handler.
406 epic_ifioctl(ifp, command, data)
411 epic_softc_t *sc = ifp->if_softc;
412 struct mii_data *mii;
413 struct ifreq *ifr = (struct ifreq *) data;
421 error = ether_ioctl(ifp, command, data);
424 if (ifp->if_mtu == ifr->ifr_mtu)
427 /* XXX Though the datasheet doesn't imply any
428 * limitations on RX and TX sizes beside max 64Kb
429 * DMA transfer, seems we can't send more then 1600
430 * data bytes per ethernet packet. (Transmitter hangs
431 * up if more data is sent)
433 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) {
434 ifp->if_mtu = ifr->ifr_mtu;
443 * If the interface is marked up and stopped, then start it.
444 * If it is marked down and running, then stop it.
446 if (ifp->if_flags & IFF_UP) {
447 if ((ifp->if_flags & IFF_RUNNING) == 0) {
452 if (ifp->if_flags & IFF_RUNNING) {
458 /* Handle IFF_PROMISC and IFF_ALLMULTI flags */
459 epic_stop_activity(sc);
460 epic_set_mc_table(sc);
461 epic_set_rx_mode(sc);
462 epic_start_activity(sc);
467 epic_set_mc_table(sc);
473 mii = device_get_softc(sc->miibus);
474 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
486 * OS-independed part of attach process. allocate memory for descriptors
487 * and frag lists, wake up chip, read MAC address and PHY identyfier.
488 * Return -1 on failure.
491 epic_common_attach(sc)
496 sc->tx_flist = malloc(sizeof(struct epic_frag_list)*TX_RING_SIZE,
497 M_DEVBUF, M_NOWAIT | M_ZERO);
498 sc->tx_desc = malloc(sizeof(struct epic_tx_desc)*TX_RING_SIZE,
499 M_DEVBUF, M_NOWAIT | M_ZERO);
500 sc->rx_desc = malloc(sizeof(struct epic_rx_desc)*RX_RING_SIZE,
501 M_DEVBUF, M_NOWAIT | M_ZERO);
503 if (sc->tx_flist == NULL || sc->tx_desc == NULL || sc->rx_desc == NULL){
504 device_printf(sc->dev, "failed to malloc memory\n");
505 if (sc->tx_flist) free(sc->tx_flist, M_DEVBUF);
506 if (sc->tx_desc) free(sc->tx_desc, M_DEVBUF);
507 if (sc->rx_desc) free(sc->rx_desc, M_DEVBUF);
511 /* Bring the chip out of low-power mode. */
512 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
515 /* Workaround for Application Note 7-15 */
516 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
518 /* Read mac address from EEPROM */
519 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
520 ((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i);
522 /* Set Non-Volatile Control Register from EEPROM */
523 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
526 sc->tx_threshold = TRANSMIT_THRESHOLD;
527 sc->txcon = TXCON_DEFAULT;
528 sc->miicfg = MIICFG_SMI_ENABLE;
529 sc->phyid = EPIC_UNKN_PHY;
533 sc->cardvend = pci_read_config(sc->dev, PCIR_SUBVEND_0, 2);
534 sc->cardid = pci_read_config(sc->dev, PCIR_SUBDEV_0, 2);
536 if (sc->cardvend != SMC_VENDORID)
537 device_printf(sc->dev, "unknown card vendor %04xh\n", sc->cardvend);
543 * This is if_start handler. It takes mbufs from if_snd queue
544 * and queue them for transmit, one by one, until TX ring become full
545 * or queue become empty.
551 epic_softc_t *sc = ifp->if_softc;
552 struct epic_tx_buffer *buf;
553 struct epic_tx_desc *desc;
554 struct epic_frag_list *flist;
559 while (sc->pending_txs < TX_RING_SIZE) {
560 buf = sc->tx_buffer + sc->cur_tx;
561 desc = sc->tx_desc + sc->cur_tx;
562 flist = sc->tx_flist + sc->cur_tx;
564 /* Get next packet to send */
565 IF_DEQUEUE(&ifp->if_snd, m0);
567 /* If nothing to send, return */
568 if (NULL == m0) return;
570 /* Fill fragments list */
572 (NULL != m) && (i < EPIC_MAX_FRAGS);
573 m = m->m_next, i++) {
574 flist->frag[i].fraglen = m->m_len;
575 flist->frag[i].fragaddr = vtophys(mtod(m, caddr_t));
579 /* If packet was more than EPIC_MAX_FRAGS parts, */
580 /* recopy packet to new allocated mbuf cluster */
589 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
590 flist->frag[0].fraglen =
591 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
592 m->m_pkthdr.rcvif = ifp;
595 flist->frag[0].fragaddr = vtophys(mtod(m, caddr_t));
602 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
603 desc->control = 0x01;
605 max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
606 desc->status = 0x8000;
607 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED);
609 /* Set watchdog timer */
616 ifp->if_flags |= IFF_OACTIVE;
623 * Synopsis: Finish all received frames.
630 struct epic_rx_buffer *buf;
631 struct epic_rx_desc *desc;
633 struct ether_header *eh;
635 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) {
636 buf = sc->rx_buffer + sc->cur_rx;
637 desc = sc->rx_desc + sc->cur_rx;
639 /* Switch to next descriptor */
640 sc->cur_rx = (sc->cur_rx+1) & RX_RING_MASK;
643 * Check for RX errors. This should only happen if
644 * SAVE_ERRORED_PACKETS is set. RX errors generate
645 * RXE interrupt usually.
647 if ((desc->status & 1) == 0) {
648 sc->sc_if.if_ierrors++;
649 desc->status = 0x8000;
653 /* Save packet length and mbuf contained packet */
654 len = desc->rxlength - ETHER_CRC_LEN;
657 /* Try to get mbuf cluster */
658 EPIC_MGETCLUSTER(buf->mbuf);
659 if (NULL == buf->mbuf) {
661 desc->status = 0x8000;
662 sc->sc_if.if_ierrors++;
666 /* Point to new mbuf, and give descriptor to chip */
667 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
668 desc->status = 0x8000;
670 /* First mbuf in packet holds the ethernet and packet headers */
671 eh = mtod(m, struct ether_header *);
672 m->m_pkthdr.rcvif = &(sc->sc_if);
673 m->m_pkthdr.len = m->m_len = len;
675 /* Second mbuf holds packet ifself */
676 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header);
677 m->m_data += sizeof(struct ether_header);
679 /* Give mbuf to OS */
680 ether_input(&sc->sc_if, eh, m);
682 /* Successfuly received frame */
683 sc->sc_if.if_ipackets++;
690 * Synopsis: Do last phase of transmission. I.e. if desc is
691 * transmitted, decrease pending_txs counter, free mbuf contained
692 * packet, switch to next descriptor and repeat until no packets
693 * are pending or descriptor is not transmitted yet.
699 struct epic_tx_buffer *buf;
700 struct epic_tx_desc *desc;
703 while (sc->pending_txs > 0) {
704 buf = sc->tx_buffer + sc->dirty_tx;
705 desc = sc->tx_desc + sc->dirty_tx;
706 status = desc->status;
708 /* If packet is not transmitted, thou followed */
709 /* packets are not transmitted too */
710 if (status & 0x8000) break;
712 /* Packet is transmitted. Switch to next and */
715 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK;
719 /* Check for errors and collisions */
720 if (status & 0x0001) sc->sc_if.if_opackets++;
721 else sc->sc_if.if_oerrors++;
722 sc->sc_if.if_collisions += (status >> 8) & 0x1F;
723 #if defined(EPIC_DIAG)
724 if ((status & 0x1001) == 0x1001)
725 device_printf(sc->dev, "Tx ERROR: excessive coll. number\n");
729 if (sc->pending_txs < TX_RING_SIZE)
730 sc->sc_if.if_flags &= ~IFF_OACTIVE;
740 epic_softc_t * sc = (epic_softc_t *) arg;
743 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) {
744 CSR_WRITE_4(sc, INTSTAT, status);
746 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) {
748 if (status & (INTSTAT_RQE|INTSTAT_OVW)) {
749 #if defined(EPIC_DIAG)
750 if (status & INTSTAT_OVW)
751 device_printf(sc->dev, "RX buffer overflow\n");
752 if (status & INTSTAT_RQE)
753 device_printf(sc->dev, "RX FIFO overflow\n");
755 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0)
756 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED);
757 sc->sc_if.if_ierrors++;
761 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) {
763 if (sc->sc_if.if_snd.ifq_head != NULL)
764 epic_ifstart(&sc->sc_if);
767 /* Check for rare errors */
768 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
769 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) {
770 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
771 INTSTAT_APE|INTSTAT_DPE)) {
772 device_printf(sc->dev, "PCI fatal errors occured: %s%s%s%s\n",
773 (status&INTSTAT_PMA)?"PMA ":"",
774 (status&INTSTAT_PTA)?"PTA ":"",
775 (status&INTSTAT_APE)?"APE ":"",
776 (status&INTSTAT_DPE)?"DPE":""
785 if (status & INTSTAT_RXE) {
786 #if defined(EPIC_DIAG)
787 device_printf(sc->dev, "CRC/Alignment error\n");
789 sc->sc_if.if_ierrors++;
792 if (status & INTSTAT_TXU) {
793 epic_tx_underrun(sc);
794 sc->sc_if.if_oerrors++;
799 /* If no packets are pending, then no timeouts */
800 if (sc->pending_txs == 0) sc->sc_if.if_timer = 0;
806 * Handle the TX underrun error: increase the TX threshold
807 * and restart the transmitter.
813 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) {
814 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE;
815 #if defined(EPIC_DIAG)
816 device_printf(sc->dev, "Tx UNDERRUN: early TX disabled\n");
819 sc->tx_threshold += 0x40;
820 #if defined(EPIC_DIAG)
821 device_printf(sc->dev, "Tx UNDERRUN: TX threshold increased to %d\n",
826 /* We must set TXUGO to reset the stuck transmitter */
827 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO);
829 /* Update the TX threshold */
830 epic_stop_activity(sc);
831 epic_set_tx_mode(sc);
832 epic_start_activity(sc);
838 * Synopsis: This one is called if packets wasn't transmitted
839 * during timeout. Try to deallocate transmitted packets, and
840 * if success continue to work.
846 epic_softc_t *sc = ifp->if_softc;
851 device_printf(sc->dev, "device timeout %d packets\n", sc->pending_txs);
853 /* Try to finish queued packets */
856 /* If not successful */
857 if (sc->pending_txs > 0) {
859 ifp->if_oerrors+=sc->pending_txs;
861 /* Reinitialize board */
862 device_printf(sc->dev, "reinitialization\n");
867 device_printf(sc->dev, "seems we can continue normaly\n");
870 if (ifp->if_snd.ifq_head) epic_ifstart(ifp);
876 * Despite the name of this function, it doesn't update statistics, it only
877 * helps in autonegotiation process.
880 epic_stats_update(epic_softc_t * sc)
882 struct mii_data * mii;
887 mii = device_get_softc(sc->miibus);
890 sc->stat_ch = timeout((timeout_t *)epic_stats_update, sc, hz);
899 epic_ifmedia_upd(ifp)
903 struct mii_data *mii;
905 struct mii_softc *miisc;
909 mii = device_get_softc(sc->miibus);
910 ifm = &mii->mii_media;
911 media = ifm->ifm_cur->ifm_media;
913 /* Do not do anything if interface is not up */
914 if ((ifp->if_flags & IFF_UP) == 0)
918 * Lookup current selected PHY
920 if (IFM_INST(media) == sc->serinst) {
921 sc->phyid = EPIC_SERIAL;
924 /* If we're not selecting serial interface, select MII mode */
925 sc->miicfg &= ~MIICFG_SERIAL_ENABLE;
926 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
928 /* Default to unknown PHY */
929 sc->phyid = EPIC_UNKN_PHY;
931 /* Lookup selected PHY */
932 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
933 miisc = LIST_NEXT(miisc, mii_list)) {
934 if (IFM_INST(media) == miisc->mii_inst) {
940 /* Identify selected PHY */
942 int id1, id2, model, oui;
944 id1 = PHY_READ(sc->physc, MII_PHYIDR1);
945 id2 = PHY_READ(sc->physc, MII_PHYIDR2);
947 oui = MII_OUI(id1, id2);
948 model = MII_MODEL(id2);
950 case MII_OUI_QUALSEMI:
951 if (model == MII_MODEL_QUALSEMI_QS6612)
952 sc->phyid = EPIC_QS6612_PHY;
954 case MII_OUI_xxALTIMA:
955 if (model == MII_MODEL_xxALTIMA_AC101)
956 sc->phyid = EPIC_AC101_PHY;
958 case MII_OUI_xxLEVEL1:
959 if (model == MII_MODEL_xxLEVEL1_LXT970)
960 sc->phyid = EPIC_LXT970_PHY;
967 * Do PHY specific card setup
970 /* Call this, to isolate all not selected PHYs and
975 /* Do our own setup */
977 case EPIC_QS6612_PHY:
980 /* We have to powerup fiber tranceivers */
981 if (IFM_SUBTYPE(media) == IFM_100_FX)
982 sc->miicfg |= MIICFG_694_ENABLE;
984 sc->miicfg &= ~MIICFG_694_ENABLE;
985 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
988 case EPIC_LXT970_PHY:
989 /* We have to powerup fiber tranceivers */
990 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG);
991 if (IFM_SUBTYPE(media) == IFM_100_FX)
992 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0;
994 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
995 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg);
999 /* Select serial PHY, (10base2/BNC usually) */
1000 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE;
1001 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1003 /* There is no driver to fill this */
1004 mii->mii_media_active = media;
1005 mii->mii_media_status = 0;
1007 /* We need to call this manualy as i wasn't called
1010 epic_miibus_statchg(sc->dev);
1014 device_printf(sc->dev, "ERROR! Unknown PHY selected\n");
1022 * Report current media status.
1025 epic_ifmedia_sts(ifp, ifmr)
1027 struct ifmediareq *ifmr;
1030 struct mii_data *mii;
1031 struct ifmedia *ifm;
1034 mii = device_get_softc(sc->miibus);
1035 ifm = &mii->mii_media;
1037 /* Nothing should be selected if interface is down */
1038 if ((ifp->if_flags & IFF_UP) == 0) {
1039 ifmr->ifm_active = IFM_NONE;
1040 ifmr->ifm_status = 0;
1045 /* Call underlying pollstat, if not serial PHY */
1046 if (sc->phyid != EPIC_SERIAL)
1049 /* Simply copy media info */
1050 ifmr->ifm_active = mii->mii_media_active;
1051 ifmr->ifm_status = mii->mii_media_status;
1057 * Callback routine, called on media change.
1060 epic_miibus_statchg(dev)
1064 struct mii_data *mii;
1067 sc = device_get_softc(dev);
1068 mii = device_get_softc(sc->miibus);
1069 media = mii->mii_media_active;
1071 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
1073 /* If we are in full-duplex mode or loopback operation,
1074 * we need to decouple receiver and transmitter.
1076 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP))
1077 sc->txcon |= TXCON_FULL_DUPLEX;
1079 /* On some cards we need manualy set fullduplex led */
1080 if (sc->cardid == SMC9432FTX ||
1081 sc->cardid == SMC9432FTX_SC) {
1082 if (IFM_OPTIONS(media) & IFM_FDX)
1083 sc->miicfg |= MIICFG_694_ENABLE;
1085 sc->miicfg &= ~MIICFG_694_ENABLE;
1087 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1090 /* Update baudrate */
1091 if (IFM_SUBTYPE(media) == IFM_100_TX ||
1092 IFM_SUBTYPE(media) == IFM_100_FX)
1093 sc->sc_if.if_baudrate = 100000000;
1095 sc->sc_if.if_baudrate = 10000000;
1097 epic_stop_activity(sc);
1098 epic_set_tx_mode(sc);
1099 epic_start_activity(sc);
1105 epic_miibus_mediainit(dev)
1109 struct mii_data *mii;
1110 struct ifmedia *ifm;
1113 sc = device_get_softc(dev);
1114 mii = device_get_softc(sc->miibus);
1115 ifm = &mii->mii_media;
1117 /* Add Serial Media Interface if present, this applies to
1120 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
1121 /* Store its instance */
1122 sc->serinst = mii->mii_instance++;
1124 /* Add as 10base2/BNC media */
1125 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst);
1126 ifmedia_add(ifm, media, 0, NULL);
1128 /* Report to user */
1129 device_printf(sc->dev, "serial PHY detected (10Base2/BNC)\n");
1136 * Reset chip, allocate rings, and update media.
1142 struct ifnet *ifp = &sc->sc_if;
1147 /* If interface is already running, then we need not do anything */
1148 if (ifp->if_flags & IFF_RUNNING) {
1153 /* Soft reset the chip (we have to power up card before) */
1154 CSR_WRITE_4(sc, GENCTL, 0);
1155 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1158 * Reset takes 15 pci ticks which depends on PCI bus speed.
1159 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec.
1164 CSR_WRITE_4(sc, GENCTL, 0);
1166 /* Workaround for Application Note 7-15 */
1167 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1169 /* Initialize rings */
1170 if (epic_init_rings(sc)) {
1171 device_printf(sc->dev, "failed to init rings\n");
1176 /* Give rings to EPIC */
1177 CSR_WRITE_4(sc, PRCDAR, vtophys(sc->rx_desc));
1178 CSR_WRITE_4(sc, PTCDAR, vtophys(sc->tx_desc));
1180 /* Put node address to EPIC */
1181 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)sc->sc_macaddr)[0]);
1182 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)sc->sc_macaddr)[1]);
1183 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)sc->sc_macaddr)[2]);
1185 /* Set tx mode, includeing transmit threshold */
1186 epic_set_tx_mode(sc);
1188 /* Compute and set RXCON. */
1189 epic_set_rx_mode(sc);
1191 /* Set multicast table */
1192 epic_set_mc_table(sc);
1194 /* Enable interrupts by setting the interrupt mask. */
1195 CSR_WRITE_4(sc, INTMASK,
1196 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */
1197 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU |
1200 /* Acknowledge all pending interrupts */
1201 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1203 /* Enable interrupts, set for PCI read multiple and etc */
1204 CSR_WRITE_4(sc, GENCTL,
1205 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE |
1206 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64);
1208 /* Mark interface running ... */
1209 if (ifp->if_flags & IFF_UP) ifp->if_flags |= IFF_RUNNING;
1210 else ifp->if_flags &= ~IFF_RUNNING;
1213 ifp->if_flags &= ~IFF_OACTIVE;
1215 /* Start Rx process */
1216 epic_start_activity(sc);
1218 /* Set appropriate media */
1219 epic_ifmedia_upd(ifp);
1221 sc->stat_ch = timeout((timeout_t *)epic_stats_update, sc, hz);
1229 * Synopsis: calculate and set Rx mode. Chip must be in idle state to
1233 epic_set_rx_mode(sc)
1236 u_int32_t flags = sc->sc_if.if_flags;
1237 u_int32_t rxcon = RXCON_DEFAULT;
1239 #if defined(EPIC_EARLY_RX)
1240 rxcon |= RXCON_EARLY_RX;
1243 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0;
1245 CSR_WRITE_4(sc, RXCON, rxcon);
1251 * Synopsis: Set transmit control register. Chip must be in idle state to
1255 epic_set_tx_mode(sc)
1258 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE)
1259 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold);
1261 CSR_WRITE_4(sc, TXCON, sc->txcon);
1265 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC
1266 * flags. (Note, that setting PROMISC bit in EPIC's RXCON will only touch
1267 * individual frames, multicast filter must be manually programmed)
1269 * Note: EPIC must be in idle state.
1272 epic_set_mc_table(sc)
1275 struct ifnet *ifp = &sc->sc_if;
1276 struct ifmultiaddr *ifma;
1277 u_int16_t filter[4];
1280 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1281 CSR_WRITE_4(sc, MC0, 0xFFFF);
1282 CSR_WRITE_4(sc, MC1, 0xFFFF);
1283 CSR_WRITE_4(sc, MC2, 0xFFFF);
1284 CSR_WRITE_4(sc, MC3, 0xFFFF);
1294 #if __FreeBSD_version < 500000
1295 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1297 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1299 if (ifma->ifma_addr->sa_family != AF_LINK)
1301 h = epic_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1302 filter[h >> 4] |= 1 << (h & 0xF);
1305 CSR_WRITE_4(sc, MC0, filter[0]);
1306 CSR_WRITE_4(sc, MC1, filter[1]);
1307 CSR_WRITE_4(sc, MC2, filter[2]);
1308 CSR_WRITE_4(sc, MC3, filter[3]);
1314 * Synopsis: calculate EPIC's hash of multicast address.
1320 u_int32_t crc, carry;
1324 /* Compute CRC for the address value. */
1325 crc = 0xFFFFFFFF; /* initial value */
1327 for (i = 0; i < 6; i++) {
1329 for (j = 0; j < 8; j++) {
1330 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
1334 crc = (crc ^ 0x04c11db6) | carry;
1338 return ((crc >> 26) & 0x3F);
1343 * Synopsis: Start receive process and transmit one, if they need.
1346 epic_start_activity(sc)
1349 /* Start rx process */
1350 CSR_WRITE_4(sc, COMMAND,
1351 COMMAND_RXQUEUED | COMMAND_START_RX |
1352 (sc->pending_txs?COMMAND_TXQUEUED:0));
1356 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional
1357 * packet needs to be queued to stop Tx DMA.
1360 epic_stop_activity(sc)
1365 /* Stop Tx and Rx DMA */
1366 CSR_WRITE_4(sc, COMMAND,
1367 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA);
1369 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX) */
1370 for (i=0; i<0x1000; i++) {
1371 status = CSR_READ_4(sc, INTSTAT) & (INTSTAT_TXIDLE | INTSTAT_RXIDLE);
1372 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE))
1377 /* Catch all finished packets */
1381 status = CSR_READ_4(sc, INTSTAT);
1383 if ((status & INTSTAT_RXIDLE) == 0)
1384 device_printf(sc->dev, "ERROR! Can't stop Rx DMA\n");
1386 if ((status & INTSTAT_TXIDLE) == 0)
1387 device_printf(sc->dev, "ERROR! Can't stop Tx DMA\n");
1390 * May need to queue one more packet if TQE, this is rare
1391 * but existing case.
1393 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE))
1394 (void) epic_queue_last_packet(sc);
1399 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until
1400 * a packet from current descriptor will be copied to internal RAM. We
1401 * compose a dummy packet here and queue it for transmission.
1403 * XXX the packet will then be actually sent over network...
1406 epic_queue_last_packet(sc)
1409 struct epic_tx_desc *desc;
1410 struct epic_frag_list *flist;
1411 struct epic_tx_buffer *buf;
1415 device_printf(sc->dev, "queue last packet\n");
1417 desc = sc->tx_desc + sc->cur_tx;
1418 flist = sc->tx_flist + sc->cur_tx;
1419 buf = sc->tx_buffer + sc->cur_tx;
1421 if ((desc->status & 0x8000) || (buf->mbuf != NULL))
1424 MGETHDR(m0, M_DONTWAIT, MT_DATA);
1429 m0->m_len = min(MHLEN, ETHER_MIN_LEN-ETHER_CRC_LEN);
1430 flist->frag[0].fraglen = m0->m_len;
1431 m0->m_pkthdr.len = m0->m_len;
1432 m0->m_pkthdr.rcvif = &sc->sc_if;
1433 bzero(mtod(m0,caddr_t), m0->m_len);
1435 /* Fill fragments list */
1436 flist->frag[0].fraglen = m0->m_len;
1437 flist->frag[0].fragaddr = vtophys(mtod(m0, caddr_t));
1438 flist->numfrags = 1;
1440 /* Fill in descriptor */
1443 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
1444 desc->control = 0x01;
1445 desc->txlength = max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
1446 desc->status = 0x8000;
1448 /* Launch transmition */
1449 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED);
1451 /* Wait Tx DMA to stop (for how long??? XXX) */
1452 for (i=0; i<1000; i++) {
1453 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE)
1458 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0)
1459 device_printf(sc->dev, "ERROR! can't stop Tx DMA (2)\n");
1467 * Synopsis: Shut down board and deallocates rings.
1477 sc->sc_if.if_timer = 0;
1479 untimeout((timeout_t *)epic_stats_update, sc, sc->stat_ch);
1481 /* Disable interrupts */
1482 CSR_WRITE_4(sc, INTMASK, 0);
1483 CSR_WRITE_4(sc, GENCTL, 0);
1485 /* Try to stop Rx and TX processes */
1486 epic_stop_activity(sc);
1489 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1492 /* Make chip go to bed */
1493 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN);
1495 /* Free memory allocated for rings */
1496 epic_free_rings(sc);
1498 /* Mark as stoped */
1499 sc->sc_if.if_flags &= ~IFF_RUNNING;
1506 * Synopsis: This function should free all memory allocated for rings.
1514 for (i=0; i<RX_RING_SIZE; i++) {
1515 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1516 struct epic_rx_desc *desc = sc->rx_desc + i;
1519 desc->buflength = 0;
1522 if (buf->mbuf) m_freem(buf->mbuf);
1526 for (i=0; i<TX_RING_SIZE; i++) {
1527 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1528 struct epic_tx_desc *desc = sc->tx_desc + i;
1531 desc->buflength = 0;
1534 if (buf->mbuf) m_freem(buf->mbuf);
1540 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them.
1541 * Point Tx descs to fragment lists. Check that all descs and fraglists
1542 * are bounded and aligned properly.
1550 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0;
1552 for (i = 0; i < RX_RING_SIZE; i++) {
1553 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1554 struct epic_rx_desc *desc = sc->rx_desc + i;
1556 desc->status = 0; /* Owned by driver */
1557 desc->next = vtophys(sc->rx_desc + ((i+1) & RX_RING_MASK));
1559 if ((desc->next & 3) ||
1560 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1561 epic_free_rings(sc);
1565 EPIC_MGETCLUSTER(buf->mbuf);
1566 if (NULL == buf->mbuf) {
1567 epic_free_rings(sc);
1570 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
1572 desc->buflength = MCLBYTES; /* Max RX buffer length */
1573 desc->status = 0x8000; /* Set owner bit to NIC */
1576 for (i = 0; i < TX_RING_SIZE; i++) {
1577 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1578 struct epic_tx_desc *desc = sc->tx_desc + i;
1581 desc->next = vtophys(sc->tx_desc + ((i+1) & TX_RING_MASK));
1583 if ((desc->next & 3) ||
1584 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1585 epic_free_rings(sc);
1590 desc->bufaddr = vtophys(sc->tx_flist + i);
1592 if ((desc->bufaddr & 3) ||
1593 ((desc->bufaddr & PAGE_MASK) + sizeof(struct epic_frag_list)) > PAGE_SIZE) {
1594 epic_free_rings(sc);
1603 * EEPROM operation functions
1606 epic_write_eepromreg(sc, val)
1612 CSR_WRITE_1(sc, EECTL, val);
1614 for (i=0; i<0xFF; i++)
1615 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0) break;
1621 epic_read_eepromreg(sc)
1624 return CSR_READ_1(sc, EECTL);
1628 epic_eeprom_clock(sc, val)
1632 epic_write_eepromreg(sc, val);
1633 epic_write_eepromreg(sc, (val | 0x4));
1634 epic_write_eepromreg(sc, val);
1636 return epic_read_eepromreg(sc);
1640 epic_output_eepromw(sc, val)
1646 for (i = 0xF; i >= 0; i--) {
1648 epic_eeprom_clock(sc, 0x0B);
1650 epic_eeprom_clock(sc, 0x03);
1655 epic_input_eepromw(sc)
1658 u_int16_t retval = 0;
1661 for (i = 0xF; i >= 0; i--) {
1662 if (epic_eeprom_clock(sc, 0x3) & 0x10)
1670 epic_read_eeprom(sc, loc)
1677 epic_write_eepromreg(sc, 3);
1679 if (epic_read_eepromreg(sc) & 0x40)
1680 read_cmd = (loc & 0x3F) | 0x180;
1682 read_cmd = (loc & 0xFF) | 0x600;
1684 epic_output_eepromw(sc, read_cmd);
1686 dataval = epic_input_eepromw(sc);
1688 epic_write_eepromreg(sc, 1);
1694 * Here goes MII read/write routines
1697 epic_read_phy_reg(sc, phy, reg)
1703 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1705 for (i = 0; i < 0x100; i++) {
1706 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0) break;
1710 return (CSR_READ_4(sc, MIIDATA));
1714 epic_write_phy_reg(sc, phy, reg, val)
1720 CSR_WRITE_4(sc, MIIDATA, val);
1721 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));
1723 for(i=0;i<0x100;i++) {
1724 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0) break;
1732 epic_miibus_readreg(dev, phy, reg)
1738 sc = device_get_softc(dev);
1740 return (PHY_READ_2(sc, phy, reg));
1744 epic_miibus_writereg(dev, phy, reg, data)
1750 sc = device_get_softc(dev);
1752 PHY_WRITE_2(sc, phy, reg, data);