3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
39 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
41 * Written by Bill Paul <wpaul@windriver.com>
42 * Senior Networking Software Engineer
47 * This driver is designed to support RealTek's next generation of
48 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
49 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
50 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
52 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
53 * with the older 8139 family, however it also supports a special
54 * C+ mode of operation that provides several new performance enhancing
55 * features. These include:
57 * o Descriptor based DMA mechanism. Each descriptor represents
58 * a single packet fragment. Data buffers may be aligned on
63 * o TCP/IP checksum offload for both RX and TX
65 * o High and normal priority transmit DMA rings
67 * o VLAN tag insertion and extraction
69 * o TCP large send (segmentation offload)
71 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
72 * programming API is fairly straightforward. The RX filtering, EEPROM
73 * access and PHY access is the same as it is on the older 8139 series
76 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
77 * same programming API and feature set as the 8139C+ with the following
78 * differences and additions:
84 * o GMII and TBI ports/registers for interfacing with copper
87 * o RX and TX DMA rings can have up to 1024 descriptors
88 * (the 8139C+ allows a maximum of 64)
90 * o Slight differences in register layout from the 8139C+
92 * The TX start and timer interrupt registers are at different locations
93 * on the 8169 than they are on the 8139C+. Also, the status word in the
94 * RX descriptor has a slightly different bit layout. The 8169 does not
95 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
98 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
99 * (the 'S' stands for 'single-chip'). These devices have the same
100 * programming API as the older 8169, but also have some vendor-specific
101 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
102 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
104 * This driver takes advantage of the RX and TX checksum offload and
105 * VLAN tag insertion/extraction features. It also implements TX
106 * interrupt moderation using the timer interrupt registers, which
107 * significantly reduces TX interrupt load. There is also support
108 * for jumbo frames, however the 8169/8169S/8110S can not transmit
109 * jumbo frames larger than 7440, so the max MTU possible with this
110 * driver is 7422 bytes.
115 #include "opt_polling.h"
117 #include <sys/param.h>
119 #include <sys/endian.h>
120 #include <sys/kernel.h>
121 #include <sys/in_cksum.h>
122 #include <sys/interrupt.h>
123 #include <sys/malloc.h>
124 #include <sys/mbuf.h>
125 #include <sys/rman.h>
126 #include <sys/serialize.h>
127 #include <sys/socket.h>
128 #include <sys/sockio.h>
129 #include <sys/sysctl.h>
132 #include <net/ethernet.h>
134 #include <net/ifq_var.h>
135 #include <net/if_arp.h>
136 #include <net/if_dl.h>
137 #include <net/if_media.h>
138 #include <net/if_types.h>
139 #include <net/vlan/if_vlan_var.h>
140 #include <net/vlan/if_vlan_ether.h>
142 #include <netinet/ip.h>
144 #include <dev/netif/mii_layer/mii.h>
145 #include <dev/netif/mii_layer/miivar.h>
147 #include <bus/pci/pcidevs.h>
148 #include <bus/pci/pcireg.h>
149 #include <bus/pci/pcivar.h>
151 /* "device miibus" required. See GENERIC if you get errors here. */
152 #include "miibus_if.h"
154 #include <dev/netif/re/if_rereg.h>
155 #include <dev/netif/re/if_revar.h>
157 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
160 * Various supported device vendors/types and their names.
162 static const struct re_type {
167 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T,
168 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
170 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139,
171 "RealTek 8139C+ 10/100BaseTX" },
173 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E,
174 "RealTek 810x PCIe 10/100baseTX" },
176 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168,
177 "RealTek 8111/8168 PCIe Gigabit Ethernet" },
179 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169,
180 "RealTek 8110/8169 Gigabit Ethernet" },
182 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC,
183 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
185 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT,
186 "Corega CG-LAPCIGT Gigabit Ethernet" },
188 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032,
189 "Linksys EG1032 Gigabit Ethernet" },
191 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902,
192 "US Robotics 997902 Gigabit Ethernet" },
194 { PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322,
195 "TTTech MC322 Gigabit Ethernet" },
200 static const struct re_hwrev re_hwrevs[] = {
201 { RE_HWREV_8139CPLUS, RE_MACVER_UNKN, ETHERMTU,
202 RE_C_HWCSUM | RE_C_8139CP | RE_C_FASTE },
204 { RE_HWREV_8169, RE_MACVER_UNKN, ETHERMTU,
205 RE_C_HWCSUM | RE_C_8169 },
207 { RE_HWREV_8110S, RE_MACVER_03, RE_MTU_6K,
208 RE_C_HWCSUM | RE_C_8169 },
210 { RE_HWREV_8169S, RE_MACVER_03, RE_MTU_6K,
211 RE_C_HWCSUM | RE_C_8169 },
213 { RE_HWREV_8169SB, RE_MACVER_04, RE_MTU_6K,
214 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
216 { RE_HWREV_8169SC1, RE_MACVER_05, RE_MTU_6K,
217 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
219 { RE_HWREV_8169SC2, RE_MACVER_06, RE_MTU_6K,
220 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
222 { RE_HWREV_8168B1, RE_MACVER_21, RE_MTU_6K,
223 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT },
225 { RE_HWREV_8168B2, RE_MACVER_23, RE_MTU_6K,
226 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD },
228 { RE_HWREV_8168B3, RE_MACVER_23, RE_MTU_6K,
229 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD },
231 { RE_HWREV_8168C, RE_MACVER_29, RE_MTU_6K,
232 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
233 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
235 { RE_HWREV_8168CP, RE_MACVER_2B, RE_MTU_6K,
236 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
237 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
239 { RE_HWREV_8168D, RE_MACVER_2A, RE_MTU_9K,
240 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
241 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
243 { RE_HWREV_8168DP, RE_MACVER_2D, RE_MTU_9K,
244 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
245 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
247 { RE_HWREV_8168E, RE_MACVER_UNKN, RE_MTU_9K,
248 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
249 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
251 { RE_HWREV_8168F, RE_MACVER_UNKN, RE_MTU_9K,
252 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
253 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
255 { RE_HWREV_8100E, RE_MACVER_UNKN, ETHERMTU,
256 RE_C_HWCSUM | RE_C_FASTE },
258 { RE_HWREV_8101E1, RE_MACVER_16, ETHERMTU,
259 RE_C_HWCSUM | RE_C_FASTE },
261 { RE_HWREV_8101E2, RE_MACVER_16, ETHERMTU,
262 RE_C_HWCSUM | RE_C_FASTE },
264 { RE_HWREV_8102E, RE_MACVER_15, ETHERMTU,
265 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX |
268 { RE_HWREV_8102EL, RE_MACVER_15, ETHERMTU,
269 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX |
272 { RE_HWREV_NULL, 0, 0, 0 }
275 static int re_probe(device_t);
276 static int re_attach(device_t);
277 static int re_detach(device_t);
278 static int re_suspend(device_t);
279 static int re_resume(device_t);
280 static void re_shutdown(device_t);
282 static int re_allocmem(device_t);
283 static void re_freemem(device_t);
284 static void re_freebufmem(struct re_softc *, int, int);
285 static int re_encap(struct re_softc *, struct mbuf **, int *);
286 static int re_newbuf_std(struct re_softc *, int, int);
287 static int re_newbuf_jumbo(struct re_softc *, int, int);
288 static void re_setup_rxdesc(struct re_softc *, int);
289 static int re_rx_list_init(struct re_softc *);
290 static int re_tx_list_init(struct re_softc *);
291 static int re_rxeof(struct re_softc *);
292 static int re_txeof(struct re_softc *);
293 static int re_tx_collect(struct re_softc *);
294 static void re_intr(void *);
295 static void re_tick(void *);
296 static void re_tick_serialized(void *);
298 static void re_start(struct ifnet *);
299 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
300 static void re_init(void *);
301 static void re_stop(struct re_softc *);
302 static void re_watchdog(struct ifnet *);
303 static int re_ifmedia_upd(struct ifnet *);
304 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
306 static void re_eeprom_putbyte(struct re_softc *, int);
307 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
308 static void re_read_eeprom(struct re_softc *, caddr_t, int, int);
309 static void re_get_eewidth(struct re_softc *);
311 static int re_gmii_readreg(device_t, int, int);
312 static int re_gmii_writereg(device_t, int, int, int);
314 static int re_miibus_readreg(device_t, int, int);
315 static int re_miibus_writereg(device_t, int, int, int);
316 static void re_miibus_statchg(device_t);
318 static void re_setmulti(struct re_softc *);
319 static void re_reset(struct re_softc *, int);
320 static void re_get_eaddr(struct re_softc *, uint8_t *);
322 static void re_setup_hw_im(struct re_softc *);
323 static void re_setup_sim_im(struct re_softc *);
324 static void re_disable_hw_im(struct re_softc *);
325 static void re_disable_sim_im(struct re_softc *);
326 static void re_config_imtype(struct re_softc *, int);
327 static void re_setup_intr(struct re_softc *, int, int);
329 static int re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *);
330 static int re_sysctl_rxtime(SYSCTL_HANDLER_ARGS);
331 static int re_sysctl_txtime(SYSCTL_HANDLER_ARGS);
332 static int re_sysctl_simtime(SYSCTL_HANDLER_ARGS);
333 static int re_sysctl_imtype(SYSCTL_HANDLER_ARGS);
335 static int re_jpool_alloc(struct re_softc *);
336 static void re_jpool_free(struct re_softc *);
337 static struct re_jbuf *re_jbuf_alloc(struct re_softc *);
338 static void re_jbuf_free(void *);
339 static void re_jbuf_ref(void *);
342 static int re_diag(struct re_softc *);
345 #ifdef DEVICE_POLLING
346 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
349 static device_method_t re_methods[] = {
350 /* Device interface */
351 DEVMETHOD(device_probe, re_probe),
352 DEVMETHOD(device_attach, re_attach),
353 DEVMETHOD(device_detach, re_detach),
354 DEVMETHOD(device_suspend, re_suspend),
355 DEVMETHOD(device_resume, re_resume),
356 DEVMETHOD(device_shutdown, re_shutdown),
359 DEVMETHOD(bus_print_child, bus_generic_print_child),
360 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
363 DEVMETHOD(miibus_readreg, re_miibus_readreg),
364 DEVMETHOD(miibus_writereg, re_miibus_writereg),
365 DEVMETHOD(miibus_statchg, re_miibus_statchg),
370 static driver_t re_driver = {
373 sizeof(struct re_softc)
376 static devclass_t re_devclass;
378 DECLARE_DUMMY_MODULE(if_re);
379 MODULE_DEPEND(if_re, miibus, 1, 1, 1);
380 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, NULL, NULL);
381 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, NULL, NULL);
382 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, NULL, NULL);
384 static int re_rx_desc_count = RE_RX_DESC_CNT_DEF;
385 static int re_tx_desc_count = RE_TX_DESC_CNT_DEF;
387 TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count);
388 TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count);
391 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
394 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
397 re_free_rxchain(struct re_softc *sc)
399 if (sc->re_head != NULL) {
400 m_freem(sc->re_head);
401 sc->re_head = sc->re_tail = NULL;
406 * Send a read command and address to the EEPROM, check for ACK.
409 re_eeprom_putbyte(struct re_softc *sc, int addr)
413 d = addr | (RE_9346_READ << sc->re_eewidth);
416 * Feed in each bit and strobe the clock.
418 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) {
420 EE_SET(RE_EE_DATAIN);
422 EE_CLR(RE_EE_DATAIN);
432 * Read a word of data stored in the EEPROM at address 'addr.'
435 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
441 * Send address of word we want to read.
443 re_eeprom_putbyte(sc, addr);
446 * Start reading bits from EEPROM.
448 for (i = 0x8000; i != 0; i >>= 1) {
451 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
461 * Read a sequence of words from the EEPROM.
464 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt)
467 uint16_t word = 0, *ptr;
469 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
472 for (i = 0; i < cnt; i++) {
473 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL);
474 re_eeprom_getword(sc, off + i, &word);
475 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL);
476 ptr = (uint16_t *)(dest + (i * 2));
480 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
484 re_get_eewidth(struct re_softc *sc)
489 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
490 if (re_did != 0x8129)
495 re_gmii_readreg(device_t dev, int phy, int reg)
497 struct re_softc *sc = device_get_softc(dev);
504 /* Let the rgephy driver read the GMEDIASTAT register */
506 if (reg == RE_GMEDIASTAT)
507 return(CSR_READ_1(sc, RE_GMEDIASTAT));
509 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
512 for (i = 0; i < RE_TIMEOUT; i++) {
513 rval = CSR_READ_4(sc, RE_PHYAR);
514 if (rval & RE_PHYAR_BUSY)
519 if (i == RE_TIMEOUT) {
520 device_printf(dev, "PHY read failed\n");
524 return(rval & RE_PHYAR_PHYDATA);
528 re_gmii_writereg(device_t dev, int phy, int reg, int data)
530 struct re_softc *sc = device_get_softc(dev);
534 CSR_WRITE_4(sc, RE_PHYAR,
535 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
538 for (i = 0; i < RE_TIMEOUT; i++) {
539 rval = CSR_READ_4(sc, RE_PHYAR);
540 if ((rval & RE_PHYAR_BUSY) == 0)
546 device_printf(dev, "PHY write failed\n");
552 re_miibus_readreg(device_t dev, int phy, int reg)
554 struct re_softc *sc = device_get_softc(dev);
556 uint16_t re8139_reg = 0;
558 if (!RE_IS_8139CP(sc)) {
559 rval = re_gmii_readreg(dev, phy, reg);
563 /* Pretend the internal PHY is only at address 0 */
569 re8139_reg = RE_BMCR;
572 re8139_reg = RE_BMSR;
575 re8139_reg = RE_ANAR;
578 re8139_reg = RE_ANER;
581 re8139_reg = RE_LPAR;
587 * Allow the rlphy driver to read the media status
588 * register. If we have a link partner which does not
589 * support NWAY, this is the register which will tell
590 * us the results of parallel detection.
593 return(CSR_READ_1(sc, RE_MEDIASTAT));
595 device_printf(dev, "bad phy register\n");
598 rval = CSR_READ_2(sc, re8139_reg);
599 if (re8139_reg == RE_BMCR) {
600 /* 8139C+ has different bit layout. */
601 rval &= ~(BMCR_LOOP | BMCR_ISO);
607 re_miibus_writereg(device_t dev, int phy, int reg, int data)
609 struct re_softc *sc= device_get_softc(dev);
610 u_int16_t re8139_reg = 0;
612 if (!RE_IS_8139CP(sc))
613 return(re_gmii_writereg(dev, phy, reg, data));
615 /* Pretend the internal PHY is only at address 0 */
621 re8139_reg = RE_BMCR;
622 /* 8139C+ has different bit layout. */
623 data &= ~(BMCR_LOOP | BMCR_ISO);
626 re8139_reg = RE_BMSR;
629 re8139_reg = RE_ANAR;
632 re8139_reg = RE_ANER;
635 re8139_reg = RE_LPAR;
641 device_printf(dev, "bad phy register\n");
644 CSR_WRITE_2(sc, re8139_reg, data);
649 re_miibus_statchg(device_t dev)
654 * Program the 64-bit multicast hash filter.
657 re_setmulti(struct re_softc *sc)
659 struct ifnet *ifp = &sc->arpcom.ac_if;
661 uint32_t hashes[2] = { 0, 0 };
662 struct ifmultiaddr *ifma;
666 rxfilt = CSR_READ_4(sc, RE_RXCFG);
668 /* Set the individual bit to receive frames for this host only. */
669 rxfilt |= RE_RXCFG_RX_INDIV;
670 /* Set capture broadcast bit to capture broadcast frames. */
671 rxfilt |= RE_RXCFG_RX_BROAD;
673 rxfilt &= ~(RE_RXCFG_RX_ALLPHYS | RE_RXCFG_RX_MULTI);
674 if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) {
675 rxfilt |= RE_RXCFG_RX_MULTI;
677 /* If we want promiscuous mode, set the allframes bit. */
678 if (ifp->if_flags & IFF_PROMISC)
679 rxfilt |= RE_RXCFG_RX_ALLPHYS;
681 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
682 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
683 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
687 /* first, zot all the existing hash bits */
688 CSR_WRITE_4(sc, RE_MAR0, 0);
689 CSR_WRITE_4(sc, RE_MAR4, 0);
691 /* now program new ones */
692 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
693 if (ifma->ifma_addr->sa_family != AF_LINK)
695 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
696 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
698 hashes[0] |= (1 << h);
700 hashes[1] |= (1 << (h - 32));
705 rxfilt |= RE_RXCFG_RX_MULTI;
707 rxfilt &= ~RE_RXCFG_RX_MULTI;
709 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
712 * For some unfathomable reason, RealTek decided to reverse
713 * the order of the multicast hash registers in the PCI Express
714 * parts. This means we have to write the hash pattern in reverse
715 * order for those devices.
717 if (sc->re_caps & RE_C_PCIE) {
718 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[1]));
719 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[0]));
721 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
722 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
727 re_reset(struct re_softc *sc, int running)
731 if ((sc->re_caps & RE_C_STOP_RXTX) && running) {
732 CSR_WRITE_1(sc, RE_COMMAND,
733 RE_CMD_STOPREQ | RE_CMD_TX_ENB | RE_CMD_RX_ENB);
737 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
739 for (i = 0; i < RE_TIMEOUT; i++) {
741 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
745 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
750 * The following routine is designed to test for a defect on some
751 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
752 * lines connected to the bus, however for a 32-bit only card, they
753 * should be pulled high. The result of this defect is that the
754 * NIC will not work right if you plug it into a 64-bit slot: DMA
755 * operations will be done with 64-bit transfers, which will fail
756 * because the 64-bit data lines aren't connected.
758 * There's no way to work around this (short of talking a soldering
759 * iron to the board), however we can detect it. The method we use
760 * here is to put the NIC into digital loopback mode, set the receiver
761 * to promiscuous mode, and then try to send a frame. We then compare
762 * the frame data we sent to what was received. If the data matches,
763 * then the NIC is working correctly, otherwise we know the user has
764 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
765 * slot. In the latter case, there's no way the NIC can work correctly,
766 * so we print out a message on the console and abort the device attach.
770 re_diag(struct re_softc *sc)
772 struct ifnet *ifp = &sc->arpcom.ac_if;
774 struct ether_header *eh;
775 struct re_desc *cur_rx;
778 int total_len, i, error = 0, phyaddr;
779 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
780 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
782 /* Allocate a single mbuf */
784 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
789 * Initialize the NIC in test mode. This sets the chip up
790 * so that it can send and receive frames, but performs the
791 * following special functions:
792 * - Puts receiver in promiscuous mode
793 * - Enables digital loopback mode
794 * - Leaves interrupts turned off
797 ifp->if_flags |= IFF_PROMISC;
798 sc->re_flags |= RE_F_TESTMODE;
800 sc->re_flags |= RE_F_LINKED;
801 if (!RE_IS_8139CP(sc))
806 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET);
807 for (i = 0; i < RE_TIMEOUT; i++) {
808 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR);
809 if (!(status & BMCR_RESET))
813 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP);
814 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG);
818 /* Put some data in the mbuf */
820 eh = mtod(m0, struct ether_header *);
821 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
822 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
823 eh->ether_type = htons(ETHERTYPE_IP);
824 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
827 * Queue the packet, start transmission.
828 * Note: ifq_handoff() ultimately calls re_start() for us.
831 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
832 error = ifq_handoff(ifp, m0, NULL);
839 /* Wait for it to propagate through the chip */
842 for (i = 0; i < RE_TIMEOUT; i++) {
843 status = CSR_READ_2(sc, RE_ISR);
844 CSR_WRITE_2(sc, RE_ISR, status);
845 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
846 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
851 if (i == RE_TIMEOUT) {
852 if_printf(ifp, "diagnostic failed to receive packet "
853 "in loopback mode\n");
859 * The packet should have been dumped into the first
860 * entry in the RX DMA ring. Grab it from there.
863 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, sc->re_ldata.re_rx_dmamap[0],
864 BUS_DMASYNC_POSTREAD);
865 bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
866 sc->re_ldata.re_rx_dmamap[0]);
868 m0 = sc->re_ldata.re_rx_mbuf[0];
869 sc->re_ldata.re_rx_mbuf[0] = NULL;
870 eh = mtod(m0, struct ether_header *);
872 cur_rx = &sc->re_ldata.re_rx_list[0];
873 total_len = RE_RXBYTES(cur_rx);
874 rxstat = le32toh(cur_rx->re_cmdstat);
876 if (total_len != ETHER_MIN_LEN) {
877 if_printf(ifp, "diagnostic failed, received short packet\n");
882 /* Test that the received packet data matches what we sent. */
884 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
885 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
886 be16toh(eh->ether_type) != ETHERTYPE_IP) {
887 if_printf(ifp, "WARNING, DMA FAILURE!\n");
888 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
889 dst, ":", src, ":", ETHERTYPE_IP);
890 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
891 eh->ether_dhost, ":", eh->ether_shost, ":",
892 ntohs(eh->ether_type));
893 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
894 "into a 64-bit PCI slot.\n");
895 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
896 "for proper operation.\n");
897 if_printf(ifp, "Read the re(4) man page for more details.\n");
902 /* Turn interface off, release resources */
904 sc->re_flags &= ~(RE_F_LINKED | RE_F_TESTMODE);
905 ifp->if_flags &= ~IFF_PROMISC;
915 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
916 * IDs against our list and return a device name if we find a match.
919 re_probe(device_t dev)
921 const struct re_type *t;
922 const struct re_hwrev *hw_rev;
925 uint32_t hwrev, macmode, txcfg;
926 uint16_t vendor, product;
928 vendor = pci_get_vendor(dev);
929 product = pci_get_device(dev);
932 * Only attach to rev.3 of the Linksys EG1032 adapter.
933 * Rev.2 is supported by sk(4).
935 if (vendor == PCI_VENDOR_LINKSYS &&
936 product == PCI_PRODUCT_LINKSYS_EG1032 &&
937 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3)
940 if (vendor == PCI_VENDOR_REALTEK &&
941 product == PCI_PRODUCT_REALTEK_RT8139 &&
942 pci_get_revid(dev) != PCI_REVID_REALTEK_RT8139CP) {
947 for (t = re_devs; t->re_name != NULL; t++) {
948 if (product == t->re_did && vendor == t->re_vid)
953 * Check if we found a RealTek device.
955 if (t->re_name == NULL)
959 * Temporarily map the I/O space so we can read the chip ID register.
961 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
963 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
965 if (sc->re_res == NULL) {
966 device_printf(dev, "couldn't map ports/memory\n");
971 sc->re_btag = rman_get_bustag(sc->re_res);
972 sc->re_bhandle = rman_get_bushandle(sc->re_res);
974 txcfg = CSR_READ_4(sc, RE_TXCFG);
975 hwrev = txcfg & RE_TXCFG_HWREV;
976 macmode = txcfg & RE_TXCFG_MACMODE;
977 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
981 * and continue matching for the specific chip...
983 for (hw_rev = re_hwrevs; hw_rev->re_hwrev != RE_HWREV_NULL; hw_rev++) {
984 if (hw_rev->re_hwrev == hwrev) {
985 sc = device_get_softc(dev);
987 sc->re_hwrev = hw_rev->re_hwrev;
988 sc->re_macver = hw_rev->re_macver;
989 sc->re_caps = hw_rev->re_caps;
990 sc->re_maxmtu = hw_rev->re_maxmtu;
993 * Apply chip property fixup
995 switch (sc->re_hwrev) {
996 case RE_HWREV_8101E1:
997 case RE_HWREV_8101E2:
999 sc->re_macver = RE_MACVER_11;
1000 else if (macmode == 0x200000)
1001 sc->re_macver = RE_MACVER_12;
1003 case RE_HWREV_8102E:
1004 case RE_HWREV_8102EL:
1006 sc->re_macver = RE_MACVER_13;
1007 else if (macmode == 0x100000)
1008 sc->re_macver = RE_MACVER_14;
1010 case RE_HWREV_8168B2:
1011 case RE_HWREV_8168B3:
1013 sc->re_macver = RE_MACVER_22;
1015 case RE_HWREV_8168C:
1017 sc->re_macver = RE_MACVER_24;
1018 else if (macmode == 0x200000)
1019 sc->re_macver = RE_MACVER_25;
1020 else if (macmode == 0x300000)
1021 sc->re_macver = RE_MACVER_27;
1023 case RE_HWREV_8168CP:
1025 sc->re_macver = RE_MACVER_26;
1026 else if (macmode == 0x100000)
1027 sc->re_macver = RE_MACVER_28;
1029 case RE_HWREV_8168DP:
1031 sc->re_macver = RE_MACVER_2B;
1032 else if (macmode == 0x200000)
1033 sc->re_macver = RE_MACVER_2C;
1035 case RE_HWREV_8168E:
1036 if (macmode == 0x100000)
1037 sc->re_macver = RE_MACVER_2E;
1038 else if (macmode == 0x200000)
1039 sc->re_macver = RE_MACVER_2F;
1041 case RE_HWREV_8168F:
1042 if (macmode == 0x000000)
1043 sc->re_macver = RE_MACVER_30;
1044 else if (macmode == 0x100000)
1045 sc->re_macver = RE_MACVER_31;
1048 if (pci_is_pcie(dev))
1049 sc->re_caps |= RE_C_PCIE;
1051 device_set_desc(dev, t->re_name);
1057 device_printf(dev, "unknown hwrev 0x%08x, macmode 0x%08x\n",
1064 re_allocmem(device_t dev)
1066 struct re_softc *sc = device_get_softc(dev);
1071 * Allocate list data
1073 sc->re_ldata.re_tx_mbuf =
1074 kmalloc(sc->re_tx_desc_cnt * sizeof(struct mbuf *),
1075 M_DEVBUF, M_ZERO | M_WAITOK);
1077 sc->re_ldata.re_rx_mbuf =
1078 kmalloc(sc->re_rx_desc_cnt * sizeof(struct mbuf *),
1079 M_DEVBUF, M_ZERO | M_WAITOK);
1081 sc->re_ldata.re_rx_paddr =
1082 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_addr_t),
1083 M_DEVBUF, M_ZERO | M_WAITOK);
1085 sc->re_ldata.re_tx_dmamap =
1086 kmalloc(sc->re_tx_desc_cnt * sizeof(bus_dmamap_t),
1087 M_DEVBUF, M_ZERO | M_WAITOK);
1089 sc->re_ldata.re_rx_dmamap =
1090 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_dmamap_t),
1091 M_DEVBUF, M_ZERO | M_WAITOK);
1094 * Allocate the parent bus DMA tag appropriate for PCI.
1096 error = bus_dma_tag_create(NULL, /* parent */
1097 1, 0, /* alignment, boundary */
1098 BUS_SPACE_MAXADDR, /* lowaddr */
1099 BUS_SPACE_MAXADDR, /* highaddr */
1100 NULL, NULL, /* filter, filterarg */
1101 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
1103 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1105 &sc->re_parent_tag);
1107 device_printf(dev, "could not allocate parent dma tag\n");
1111 /* Allocate TX descriptor list. */
1112 error = bus_dmamem_coherent(sc->re_parent_tag,
1114 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1115 RE_TX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO,
1118 device_printf(dev, "could not allocate TX ring\n");
1121 sc->re_ldata.re_tx_list_tag = dmem.dmem_tag;
1122 sc->re_ldata.re_tx_list_map = dmem.dmem_map;
1123 sc->re_ldata.re_tx_list = dmem.dmem_addr;
1124 sc->re_ldata.re_tx_list_addr = dmem.dmem_busaddr;
1126 /* Allocate RX descriptor list. */
1127 error = bus_dmamem_coherent(sc->re_parent_tag,
1129 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1130 RE_RX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO,
1133 device_printf(dev, "could not allocate RX ring\n");
1136 sc->re_ldata.re_rx_list_tag = dmem.dmem_tag;
1137 sc->re_ldata.re_rx_list_map = dmem.dmem_map;
1138 sc->re_ldata.re_rx_list = dmem.dmem_addr;
1139 sc->re_ldata.re_rx_list_addr = dmem.dmem_busaddr;
1141 /* Allocate maps for TX mbufs. */
1142 error = bus_dma_tag_create(sc->re_parent_tag,
1144 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1146 RE_FRAMELEN_MAX, RE_MAXSEGS, MCLBYTES,
1147 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1148 &sc->re_ldata.re_tx_mtag);
1150 device_printf(dev, "could not allocate TX buf dma tag\n");
1154 /* Create DMA maps for TX buffers */
1155 for (i = 0; i < sc->re_tx_desc_cnt; i++) {
1156 error = bus_dmamap_create(sc->re_ldata.re_tx_mtag,
1157 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1158 &sc->re_ldata.re_tx_dmamap[i]);
1160 device_printf(dev, "can't create DMA map for TX buf\n");
1161 re_freebufmem(sc, i, 0);
1166 /* Allocate maps for RX mbufs. */
1167 error = bus_dma_tag_create(sc->re_parent_tag,
1169 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1171 MCLBYTES, 1, MCLBYTES,
1172 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,
1173 &sc->re_ldata.re_rx_mtag);
1175 device_printf(dev, "could not allocate RX buf dma tag\n");
1179 /* Create spare DMA map for RX */
1180 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, BUS_DMA_WAITOK,
1181 &sc->re_ldata.re_rx_spare);
1183 device_printf(dev, "can't create spare DMA map for RX\n");
1184 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag);
1185 sc->re_ldata.re_rx_mtag = NULL;
1189 /* Create DMA maps for RX buffers */
1190 for (i = 0; i < sc->re_rx_desc_cnt; i++) {
1191 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag,
1192 BUS_DMA_WAITOK, &sc->re_ldata.re_rx_dmamap[i]);
1194 device_printf(dev, "can't create DMA map for RX buf\n");
1195 re_freebufmem(sc, sc->re_tx_desc_cnt, i);
1200 /* Create jumbo buffer pool for RX if required */
1201 if (sc->re_caps & RE_C_CONTIGRX) {
1202 error = re_jpool_alloc(sc);
1205 /* Disable jumbo frame support */
1206 sc->re_maxmtu = ETHERMTU;
1213 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt)
1217 /* Destroy all the RX and TX buffer maps */
1218 if (sc->re_ldata.re_tx_mtag) {
1219 for (i = 0; i < tx_cnt; i++) {
1220 bus_dmamap_destroy(sc->re_ldata.re_tx_mtag,
1221 sc->re_ldata.re_tx_dmamap[i]);
1223 bus_dma_tag_destroy(sc->re_ldata.re_tx_mtag);
1224 sc->re_ldata.re_tx_mtag = NULL;
1227 if (sc->re_ldata.re_rx_mtag) {
1228 for (i = 0; i < rx_cnt; i++) {
1229 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag,
1230 sc->re_ldata.re_rx_dmamap[i]);
1232 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag,
1233 sc->re_ldata.re_rx_spare);
1234 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag);
1235 sc->re_ldata.re_rx_mtag = NULL;
1240 re_freemem(device_t dev)
1242 struct re_softc *sc = device_get_softc(dev);
1244 /* Unload and free the RX DMA ring memory and map */
1245 if (sc->re_ldata.re_rx_list_tag) {
1246 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1247 sc->re_ldata.re_rx_list_map);
1248 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1249 sc->re_ldata.re_rx_list,
1250 sc->re_ldata.re_rx_list_map);
1251 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1254 /* Unload and free the TX DMA ring memory and map */
1255 if (sc->re_ldata.re_tx_list_tag) {
1256 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1257 sc->re_ldata.re_tx_list_map);
1258 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1259 sc->re_ldata.re_tx_list,
1260 sc->re_ldata.re_tx_list_map);
1261 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1264 /* Free RX/TX buf DMA stuffs */
1265 re_freebufmem(sc, sc->re_tx_desc_cnt, sc->re_rx_desc_cnt);
1267 /* Unload and free the stats buffer and map */
1268 if (sc->re_ldata.re_stag) {
1269 bus_dmamap_unload(sc->re_ldata.re_stag, sc->re_ldata.re_smap);
1270 bus_dmamem_free(sc->re_ldata.re_stag,
1271 sc->re_ldata.re_stats,
1272 sc->re_ldata.re_smap);
1273 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1276 if (sc->re_caps & RE_C_CONTIGRX)
1279 if (sc->re_parent_tag)
1280 bus_dma_tag_destroy(sc->re_parent_tag);
1282 if (sc->re_ldata.re_tx_mbuf != NULL)
1283 kfree(sc->re_ldata.re_tx_mbuf, M_DEVBUF);
1284 if (sc->re_ldata.re_rx_mbuf != NULL)
1285 kfree(sc->re_ldata.re_rx_mbuf, M_DEVBUF);
1286 if (sc->re_ldata.re_rx_paddr != NULL)
1287 kfree(sc->re_ldata.re_rx_paddr, M_DEVBUF);
1288 if (sc->re_ldata.re_tx_dmamap != NULL)
1289 kfree(sc->re_ldata.re_tx_dmamap, M_DEVBUF);
1290 if (sc->re_ldata.re_rx_dmamap != NULL)
1291 kfree(sc->re_ldata.re_rx_dmamap, M_DEVBUF);
1295 * Attach the interface. Allocate softc structures, do ifmedia
1296 * setup and ethernet/BPF attach.
1299 re_attach(device_t dev)
1301 struct re_softc *sc = device_get_softc(dev);
1303 uint8_t eaddr[ETHER_ADDR_LEN];
1304 int error = 0, rid, qlen;
1306 callout_init(&sc->re_timer);
1309 if (RE_IS_8139CP(sc)) {
1310 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_8139CP;
1311 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_8139CP;
1313 sc->re_rx_desc_cnt = re_rx_desc_count;
1314 if (sc->re_rx_desc_cnt > RE_RX_DESC_CNT_MAX)
1315 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_MAX;
1317 sc->re_tx_desc_cnt = re_tx_desc_count;
1318 if (sc->re_tx_desc_cnt > RE_TX_DESC_CNT_MAX)
1319 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_MAX;
1322 qlen = RE_IFQ_MAXLEN;
1323 if (sc->re_tx_desc_cnt > qlen)
1324 qlen = sc->re_tx_desc_cnt;
1326 sc->re_rxbuf_size = MCLBYTES;
1327 sc->re_newbuf = re_newbuf_std;
1329 sc->re_tx_time = 5; /* 125us */
1330 sc->re_rx_time = 2; /* 50us */
1331 if (sc->re_caps & RE_C_PCIE)
1332 sc->re_sim_time = 75; /* 75us */
1334 sc->re_sim_time = 125; /* 125us */
1335 if (!RE_IS_8139CP(sc)) {
1336 /* simulated interrupt moderation */
1337 sc->re_imtype = RE_IMTYPE_SIM;
1339 sc->re_imtype = RE_IMTYPE_NONE;
1341 re_config_imtype(sc, sc->re_imtype);
1343 sysctl_ctx_init(&sc->re_sysctl_ctx);
1344 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx,
1345 SYSCTL_STATIC_CHILDREN(_hw),
1347 device_get_nameunit(dev),
1349 if (sc->re_sysctl_tree == NULL) {
1350 device_printf(dev, "can't add sysctl node\n");
1354 SYSCTL_ADD_INT(&sc->re_sysctl_ctx,
1355 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO,
1356 "rx_desc_count", CTLFLAG_RD, &sc->re_rx_desc_cnt,
1357 0, "RX desc count");
1358 SYSCTL_ADD_INT(&sc->re_sysctl_ctx,
1359 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO,
1360 "tx_desc_count", CTLFLAG_RD, &sc->re_tx_desc_cnt,
1361 0, "TX desc count");
1362 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1363 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1364 OID_AUTO, "sim_time",
1365 CTLTYPE_INT | CTLFLAG_RW,
1366 sc, 0, re_sysctl_simtime, "I",
1367 "Simulated interrupt moderation time (usec).");
1368 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1369 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1371 CTLTYPE_INT | CTLFLAG_RW,
1372 sc, 0, re_sysctl_imtype, "I",
1373 "Interrupt moderation type -- "
1374 "0:disable, 1:simulated, "
1375 "2:hardware(if supported)");
1376 if (sc->re_caps & RE_C_HWIM) {
1377 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1378 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1379 OID_AUTO, "hw_rxtime",
1380 CTLTYPE_INT | CTLFLAG_RW,
1381 sc, 0, re_sysctl_rxtime, "I",
1382 "Hardware interrupt moderation time "
1384 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1385 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1386 OID_AUTO, "hw_txtime",
1387 CTLTYPE_INT | CTLFLAG_RW,
1388 sc, 0, re_sysctl_txtime, "I",
1389 "Hardware interrupt moderation time "
1393 #ifndef BURN_BRIDGES
1395 * Handle power management nonsense.
1398 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1399 uint32_t membase, irq;
1401 /* Save important PCI config data. */
1402 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1403 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1405 /* Reset the power state. */
1406 device_printf(dev, "chip is in D%d power mode "
1407 "-- setting to D0\n", pci_get_powerstate(dev));
1409 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1411 /* Restore PCI config data. */
1412 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1413 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1417 * Map control/status registers.
1419 pci_enable_busmaster(dev);
1422 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1425 if (sc->re_res == NULL) {
1426 device_printf(dev, "couldn't map ports\n");
1431 sc->re_btag = rman_get_bustag(sc->re_res);
1432 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1434 /* Allocate interrupt */
1436 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1437 RF_SHAREABLE | RF_ACTIVE);
1439 if (sc->re_irq == NULL) {
1440 device_printf(dev, "couldn't map interrupt\n");
1445 /* Reset the adapter. */
1448 if (RE_IS_8139CP(sc)) {
1449 sc->re_bus_speed = 33; /* XXX */
1450 } else if (sc->re_caps & RE_C_PCIE) {
1451 sc->re_bus_speed = 125;
1455 cfg2 = CSR_READ_1(sc, RE_CFG2);
1456 switch (cfg2 & RE_CFG2_PCICLK_MASK) {
1457 case RE_CFG2_PCICLK_33MHZ:
1458 sc->re_bus_speed = 33;
1460 case RE_CFG2_PCICLK_66MHZ:
1461 sc->re_bus_speed = 66;
1464 device_printf(dev, "unknown bus speed, assume 33MHz\n");
1465 sc->re_bus_speed = 33;
1468 if (cfg2 & RE_CFG2_PCI64)
1469 sc->re_caps |= RE_C_PCI64;
1471 device_printf(dev, "Hardware rev. 0x%08x; MAC ver. 0x%02x; "
1473 sc->re_hwrev, sc->re_macver,
1474 (sc->re_caps & RE_C_PCIE) ?
1475 "-E" : ((sc->re_caps & RE_C_PCI64) ? "64" : "32"),
1480 * DO NOT try to adjust config1 and config5 which was spotted in
1481 * Realtek's Linux drivers. It will _permanently_ damage certain
1482 * cards EEPROM, e.g. one of my 8168B (0x38000000) card ...
1485 re_get_eaddr(sc, eaddr);
1487 if (!RE_IS_8139CP(sc)) {
1488 /* Set RX length mask */
1489 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1490 sc->re_txstart = RE_GTXSTART;
1492 /* Set RX length mask */
1493 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1494 sc->re_txstart = RE_TXSTART;
1497 /* Allocate DMA stuffs */
1498 error = re_allocmem(dev);
1503 * Apply some magic PCI settings from Realtek ...
1505 if (RE_IS_8169(sc)) {
1506 CSR_WRITE_1(sc, 0x82, 1);
1507 pci_write_config(dev, PCIR_CACHELNSZ, 0x8, 1);
1509 pci_write_config(dev, PCIR_LATTIMER, 0x40, 1);
1511 if (sc->re_caps & RE_C_MAC2) {
1513 * Following part is extracted from Realtek BSD driver v176.
1514 * However, this does _not_ make much/any sense:
1515 * 8168C's PCI Express device control is located at 0x78,
1516 * so the reading from 0x79 (higher part of 0x78) and setting
1517 * the 4~6bits intend to enlarge the "max read request size"
1518 * (we will do it). The content of the rest part of this
1519 * register is not meaningful to other PCI registers, so
1520 * writing the value to 0x54 could be completely wrong.
1521 * 0x80 is the lower part of PCI Express device status, non-
1522 * reserved bits are RW1C, writing 0 to them will not have
1523 * any effect at all.
1528 val = pci_read_config(dev, 0x79, 1);
1529 val = (val & ~0x70) | 0x50;
1530 pci_write_config(dev, 0x54, val, 1);
1531 pci_write_config(dev, 0x80, 0, 1);
1536 * Apply some PHY fixup from Realtek ...
1538 if (sc->re_hwrev == RE_HWREV_8110S) {
1539 CSR_WRITE_1(sc, 0x82, 1);
1540 re_miibus_writereg(dev, 1, 0xb, 0);
1542 if (sc->re_caps & RE_C_PHYPMGT) {
1544 re_miibus_writereg(dev, 1, 0x1f, 0);
1545 re_miibus_writereg(dev, 1, 0xe, 0);
1549 if (mii_phy_probe(dev, &sc->re_miibus,
1550 re_ifmedia_upd, re_ifmedia_sts)) {
1551 device_printf(dev, "MII without any phy!\n");
1556 ifp = &sc->arpcom.ac_if;
1558 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1559 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1560 ifp->if_ioctl = re_ioctl;
1561 ifp->if_start = re_start;
1562 #ifdef DEVICE_POLLING
1563 ifp->if_poll = re_poll;
1565 ifp->if_watchdog = re_watchdog;
1566 ifp->if_init = re_init;
1567 if (!RE_IS_8139CP(sc)) /* XXX */
1568 ifp->if_baudrate = 1000000000;
1570 ifp->if_baudrate = 100000000;
1571 ifq_set_maxlen(&ifp->if_snd, qlen);
1572 ifq_set_ready(&ifp->if_snd);
1574 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1575 if (sc->re_caps & RE_C_HWCSUM)
1576 ifp->if_capabilities |= IFCAP_HWCSUM;
1578 ifp->if_capenable = ifp->if_capabilities;
1579 if (ifp->if_capabilities & IFCAP_HWCSUM)
1580 ifp->if_hwassist = RE_CSUM_FEATURES;
1582 ifp->if_hwassist = 0;
1585 * Call MI attach routine.
1587 ether_ifattach(ifp, eaddr, NULL);
1591 * Perform hardware diagnostic on the original RTL8169.
1592 * Some 32-bit cards were incorrectly wired and would
1593 * malfunction if plugged into a 64-bit slot.
1595 if (sc->re_hwrev == RE_HWREV_8169) {
1596 lwkt_serialize_enter(ifp->if_serializer);
1597 error = re_diag(sc);
1598 lwkt_serialize_exit(ifp->if_serializer);
1601 device_printf(dev, "hardware diagnostic failure\n");
1602 ether_ifdetach(ifp);
1606 #endif /* RE_DIAG */
1608 /* Hook interrupt last to avoid having to lock softc */
1609 error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc,
1610 &sc->re_intrhand, ifp->if_serializer);
1613 device_printf(dev, "couldn't set up irq\n");
1614 ether_ifdetach(ifp);
1618 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->re_irq));
1619 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1629 * Shutdown hardware and free up resources. This can be called any
1630 * time after the mutex has been initialized. It is called in both
1631 * the error case in attach and the normal detach case so it needs
1632 * to be careful about only freeing resources that have actually been
1636 re_detach(device_t dev)
1638 struct re_softc *sc = device_get_softc(dev);
1639 struct ifnet *ifp = &sc->arpcom.ac_if;
1641 /* These should only be active if attach succeeded */
1642 if (device_is_attached(dev)) {
1643 lwkt_serialize_enter(ifp->if_serializer);
1645 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1646 lwkt_serialize_exit(ifp->if_serializer);
1648 ether_ifdetach(ifp);
1651 device_delete_child(dev, sc->re_miibus);
1652 bus_generic_detach(dev);
1654 if (sc->re_sysctl_tree != NULL)
1655 sysctl_ctx_free(&sc->re_sysctl_ctx);
1658 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1660 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1664 /* Free DMA stuffs */
1671 re_setup_rxdesc(struct re_softc *sc, int idx)
1677 paddr = sc->re_ldata.re_rx_paddr[idx];
1678 d = &sc->re_ldata.re_rx_list[idx];
1680 d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr));
1681 d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr));
1683 cmdstat = sc->re_rxbuf_size | RE_RDESC_CMD_OWN;
1684 if (idx == (sc->re_rx_desc_cnt - 1))
1685 cmdstat |= RE_RDESC_CMD_EOR;
1686 d->re_cmdstat = htole32(cmdstat);
1690 re_newbuf_std(struct re_softc *sc, int idx, int init)
1692 bus_dma_segment_t seg;
1697 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1702 if_printf(&sc->arpcom.ac_if, "m_getcl failed\n");
1708 m->m_len = m->m_pkthdr.len = MCLBYTES;
1712 * re(4) chips need address of the receive buffer to be 8-byte
1713 * aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1716 error = bus_dmamap_load_mbuf_segment(sc->re_ldata.re_rx_mtag,
1717 sc->re_ldata.re_rx_spare, m,
1718 &seg, 1, &nsegs, BUS_DMA_NOWAIT);
1722 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
1730 bus_dmamap_sync(sc->re_ldata.re_rx_mtag,
1731 sc->re_ldata.re_rx_dmamap[idx],
1732 BUS_DMASYNC_POSTREAD);
1733 bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
1734 sc->re_ldata.re_rx_dmamap[idx]);
1736 sc->re_ldata.re_rx_mbuf[idx] = m;
1737 sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr;
1739 map = sc->re_ldata.re_rx_dmamap[idx];
1740 sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare;
1741 sc->re_ldata.re_rx_spare = map;
1743 re_setup_rxdesc(sc, idx);
1748 re_newbuf_jumbo(struct re_softc *sc, int idx, int init)
1751 struct re_jbuf *jbuf;
1754 MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1758 if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n");
1765 jbuf = re_jbuf_alloc(sc);
1771 if_printf(&sc->arpcom.ac_if, "jpool is empty\n");
1778 m->m_ext.ext_arg = jbuf;
1779 m->m_ext.ext_buf = jbuf->re_buf;
1780 m->m_ext.ext_free = re_jbuf_free;
1781 m->m_ext.ext_ref = re_jbuf_ref;
1782 m->m_ext.ext_size = sc->re_rxbuf_size;
1784 m->m_data = m->m_ext.ext_buf;
1785 m->m_flags |= M_EXT;
1786 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1790 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1791 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1794 sc->re_ldata.re_rx_mbuf[idx] = m;
1795 sc->re_ldata.re_rx_paddr[idx] = jbuf->re_paddr;
1797 re_setup_rxdesc(sc, idx);
1802 re_tx_list_init(struct re_softc *sc)
1804 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc));
1806 sc->re_ldata.re_tx_prodidx = 0;
1807 sc->re_ldata.re_tx_considx = 0;
1808 sc->re_ldata.re_tx_free = sc->re_tx_desc_cnt;
1814 re_rx_list_init(struct re_softc *sc)
1818 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc));
1820 for (i = 0; i < sc->re_rx_desc_cnt; i++) {
1821 error = sc->re_newbuf(sc, i, 1);
1826 sc->re_ldata.re_rx_prodidx = 0;
1827 sc->re_head = sc->re_tail = NULL;
1832 #define RE_IP4_PACKET 0x1
1833 #define RE_TCP_PACKET 0x2
1834 #define RE_UDP_PACKET 0x4
1836 static __inline uint8_t
1837 re_packet_type(struct re_softc *sc, uint32_t rxstat, uint32_t rxctrl)
1839 uint8_t packet_type = 0;
1841 if (sc->re_caps & RE_C_MAC2) {
1842 if (rxctrl & RE_RDESC_CTL_PROTOIP4)
1843 packet_type |= RE_IP4_PACKET;
1845 if (rxstat & RE_RDESC_STAT_PROTOID)
1846 packet_type |= RE_IP4_PACKET;
1848 if (RE_TCPPKT(rxstat))
1849 packet_type |= RE_TCP_PACKET;
1850 else if (RE_UDPPKT(rxstat))
1851 packet_type |= RE_UDP_PACKET;
1856 * RX handler for C+ and 8169. For the gigE chips, we support
1857 * the reception of jumbo frames that have been fragmented
1858 * across multiple 2K mbuf cluster buffers.
1861 re_rxeof(struct re_softc *sc)
1863 struct ifnet *ifp = &sc->arpcom.ac_if;
1865 struct re_desc *cur_rx;
1866 uint32_t rxstat, rxctrl;
1867 int i, total_len, rx = 0;
1868 struct mbuf_chain chain[MAXCPU];
1870 ether_input_chain_init(chain);
1872 for (i = sc->re_ldata.re_rx_prodidx;
1873 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_RXDESC_INC(sc, i)) {
1874 cur_rx = &sc->re_ldata.re_rx_list[i];
1875 m = sc->re_ldata.re_rx_mbuf[i];
1876 total_len = RE_RXBYTES(cur_rx);
1877 rxstat = le32toh(cur_rx->re_cmdstat);
1878 rxctrl = le32toh(cur_rx->re_control);
1883 if (sc->re_flags & RE_F_USE_JPOOL)
1884 KKASSERT(rxstat & RE_RDESC_STAT_EOF);
1887 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1888 if (sc->re_flags & RE_F_DROP_RXFRAG) {
1889 re_setup_rxdesc(sc, i);
1893 if (sc->re_newbuf(sc, i, 0)) {
1894 /* Drop upcoming fragments */
1895 sc->re_flags |= RE_F_DROP_RXFRAG;
1899 m->m_len = MCLBYTES;
1900 if (sc->re_head == NULL) {
1901 sc->re_head = sc->re_tail = m;
1903 sc->re_tail->m_next = m;
1907 } else if (sc->re_flags & RE_F_DROP_RXFRAG) {
1909 * Last fragment of a multi-fragment packet.
1911 * Since error already happened, this fragment
1912 * must be dropped as well as the fragment chain.
1914 re_setup_rxdesc(sc, i);
1915 re_free_rxchain(sc);
1916 sc->re_flags &= ~RE_F_DROP_RXFRAG;
1921 * NOTE: for the 8139C+, the frame length field
1922 * is always 12 bits in size, but for the gigE chips,
1923 * it is 13 bits (since the max RX frame length is 16K).
1924 * Unfortunately, all 32 bits in the status word
1925 * were already used, so to make room for the extra
1926 * length bit, RealTek took out the 'frame alignment
1927 * error' bit and shifted the other status bits
1928 * over one slot. The OWN, EOR, FS and LS bits are
1929 * still in the same places. We have already extracted
1930 * the frame length and checked the OWN bit, so rather
1931 * than using an alternate bit mapping, we shift the
1932 * status bits one space to the right so we can evaluate
1933 * them using the 8169 status as though it was in the
1934 * same format as that of the 8139C+.
1936 if (!RE_IS_8139CP(sc))
1939 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1942 * If this is part of a multi-fragment packet,
1943 * discard all the pieces.
1945 re_free_rxchain(sc);
1946 re_setup_rxdesc(sc, i);
1951 * If allocating a replacement mbuf fails,
1952 * reload the current one.
1955 if (sc->re_newbuf(sc, i, 0)) {
1960 if (sc->re_head != NULL) {
1961 m->m_len = total_len % MCLBYTES;
1963 * Special case: if there's 4 bytes or less
1964 * in this buffer, the mbuf can be discarded:
1965 * the last 4 bytes is the CRC, which we don't
1966 * care about anyway.
1968 if (m->m_len <= ETHER_CRC_LEN) {
1969 sc->re_tail->m_len -=
1970 (ETHER_CRC_LEN - m->m_len);
1973 m->m_len -= ETHER_CRC_LEN;
1974 sc->re_tail->m_next = m;
1977 sc->re_head = sc->re_tail = NULL;
1978 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1980 m->m_pkthdr.len = m->m_len =
1981 (total_len - ETHER_CRC_LEN);
1985 m->m_pkthdr.rcvif = ifp;
1987 /* Do RX checksumming if enabled */
1989 if (ifp->if_capenable & IFCAP_RXCSUM) {
1990 uint8_t packet_type;
1992 packet_type = re_packet_type(sc, rxstat, rxctrl);
1994 /* Check IP header checksum */
1995 if (packet_type & RE_IP4_PACKET) {
1996 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1997 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1998 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2001 /* Check TCP/UDP checksum */
2002 if (((packet_type & RE_TCP_PACKET) &&
2003 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
2004 ((packet_type & RE_UDP_PACKET) &&
2005 (rxstat & RE_RDESC_STAT_UDPSUMBAD) == 0)) {
2006 m->m_pkthdr.csum_flags |=
2007 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
2008 CSUM_FRAG_NOT_CHECKED;
2009 m->m_pkthdr.csum_data = 0xffff;
2013 if (rxctrl & RE_RDESC_CTL_HASTAG) {
2014 m->m_flags |= M_VLANTAG;
2015 m->m_pkthdr.ether_vlantag =
2016 be16toh((rxctrl & RE_RDESC_CTL_TAGDATA));
2018 ether_input_chain(ifp, m, NULL, chain);
2021 ether_input_dispatch(chain);
2023 sc->re_ldata.re_rx_prodidx = i;
2028 #undef RE_IP4_PACKET
2029 #undef RE_TCP_PACKET
2030 #undef RE_UDP_PACKET
2033 re_tx_collect(struct re_softc *sc)
2035 struct ifnet *ifp = &sc->arpcom.ac_if;
2039 for (idx = sc->re_ldata.re_tx_considx;
2040 sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt;
2041 RE_TXDESC_INC(sc, idx)) {
2042 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
2043 if (txstat & RE_TDESC_CMD_OWN)
2048 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0;
2051 * We only stash mbufs in the last descriptor
2052 * in a fragment chain, which also happens to
2053 * be the only place where the TX status bits
2056 if (txstat & RE_TDESC_CMD_EOF) {
2057 bus_dmamap_unload(sc->re_ldata.re_tx_mtag,
2058 sc->re_ldata.re_tx_dmamap[idx]);
2059 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
2060 sc->re_ldata.re_tx_mbuf[idx] = NULL;
2061 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
2062 RE_TDESC_STAT_COLCNT))
2063 ifp->if_collisions++;
2064 if (txstat & RE_TDESC_STAT_TXERRSUM)
2069 sc->re_ldata.re_tx_free++;
2071 sc->re_ldata.re_tx_considx = idx;
2077 re_txeof(struct re_softc *sc)
2079 struct ifnet *ifp = &sc->arpcom.ac_if;
2082 tx = re_tx_collect(sc);
2084 /* There is enough free TX descs */
2085 if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE)
2086 ifp->if_flags &= ~IFF_OACTIVE;
2089 * Some chips will ignore a second TX request issued while an
2090 * existing transmission is in progress. If the transmitter goes
2091 * idle but there are still packets waiting to be sent, we need
2092 * to restart the channel here to flush them out. This only seems
2093 * to be required with the PCIe devices.
2095 if (sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt)
2096 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2106 struct re_softc *sc = xsc;
2108 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
2109 re_tick_serialized(xsc);
2110 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
2114 re_tick_serialized(void *xsc)
2116 struct re_softc *sc = xsc;
2117 struct ifnet *ifp = &sc->arpcom.ac_if;
2118 struct mii_data *mii;
2120 ASSERT_SERIALIZED(ifp->if_serializer);
2122 mii = device_get_softc(sc->re_miibus);
2124 if (sc->re_flags & RE_F_LINKED) {
2125 if (!(mii->mii_media_status & IFM_ACTIVE))
2126 sc->re_flags &= ~RE_F_LINKED;
2128 if (mii->mii_media_status & IFM_ACTIVE &&
2129 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2130 sc->re_flags |= RE_F_LINKED;
2131 if (!ifq_is_empty(&ifp->if_snd))
2136 callout_reset(&sc->re_timer, hz, re_tick, sc);
2139 #ifdef DEVICE_POLLING
2142 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2144 struct re_softc *sc = ifp->if_softc;
2146 ASSERT_SERIALIZED(ifp->if_serializer);
2150 /* disable interrupts */
2151 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
2154 case POLL_DEREGISTER:
2155 /* enable interrupts */
2156 re_setup_intr(sc, 1, sc->re_imtype);
2160 sc->rxcycles = count;
2164 if (!ifq_is_empty(&ifp->if_snd))
2167 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2170 status = CSR_READ_2(sc, RE_ISR);
2171 if (status == 0xffff)
2174 CSR_WRITE_2(sc, RE_ISR, status);
2177 * XXX check behaviour on receiver stalls.
2180 if (status & RE_ISR_SYSTEM_ERR)
2186 #endif /* DEVICE_POLLING */
2191 struct re_softc *sc = arg;
2192 struct ifnet *ifp = &sc->arpcom.ac_if;
2196 ASSERT_SERIALIZED(ifp->if_serializer);
2198 if ((sc->re_flags & RE_F_SUSPENDED) ||
2199 (ifp->if_flags & IFF_RUNNING) == 0)
2204 status = CSR_READ_2(sc, RE_ISR);
2205 /* If the card has gone away the read returns 0xffff. */
2206 if (status == 0xffff)
2209 CSR_WRITE_2(sc, RE_ISR, status);
2211 if ((status & sc->re_intrs) == 0)
2214 if (status & (sc->re_rx_ack | RE_ISR_RX_ERR))
2217 if (status & (sc->re_tx_ack | RE_ISR_TX_ERR))
2220 if (status & RE_ISR_SYSTEM_ERR)
2223 if (status & RE_ISR_LINKCHG) {
2224 callout_stop(&sc->re_timer);
2225 re_tick_serialized(sc);
2229 if (sc->re_imtype == RE_IMTYPE_SIM) {
2230 if ((sc->re_flags & RE_F_TIMER_INTR)) {
2231 if ((tx | rx) == 0) {
2233 * Nothing needs to be processed, fallback
2234 * to use TX/RX interrupts.
2236 re_setup_intr(sc, 1, RE_IMTYPE_NONE);
2239 * Recollect, mainly to avoid the possible
2240 * race introduced by changing interrupt
2246 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */
2248 } else if (tx | rx) {
2250 * Assume that using simulated interrupt moderation
2251 * (hardware timer based) could reduce the interript
2254 re_setup_intr(sc, 1, RE_IMTYPE_SIM);
2258 if (tx && !ifq_is_empty(&ifp->if_snd))
2263 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0)
2265 struct mbuf *m = *m_head;
2266 bus_dma_segment_t segs[RE_MAXSEGS];
2268 int error, maxsegs, idx, i, nsegs;
2269 struct re_desc *d, *tx_ring;
2270 uint32_t cmd_csum, ctl_csum, vlantag;
2272 KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE,
2273 ("not enough free TX desc\n"));
2275 map = sc->re_ldata.re_tx_dmamap[*idx0];
2278 * Set up checksum offload. Note: checksum offload bits must
2279 * appear in all descriptors of a multi-descriptor transmit
2280 * attempt. (This is according to testing done with an 8169
2281 * chip. I'm not sure if this is a requirement or a bug.)
2283 cmd_csum = ctl_csum = 0;
2284 if (m->m_pkthdr.csum_flags & CSUM_IP) {
2285 cmd_csum |= RE_TDESC_CMD_IPCSUM;
2286 ctl_csum |= RE_TDESC_CTL_IPCSUM;
2288 if (m->m_pkthdr.csum_flags & CSUM_TCP) {
2289 cmd_csum |= RE_TDESC_CMD_TCPCSUM;
2290 ctl_csum |= RE_TDESC_CTL_TCPCSUM;
2292 if (m->m_pkthdr.csum_flags & CSUM_UDP) {
2293 cmd_csum |= RE_TDESC_CMD_UDPCSUM;
2294 ctl_csum |= RE_TDESC_CTL_UDPCSUM;
2297 /* For MAC2 chips, csum flags are set on re_control */
2298 if (sc->re_caps & RE_C_MAC2)
2303 if ((sc->re_caps & RE_C_AUTOPAD) == 0) {
2305 * With some of the RealTek chips, using the checksum offload
2306 * support in conjunction with the autopadding feature results
2307 * in the transmission of corrupt frames. For example, if we
2308 * need to send a really small IP fragment that's less than 60
2309 * bytes in size, and IP header checksumming is enabled, the
2310 * resulting ethernet frame that appears on the wire will
2311 * have garbled payload. To work around this, if TX checksum
2312 * offload is enabled, we always manually pad short frames out
2313 * to the minimum ethernet frame size.
2315 * Note: this appears unnecessary for TCP, and doing it for TCP
2316 * with PCIe adapters seems to result in bad checksums.
2318 if ((m->m_pkthdr.csum_flags &
2319 (CSUM_DELAY_IP | CSUM_DELAY_DATA)) &&
2320 (m->m_pkthdr.csum_flags & CSUM_TCP) == 0 &&
2321 m->m_pkthdr.len < RE_MIN_FRAMELEN) {
2322 error = m_devpad(m, RE_MIN_FRAMELEN);
2329 if (m->m_flags & M_VLANTAG) {
2330 vlantag = htobe16(m->m_pkthdr.ether_vlantag) |
2331 RE_TDESC_CTL_INSTAG;
2334 maxsegs = sc->re_ldata.re_tx_free;
2335 if (maxsegs > RE_MAXSEGS)
2336 maxsegs = RE_MAXSEGS;
2338 error = bus_dmamap_load_mbuf_defrag(sc->re_ldata.re_tx_mtag, map,
2339 m_head, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2344 bus_dmamap_sync(sc->re_ldata.re_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2347 * Map the segment array into descriptors. We also keep track
2348 * of the end of the ring and set the end-of-ring bits as needed,
2349 * and we set the ownership bits in all except the very first
2350 * descriptor, whose ownership bits will be turned on later.
2352 tx_ring = sc->re_ldata.re_tx_list;
2360 cmdstat = segs[i].ds_len;
2361 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
2362 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
2364 cmdstat |= RE_TDESC_CMD_SOF;
2366 cmdstat |= RE_TDESC_CMD_OWN;
2367 if (idx == (sc->re_tx_desc_cnt - 1))
2368 cmdstat |= RE_TDESC_CMD_EOR;
2369 d->re_cmdstat = htole32(cmdstat | cmd_csum);
2370 d->re_control = htole32(ctl_csum | vlantag);
2375 RE_TXDESC_INC(sc, idx);
2377 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
2379 /* Transfer ownership of packet to the chip. */
2380 d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
2382 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
2385 * Insure that the map for this transmission
2386 * is placed at the array index of the last descriptor
2389 sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx];
2390 sc->re_ldata.re_tx_dmamap[idx] = map;
2392 sc->re_ldata.re_tx_mbuf[idx] = m;
2393 sc->re_ldata.re_tx_free -= nsegs;
2395 RE_TXDESC_INC(sc, idx);
2406 * Main transmit routine for C+ and gigE NICs.
2410 re_start(struct ifnet *ifp)
2412 struct re_softc *sc = ifp->if_softc;
2413 struct mbuf *m_head;
2414 int idx, need_trans, oactive, error;
2416 ASSERT_SERIALIZED(ifp->if_serializer);
2418 if ((sc->re_flags & RE_F_LINKED) == 0) {
2419 ifq_purge(&ifp->if_snd);
2423 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
2426 idx = sc->re_ldata.re_tx_prodidx;
2430 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
2431 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) {
2433 if (re_tx_collect(sc)) {
2438 ifp->if_flags |= IFF_OACTIVE;
2442 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2446 error = re_encap(sc, &m_head, &idx);
2448 /* m_head is freed by re_encap(), if we reach here */
2451 if (error == EFBIG && !oactive) {
2452 if (re_tx_collect(sc)) {
2457 ifp->if_flags |= IFF_OACTIVE;
2465 * If there's a BPF listener, bounce a copy of this frame
2468 ETHER_BPF_MTAP(ifp, m_head);
2474 sc->re_ldata.re_tx_prodidx = idx;
2477 * RealTek put the TX poll request register in a different
2478 * location on the 8169 gigE chip. I don't know why.
2480 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2483 * Set a timeout in case the chip goes out to lunch.
2491 struct re_softc *sc = xsc;
2492 struct ifnet *ifp = &sc->arpcom.ac_if;
2493 struct mii_data *mii;
2494 int error, framelen;
2496 ASSERT_SERIALIZED(ifp->if_serializer);
2498 mii = device_get_softc(sc->re_miibus);
2501 * Cancel pending I/O and free all RX/TX buffers.
2505 if (sc->re_caps & RE_C_CONTIGRX) {
2506 if (ifp->if_mtu > ETHERMTU) {
2507 KKASSERT(sc->re_ldata.re_jbuf != NULL);
2508 sc->re_flags |= RE_F_USE_JPOOL;
2509 sc->re_rxbuf_size = RE_FRAMELEN_MAX;
2510 sc->re_newbuf = re_newbuf_jumbo;
2512 sc->re_flags &= ~RE_F_USE_JPOOL;
2513 sc->re_rxbuf_size = MCLBYTES;
2514 sc->re_newbuf = re_newbuf_std;
2519 * Adjust max read request size according to MTU; mainly to
2520 * improve TX performance for common case (ETHERMTU) on GigE
2521 * NICs. However, this could _not_ be done on 10/100 only
2522 * NICs; their DMA engines will malfunction using non-default
2523 * max read request size.
2525 if ((sc->re_caps & (RE_C_PCIE | RE_C_FASTE)) == RE_C_PCIE) {
2526 if (ifp->if_mtu > ETHERMTU) {
2528 * 512 seems to be the only value that works
2529 * reliably with jumbo frame
2531 pcie_set_max_readrq(sc->re_dev,
2532 PCIEM_DEVCTL_MAX_READRQ_512);
2534 pcie_set_max_readrq(sc->re_dev,
2535 PCIEM_DEVCTL_MAX_READRQ_4096);
2540 * Enable C+ RX and TX mode, as well as VLAN stripping and
2541 * RX checksum offload. We must configure the C+ register
2542 * before all others.
2544 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
2545 RE_CPLUSCMD_PCI_MRW |
2546 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING ?
2547 RE_CPLUSCMD_VLANSTRIP : 0) |
2548 (ifp->if_capenable & IFCAP_RXCSUM ?
2549 RE_CPLUSCMD_RXCSUM_ENB : 0));
2552 * Init our MAC address. Even though the chipset
2553 * documentation doesn't mention it, we need to enter "Config
2554 * register write enable" mode to modify the ID registers.
2556 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
2557 CSR_WRITE_4(sc, RE_IDR0,
2558 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0])));
2559 CSR_WRITE_2(sc, RE_IDR4,
2560 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4])));
2561 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
2564 * For C+ mode, initialize the RX descriptors and mbufs.
2566 error = re_rx_list_init(sc);
2571 error = re_tx_list_init(sc);
2578 * Load the addresses of the RX and TX lists into the chip.
2580 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2581 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2582 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2583 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2585 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2586 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2587 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2588 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2591 * Enable transmit and receive.
2593 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2596 * Set the initial TX and RX configuration.
2598 if (sc->re_flags & RE_F_TESTMODE) {
2599 if (!RE_IS_8139CP(sc))
2600 CSR_WRITE_4(sc, RE_TXCFG,
2601 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
2603 CSR_WRITE_4(sc, RE_TXCFG,
2604 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
2606 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
2608 framelen = RE_FRAMELEN(ifp->if_mtu);
2609 if (framelen < MCLBYTES)
2610 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(MCLBYTES, 128));
2612 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128));
2614 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
2617 * Program the multicast filter, if necessary.
2621 #ifdef DEVICE_POLLING
2623 * Disable interrupts if we are polling.
2625 if (ifp->if_flags & IFF_POLLING)
2626 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
2627 else /* otherwise ... */
2628 #endif /* DEVICE_POLLING */
2630 * Enable interrupts.
2632 if (sc->re_flags & RE_F_TESTMODE)
2633 CSR_WRITE_2(sc, RE_IMR, 0);
2635 re_setup_intr(sc, 1, sc->re_imtype);
2636 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs);
2638 /* Start RX/TX process. */
2639 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
2642 /* Enable receiver and transmitter. */
2643 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2647 * For 8169 gigE NICs, set the max allowed RX packet
2648 * size so we can receive jumbo frames.
2650 if (!RE_IS_8139CP(sc)) {
2651 if (sc->re_caps & RE_C_CONTIGRX)
2652 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, sc->re_rxbuf_size);
2654 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2657 if (sc->re_flags & RE_F_TESTMODE)
2662 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2664 ifp->if_flags |= IFF_RUNNING;
2665 ifp->if_flags &= ~IFF_OACTIVE;
2667 callout_reset(&sc->re_timer, hz, re_tick, sc);
2671 * Set media options.
2674 re_ifmedia_upd(struct ifnet *ifp)
2676 struct re_softc *sc = ifp->if_softc;
2677 struct mii_data *mii;
2679 ASSERT_SERIALIZED(ifp->if_serializer);
2681 mii = device_get_softc(sc->re_miibus);
2688 * Report current media status.
2691 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2693 struct re_softc *sc = ifp->if_softc;
2694 struct mii_data *mii;
2696 ASSERT_SERIALIZED(ifp->if_serializer);
2698 mii = device_get_softc(sc->re_miibus);
2701 ifmr->ifm_active = mii->mii_media_active;
2702 ifmr->ifm_status = mii->mii_media_status;
2706 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2708 struct re_softc *sc = ifp->if_softc;
2709 struct ifreq *ifr = (struct ifreq *) data;
2710 struct mii_data *mii;
2711 int error = 0, mask;
2713 ASSERT_SERIALIZED(ifp->if_serializer);
2717 if (ifr->ifr_mtu > sc->re_maxmtu) {
2719 } else if (ifp->if_mtu != ifr->ifr_mtu) {
2720 ifp->if_mtu = ifr->ifr_mtu;
2721 if (ifp->if_flags & IFF_RUNNING)
2727 if (ifp->if_flags & IFF_UP) {
2728 if (ifp->if_flags & IFF_RUNNING) {
2729 if ((ifp->if_flags ^ sc->re_if_flags) &
2730 (IFF_PROMISC | IFF_ALLMULTI))
2735 } else if (ifp->if_flags & IFF_RUNNING) {
2738 sc->re_if_flags = ifp->if_flags;
2748 mii = device_get_softc(sc->re_miibus);
2749 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2753 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) &
2754 ifp->if_capabilities;
2755 ifp->if_capenable ^= mask;
2757 if (mask & IFCAP_HWCSUM) {
2758 if (ifp->if_capenable & IFCAP_TXCSUM)
2759 ifp->if_hwassist = RE_CSUM_FEATURES;
2761 ifp->if_hwassist = 0;
2763 if (mask && (ifp->if_flags & IFF_RUNNING))
2768 error = ether_ioctl(ifp, command, data);
2775 re_watchdog(struct ifnet *ifp)
2777 struct re_softc *sc = ifp->if_softc;
2779 ASSERT_SERIALIZED(ifp->if_serializer);
2781 if_printf(ifp, "watchdog timeout\n");
2790 if (!ifq_is_empty(&ifp->if_snd))
2795 * Stop the adapter and free any mbufs allocated to the
2799 re_stop(struct re_softc *sc)
2801 struct ifnet *ifp = &sc->arpcom.ac_if;
2804 ASSERT_SERIALIZED(ifp->if_serializer);
2806 /* Reset the adapter. */
2807 re_reset(sc, ifp->if_flags & IFF_RUNNING);
2810 callout_stop(&sc->re_timer);
2812 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2813 sc->re_flags &= ~(RE_F_TIMER_INTR | RE_F_DROP_RXFRAG | RE_F_LINKED);
2815 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2816 CSR_WRITE_2(sc, RE_IMR, 0x0000);
2817 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
2819 re_free_rxchain(sc);
2821 /* Free the TX list buffers. */
2822 for (i = 0; i < sc->re_tx_desc_cnt; i++) {
2823 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2824 bus_dmamap_unload(sc->re_ldata.re_tx_mtag,
2825 sc->re_ldata.re_tx_dmamap[i]);
2826 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2827 sc->re_ldata.re_tx_mbuf[i] = NULL;
2831 /* Free the RX list buffers. */
2832 for (i = 0; i < sc->re_rx_desc_cnt; i++) {
2833 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2834 if ((sc->re_flags & RE_F_USE_JPOOL) == 0) {
2835 bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
2836 sc->re_ldata.re_rx_dmamap[i]);
2838 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2839 sc->re_ldata.re_rx_mbuf[i] = NULL;
2845 * Device suspend routine. Stop the interface and save some PCI
2846 * settings in case the BIOS doesn't restore them properly on
2850 re_suspend(device_t dev)
2852 #ifndef BURN_BRIDGES
2855 struct re_softc *sc = device_get_softc(dev);
2856 struct ifnet *ifp = &sc->arpcom.ac_if;
2858 lwkt_serialize_enter(ifp->if_serializer);
2862 #ifndef BURN_BRIDGES
2863 for (i = 0; i < 5; i++)
2864 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2865 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2866 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2867 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2868 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2871 sc->re_flags |= RE_F_SUSPENDED;
2873 lwkt_serialize_exit(ifp->if_serializer);
2879 * Device resume routine. Restore some PCI settings in case the BIOS
2880 * doesn't, re-enable busmastering, and restart the interface if
2884 re_resume(device_t dev)
2886 struct re_softc *sc = device_get_softc(dev);
2887 struct ifnet *ifp = &sc->arpcom.ac_if;
2888 #ifndef BURN_BRIDGES
2892 lwkt_serialize_enter(ifp->if_serializer);
2894 #ifndef BURN_BRIDGES
2895 /* better way to do this? */
2896 for (i = 0; i < 5; i++)
2897 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2898 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2899 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2900 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2901 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2903 /* reenable busmastering */
2904 pci_enable_busmaster(dev);
2905 pci_enable_io(dev, SYS_RES_IOPORT);
2908 /* reinitialize interface if necessary */
2909 if (ifp->if_flags & IFF_UP)
2912 sc->re_flags &= ~RE_F_SUSPENDED;
2914 lwkt_serialize_exit(ifp->if_serializer);
2920 * Stop all chip I/O so that the kernel's probe routines don't
2921 * get confused by errant DMAs when rebooting.
2924 re_shutdown(device_t dev)
2926 struct re_softc *sc = device_get_softc(dev);
2927 struct ifnet *ifp = &sc->arpcom.ac_if;
2929 lwkt_serialize_enter(ifp->if_serializer);
2931 lwkt_serialize_exit(ifp->if_serializer);
2935 re_sysctl_rxtime(SYSCTL_HANDLER_ARGS)
2937 struct re_softc *sc = arg1;
2939 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_rx_time);
2943 re_sysctl_txtime(SYSCTL_HANDLER_ARGS)
2945 struct re_softc *sc = arg1;
2947 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_tx_time);
2951 re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *hwtime)
2953 struct re_softc *sc = arg1;
2954 struct ifnet *ifp = &sc->arpcom.ac_if;
2957 lwkt_serialize_enter(ifp->if_serializer);
2960 error = sysctl_handle_int(oidp, &v, 0, req);
2961 if (error || req->newptr == NULL)
2972 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
2973 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_HW)
2977 lwkt_serialize_exit(ifp->if_serializer);
2982 re_sysctl_simtime(SYSCTL_HANDLER_ARGS)
2984 struct re_softc *sc = arg1;
2985 struct ifnet *ifp = &sc->arpcom.ac_if;
2988 lwkt_serialize_enter(ifp->if_serializer);
2990 v = sc->re_sim_time;
2991 error = sysctl_handle_int(oidp, &v, 0, req);
2992 if (error || req->newptr == NULL)
3000 if (v != sc->re_sim_time) {
3001 sc->re_sim_time = v;
3003 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
3004 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_SIM) {
3009 * Following code causes various strange
3010 * performance problems. Hmm ...
3012 CSR_WRITE_2(sc, RE_IMR, 0);
3013 if (!RE_IS_8139CP(sc))
3014 reg = RE_TIMERINT_8169;
3017 CSR_WRITE_4(sc, reg, 0);
3018 CSR_READ_4(sc, reg); /* flush */
3020 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
3021 re_setup_sim_im(sc);
3023 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
3025 re_setup_intr(sc, 1, RE_IMTYPE_SIM);
3030 lwkt_serialize_exit(ifp->if_serializer);
3035 re_sysctl_imtype(SYSCTL_HANDLER_ARGS)
3037 struct re_softc *sc = arg1;
3038 struct ifnet *ifp = &sc->arpcom.ac_if;
3041 lwkt_serialize_enter(ifp->if_serializer);
3044 error = sysctl_handle_int(oidp, &v, 0, req);
3045 if (error || req->newptr == NULL)
3048 if (v != RE_IMTYPE_HW && v != RE_IMTYPE_SIM && v != RE_IMTYPE_NONE) {
3052 if (v == RE_IMTYPE_HW && (sc->re_caps & RE_C_HWIM) == 0) {
3053 /* Can't do hardware interrupt moderation */
3058 if (v != sc->re_imtype) {
3060 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
3062 re_setup_intr(sc, 1, sc->re_imtype);
3065 lwkt_serialize_exit(ifp->if_serializer);
3070 re_setup_hw_im(struct re_softc *sc)
3072 KKASSERT(sc->re_caps & RE_C_HWIM);
3075 * Interrupt moderation
3078 * A - unknown (maybe TX related)
3079 * B - TX timer (unit: 25us)
3080 * C - unknown (maybe RX related)
3081 * D - RX timer (unit: 25us)
3084 * re(4)'s interrupt moderation is actually controlled by
3085 * two variables, like most other NICs (bge, bce etc.)
3087 * o number of packets [P]
3089 * The logic relationship between these two variables is
3090 * similar to other NICs too:
3091 * if (timer expire || packets > [P])
3092 * Interrupt is delivered
3094 * Currently we only know how to set 'timer', but not
3095 * 'number of packets', which should be ~30, as far as I
3096 * tested (sink ~900Kpps, interrupt rate is 30KHz)
3098 CSR_WRITE_2(sc, RE_IM,
3099 RE_IM_RXTIME(sc->re_rx_time) |
3100 RE_IM_TXTIME(sc->re_tx_time) |
3105 re_disable_hw_im(struct re_softc *sc)
3107 if (sc->re_caps & RE_C_HWIM)
3108 CSR_WRITE_2(sc, RE_IM, 0);
3112 re_setup_sim_im(struct re_softc *sc)
3114 if (!RE_IS_8139CP(sc)) {
3118 * Datasheet says tick decreases at bus speed,
3119 * but it seems the clock runs a little bit
3120 * faster, so we do some compensation here.
3122 ticks = (sc->re_sim_time * sc->re_bus_speed * 8) / 5;
3123 CSR_WRITE_4(sc, RE_TIMERINT_8169, ticks);
3125 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); /* XXX */
3127 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */
3128 sc->re_flags |= RE_F_TIMER_INTR;
3132 re_disable_sim_im(struct re_softc *sc)
3134 if (!RE_IS_8139CP(sc))
3135 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0);
3137 CSR_WRITE_4(sc, RE_TIMERINT, 0);
3138 sc->re_flags &= ~RE_F_TIMER_INTR;
3142 re_config_imtype(struct re_softc *sc, int imtype)
3146 KKASSERT(sc->re_caps & RE_C_HWIM);
3148 case RE_IMTYPE_NONE:
3149 sc->re_intrs = RE_INTRS;
3150 sc->re_rx_ack = RE_ISR_RX_OK | RE_ISR_FIFO_OFLOW |
3152 sc->re_tx_ack = RE_ISR_TX_OK;
3156 sc->re_intrs = RE_INTRS_TIMER;
3157 sc->re_rx_ack = RE_ISR_TIMEOUT_EXPIRED;
3158 sc->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED;
3162 panic("%s: unknown imtype %d\n",
3163 sc->arpcom.ac_if.if_xname, imtype);
3168 re_setup_intr(struct re_softc *sc, int enable_intrs, int imtype)
3170 re_config_imtype(sc, imtype);
3173 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
3175 CSR_WRITE_2(sc, RE_IMR, 0);
3178 case RE_IMTYPE_NONE:
3179 re_disable_sim_im(sc);
3180 re_disable_hw_im(sc);
3184 KKASSERT(sc->re_caps & RE_C_HWIM);
3185 re_disable_sim_im(sc);
3190 re_disable_hw_im(sc);
3191 re_setup_sim_im(sc);
3195 panic("%s: unknown imtype %d\n",
3196 sc->arpcom.ac_if.if_xname, imtype);
3201 re_get_eaddr(struct re_softc *sc, uint8_t *eaddr)
3205 if (sc->re_macver == RE_MACVER_11 ||
3206 sc->re_macver == RE_MACVER_12 ||
3207 sc->re_macver == RE_MACVER_30 ||
3208 sc->re_macver == RE_MACVER_31) {
3212 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
3213 if (re_did == 0x8128) {
3214 uint16_t as[ETHER_ADDR_LEN / 2];
3217 if (sc->re_macver == RE_MACVER_30 ||
3218 sc->re_macver == RE_MACVER_31)
3219 eaddr_off = RE_EE_EADDR1;
3221 eaddr_off = RE_EE_EADDR0;
3224 * Get station address from the EEPROM.
3226 re_read_eeprom(sc, (caddr_t)as, eaddr_off, 3);
3227 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
3228 as[i] = le16toh(as[i]);
3229 bcopy(as, eaddr, sizeof(eaddr));
3235 * Get station address from IDRx.
3237 for (i = 0; i < ETHER_ADDR_LEN; ++i)
3238 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i);
3242 re_jpool_alloc(struct re_softc *sc)
3244 struct re_list_data *ldata = &sc->re_ldata;
3245 struct re_jbuf *jbuf;
3247 bus_size_t jpool_size;
3252 lwkt_serialize_init(&ldata->re_jbuf_serializer);
3254 ldata->re_jbuf = kmalloc(sizeof(struct re_jbuf) * RE_JBUF_COUNT(sc),
3255 M_DEVBUF, M_WAITOK | M_ZERO);
3257 jpool_size = RE_JBUF_COUNT(sc) * RE_JBUF_SIZE;
3259 error = bus_dmamem_coherent(sc->re_parent_tag,
3261 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3262 jpool_size, BUS_DMA_WAITOK, &dmem);
3264 device_printf(sc->re_dev, "could not allocate jumbo memory\n");
3267 ldata->re_jpool_tag = dmem.dmem_tag;
3268 ldata->re_jpool_map = dmem.dmem_map;
3269 ldata->re_jpool = dmem.dmem_addr;
3270 paddr = dmem.dmem_busaddr;
3272 /* ..and split it into 9KB chunks */
3273 SLIST_INIT(&ldata->re_jbuf_free);
3275 buf = ldata->re_jpool;
3276 for (i = 0; i < RE_JBUF_COUNT(sc); i++) {
3277 jbuf = &ldata->re_jbuf[i];
3283 jbuf->re_paddr = paddr;
3285 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link);
3287 buf += RE_JBUF_SIZE;
3288 paddr += RE_JBUF_SIZE;
3294 re_jpool_free(struct re_softc *sc)
3296 struct re_list_data *ldata = &sc->re_ldata;
3298 if (ldata->re_jpool_tag != NULL) {
3299 bus_dmamap_unload(ldata->re_jpool_tag, ldata->re_jpool_map);
3300 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool,
3301 ldata->re_jpool_map);
3302 bus_dma_tag_destroy(ldata->re_jpool_tag);
3303 ldata->re_jpool_tag = NULL;
3306 if (ldata->re_jbuf != NULL) {
3307 kfree(ldata->re_jbuf, M_DEVBUF);
3308 ldata->re_jbuf = NULL;
3312 static struct re_jbuf *
3313 re_jbuf_alloc(struct re_softc *sc)
3315 struct re_list_data *ldata = &sc->re_ldata;
3316 struct re_jbuf *jbuf;
3318 lwkt_serialize_enter(&ldata->re_jbuf_serializer);
3320 jbuf = SLIST_FIRST(&ldata->re_jbuf_free);
3322 SLIST_REMOVE_HEAD(&ldata->re_jbuf_free, re_link);
3326 lwkt_serialize_exit(&ldata->re_jbuf_serializer);
3332 re_jbuf_free(void *arg)
3334 struct re_jbuf *jbuf = arg;
3335 struct re_softc *sc = jbuf->re_sc;
3336 struct re_list_data *ldata = &sc->re_ldata;
3338 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) {
3339 panic("%s: free wrong jumbo buffer\n",
3340 sc->arpcom.ac_if.if_xname);
3341 } else if (jbuf->re_inuse == 0) {
3342 panic("%s: jumbo buffer already freed\n",
3343 sc->arpcom.ac_if.if_xname);
3346 lwkt_serialize_enter(&ldata->re_jbuf_serializer);
3347 atomic_subtract_int(&jbuf->re_inuse, 1);
3348 if (jbuf->re_inuse == 0)
3349 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link);
3350 lwkt_serialize_exit(&ldata->re_jbuf_serializer);
3354 re_jbuf_ref(void *arg)
3356 struct re_jbuf *jbuf = arg;
3357 struct re_softc *sc = jbuf->re_sc;
3358 struct re_list_data *ldata = &sc->re_ldata;
3360 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) {
3361 panic("%s: ref wrong jumbo buffer\n",
3362 sc->arpcom.ac_if.if_xname);
3363 } else if (jbuf->re_inuse == 0) {
3364 panic("%s: jumbo buffer already freed\n",
3365 sc->arpcom.ac_if.if_xname);
3367 atomic_add_int(&jbuf->re_inuse, 1);