2 * Copyright (c) 1997, 1998, 1999, 2000
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $
33 * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.4 2003/08/07 21:17:05 dillon Exp $
35 * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $
39 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
40 * the SK-984x series adapters, both single port and dual port.
42 * The XaQti XMAC II datasheet,
43 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
44 * The SysKonnect GEnesis manual, http://www.syskonnect.com
46 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the
47 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
48 * convenience to others until Vitesse corrects this problem:
50 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
52 * Written by Bill Paul <wpaul@ee.columbia.edu>
53 * Department of Electrical Engineering
54 * Columbia University, New York City
58 * The SysKonnect gigabit ethernet adapters consist of two main
59 * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
60 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
61 * components and a PHY while the GEnesis controller provides a PCI
62 * interface with DMA support. Each card may have between 512K and
63 * 2MB of SRAM on board depending on the configuration.
65 * The SysKonnect GEnesis controller can have either one or two XMAC
66 * chips connected to it, allowing single or dual port NIC configurations.
67 * SysKonnect has the distinction of being the only vendor on the market
68 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
69 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
70 * XMAC registers. This driver takes advantage of these features to allow
71 * both XMACs to operate as independent interfaces.
74 #include <sys/param.h>
75 #include <sys/systm.h>
76 #include <sys/sockio.h>
78 #include <sys/malloc.h>
79 #include <sys/kernel.h>
80 #include <sys/socket.h>
81 #include <sys/queue.h>
84 #include <net/if_arp.h>
85 #include <net/ethernet.h>
86 #include <net/if_dl.h>
87 #include <net/if_media.h>
91 #include <vm/vm.h> /* for vtophys */
92 #include <vm/pmap.h> /* for vtophys */
93 #include <machine/clock.h> /* for DELAY */
94 #include <machine/bus_pio.h>
95 #include <machine/bus_memio.h>
96 #include <machine/bus.h>
97 #include <machine/resource.h>
101 #include "../mii_layer/mii.h"
102 #include "../mii_layer/miivar.h"
103 #include "../mii_layer/brgphyreg.h"
105 #include <bus/pci/pcireg.h>
106 #include <bus/pci/pcivar.h>
108 #define SK_USEIOSPACE
110 #include "if_skreg.h"
111 #include "xmaciireg.h"
113 /* "controller miibus0" required. See GENERIC if you get errors here. */
114 #include "miibus_if.h"
116 static struct sk_type sk_devs[] = {
117 { SK_VENDORID, SK_DEVICEID_GE, "SysKonnect Gigabit Ethernet" },
121 static int sk_probe __P((device_t));
122 static int sk_attach __P((device_t));
123 static int sk_detach __P((device_t));
124 static int sk_detach_xmac __P((device_t));
125 static int sk_probe_xmac __P((device_t));
126 static int sk_attach_xmac __P((device_t));
127 static void sk_tick __P((void *));
128 static void sk_intr __P((void *));
129 static void sk_intr_xmac __P((struct sk_if_softc *));
130 static void sk_intr_bcom __P((struct sk_if_softc *));
131 static void sk_rxeof __P((struct sk_if_softc *));
132 static void sk_txeof __P((struct sk_if_softc *));
133 static int sk_encap __P((struct sk_if_softc *, struct mbuf *,
135 static void sk_start __P((struct ifnet *));
136 static int sk_ioctl __P((struct ifnet *, u_long, caddr_t));
137 static void sk_init __P((void *));
138 static void sk_init_xmac __P((struct sk_if_softc *));
139 static void sk_stop __P((struct sk_if_softc *));
140 static void sk_watchdog __P((struct ifnet *));
141 static void sk_shutdown __P((device_t));
142 static int sk_ifmedia_upd __P((struct ifnet *));
143 static void sk_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
144 static void sk_reset __P((struct sk_softc *));
145 static int sk_newbuf __P((struct sk_if_softc *,
146 struct sk_chain *, struct mbuf *));
147 static int sk_alloc_jumbo_mem __P((struct sk_if_softc *));
148 static void *sk_jalloc __P((struct sk_if_softc *));
149 static void sk_jfree __P((caddr_t, u_int));
150 static void sk_jref __P((caddr_t, u_int));
151 static int sk_init_rx_ring __P((struct sk_if_softc *));
152 static void sk_init_tx_ring __P((struct sk_if_softc *));
153 static u_int32_t sk_win_read_4 __P((struct sk_softc *, int));
154 static u_int16_t sk_win_read_2 __P((struct sk_softc *, int));
155 static u_int8_t sk_win_read_1 __P((struct sk_softc *, int));
156 static void sk_win_write_4 __P((struct sk_softc *, int, u_int32_t));
157 static void sk_win_write_2 __P((struct sk_softc *, int, u_int32_t));
158 static void sk_win_write_1 __P((struct sk_softc *, int, u_int32_t));
159 static u_int8_t sk_vpd_readbyte __P((struct sk_softc *, int));
160 static void sk_vpd_read_res __P((struct sk_softc *,
161 struct vpd_res *, int));
162 static void sk_vpd_read __P((struct sk_softc *));
164 static int sk_miibus_readreg __P((device_t, int, int));
165 static int sk_miibus_writereg __P((device_t, int, int, int));
166 static void sk_miibus_statchg __P((device_t));
168 static u_int32_t sk_calchash __P((caddr_t));
169 static void sk_setfilt __P((struct sk_if_softc *, caddr_t, int));
170 static void sk_setmulti __P((struct sk_if_softc *));
173 #define SK_RES SYS_RES_IOPORT
174 #define SK_RID SK_PCI_LOIO
176 #define SK_RES SYS_RES_MEMORY
177 #define SK_RID SK_PCI_LOMEM
181 * Note that we have newbus methods for both the GEnesis controller
182 * itself and the XMAC(s). The XMACs are children of the GEnesis, and
183 * the miibus code is a child of the XMACs. We need to do it this way
184 * so that the miibus drivers can access the PHY registers on the
185 * right PHY. It's not quite what I had in mind, but it's the only
186 * design that achieves the desired effect.
188 static device_method_t skc_methods[] = {
189 /* Device interface */
190 DEVMETHOD(device_probe, sk_probe),
191 DEVMETHOD(device_attach, sk_attach),
192 DEVMETHOD(device_detach, sk_detach),
193 DEVMETHOD(device_shutdown, sk_shutdown),
196 DEVMETHOD(bus_print_child, bus_generic_print_child),
197 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
202 static driver_t skc_driver = {
205 sizeof(struct sk_softc)
208 static devclass_t skc_devclass;
210 static device_method_t sk_methods[] = {
211 /* Device interface */
212 DEVMETHOD(device_probe, sk_probe_xmac),
213 DEVMETHOD(device_attach, sk_attach_xmac),
214 DEVMETHOD(device_detach, sk_detach_xmac),
215 DEVMETHOD(device_shutdown, bus_generic_shutdown),
218 DEVMETHOD(bus_print_child, bus_generic_print_child),
219 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
222 DEVMETHOD(miibus_readreg, sk_miibus_readreg),
223 DEVMETHOD(miibus_writereg, sk_miibus_writereg),
224 DEVMETHOD(miibus_statchg, sk_miibus_statchg),
229 static driver_t sk_driver = {
232 sizeof(struct sk_if_softc)
235 static devclass_t sk_devclass;
237 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0);
238 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0);
239 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
241 #define SK_SETBIT(sc, reg, x) \
242 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
244 #define SK_CLRBIT(sc, reg, x) \
245 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
247 #define SK_WIN_SETBIT_4(sc, reg, x) \
248 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
250 #define SK_WIN_CLRBIT_4(sc, reg, x) \
251 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
253 #define SK_WIN_SETBIT_2(sc, reg, x) \
254 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
256 #define SK_WIN_CLRBIT_2(sc, reg, x) \
257 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
259 static u_int32_t sk_win_read_4(sc, reg)
263 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
264 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
267 static u_int16_t sk_win_read_2(sc, reg)
271 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
272 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
275 static u_int8_t sk_win_read_1(sc, reg)
279 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
280 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
283 static void sk_win_write_4(sc, reg, val)
288 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
289 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
293 static void sk_win_write_2(sc, reg, val)
298 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
299 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), (u_int32_t)val);
303 static void sk_win_write_1(sc, reg, val)
308 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
309 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
314 * The VPD EEPROM contains Vital Product Data, as suggested in
315 * the PCI 2.1 specification. The VPD data is separared into areas
316 * denoted by resource IDs. The SysKonnect VPD contains an ID string
317 * resource (the name of the adapter), a read-only area resource
318 * containing various key/data fields and a read/write area which
319 * can be used to store asset management information or log messages.
320 * We read the ID string and read-only into buffers attached to
321 * the controller softc structure for later use. At the moment,
322 * we only use the ID string during sk_attach().
324 static u_int8_t sk_vpd_readbyte(sc, addr)
330 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr);
331 for (i = 0; i < SK_TIMEOUT; i++) {
333 if (sk_win_read_2(sc,
334 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG)
341 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)));
344 static void sk_vpd_read_res(sc, res, addr)
352 ptr = (u_int8_t *)res;
353 for (i = 0; i < sizeof(struct vpd_res); i++)
354 ptr[i] = sk_vpd_readbyte(sc, i + addr);
359 static void sk_vpd_read(sc)
365 if (sc->sk_vpd_prodname != NULL)
366 free(sc->sk_vpd_prodname, M_DEVBUF);
367 if (sc->sk_vpd_readonly != NULL)
368 free(sc->sk_vpd_readonly, M_DEVBUF);
369 sc->sk_vpd_prodname = NULL;
370 sc->sk_vpd_readonly = NULL;
372 sk_vpd_read_res(sc, &res, pos);
374 if (res.vr_id != VPD_RES_ID) {
375 printf("skc%d: bad VPD resource id: expected %x got %x\n",
376 sc->sk_unit, VPD_RES_ID, res.vr_id);
381 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
382 for (i = 0; i < res.vr_len; i++)
383 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos);
384 sc->sk_vpd_prodname[i] = '\0';
387 sk_vpd_read_res(sc, &res, pos);
389 if (res.vr_id != VPD_RES_READ) {
390 printf("skc%d: bad VPD resource id: expected %x got %x\n",
391 sc->sk_unit, VPD_RES_READ, res.vr_id);
396 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
397 for (i = 0; i < res.vr_len + 1; i++)
398 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos);
403 static int sk_miibus_readreg(dev, phy, reg)
407 struct sk_if_softc *sc_if;
410 sc_if = device_get_softc(dev);
412 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
415 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
416 SK_XM_READ_2(sc_if, XM_PHY_DATA);
417 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
418 for (i = 0; i < SK_TIMEOUT; i++) {
420 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
421 XM_MMUCMD_PHYDATARDY)
425 if (i == SK_TIMEOUT) {
426 printf("sk%d: phy failed to come ready\n",
432 return(SK_XM_READ_2(sc_if, XM_PHY_DATA));
435 static int sk_miibus_writereg(dev, phy, reg, val)
439 struct sk_if_softc *sc_if;
442 sc_if = device_get_softc(dev);
444 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
445 for (i = 0; i < SK_TIMEOUT; i++) {
446 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
450 if (i == SK_TIMEOUT) {
451 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit);
455 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
456 for (i = 0; i < SK_TIMEOUT; i++) {
458 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
463 printf("sk%d: phy write timed out\n", sc_if->sk_unit);
468 static void sk_miibus_statchg(dev)
471 struct sk_if_softc *sc_if;
472 struct mii_data *mii;
474 sc_if = device_get_softc(dev);
475 mii = device_get_softc(sc_if->sk_miibus);
478 * If this is a GMII PHY, manually set the XMAC's
479 * duplex mode accordingly.
481 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
482 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
483 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
485 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
492 #define SK_POLY 0xEDB88320
495 static u_int32_t sk_calchash(addr)
498 u_int32_t idx, bit, data, crc;
500 /* Compute CRC for the address value. */
501 crc = 0xFFFFFFFF; /* initial value */
503 for (idx = 0; idx < 6; idx++) {
504 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
505 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? SK_POLY : 0);
508 return (~crc & ((1 << SK_BITS) - 1));
511 static void sk_setfilt(sc_if, addr, slot)
512 struct sk_if_softc *sc_if;
518 base = XM_RXFILT_ENTRY(slot);
520 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0]));
521 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2]));
522 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4]));
527 static void sk_setmulti(sc_if)
528 struct sk_if_softc *sc_if;
531 u_int32_t hashes[2] = { 0, 0 };
533 struct ifmultiaddr *ifma;
534 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
536 ifp = &sc_if->arpcom.ac_if;
538 /* First, zot all the existing filters. */
539 for (i = 1; i < XM_RXFILT_MAX; i++)
540 sk_setfilt(sc_if, (caddr_t)&dummy, i);
541 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
542 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
544 /* Now program new ones. */
545 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
546 hashes[0] = 0xFFFFFFFF;
547 hashes[1] = 0xFFFFFFFF;
550 /* First find the tail of the list. */
551 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
552 ifma = ifma->ifma_link.le_next) {
553 if (ifma->ifma_link.le_next == NULL)
556 /* Now traverse the list backwards. */
557 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
558 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
559 if (ifma->ifma_addr->sa_family != AF_LINK)
562 * Program the first XM_RXFILT_MAX multicast groups
563 * into the perfect filter. For all others,
564 * use the hash table.
566 if (i < XM_RXFILT_MAX) {
568 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
574 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
576 hashes[0] |= (1 << h);
578 hashes[1] |= (1 << (h - 32));
582 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
583 XM_MODE_RX_USE_PERFECT);
584 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
585 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
590 static int sk_init_rx_ring(sc_if)
591 struct sk_if_softc *sc_if;
593 struct sk_chain_data *cd;
594 struct sk_ring_data *rd;
597 cd = &sc_if->sk_cdata;
598 rd = sc_if->sk_rdata;
600 bzero((char *)rd->sk_rx_ring,
601 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
603 for (i = 0; i < SK_RX_RING_CNT; i++) {
604 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i];
605 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS)
607 if (i == (SK_RX_RING_CNT - 1)) {
608 cd->sk_rx_chain[i].sk_next =
610 rd->sk_rx_ring[i].sk_next =
611 vtophys(&rd->sk_rx_ring[0]);
613 cd->sk_rx_chain[i].sk_next =
614 &cd->sk_rx_chain[i + 1];
615 rd->sk_rx_ring[i].sk_next =
616 vtophys(&rd->sk_rx_ring[i + 1]);
620 sc_if->sk_cdata.sk_rx_prod = 0;
621 sc_if->sk_cdata.sk_rx_cons = 0;
626 static void sk_init_tx_ring(sc_if)
627 struct sk_if_softc *sc_if;
629 struct sk_chain_data *cd;
630 struct sk_ring_data *rd;
633 cd = &sc_if->sk_cdata;
634 rd = sc_if->sk_rdata;
636 bzero((char *)sc_if->sk_rdata->sk_tx_ring,
637 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
639 for (i = 0; i < SK_TX_RING_CNT; i++) {
640 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i];
641 if (i == (SK_TX_RING_CNT - 1)) {
642 cd->sk_tx_chain[i].sk_next =
644 rd->sk_tx_ring[i].sk_next =
645 vtophys(&rd->sk_tx_ring[0]);
647 cd->sk_tx_chain[i].sk_next =
648 &cd->sk_tx_chain[i + 1];
649 rd->sk_tx_ring[i].sk_next =
650 vtophys(&rd->sk_tx_ring[i + 1]);
654 sc_if->sk_cdata.sk_tx_prod = 0;
655 sc_if->sk_cdata.sk_tx_cons = 0;
656 sc_if->sk_cdata.sk_tx_cnt = 0;
661 static int sk_newbuf(sc_if, c, m)
662 struct sk_if_softc *sc_if;
666 struct mbuf *m_new = NULL;
667 struct sk_rx_desc *r;
672 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
676 /* Allocate the jumbo buffer */
677 buf = sk_jalloc(sc_if);
681 printf("sk%d: jumbo allocation failed "
682 "-- packet dropped!\n", sc_if->sk_unit);
687 /* Attach the buffer to the mbuf */
688 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
689 m_new->m_flags |= M_EXT;
690 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
691 m_new->m_len = SK_MCLBYTES;
692 m_new->m_ext.ext_free = sk_jfree;
693 m_new->m_ext.ext_ref = sk_jref;
696 * We're re-using a previously allocated mbuf;
697 * be sure to re-init pointers and lengths to
701 m_new->m_len = m_new->m_pkthdr.len = SK_MCLBYTES;
702 m_new->m_data = m_new->m_ext.ext_buf;
706 * Adjust alignment so packet payload begins on a
707 * longword boundary. Mandatory for Alpha, useful on
710 m_adj(m_new, ETHER_ALIGN);
714 r->sk_data_lo = vtophys(mtod(m_new, caddr_t));
715 r->sk_ctl = m_new->m_len | SK_RXSTAT;
721 * Allocate jumbo buffer storage. The SysKonnect adapters support
722 * "jumbograms" (9K frames), although SysKonnect doesn't currently
723 * use them in their drivers. In order for us to use them, we need
724 * large 9K receive buffers, however standard mbuf clusters are only
725 * 2048 bytes in size. Consequently, we need to allocate and manage
726 * our own jumbo buffer pool. Fortunately, this does not require an
727 * excessive amount of additional code.
729 static int sk_alloc_jumbo_mem(sc_if)
730 struct sk_if_softc *sc_if;
734 struct sk_jpool_entry *entry;
736 /* Grab a big chunk o' storage. */
737 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF,
738 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
740 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) {
741 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit);
745 SLIST_INIT(&sc_if->sk_jfree_listhead);
746 SLIST_INIT(&sc_if->sk_jinuse_listhead);
749 * Now divide it up into 9K pieces and save the addresses
750 * in an array. Note that we play an evil trick here by using
751 * the first few bytes in the buffer to hold the the address
752 * of the softc structure for this interface. This is because
753 * sk_jfree() needs it, but it is called by the mbuf management
754 * code which will not pass it to us explicitly.
756 ptr = sc_if->sk_cdata.sk_jumbo_buf;
757 for (i = 0; i < SK_JSLOTS; i++) {
759 aptr = (u_int64_t **)ptr;
760 aptr[0] = (u_int64_t *)sc_if;
761 ptr += sizeof(u_int64_t);
762 sc_if->sk_cdata.sk_jslots[i].sk_buf = ptr;
763 sc_if->sk_cdata.sk_jslots[i].sk_inuse = 0;
765 entry = malloc(sizeof(struct sk_jpool_entry),
768 free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF);
769 sc_if->sk_cdata.sk_jumbo_buf = NULL;
770 printf("sk%d: no memory for jumbo "
771 "buffer queue!\n", sc_if->sk_unit);
775 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
776 entry, jpool_entries);
783 * Allocate a jumbo buffer.
785 static void *sk_jalloc(sc_if)
786 struct sk_if_softc *sc_if;
788 struct sk_jpool_entry *entry;
790 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead);
794 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit);
799 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries);
800 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries);
801 sc_if->sk_cdata.sk_jslots[entry->slot].sk_inuse = 1;
802 return(sc_if->sk_cdata.sk_jslots[entry->slot].sk_buf);
806 * Adjust usage count on a jumbo buffer. In general this doesn't
807 * get used much because our jumbo buffers don't get passed around
808 * a lot, but it's implemented for correctness.
810 static void sk_jref(buf, size)
814 struct sk_if_softc *sc_if;
818 /* Extract the softc struct pointer. */
819 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
820 sc_if = (struct sk_if_softc *)(aptr[0]);
823 panic("sk_jref: can't find softc pointer!");
825 if (size != SK_MCLBYTES)
826 panic("sk_jref: adjusting refcount of buf of wrong size!");
828 /* calculate the slot this buffer belongs to */
830 i = ((vm_offset_t)aptr
831 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN;
833 if ((i < 0) || (i >= SK_JSLOTS))
834 panic("sk_jref: asked to reference buffer "
835 "that we don't manage!");
836 else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0)
837 panic("sk_jref: buffer already free!");
839 sc_if->sk_cdata.sk_jslots[i].sk_inuse++;
845 * Release a jumbo buffer.
847 static void sk_jfree(buf, size)
851 struct sk_if_softc *sc_if;
854 struct sk_jpool_entry *entry;
856 /* Extract the softc struct pointer. */
857 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
858 sc_if = (struct sk_if_softc *)(aptr[0]);
861 panic("sk_jfree: can't find softc pointer!");
863 if (size != SK_MCLBYTES)
864 panic("sk_jfree: freeing buffer of wrong size!");
866 /* calculate the slot this buffer belongs to */
868 i = ((vm_offset_t)aptr
869 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN;
871 if ((i < 0) || (i >= SK_JSLOTS))
872 panic("sk_jfree: asked to free buffer that we don't manage!");
873 else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0)
874 panic("sk_jfree: buffer already free!");
876 sc_if->sk_cdata.sk_jslots[i].sk_inuse--;
877 if(sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) {
878 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead);
880 panic("sk_jfree: buffer not in use!");
882 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead,
884 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
885 entry, jpool_entries);
895 static int sk_ifmedia_upd(ifp)
898 struct sk_if_softc *sc_if;
899 struct mii_data *mii;
901 sc_if = ifp->if_softc;
902 mii = device_get_softc(sc_if->sk_miibus);
910 * Report current media status.
912 static void sk_ifmedia_sts(ifp, ifmr)
914 struct ifmediareq *ifmr;
916 struct sk_if_softc *sc_if;
917 struct mii_data *mii;
919 sc_if = ifp->if_softc;
920 mii = device_get_softc(sc_if->sk_miibus);
923 ifmr->ifm_active = mii->mii_media_active;
924 ifmr->ifm_status = mii->mii_media_status;
929 static int sk_ioctl(ifp, command, data)
934 struct sk_if_softc *sc_if = ifp->if_softc;
935 struct ifreq *ifr = (struct ifreq *) data;
937 struct mii_data *mii;
944 error = ether_ioctl(ifp, command, data);
947 if (ifr->ifr_mtu > SK_JUMBO_MTU)
950 ifp->if_mtu = ifr->ifr_mtu;
955 if (ifp->if_flags & IFF_UP) {
956 if (ifp->if_flags & IFF_RUNNING &&
957 ifp->if_flags & IFF_PROMISC &&
958 !(sc_if->sk_if_flags & IFF_PROMISC)) {
959 SK_XM_SETBIT_4(sc_if, XM_MODE,
962 } else if (ifp->if_flags & IFF_RUNNING &&
963 !(ifp->if_flags & IFF_PROMISC) &&
964 sc_if->sk_if_flags & IFF_PROMISC) {
965 SK_XM_CLRBIT_4(sc_if, XM_MODE,
971 if (ifp->if_flags & IFF_RUNNING)
974 sc_if->sk_if_flags = ifp->if_flags;
984 mii = device_get_softc(sc_if->sk_miibus);
985 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
998 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
999 * IDs against our list and return a device name if we find a match.
1001 static int sk_probe(dev)
1008 while(t->sk_name != NULL) {
1009 if ((pci_get_vendor(dev) == t->sk_vid) &&
1010 (pci_get_device(dev) == t->sk_did)) {
1011 device_set_desc(dev, t->sk_name);
1021 * Force the GEnesis into reset, then bring it out of reset.
1023 static void sk_reset(sc)
1024 struct sk_softc *sc;
1026 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_RESET);
1027 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_RESET);
1029 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_UNRESET);
1030 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1032 /* Configure packet arbiter */
1033 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1034 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1035 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1036 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1037 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1039 /* Enable RAM interface */
1040 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1043 * Configure interrupt moderation. The moderation timer
1044 * defers interrupts specified in the interrupt moderation
1045 * timer mask based on the timeout specified in the interrupt
1046 * moderation timer init register. Each bit in the timer
1047 * register represents 18.825ns, so to specify a timeout in
1048 * microseconds, we have to multiply by 54.
1050 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200));
1051 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1052 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1053 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1058 static int sk_probe_xmac(dev)
1062 * Not much to do here. We always know there will be
1063 * at least one XMAC present, and if there are two,
1064 * sk_attach() will create a second device instance
1067 device_set_desc(dev, "XaQti Corp. XMAC II");
1073 * Each XMAC chip is attached as a separate logical IP interface.
1074 * Single port cards will have only one logical interface of course.
1076 static int sk_attach_xmac(dev)
1079 struct sk_softc *sc;
1080 struct sk_if_softc *sc_if;
1087 sc_if = device_get_softc(dev);
1088 sc = device_get_softc(device_get_parent(dev));
1089 port = *(int *)device_get_ivars(dev);
1090 free(device_get_ivars(dev), M_DEVBUF);
1091 device_set_ivars(dev, NULL);
1092 sc_if->sk_dev = dev;
1094 bzero((char *)sc_if, sizeof(struct sk_if_softc));
1096 sc_if->sk_dev = dev;
1097 sc_if->sk_unit = device_get_unit(dev);
1098 sc_if->sk_port = port;
1099 sc_if->sk_softc = sc;
1100 sc->sk_if[port] = sc_if;
1101 if (port == SK_PORT_A)
1102 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1103 if (port == SK_PORT_B)
1104 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1107 * Get station address for this interface. Note that
1108 * dual port cards actually come with three station
1109 * addresses: one for each port, plus an extra. The
1110 * extra one is used by the SysKonnect driver software
1111 * as a 'virtual' station address for when both ports
1112 * are operating in failover mode. Currently we don't
1113 * use this extra address.
1115 for (i = 0; i < ETHER_ADDR_LEN; i++)
1116 sc_if->arpcom.ac_enaddr[i] =
1117 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1119 printf("sk%d: Ethernet address: %6D\n",
1120 sc_if->sk_unit, sc_if->arpcom.ac_enaddr, ":");
1123 * Set up RAM buffer addresses. The NIC will have a certain
1124 * amount of SRAM on it, somewhere between 512K and 2MB. We
1125 * need to divide this up a) between the transmitter and
1126 * receiver and b) between the two XMACs, if this is a
1127 * dual port NIC. Our algotithm is to divide up the memory
1128 * evenly so that everyone gets a fair share.
1130 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1131 u_int32_t chunk, val;
1133 chunk = sc->sk_ramsize / 2;
1134 val = sc->sk_rboff / sizeof(u_int64_t);
1135 sc_if->sk_rx_ramstart = val;
1136 val += (chunk / sizeof(u_int64_t));
1137 sc_if->sk_rx_ramend = val - 1;
1138 sc_if->sk_tx_ramstart = val;
1139 val += (chunk / sizeof(u_int64_t));
1140 sc_if->sk_tx_ramend = val - 1;
1142 u_int32_t chunk, val;
1144 chunk = sc->sk_ramsize / 4;
1145 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1147 sc_if->sk_rx_ramstart = val;
1148 val += (chunk / sizeof(u_int64_t));
1149 sc_if->sk_rx_ramend = val - 1;
1150 sc_if->sk_tx_ramstart = val;
1151 val += (chunk / sizeof(u_int64_t));
1152 sc_if->sk_tx_ramend = val - 1;
1155 /* Read and save PHY type and set PHY address */
1156 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1157 switch(sc_if->sk_phytype) {
1158 case SK_PHYTYPE_XMAC:
1159 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1161 case SK_PHYTYPE_BCOM:
1162 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1165 printf("skc%d: unsupported PHY type: %d\n",
1166 sc->sk_unit, sc_if->sk_phytype);
1170 /* Allocate the descriptor queues. */
1171 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF,
1172 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1174 if (sc_if->sk_rdata == NULL) {
1175 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit);
1176 sc->sk_if[port] = NULL;
1180 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data));
1182 /* Try to allocate memory for jumbo buffers. */
1183 if (sk_alloc_jumbo_mem(sc_if)) {
1184 printf("sk%d: jumbo buffer allocation failed\n",
1186 contigfree(sc_if->sk_rdata,
1187 sizeof(struct sk_ring_data), M_DEVBUF);
1188 sc->sk_if[port] = NULL;
1192 ifp = &sc_if->arpcom.ac_if;
1193 ifp->if_softc = sc_if;
1194 ifp->if_unit = sc_if->sk_unit;
1195 ifp->if_name = "sk";
1196 ifp->if_mtu = ETHERMTU;
1197 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1198 ifp->if_ioctl = sk_ioctl;
1199 ifp->if_output = ether_output;
1200 ifp->if_start = sk_start;
1201 ifp->if_watchdog = sk_watchdog;
1202 ifp->if_init = sk_init;
1203 ifp->if_baudrate = 1000000000;
1204 ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1;
1209 sk_init_xmac(sc_if);
1210 if (mii_phy_probe(dev, &sc_if->sk_miibus,
1211 sk_ifmedia_upd, sk_ifmedia_sts)) {
1212 printf("skc%d: no PHY found!\n", sc_if->sk_unit);
1213 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM,
1215 contigfree(sc_if->sk_rdata,
1216 sizeof(struct sk_ring_data), M_DEVBUF);
1221 * Call MI attach routine.
1223 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1224 callout_handle_init(&sc_if->sk_tick_ch);
1230 * Attach the interface. Allocate softc structures, do ifmedia
1231 * setup and ethernet/BPF attach.
1233 static int sk_attach(dev)
1238 struct sk_softc *sc;
1239 int unit, error = 0, rid, *port;
1243 sc = device_get_softc(dev);
1244 unit = device_get_unit(dev);
1245 bzero(sc, sizeof(struct sk_softc));
1248 * Handle power management nonsense.
1250 command = pci_read_config(dev, SK_PCI_CAPID, 4) & 0x000000FF;
1251 if (command == 0x01) {
1253 command = pci_read_config(dev, SK_PCI_PWRMGMTCTRL, 4);
1254 if (command & SK_PSTATE_MASK) {
1255 u_int32_t iobase, membase, irq;
1257 /* Save important PCI config data. */
1258 iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1259 membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1260 irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1262 /* Reset the power state. */
1263 printf("skc%d: chip is in D%d power mode "
1264 "-- setting to D0\n", unit, command & SK_PSTATE_MASK);
1265 command &= 0xFFFFFFFC;
1266 pci_write_config(dev, SK_PCI_PWRMGMTCTRL, command, 4);
1268 /* Restore PCI config data. */
1269 pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1270 pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1271 pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
1276 * Map control/status registers.
1278 command = pci_read_config(dev, PCIR_COMMAND, 4);
1279 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1280 pci_write_config(dev, PCIR_COMMAND, command, 4);
1281 command = pci_read_config(dev, PCIR_COMMAND, 4);
1283 #ifdef SK_USEIOSPACE
1284 if (!(command & PCIM_CMD_PORTEN)) {
1285 printf("skc%d: failed to enable I/O ports!\n", unit);
1290 if (!(command & PCIM_CMD_MEMEN)) {
1291 printf("skc%d: failed to enable memory mapping!\n", unit);
1298 sc->sk_res = bus_alloc_resource(dev, SK_RES, &rid,
1299 0, ~0, 1, RF_ACTIVE);
1301 if (sc->sk_res == NULL) {
1302 printf("sk%d: couldn't map ports/memory\n", unit);
1307 sc->sk_btag = rman_get_bustag(sc->sk_res);
1308 sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1310 /* Allocate interrupt */
1312 sc->sk_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1313 RF_SHAREABLE | RF_ACTIVE);
1315 if (sc->sk_irq == NULL) {
1316 printf("skc%d: couldn't map interrupt\n", unit);
1317 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1322 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET,
1323 sk_intr, sc, &sc->sk_intrhand);
1326 printf("skc%d: couldn't set up irq\n", unit);
1327 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1328 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1332 /* Reset the adapter. */
1337 /* Read and save vital product data from EEPROM. */
1340 /* Read and save RAM size and RAMbuffer offset */
1341 switch(sk_win_read_1(sc, SK_EPROM0)) {
1342 case SK_RAMSIZE_512K_64:
1343 sc->sk_ramsize = 0x80000;
1344 sc->sk_rboff = SK_RBOFF_0;
1346 case SK_RAMSIZE_1024K_64:
1347 sc->sk_ramsize = 0x100000;
1348 sc->sk_rboff = SK_RBOFF_80000;
1350 case SK_RAMSIZE_1024K_128:
1351 sc->sk_ramsize = 0x100000;
1352 sc->sk_rboff = SK_RBOFF_0;
1354 case SK_RAMSIZE_2048K_128:
1355 sc->sk_ramsize = 0x200000;
1356 sc->sk_rboff = SK_RBOFF_0;
1359 printf("skc%d: unknown ram size: %d\n",
1360 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0));
1361 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1362 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1363 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1369 /* Read and save physical media type */
1370 switch(sk_win_read_1(sc, SK_PMDTYPE)) {
1371 case SK_PMD_1000BASESX:
1372 sc->sk_pmd = IFM_1000_SX;
1374 case SK_PMD_1000BASELX:
1375 sc->sk_pmd = IFM_1000_LX;
1377 case SK_PMD_1000BASECX:
1378 sc->sk_pmd = IFM_1000_CX;
1380 case SK_PMD_1000BASETX:
1381 sc->sk_pmd = IFM_1000_TX;
1384 printf("skc%d: unknown media type: 0x%x\n",
1385 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE));
1386 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1387 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1388 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1393 /* Announce the product name. */
1394 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname);
1395 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1396 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1398 device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1400 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1401 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1402 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1404 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1407 /* Turn on the 'driver is loaded' LED. */
1408 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1410 bus_generic_attach(dev);
1417 static int sk_detach_xmac(dev)
1420 struct sk_softc *sc;
1421 struct sk_if_softc *sc_if;
1427 sc = device_get_softc(device_get_parent(dev));
1428 sc_if = device_get_softc(dev);
1429 ifp = &sc_if->arpcom.ac_if;
1431 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1432 bus_generic_detach(dev);
1433 if (sc_if->sk_miibus != NULL)
1434 device_delete_child(dev, sc_if->sk_miibus);
1435 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF);
1436 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF);
1441 static int sk_detach(dev)
1444 struct sk_softc *sc;
1449 sc = device_get_softc(dev);
1451 bus_generic_detach(dev);
1452 if (sc->sk_devs[SK_PORT_A] != NULL)
1453 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1454 if (sc->sk_devs[SK_PORT_B] != NULL)
1455 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1457 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1458 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1459 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1466 static int sk_encap(sc_if, m_head, txidx)
1467 struct sk_if_softc *sc_if;
1468 struct mbuf *m_head;
1471 struct sk_tx_desc *f = NULL;
1473 u_int32_t frag, cur, cnt = 0;
1476 cur = frag = *txidx;
1479 * Start packing the mbufs in this chain into
1480 * the fragment pointers. Stop when we run out
1481 * of fragments or hit the end of the mbuf chain.
1483 for (m = m_head; m != NULL; m = m->m_next) {
1484 if (m->m_len != 0) {
1485 if ((SK_TX_RING_CNT -
1486 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2)
1488 f = &sc_if->sk_rdata->sk_tx_ring[frag];
1489 f->sk_data_lo = vtophys(mtod(m, vm_offset_t));
1490 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT;
1492 f->sk_ctl |= SK_TXCTL_FIRSTFRAG;
1494 f->sk_ctl |= SK_TXCTL_OWN;
1496 SK_INC(frag, SK_TX_RING_CNT);
1504 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |=
1505 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR;
1506 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
1507 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN;
1508 sc_if->sk_cdata.sk_tx_cnt += cnt;
1515 static void sk_start(ifp)
1518 struct sk_softc *sc;
1519 struct sk_if_softc *sc_if;
1520 struct mbuf *m_head = NULL;
1523 sc_if = ifp->if_softc;
1524 sc = sc_if->sk_softc;
1526 idx = sc_if->sk_cdata.sk_tx_prod;
1528 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
1529 IF_DEQUEUE(&ifp->if_snd, m_head);
1534 * Pack the data into the transmit ring. If we
1535 * don't have room, set the OACTIVE flag and wait
1536 * for the NIC to drain the ring.
1538 if (sk_encap(sc_if, m_head, &idx)) {
1539 IF_PREPEND(&ifp->if_snd, m_head);
1540 ifp->if_flags |= IFF_OACTIVE;
1545 * If there's a BPF listener, bounce a copy of this frame
1549 bpf_mtap(ifp, m_head);
1553 sc_if->sk_cdata.sk_tx_prod = idx;
1554 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1556 /* Set a timeout in case the chip goes out to lunch. */
1563 static void sk_watchdog(ifp)
1566 struct sk_if_softc *sc_if;
1568 sc_if = ifp->if_softc;
1570 printf("sk%d: watchdog timeout\n", sc_if->sk_unit);
1576 static void sk_shutdown(dev)
1579 struct sk_softc *sc;
1581 sc = device_get_softc(dev);
1583 /* Turn off the 'driver is loaded' LED. */
1584 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1587 * Reset the GEnesis controller. Doing this should also
1588 * assert the resets on the attached XMAC(s).
1595 static void sk_rxeof(sc_if)
1596 struct sk_if_softc *sc_if;
1598 struct ether_header *eh;
1601 struct sk_chain *cur_rx;
1606 ifp = &sc_if->arpcom.ac_if;
1607 i = sc_if->sk_cdata.sk_rx_prod;
1608 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1610 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) {
1612 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1613 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat;
1614 m = cur_rx->sk_mbuf;
1615 cur_rx->sk_mbuf = NULL;
1616 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl);
1617 SK_INC(i, SK_RX_RING_CNT);
1619 if (rxstat & XM_RXSTAT_ERRFRAME) {
1621 sk_newbuf(sc_if, cur_rx, m);
1626 * Try to allocate a new jumbo buffer. If that
1627 * fails, copy the packet to mbufs and put the
1628 * jumbo buffer back in the ring so it can be
1629 * re-used. If allocating mbufs fails, then we
1630 * have to drop the packet.
1632 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) {
1634 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1635 total_len + ETHER_ALIGN, 0, ifp, NULL);
1636 sk_newbuf(sc_if, cur_rx, m);
1638 printf("sk%d: no receive buffers "
1639 "available -- packet dropped!\n",
1644 m_adj(m0, ETHER_ALIGN);
1647 m->m_pkthdr.rcvif = ifp;
1648 m->m_pkthdr.len = m->m_len = total_len;
1652 eh = mtod(m, struct ether_header *);
1654 /* Remove header from mbuf and pass it on. */
1655 m_adj(m, sizeof(struct ether_header));
1656 ether_input(ifp, eh, m);
1659 sc_if->sk_cdata.sk_rx_prod = i;
1664 static void sk_txeof(sc_if)
1665 struct sk_if_softc *sc_if;
1667 struct sk_tx_desc *cur_tx = NULL;
1671 ifp = &sc_if->arpcom.ac_if;
1674 * Go through our tx ring and free mbufs for those
1675 * frames that have been sent.
1677 idx = sc_if->sk_cdata.sk_tx_cons;
1678 while(idx != sc_if->sk_cdata.sk_tx_prod) {
1679 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
1680 if (cur_tx->sk_ctl & SK_TXCTL_OWN)
1682 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG)
1684 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
1685 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf);
1686 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL;
1688 sc_if->sk_cdata.sk_tx_cnt--;
1689 SK_INC(idx, SK_TX_RING_CNT);
1693 sc_if->sk_cdata.sk_tx_cons = idx;
1696 ifp->if_flags &= ~IFF_OACTIVE;
1701 static void sk_tick(xsc_if)
1704 struct sk_if_softc *sc_if;
1705 struct mii_data *mii;
1710 ifp = &sc_if->arpcom.ac_if;
1711 mii = device_get_softc(sc_if->sk_miibus);
1713 if (!(ifp->if_flags & IFF_UP))
1716 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
1717 sk_intr_bcom(sc_if);
1722 * According to SysKonnect, the correct way to verify that
1723 * the link has come back up is to poll bit 0 of the GPIO
1724 * register three times. This pin has the signal from the
1725 * link_sync pin connected to it; if we read the same link
1726 * state 3 times in a row, we know the link is up.
1728 for (i = 0; i < 3; i++) {
1729 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
1734 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
1738 /* Turn the GP0 interrupt back on. */
1739 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
1740 SK_XM_READ_2(sc_if, XM_ISR);
1743 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch);
1748 static void sk_intr_bcom(sc_if)
1749 struct sk_if_softc *sc_if;
1751 struct sk_softc *sc;
1752 struct mii_data *mii;
1756 sc = sc_if->sk_softc;
1757 mii = device_get_softc(sc_if->sk_miibus);
1758 ifp = &sc_if->arpcom.ac_if;
1760 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
1763 * Read the PHY interrupt register to make sure
1764 * we clear any pending interrupts.
1766 status = sk_miibus_readreg(sc_if->sk_dev,
1767 SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
1769 if (!(ifp->if_flags & IFF_RUNNING)) {
1770 sk_init_xmac(sc_if);
1774 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
1776 lstat = sk_miibus_readreg(sc_if->sk_dev,
1777 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS);
1779 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
1781 /* Turn off the link LED. */
1782 SK_IF_WRITE_1(sc_if, 0,
1783 SK_LINKLED1_CTL, SK_LINKLED_OFF);
1785 } else if (status & BRGPHY_ISR_LNK_CHG) {
1786 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM,
1787 BRGPHY_MII_IMR, 0xFF00);
1790 /* Turn on the link LED. */
1791 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
1792 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
1793 SK_LINKLED_BLINK_OFF);
1797 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
1801 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
1806 static void sk_intr_xmac(sc_if)
1807 struct sk_if_softc *sc_if;
1809 struct sk_softc *sc;
1811 struct mii_data *mii;
1813 sc = sc_if->sk_softc;
1814 mii = device_get_softc(sc_if->sk_miibus);
1815 status = SK_XM_READ_2(sc_if, XM_ISR);
1818 * Link has gone down. Start MII tick timeout to
1819 * watch for link resync.
1821 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
1822 if (status & XM_ISR_GP0_SET) {
1823 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
1824 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
1827 if (status & XM_ISR_AUTONEG_DONE) {
1828 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
1832 if (status & XM_IMR_TX_UNDERRUN)
1833 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
1835 if (status & XM_IMR_RX_OVERRUN)
1836 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
1838 status = SK_XM_READ_2(sc_if, XM_ISR);
1843 static void sk_intr(xsc)
1846 struct sk_softc *sc = xsc;
1847 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL;
1848 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
1851 sc_if0 = sc->sk_if[SK_PORT_A];
1852 sc_if1 = sc->sk_if[SK_PORT_B];
1855 ifp0 = &sc_if0->arpcom.ac_if;
1857 ifp1 = &sc_if1->arpcom.ac_if;
1860 status = CSR_READ_4(sc, SK_ISSR);
1861 if (!(status & sc->sk_intrmask))
1864 /* Handle receive interrupts first. */
1865 if (status & SK_ISR_RX1_EOF) {
1867 CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
1868 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
1870 if (status & SK_ISR_RX2_EOF) {
1872 CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
1873 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
1876 /* Then transmit interrupts. */
1877 if (status & SK_ISR_TX1_S_EOF) {
1879 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
1880 SK_TXBMU_CLR_IRQ_EOF);
1882 if (status & SK_ISR_TX2_S_EOF) {
1884 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
1885 SK_TXBMU_CLR_IRQ_EOF);
1888 /* Then MAC interrupts. */
1889 if (status & SK_ISR_MAC1 &&
1890 ifp0->if_flags & IFF_RUNNING)
1891 sk_intr_xmac(sc_if0);
1893 if (status & SK_ISR_MAC2 &&
1894 ifp1->if_flags & IFF_RUNNING)
1895 sk_intr_xmac(sc_if1);
1897 if (status & SK_ISR_EXTERNAL_REG) {
1899 sk_intr_bcom(sc_if0);
1901 sk_intr_bcom(sc_if1);
1905 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
1907 if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL)
1909 if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL)
1915 static void sk_init_xmac(sc_if)
1916 struct sk_if_softc *sc_if;
1918 struct sk_softc *sc;
1920 struct sk_bcom_hack bhack[] = {
1921 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
1922 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
1923 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1926 sc = sc_if->sk_softc;
1927 ifp = &sc_if->arpcom.ac_if;
1929 /* Unreset the XMAC. */
1930 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
1933 /* Reset the XMAC's internal state. */
1934 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
1936 /* Save the XMAC II revision */
1937 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
1940 * Perform additional initialization for external PHYs,
1941 * namely for the 1000baseTX cards that use the XMAC's
1944 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
1948 /* Take PHY out of reset. */
1949 val = sk_win_read_4(sc, SK_GPIO);
1950 if (sc_if->sk_port == SK_PORT_A)
1951 val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
1953 val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
1954 sk_win_write_4(sc, SK_GPIO, val);
1956 /* Enable GMII mode on the XMAC. */
1957 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
1959 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM,
1960 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
1962 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM,
1963 BRGPHY_MII_IMR, 0xFFF0);
1966 * Early versions of the BCM5400 apparently have
1967 * a bug that requires them to have their reserved
1968 * registers initialized to some magic values. I don't
1969 * know what the numbers do, I'm just the messenger.
1971 if (sk_miibus_readreg(sc_if->sk_dev,
1972 SK_PHYADDR_BCOM, 0x03) == 0x6041) {
1973 while(bhack[i].reg) {
1974 sk_miibus_writereg(sc_if->sk_dev,
1975 SK_PHYADDR_BCOM, bhack[i].reg,
1982 /* Set station address */
1983 SK_XM_WRITE_2(sc_if, XM_PAR0,
1984 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0]));
1985 SK_XM_WRITE_2(sc_if, XM_PAR1,
1986 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2]));
1987 SK_XM_WRITE_2(sc_if, XM_PAR2,
1988 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4]));
1989 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
1991 if (ifp->if_flags & IFF_PROMISC) {
1992 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
1994 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
1997 if (ifp->if_flags & IFF_BROADCAST) {
1998 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2000 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2003 /* We don't need the FCS appended to the packet. */
2004 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2006 /* We want short frames padded to 60 bytes. */
2007 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2010 * Enable the reception of all error frames. This is is
2011 * a necessary evil due to the design of the XMAC. The
2012 * XMAC's receive FIFO is only 8K in size, however jumbo
2013 * frames can be up to 9000 bytes in length. When bad
2014 * frame filtering is enabled, the XMAC's RX FIFO operates
2015 * in 'store and forward' mode. For this to work, the
2016 * entire frame has to fit into the FIFO, but that means
2017 * that jumbo frames larger than 8192 bytes will be
2018 * truncated. Disabling all bad frame filtering causes
2019 * the RX FIFO to operate in streaming mode, in which
2020 * case the XMAC will start transfering frames out of the
2021 * RX FIFO as soon as the FIFO threshold is reached.
2023 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2024 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2025 XM_MODE_RX_INRANGELEN);
2027 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2028 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2030 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2033 * Bump up the transmit threshold. This helps hold off transmit
2034 * underruns when we're blasting traffic from both ports at once.
2036 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2038 /* Set multicast filter */
2041 /* Clear and enable interrupts */
2042 SK_XM_READ_2(sc_if, XM_ISR);
2043 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2044 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2046 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2048 /* Configure MAC arbiter */
2049 switch(sc_if->sk_xmac_rev) {
2050 case XM_XMAC_REV_B2:
2051 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2052 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2053 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2054 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2055 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2056 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2057 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2058 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2059 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2061 case XM_XMAC_REV_C1:
2062 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2063 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2064 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2065 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2066 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2067 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2068 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2069 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2070 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2075 sk_win_write_2(sc, SK_MACARB_CTL,
2076 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2084 * Note that to properly initialize any part of the GEnesis chip,
2085 * you first have to take it out of reset mode.
2087 static void sk_init(xsc)
2090 struct sk_if_softc *sc_if = xsc;
2091 struct sk_softc *sc;
2093 struct mii_data *mii;
2098 ifp = &sc_if->arpcom.ac_if;
2099 sc = sc_if->sk_softc;
2100 mii = device_get_softc(sc_if->sk_miibus);
2102 /* Cancel pending I/O and free all RX/TX buffers. */
2105 /* Configure LINK_SYNC LED */
2106 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2107 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_ON);
2109 /* Configure RX LED */
2110 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_START);
2112 /* Configure TX LED */
2113 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_START);
2115 /* Configure I2C registers */
2117 /* Configure XMAC(s) */
2118 sk_init_xmac(sc_if);
2121 /* Configure MAC FIFOs */
2122 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2123 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2124 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2126 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2127 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2128 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2130 /* Configure transmit arbiter(s) */
2131 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2132 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
2134 /* Configure RAMbuffers */
2135 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2136 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2137 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2138 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2139 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2140 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2142 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2143 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2144 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2145 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2146 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2147 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2148 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2150 /* Configure BMUs */
2151 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2152 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2153 vtophys(&sc_if->sk_rdata->sk_rx_ring[0]));
2154 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
2156 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2157 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2158 vtophys(&sc_if->sk_rdata->sk_tx_ring[0]));
2159 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
2161 /* Init descriptors */
2162 if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2163 printf("sk%d: initialization failed: no "
2164 "memory for rx buffers\n", sc_if->sk_unit);
2169 sk_init_tx_ring(sc_if);
2171 /* Configure interrupt handling */
2172 CSR_READ_4(sc, SK_ISSR);
2173 if (sc_if->sk_port == SK_PORT_A)
2174 sc->sk_intrmask |= SK_INTRS1;
2176 sc->sk_intrmask |= SK_INTRS2;
2178 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2180 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2183 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2185 /* Enable XMACs TX and RX state machines */
2186 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2187 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2189 ifp->if_flags |= IFF_RUNNING;
2190 ifp->if_flags &= ~IFF_OACTIVE;
2197 static void sk_stop(sc_if)
2198 struct sk_if_softc *sc_if;
2201 struct sk_softc *sc;
2204 sc = sc_if->sk_softc;
2205 ifp = &sc_if->arpcom.ac_if;
2207 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch);
2209 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2212 /* Put PHY back into reset. */
2213 val = sk_win_read_4(sc, SK_GPIO);
2214 if (sc_if->sk_port == SK_PORT_A) {
2215 val |= SK_GPIO_DIR0;
2216 val &= ~SK_GPIO_DAT0;
2218 val |= SK_GPIO_DIR2;
2219 val &= ~SK_GPIO_DAT2;
2221 sk_win_write_4(sc, SK_GPIO, val);
2224 /* Turn off various components of this interface. */
2225 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2226 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2227 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2228 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2229 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2230 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2231 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2232 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2233 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2234 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2235 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2236 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2238 /* Disable interrupts */
2239 if (sc_if->sk_port == SK_PORT_A)
2240 sc->sk_intrmask &= ~SK_INTRS1;
2242 sc->sk_intrmask &= ~SK_INTRS2;
2243 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2245 SK_XM_READ_2(sc_if, XM_ISR);
2246 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2248 /* Free RX and TX mbufs still in the queues. */
2249 for (i = 0; i < SK_RX_RING_CNT; i++) {
2250 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) {
2251 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
2252 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
2256 for (i = 0; i < SK_TX_RING_CNT; i++) {
2257 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) {
2258 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
2259 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
2263 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);