sys/dev/netif/wx/if_wx.c

   1 /* $FreeBSD: src/sys/pci/if_wx.c,v 1.5.2.12 2003/03/05 18:42:34 njl Exp $ */
   2 /* $DragonFly: src/sys/dev/netif/wx/Attic/if_wx.c,v 1.3 2003/08/07 21:17:06 dillon Exp $ */
   3 /*
   4  * Principal Author: Matthew Jacob <mjacob@feral.com>
   5  * Copyright (c) 1999, 2001 by Traakan Software
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice unmodified, this list of conditions, and the following
  13  *    disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * Additional Copyright (c) 2001 by Parag Patel
  31  * under same licence for MII PHY code.
  32  */
  33
  34 /*
  35  * Intel Gigabit Ethernet (82452/82453) Driver.
  36  * Inspired by fxp driver by David Greenman for FreeBSD, and by
  37  * Bill Paul's work in other FreeBSD network drivers.
  38  */
  39
  40 /*
  41  * Many bug fixes gratefully acknowledged from:
  42  *
  43  *      The folks at Sitara Networks
  44  */
  45
  46 /*
  47  * Options
  48  */
  49
  50 /*
  51  * Use only every other 16 byte receive descriptor, leaving the ones
  52  * in between empty. This card is most efficient at reading/writing
  53  * 32 byte cache lines, so avoid all the (not working for early rev
  54  * cards) MWI and/or READ/MODIFY/WRITE cycles updating one descriptor
  55  * would have you do.
  56  *
  57  * This isn't debugged yet.
  58  */
  59 /* #define      PADDED_CELL     1 */
  60
  61 /*
  62  * Since the includes are a mess, they'll all be in if_wxvar.h
  63  */
  64
  65 #include "if_wxvar.h"
  66
  67 #ifdef __alpha__
  68 #undef vtophys
  69 #define vtophys(va)     alpha_XXX_dmamap((vm_offset_t)(va))
  70 #endif /* __alpha__ */
  71
  72 /*
  73  * Function Prototpes, yadda yadda...
  74  */
  75
  76 static int wx_intr(void *);
  77 static void wx_handle_link_intr(wx_softc_t *);
  78 static void wx_check_link(wx_softc_t *);
  79 static void wx_handle_rxint(wx_softc_t *);
  80 static void wx_gc(wx_softc_t *);
  81 static void wx_start(struct ifnet *);
  82 static int wx_ioctl(struct ifnet *, IOCTL_CMD_TYPE, caddr_t);
  83 static int wx_ifmedia_upd(struct ifnet *);
  84 static void wx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  85 static int wx_init(void *);
  86 static void wx_hw_stop(wx_softc_t *);
  87 static void wx_set_addr(wx_softc_t *, int, u_int8_t *);
  88 static int wx_hw_initialize(wx_softc_t *);
  89 static void wx_stop(wx_softc_t *);
  90 static void wx_txwatchdog(struct ifnet *);
  91 static int wx_get_rbuf(wx_softc_t *, rxpkt_t *);
  92 static void wx_rxdma_map(wx_softc_t *, rxpkt_t *, struct mbuf *);
  93
  94 static INLINE void wx_eeprom_raise_clk(wx_softc_t *, u_int32_t);
  95 static INLINE void wx_eeprom_lower_clk(wx_softc_t *, u_int32_t);
  96 static INLINE void wx_eeprom_sobits(wx_softc_t *, u_int16_t, u_int16_t);
  97 static INLINE u_int16_t wx_eeprom_sibits(wx_softc_t *);
  98 static INLINE void wx_eeprom_cleanup(wx_softc_t *);
  99 static INLINE u_int16_t wx_read_eeprom_word(wx_softc_t *, int);
 100 static void wx_read_eeprom(wx_softc_t *, u_int16_t *, int, int);
 101
 102 static int wx_attach_common(wx_softc_t *);
 103 static void wx_watchdog(void *);
 104
 105 static INLINE void wx_mwi_whackon(wx_softc_t *);
 106 static INLINE void wx_mwi_unwhack(wx_softc_t *);
 107 static int wx_dring_setup(wx_softc_t *);
 108 static void wx_dring_teardown(wx_softc_t *);
 109
 110 static int wx_attach_phy(wx_softc_t *);
 111 static int wx_miibus_readreg(void *, int, int);
 112 static int wx_miibus_writereg(void *, int, int, int);
 113 static void wx_miibus_statchg(void *);
 114 static void wx_miibus_mediainit(void *);
 115
 116 static u_int32_t wx_mii_shift_in(wx_softc_t *);
 117 static void wx_mii_shift_out(wx_softc_t *, u_int32_t, u_int32_t);
 118
 119 #define WX_DISABLE_INT(sc)      WRITE_CSR(sc, WXREG_IMCLR, WXDISABLE)
 120 #define WX_ENABLE_INT(sc)       WRITE_CSR(sc, WXREG_IMASK, sc->wx_ienable)
 121
 122 /*
 123  * Until we do a bit more work, we can get no bigger than MCLBYTES
 124  */
 125 #if     0
 126 #define WX_MAXMTU       (WX_MAX_PKT_SIZE_JUMBO - sizeof (struct ether_header))
 127 #else
 128 #define WX_MAXMTU       (MCLBYTES - sizeof (struct ether_header))
 129 #endif
 130
 131 #define DPRINTF(sc, x)  if (sc->wx_debug) printf x
 132 #define IPRINTF(sc, x)  if (sc->wx_verbose) printf x
 133
 134 static const char ldn[] = "%s: link down\n";
 135 static const char lup[] = "%s: link up\n";
 136 static const char sqe[] = "%s: receive sequence error\n";
 137 static const char ane[] = "%s: /C/ ordered sets seen- enabling ANE\n";
 138 static const char inane[] = "%s: no /C/ ordered sets seen- disabling ANE\n";
 139
 140 static int wx_txint_delay = 5000;       /* ~5ms */
 141 TUNABLE_INT("hw.wx.txint_delay", &wx_txint_delay);
 142
 143 SYSCTL_NODE(_hw, OID_AUTO, wx, CTLFLAG_RD, 0, "WX driver parameters");
 144 SYSCTL_INT(_hw_wx, OID_AUTO, txint_delay, CTLFLAG_RW,
 145         &wx_txint_delay, 0, "");
 146 static int wx_dump_stats = -1;
 147 SYSCTL_INT(_hw_wx, OID_AUTO, dump_stats, CTLFLAG_RW,
 148         &wx_dump_stats, 0, "");
 149 static int wx_clr_stats = -1;
 150 SYSCTL_INT(_hw_wx, OID_AUTO, clear_stats, CTLFLAG_RW,
 151         &wx_clr_stats, 0, "");
 152
 153
 154 /*
 155  * Program multicast addresses.
 156  *
 157  * This function must be called at splimp, but it may sleep.
 158  */
 159 static int
 160 wx_mc_setup(wx_softc_t *sc)
 161 {
 162         struct ifnet *ifp = &sc->wx_if;
 163         struct ifmultiaddr *ifma;
 164
 165         /*
 166          * XXX: drain TX queue
 167          */
 168         if (sc->tactive) {
 169                 return (EBUSY);
 170         }
 171
 172         wx_stop(sc);
 173
 174         if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) {
 175                 sc->all_mcasts = 1;
 176                 return (wx_init(sc));
 177         }
 178
 179         sc->wx_nmca = 0;
 180         for (ifma = ifp->if_multiaddrs.lh_first, sc->wx_nmca = 0;
 181             ifma != NULL; ifma = ifma->ifma_link.le_next) {
 182
 183                 if (ifma->ifma_addr->sa_family != AF_LINK) {
 184                         continue;
 185                 }
 186                 if (sc->wx_nmca >= WX_RAL_TAB_SIZE-1) {
 187                         sc->wx_nmca = 0;
 188                         sc->all_mcasts = 1;
 189                         break;
 190                 }
 191                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 192                     (void *) &sc->wx_mcaddr[sc->wx_nmca++][0], 6);
 193         }
 194         return (wx_init(sc));
 195 }
 196
 197 /*
 198  * Return identification string if this is device is ours.
 199  */
 200 static int
 201 wx_probe(device_t dev)
 202 {
 203         if (pci_get_vendor(dev) != WX_VENDOR_INTEL) {
 204                 return (ENXIO);
 205         }
 206         switch (pci_get_device(dev)) {
 207         case WX_PRODUCT_82452:
 208                 device_set_desc(dev, "Intel PRO/1000 Gigabit (WISEMAN)");
 209                 break;
 210         case WX_PRODUCT_LIVENGOOD:
 211                 device_set_desc(dev, "Intel PRO/1000 (LIVENGOOD)");
 212                 break;
 213         case WX_PRODUCT_82452_SC:
 214                 device_set_desc(dev, "Intel PRO/1000 F Gigabit Ethernet");
 215                 break;
 216         case WX_PRODUCT_82543:
 217                 device_set_desc(dev, "Intel PRO/1000 T Gigabit Ethernet");
 218                 break;
 219         default:
 220                 return (ENXIO);
 221         }
 222         return (0);
 223 }
 224
 225 static int
 226 wx_attach(device_t dev)
 227 {
 228         int error = 0;
 229         wx_softc_t *sc = device_get_softc(dev);
 230         struct ifnet *ifp;
 231         u_int32_t val;
 232         int rid;
 233
 234         bzero(sc, sizeof (wx_softc_t));
 235
 236         callout_handle_init(&sc->w.sch);
 237         sc->w.dev = dev;
 238
 239         if (bootverbose)
 240                 sc->wx_verbose = 1;
 241
 242         if (getenv_int ("wx_debug", &rid)) {
 243                 if (rid & (1 << device_get_unit(dev))) {
 244                         sc->wx_debug = 1;
 245                 }
 246         }
 247
 248         if (getenv_int("wx_no_ilos", &rid)) {
 249                 if (rid & (1 << device_get_unit(dev))) {
 250                         sc->wx_no_ilos = 1;
 251                 }
 252         }
 253
 254         if (getenv_int("wx_ilos", &rid)) {
 255                 if (rid & (1 << device_get_unit(dev))) {
 256                         sc->wx_ilos = 1;
 257                 }
 258         }
 259
 260         if (getenv_int("wx_no_flow", &rid)) {
 261                 if (rid & (1 << device_get_unit(dev))) {
 262                         sc->wx_no_flow = 1;
 263                 }
 264         }
 265
 266 #ifdef  SMPNG
 267         mtx_init(&sc->wx_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
 268 #endif
 269         WX_LOCK(sc);
 270         /*
 271          * get revision && id...
 272          */
 273         sc->wx_idnrev = (pci_get_device(dev) << 16) | (pci_get_revid(dev));
 274
 275         /*
 276          * Enable bus mastering, make sure that the cache line size is right.
 277          */
 278         pci_enable_busmaster(dev);
 279         pci_enable_io(dev, SYS_RES_MEMORY);
 280         val = pci_read_config(dev, PCIR_COMMAND, 4);
 281         if ((val & PCIM_CMD_MEMEN) == 0) {
 282                 device_printf(dev, "failed to enable memory mapping\n");
 283                 error = ENXIO;
 284                 goto out;
 285         }
 286
 287         /*
 288          * Let the BIOS do it's job- but check for sanity.
 289          */
 290         val = pci_read_config(dev, PCIR_CACHELNSZ, 1);
 291         if (val < 4 || val > 32) {
 292                 pci_write_config(dev, PCIR_CACHELNSZ, 8, 1);
 293         }
 294
 295         /*
 296          * Map control/status registers.
 297          */
 298         rid = WX_MMBA;
 299         sc->w.mem = bus_alloc_resource(dev, SYS_RES_MEMORY,
 300             &rid, 0, ~0, 1, RF_ACTIVE);
 301         if (!sc->w.mem) {
 302                 device_printf(dev, "could not map memory\n");
 303                 error = ENXIO;
 304                 goto out;
 305         }
 306         sc->w.st = rman_get_bustag(sc->w.mem);
 307         sc->w.sh = rman_get_bushandle(sc->w.mem);
 308
 309         rid = 0;
 310         sc->w.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
 311             &rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
 312         if (sc->w.irq == NULL) {
 313                 device_printf(dev, "could not map interrupt\n");
 314                 error = ENXIO;
 315                 goto out;
 316         }
 317         error = bus_setup_intr(dev, sc->w.irq, INTR_TYPE_NET,
 318             (void (*)(void *))wx_intr, sc, &sc->w.ih);
 319         if (error) {
 320                 device_printf(dev, "could not setup irq\n");
 321                 goto out;
 322         }
 323         (void) snprintf(sc->wx_name, sizeof (sc->wx_name) - 1, "wx%d",
 324             device_get_unit(dev));
 325         if (wx_attach_common(sc)) {
 326                 bus_teardown_intr(dev, sc->w.irq, sc->w.ih);
 327                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->w.irq);
 328                 bus_release_resource(dev, SYS_RES_MEMORY, WX_MMBA, sc->w.mem);
 329                 error = ENXIO;
 330                 goto out;
 331         }
 332         device_printf(dev, "Ethernet address %02x:%02x:%02x:%02x:%02x:%02x\n",
 333             sc->w.arpcom.ac_enaddr[0], sc->w.arpcom.ac_enaddr[1],
 334             sc->w.arpcom.ac_enaddr[2], sc->w.arpcom.ac_enaddr[3],
 335             sc->w.arpcom.ac_enaddr[4], sc->w.arpcom.ac_enaddr[5]);
 336
 337         ifp = &sc->w.arpcom.ac_if;
 338         ifp->if_unit = device_get_unit(dev);
 339         ifp->if_name = "wx";
 340         ifp->if_mtu = ETHERMTU; /* we always start at ETHERMTU size */
 341         ifp->if_output = ether_output;
 342         ifp->if_baudrate = 1000000000;
 343         ifp->if_init = (void (*)(void *))wx_init;
 344         ifp->if_softc = sc;
 345         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 346         ifp->if_ioctl = wx_ioctl;
 347         ifp->if_start = wx_start;
 348         ifp->if_watchdog = wx_txwatchdog;
 349         ifp->if_snd.ifq_maxlen = WX_MAX_TDESC - 1;
 350         ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
 351 out:
 352         WX_UNLOCK(sc);
 353         return (error);
 354 }
 355
 356 static int
 357 wx_attach_phy(wx_softc_t *sc)
 358 {
 359         if (mii_phy_probe(sc->w.dev, &sc->w.miibus, wx_ifmedia_upd,
 360             wx_ifmedia_sts)) {
 361                 printf("%s: no PHY probed!\n", sc->wx_name);
 362                 return (-1);
 363         }
 364         sc->wx_mii = 1;
 365         return 0;
 366 }
 367
 368 static int
 369 wx_detach(device_t dev)
 370 {
 371         wx_softc_t *sc = device_get_softc(dev);
 372
 373         WX_LOCK(sc);
 374         wx_stop(sc);
 375
 376         ether_ifdetach(&sc->w.arpcom.ac_if, ETHER_BPF_SUPPORTED);
 377         if (sc->w.miibus) {
 378                 bus_generic_detach(dev);
 379                 device_delete_child(dev, sc->w.miibus);
 380         } else {
 381                 ifmedia_removeall(&sc->wx_media);
 382         }
 383         bus_teardown_intr(dev, sc->w.irq, sc->w.ih);
 384         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->w.irq);
 385         bus_release_resource(dev, SYS_RES_MEMORY, WX_MMBA, sc->w.mem);
 386
 387         wx_dring_teardown(sc);
 388         if (sc->rbase) {
 389                 WXFREE(sc->rbase);
 390                 sc->rbase = NULL;
 391         }
 392         if (sc->tbase) {
 393                 WXFREE(sc->tbase);
 394                 sc->tbase = NULL;
 395         }
 396         WX_UNLOCK(sc);
 397 #ifdef  SMPNG
 398         mtx_destroy(&sc->wx_mtx);
 399 #endif
 400         return (0);
 401 }
 402
 403 static int
 404 wx_shutdown(device_t dev)
 405 {
 406         wx_hw_stop((wx_softc_t *) device_get_softc(dev));
 407         return (0);
 408 }
 409
 410 static INLINE void
 411 wx_mwi_whackon(wx_softc_t *sc)
 412 {
 413         sc->wx_cmdw = pci_read_config(sc->w.dev, PCIR_COMMAND, 2);
 414         pci_write_config(sc->w.dev, PCIR_COMMAND, sc->wx_cmdw & ~MWI, 2);
 415 }
 416
 417 static INLINE void
 418 wx_mwi_unwhack(wx_softc_t *sc)
 419 {
 420         if (sc->wx_cmdw & MWI) {
 421                 pci_write_config(sc->w.dev, PCIR_COMMAND, sc->wx_cmdw, 2);
 422         }
 423 }
 424
 425 static int
 426 wx_dring_setup(wx_softc_t *sc)
 427 {
 428         size_t len;
 429
 430         len = sizeof (wxrd_t) * WX_MAX_RDESC;
 431         sc->rdescriptors = (wxrd_t *)
 432             contigmalloc(len, M_DEVBUF, M_NOWAIT, 0, ~0, 4096, 0);
 433         if (sc->rdescriptors == NULL) {
 434                 printf("%s: could not allocate rcv descriptors\n", sc->wx_name);
 435                 return (-1);
 436         }
 437         if (((intptr_t)sc->rdescriptors) & 0xfff) {
 438                 contigfree(sc->rdescriptors, len, M_DEVBUF);
 439                 sc->rdescriptors = NULL;
 440                 printf("%s: rcv descriptors not 4KB aligned\n", sc->wx_name);
 441                 return (-1);
 442         }
 443         bzero(sc->rdescriptors, len);
 444
 445         len = sizeof (wxtd_t) * WX_MAX_TDESC;
 446         sc->tdescriptors = (wxtd_t *)
 447             contigmalloc(len, M_DEVBUF, M_NOWAIT, 0, ~0, 4096, 0);
 448         if (sc->tdescriptors == NULL) {
 449                 contigfree(sc->rdescriptors,
 450                     sizeof (wxrd_t) * WX_MAX_RDESC, M_DEVBUF);
 451                 sc->rdescriptors = NULL;
 452                 printf("%s: could not allocate xmt descriptors\n", sc->wx_name);
 453                 return (-1);
 454         }
 455         if (((intptr_t)sc->tdescriptors) & 0xfff) {
 456                 contigfree(sc->rdescriptors,
 457                     sizeof (wxrd_t) * WX_MAX_RDESC, M_DEVBUF);
 458                 contigfree(sc->tdescriptors, len, M_DEVBUF);
 459                 sc->rdescriptors = NULL;
 460                 sc->tdescriptors = NULL;
 461                 printf("%s: xmt descriptors not 4KB aligned\n", sc->wx_name);
 462                 return (-1);
 463         }
 464         bzero(sc->tdescriptors, len);
 465         return (0);
 466 }
 467
 468 static void
 469 wx_dring_teardown(wx_softc_t *sc)
 470 {
 471         if (sc->rdescriptors) {
 472                 contigfree(sc->rdescriptors,
 473                     sizeof (wxrd_t) * WX_MAX_RDESC, M_DEVBUF);
 474                 sc->rdescriptors = NULL;
 475         }
 476         if (sc->tdescriptors) {
 477                 contigfree(sc->tdescriptors,
 478                     sizeof (wxtd_t) * WX_MAX_TDESC, M_DEVBUF);
 479                 sc->tdescriptors = NULL;
 480         }
 481 }
 482
 483 static device_method_t wx_methods[] = {
 484         /* Device interface */
 485         DEVMETHOD(device_probe,         wx_probe),
 486         DEVMETHOD(device_attach,        wx_attach),
 487         DEVMETHOD(device_detach,        wx_detach),
 488         DEVMETHOD(device_shutdown,      wx_shutdown),
 489
 490         /* bus interface */
 491         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 492         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 493
 494         /* MII interface */
 495         DEVMETHOD(miibus_readreg,       wx_miibus_readreg),
 496         DEVMETHOD(miibus_writereg,      wx_miibus_writereg),
 497         DEVMETHOD(miibus_statchg,       wx_miibus_statchg),
 498         DEVMETHOD(miibus_mediainit,     wx_miibus_mediainit),
 499
 500         { 0, 0 }
 501 };
 502
 503 static driver_t wx_driver = {
 504         "wx", wx_methods, sizeof(wx_softc_t),
 505 };
 506 static devclass_t wx_devclass;
 507 DRIVER_MODULE(if_wx, pci, wx_driver, wx_devclass, 0, 0);
 508 DRIVER_MODULE(miibus, wx, miibus_driver, miibus_devclass, 0, 0);
 509
 510 /*
 511  * Do generic parts of attach. Our registers have been mapped
 512  * and our interrupt registered.
 513  */
 514 static int
 515 wx_attach_common(wx_softc_t *sc)
 516 {
 517         size_t len;
 518         u_int32_t tmp;
 519         int ll = 0;
 520
 521         /*
 522          * First, check for revision support.
 523          */
 524         if (sc->wx_idnrev < WX_WISEMAN_2_0) {
 525                 printf("%s: cannot support ID 0x%x, revision %d chips\n",
 526                     sc->wx_name, sc->wx_idnrev >> 16, sc->wx_idnrev & 0xffff);
 527                 return (ENXIO);
 528         }
 529
 530         /*
 531          * Second, reset the chip.
 532          */
 533         wx_hw_stop(sc);
 534
 535         /*
 536          * Third, validate our EEPROM.
 537          */
 538
 539         /* TBD */
 540
 541         /*
 542          * Fourth, read eeprom for our MAC address and other things.
 543          */
 544         wx_read_eeprom(sc, (u_int16_t *)sc->wx_enaddr, WX_EEPROM_MAC_OFF, 3);
 545
 546         /*
 547          * Fifth, establish some adapter parameters.
 548          */
 549         sc->wx_dcr = 0;
 550
 551         if (IS_LIVENGOOD_CU(sc)) {
 552
 553                 /* settings to talk to PHY */
 554                 sc->wx_dcr |= WXDCR_FRCSPD | WXDCR_FRCDPX | WXDCR_SLU;
 555                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
 556
 557                 /*
 558                  * Raise the PHY's reset line to make it operational.
 559                  */
 560                 tmp = READ_CSR(sc, WXREG_EXCT);
 561                 tmp |= WXPHY_RESET_DIR4;
 562                 WRITE_CSR(sc, WXREG_EXCT, tmp);
 563                 DELAY(20*1000);
 564
 565                 tmp = READ_CSR(sc, WXREG_EXCT);
 566                 tmp &= ~WXPHY_RESET4;
 567                 WRITE_CSR(sc, WXREG_EXCT, tmp);
 568                 DELAY(20*1000);
 569
 570                 tmp = READ_CSR(sc, WXREG_EXCT);
 571                 tmp |= WXPHY_RESET4;
 572                 WRITE_CSR(sc, WXREG_EXCT, tmp);
 573                 DELAY(20*1000);
 574
 575                 if (wx_attach_phy(sc)) {
 576                         goto fail;
 577                 }
 578         } else {
 579                 ifmedia_init(&sc->wx_media, IFM_IMASK,
 580                     wx_ifmedia_upd, wx_ifmedia_sts);
 581
 582                 ifmedia_add(&sc->wx_media, IFM_ETHER|IFM_1000_SX, 0, NULL);
 583                 ifmedia_add(&sc->wx_media,
 584                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
 585                 ifmedia_set(&sc->wx_media, IFM_ETHER|IFM_1000_SX|IFM_FDX);
 586
 587                 sc->wx_media.ifm_media = sc->wx_media.ifm_cur->ifm_media;
 588         }
 589
 590         /*
 591          * Sixth, establish a default device control register word.
 592          */
 593         ll += 1;
 594         if (sc->wx_cfg1 & WX_EEPROM_CTLR1_FD)
 595                 sc->wx_dcr |= WXDCR_FD;
 596         if (sc->wx_cfg1 & WX_EEPROM_CTLR1_ILOS)
 597                 sc->wx_dcr |= WXDCR_ILOS;
 598
 599         tmp = (sc->wx_cfg1 >> WX_EEPROM_CTLR1_SWDPIO_SHIFT) & WXDCR_SWDPIO_MASK;
 600         sc->wx_dcr |= (tmp << WXDCR_SWDPIO_SHIFT);
 601
 602         if (sc->wx_no_ilos)
 603                 sc->wx_dcr &= ~WXDCR_ILOS;
 604         if (sc->wx_ilos)
 605                 sc->wx_dcr |= WXDCR_ILOS;
 606         if (sc->wx_no_flow == 0)
 607                 sc->wx_dcr |= WXDCR_RFCE | WXDCR_TFCE;
 608
 609         /*
 610          * Seventh, allocate various sw structures...
 611          */
 612         len = sizeof (rxpkt_t) * WX_MAX_RDESC;
 613         sc->rbase = (rxpkt_t *) WXMALLOC(len);
 614         if (sc->rbase == NULL) {
 615                 goto fail;
 616         }
 617         bzero(sc->rbase, len);
 618         ll += 1;
 619
 620         len = sizeof (txpkt_t) * WX_MAX_TDESC;
 621         sc->tbase = (txpkt_t *) WXMALLOC(len);
 622         if (sc->tbase == NULL) {
 623                 goto fail;
 624         }
 625         bzero(sc->tbase, len);
 626         ll += 1;
 627
 628         /*
 629          * Eighth, allocate and dma map (platform dependent) descriptor rings.
 630          * They have to be aligned on a 4KB boundary.
 631          */
 632         if (wx_dring_setup(sc) == 0) {
 633                 return (0);
 634         }
 635
 636 fail:
 637         printf("%s: failed to do common attach (%d)\n", sc->wx_name, ll);
 638         wx_dring_teardown(sc);
 639         if (sc->rbase) {
 640                 WXFREE(sc->rbase);
 641                 sc->rbase = NULL;
 642         }
 643         if (sc->tbase) {
 644                 WXFREE(sc->tbase);
 645                 sc->tbase = NULL;
 646         }
 647         return (ENOMEM);
 648 }
 649
 650 /*
 651  * EEPROM functions.
 652  */
 653
 654 static INLINE void
 655 wx_eeprom_raise_clk(wx_softc_t *sc, u_int32_t regval)
 656 {
 657         WRITE_CSR(sc, WXREG_EECDR, regval | WXEECD_SK);
 658         DELAY(50);
 659 }
 660
 661 static INLINE void
 662 wx_eeprom_lower_clk(wx_softc_t *sc, u_int32_t regval)
 663 {
 664         WRITE_CSR(sc, WXREG_EECDR, regval & ~WXEECD_SK);
 665         DELAY(50);
 666 }
 667
 668 static INLINE void
 669 wx_eeprom_sobits(wx_softc_t *sc, u_int16_t data, u_int16_t count)
 670 {
 671         u_int32_t regval, mask;
 672
 673         mask = 1 << (count - 1);
 674         regval = READ_CSR(sc, WXREG_EECDR) & ~(WXEECD_DI|WXEECD_DO);
 675
 676         do {
 677                 if (data & mask)
 678                         regval |= WXEECD_DI;
 679                 else
 680                         regval &= ~WXEECD_DI;
 681                 WRITE_CSR(sc, WXREG_EECDR, regval); DELAY(50);
 682                 wx_eeprom_raise_clk(sc, regval);
 683                 wx_eeprom_lower_clk(sc, regval);
 684                 mask >>= 1;
 685         } while (mask != 0);
 686         WRITE_CSR(sc, WXREG_EECDR, regval & ~WXEECD_DI);
 687 }
 688
 689 static INLINE u_int16_t
 690 wx_eeprom_sibits(wx_softc_t *sc)
 691 {
 692         unsigned int regval, i;
 693         u_int16_t data;
 694
 695         data = 0;
 696         regval = READ_CSR(sc, WXREG_EECDR) & ~(WXEECD_DI|WXEECD_DO);
 697         for (i = 0; i != 16; i++) {
 698                 data <<= 1;
 699                 wx_eeprom_raise_clk(sc, regval);
 700                 regval = READ_CSR(sc, WXREG_EECDR) & ~WXEECD_DI;
 701                 if (regval & WXEECD_DO) {
 702                         data |= 1;
 703                 }
 704                 wx_eeprom_lower_clk(sc, regval);
 705         }
 706         return (data);
 707 }
 708
 709 static INLINE void
 710 wx_eeprom_cleanup(wx_softc_t *sc)
 711 {
 712         u_int32_t regval;
 713         regval = READ_CSR(sc, WXREG_EECDR) & ~(WXEECD_DI|WXEECD_CS);
 714         WRITE_CSR(sc, WXREG_EECDR, regval); DELAY(50);
 715         wx_eeprom_raise_clk(sc, regval);
 716         wx_eeprom_lower_clk(sc, regval);
 717 }
 718
 719 static u_int16_t INLINE
 720 wx_read_eeprom_word(wx_softc_t *sc, int offset)
 721 {
 722         u_int16_t       data;
 723         WRITE_CSR(sc, WXREG_EECDR, WXEECD_CS);
 724         wx_eeprom_sobits(sc, EEPROM_READ_OPCODE, 3);
 725         wx_eeprom_sobits(sc, offset, 6);
 726         data = wx_eeprom_sibits(sc);
 727         wx_eeprom_cleanup(sc);
 728         return (data);
 729 }
 730
 731 static void
 732 wx_read_eeprom(wx_softc_t *sc, u_int16_t *data, int offset, int words)
 733 {
 734         int i;
 735         for (i = 0; i < words; i++) {
 736                 *data++ = wx_read_eeprom_word(sc, offset++);
 737         }
 738         sc->wx_cfg1 = wx_read_eeprom_word(sc, WX_EEPROM_CTLR1_OFF);
 739 }
 740
 741 /*
 742  * Start packet transmission on the interface.
 743  */
 744
 745 static void
 746 wx_start(struct ifnet *ifp)
 747 {
 748         wx_softc_t *sc = SOFTC_IFP(ifp);
 749         u_int16_t widx = WX_MAX_TDESC, cidx, nactv;
 750
 751         WX_LOCK(sc);
 752         DPRINTF(sc, ("%s: wx_start\n", sc->wx_name));
 753         nactv = sc->tactive;
 754         while (nactv < WX_MAX_TDESC - 1) {
 755                 int ndesc, plen;
 756                 int gctried = 0;
 757                 struct mbuf *m, *mb_head;
 758
 759                 IF_DEQUEUE(&ifp->if_snd, mb_head);
 760                 if (mb_head == NULL) {
 761                         break;
 762                 }
 763                 sc->wx_xmitwanted++;
 764
 765                 /*
 766                  * If we have a packet less than ethermin, pad it out.
 767                  */
 768                 if (mb_head->m_pkthdr.len < WX_MIN_RPKT_SIZE) {
 769                         if (mb_head->m_next == NULL) {
 770                                 mb_head->m_len = WX_MIN_RPKT_SIZE;
 771                         } else {
 772                                 MGETHDR(m, M_DONTWAIT, MT_DATA);
 773                                 if (m == NULL) {
 774                                         m_freem(mb_head);
 775                                         break;
 776                                 }
 777                                 m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
 778                                     mtod(m, caddr_t));
 779                                 m->m_pkthdr.len = m->m_len = WX_MIN_RPKT_SIZE;
 780                                 bzero(mtod(m, char *) + mb_head->m_pkthdr.len,
 781                                      WX_MIN_RPKT_SIZE - mb_head->m_pkthdr.len);
 782                                 sc->wx_xmitpullup++;
 783                                 m_freem(mb_head);
 784                                 mb_head = m;
 785                         }
 786                 }
 787         again:
 788                 cidx = sc->tnxtfree;
 789                 nactv = sc->tactive;
 790
 791
 792                 /*
 793                  * Go through each of the mbufs in the chain and initialize
 794                  * the transmit buffer descriptors with the physical address
 795                  * and size of that mbuf. If we have a length less than our
 796                  * minimum transmit size, we bail (to do a pullup). If we run
 797                  * out of descriptors, we also bail and try and do a pullup.
 798                  */
 799                 for (plen = ndesc = 0, m = mb_head; m != NULL; m = m->m_next) {
 800                         vm_offset_t vptr;
 801                         wxtd_t *td;
 802
 803                         /*
 804                          * If this mbuf has no data, skip it.
 805                          */
 806                         if (m->m_len == 0) {
 807                                 continue;
 808                         }
 809
 810                         /*
 811                          * This appears to be a bogus check the PRO1000T.
 812                          * I think they meant that the minimum packet size
 813                          * is in fact WX_MIN_XPKT_SIZE (all data loaded)
 814                          */
 815 #if     0
 816                         /*
 817                          * If this mbuf is too small for the chip's minimum,
 818                          * break out to cluster it.
 819                          */
 820                         if (m->m_len < WX_MIN_XPKT_SIZE) {
 821                                 sc->wx_xmitrunt++;
 822                                 break;
 823                         }
 824 #endif
 825
 826                         /*
 827                          * Do we have a descriptor available for this mbuf?
 828                          */
 829                         if (++nactv == WX_MAX_TDESC) {
 830                                 if (gctried++ == 0) {
 831                                         sc->wx_xmitgc++;
 832                                         wx_gc(sc);
 833                                         goto again;
 834                                 }
 835                                 break;
 836                         }
 837                         sc->tbase[cidx].dptr = m;
 838                         td = &sc->tdescriptors[cidx];
 839                         td->length = m->m_len;
 840                         plen += m->m_len;
 841
 842                         vptr = mtod(m, vm_offset_t);
 843                         td->address.highpart = 0;
 844                         td->address.lowpart = vtophys(vptr);
 845
 846                         td->cso = 0;
 847                         td->status = 0;
 848                         td->special = 0;
 849                         td->cmd = 0;
 850                         td->css = 0;
 851
 852                         if (sc->wx_debug) {
 853                                 printf("%s: XMIT[%d] %p vptr %lx (length %d "
 854                                     "DMA addr %x) idx %d\n", sc->wx_name,
 855                                     ndesc, m, (long) vptr, td->length,
 856                                     td->address.lowpart, cidx);
 857                         }
 858                         ndesc++;
 859                         cidx = T_NXT_IDX(cidx);
 860                 }
 861
 862                 /*
 863                  * If we get here and m is NULL, we can send
 864                  * the the packet chain described by mb_head.
 865                  */
 866                 if (m == NULL) {
 867                         /*
 868                          * Mark the last descriptor with EOP and tell the
 869                          * chip to insert a final checksum.
 870                          */
 871                         wxtd_t *td = &sc->tdescriptors[T_PREV_IDX(cidx)];
 872                         td->cmd = TXCMD_EOP|TXCMD_IFCS;
 873                         /*
 874                          * Set up a delayed interrupt when this packet
 875                          * is sent and the descriptor written back.
 876                          * Additional packets completing will cause
 877                          * interrupt to be delayed further. Therefore,
 878                          * after the *last* packet is sent, after the delay
 879                          * period in TIDV, an interrupt will be generated
 880                          * which will cause us to garbage collect.
 881                          */
 882                         td->cmd |= TXCMD_IDE|TXCMD_RPS;
 883
 884                         /*
 885                          * Don't xmit odd length packets.
 886                          * We're okay with bumping things
 887                          * up as long as our mbuf allocation
 888                          * is always larger than our MTU
 889                          * by a comfortable amount.
 890                          *
 891                          * Yes, it's a hole to run past the end
 892                          * of a packet.
 893                          */
 894                         if (plen & 0x1) {
 895                                 sc->wx_oddpkt++;
 896                                 td->length++;
 897                         }
 898
 899                         sc->tbase[sc->tnxtfree].sidx = sc->tnxtfree;
 900                         sc->tbase[sc->tnxtfree].eidx = cidx;
 901                         sc->tbase[sc->tnxtfree].next = NULL;
 902                         if (sc->tbsyf) {
 903                                 sc->tbsyl->next = &sc->tbase[sc->tnxtfree];
 904                         } else {
 905                                 sc->tbsyf = &sc->tbase[sc->tnxtfree];
 906                         }
 907                         sc->tbsyl = &sc->tbase[sc->tnxtfree];
 908                         sc->tnxtfree = cidx;
 909                         sc->tactive = nactv;
 910                         ifp->if_timer = 10;
 911                         if (ifp->if_bpf)
 912                                 bpf_mtap(WX_BPFTAP_ARG(ifp), mb_head);
 913                         /* defer xmit until we've got them all */
 914                         widx = cidx;
 915                         continue;
 916                 }
 917
 918                 /*
 919                  * Otherwise, we couldn't send this packet for some reason.
 920                  *
 921                  * If don't have a descriptor available, and this is a
 922                  * single mbuf packet, freeze output so that later we
 923                  * can restart when we have more room. Otherwise, we'll
 924                  * try and cluster the request. We've already tried to
 925                  * garbage collect completed descriptors.
 926                  */
 927                 if (nactv == WX_MAX_TDESC && mb_head->m_next == NULL) {
 928                         sc->wx_xmitputback++;
 929                         ifp->if_flags |= IFF_OACTIVE;
 930                         IF_PREPEND(&ifp->if_snd, mb_head);
 931                         break;
 932                 }
 933
 934                 /*
 935                  * Otherwise, it's either a fragment length somewhere in the
 936                  * chain that isn't at least WX_MIN_XPKT_SIZE in length or
 937                  * the number of fragments exceeds the number of descriptors
 938                  * available.
 939                  *
 940                  * We could try a variety of strategies here- if this is
 941                  * a length problem for single mbuf packet or a length problem
 942                  * for the last mbuf in a chain (we could just try and adjust
 943                  * it), but it's just simpler to try and cluster it.
 944                  */
 945                 MGETHDR(m, M_DONTWAIT, MT_DATA);
 946                 if (m == NULL) {
 947                         m_freem(mb_head);
 948                         break;
 949                 }
 950                 MCLGET(m, M_DONTWAIT);
 951                 if ((m->m_flags & M_EXT) == 0) {
 952                         m_freem(m);
 953                         m_freem(mb_head);
 954                         break;
 955                 }
 956                 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, mtod(m, caddr_t));
 957                 m->m_pkthdr.len = m->m_len = mb_head->m_pkthdr.len;
 958                 m_freem(mb_head);
 959                 mb_head = m;
 960                 sc->wx_xmitcluster++;
 961                 goto again;
 962         }
 963
 964         if (widx < WX_MAX_TDESC) {
 965                 if (IS_WISEMAN(sc)) {
 966                         WRITE_CSR(sc, WXREG_TDT, widx);
 967                 } else {
 968                         WRITE_CSR(sc, WXREG_TDT_LIVENGOOD, widx);
 969                 }
 970         }
 971
 972         if (sc->tactive == WX_MAX_TDESC - 1) {
 973                 sc->wx_xmitgc++;
 974                 wx_gc(sc);
 975                 if (sc->tactive >= WX_MAX_TDESC - 1) {
 976                         sc->wx_xmitblocked++;
 977                         ifp->if_flags |= IFF_OACTIVE;
 978                 }
 979         }
 980
 981         /* used SW LED to indicate transmission active */
 982         if (sc->tactive > 0 && sc->wx_mii) {
 983                 WRITE_CSR(sc, WXREG_DCR,
 984                     READ_CSR(sc, WXREG_DCR) | (WXDCR_SWDPIO0|WXDCR_SWDPIN0));
 985         }
 986         WX_UNLOCK(sc);
 987 }
 988
 989 /*
 990  * Process interface interrupts.
 991  */
 992 static int
 993 wx_intr(void *arg)
 994 {
 995         wx_softc_t *sc = arg;
 996         int claimed = 0;
 997
 998         WX_ILOCK(sc);
 999         /*
1000          * Read interrupt cause register. Reading it clears bits.
1001          */
1002         sc->wx_icr = READ_CSR(sc, WXREG_ICR);
1003         if (sc->wx_icr) {
1004                 claimed++;
1005                 WX_DISABLE_INT(sc);
1006                 sc->wx_intr++;
1007                 if (sc->wx_icr & (WXISR_LSC|WXISR_RXSEQ|WXISR_GPI_EN1)) {
1008                         sc->wx_linkintr++;
1009                         wx_handle_link_intr(sc);
1010                 }
1011                 wx_handle_rxint(sc);
1012                 if (sc->wx_icr & WXISR_TXDW) {
1013                         sc->wx_txqe++;
1014                         wx_gc(sc);
1015                 }
1016 #if     0
1017                 if (sc->wx_icr & WXISR_TXQE) {
1018                         sc->wx_txqe++;
1019                         wx_gc(sc);
1020                 }
1021 #endif
1022                 if (sc->wx_if.if_snd.ifq_head != NULL) {
1023                         wx_start(&sc->wx_if);
1024                 }
1025                 WX_ENABLE_INT(sc);
1026         }
1027         WX_IUNLK(sc);
1028         return (claimed);
1029 }
1030
1031 static void
1032 wx_handle_link_intr(wx_softc_t *sc)
1033 {
1034         u_int32_t txcw, rxcw, dcr, dsr;
1035
1036
1037         dcr = READ_CSR(sc, WXREG_DCR);
1038         DPRINTF(sc, ("%s: handle_link_intr: icr=%#x dcr=%#x\n",
1039             sc->wx_name, sc->wx_icr, dcr));
1040         if (sc->wx_mii) {
1041                 mii_data_t *mii = WX_MII_FROM_SOFTC(sc);
1042                 mii_pollstat(mii);
1043                 if (mii->mii_media_status & IFM_ACTIVE) {
1044                         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE) {
1045                                 IPRINTF(sc, (ldn, sc->wx_name));
1046                                 sc->linkup = 0;
1047                         } else {
1048                                 IPRINTF(sc, (lup, sc->wx_name));
1049                                 sc->linkup = 1;
1050                         }
1051                         WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1052                 } else if (sc->wx_icr & WXISR_RXSEQ) {
1053                         DPRINTF(sc, (sqe, sc->wx_name));
1054                 }
1055                 return;
1056         }
1057
1058         txcw = READ_CSR(sc, WXREG_XMIT_CFGW);
1059         rxcw = READ_CSR(sc, WXREG_RECV_CFGW);
1060         dsr = READ_CSR(sc, WXREG_DSR);
1061
1062         /*
1063          * If we have LOS or are now receiving Ordered Sets and are not
1064          * doing auto-negotiation, restore autonegotiation.
1065          */
1066
1067         if (((dcr & WXDCR_SWDPIN1) || (rxcw & WXRXCW_C)) &&
1068             ((txcw & WXTXCW_ANE) == 0)) {
1069                 DPRINTF(sc, (ane, sc->wx_name));
1070                 WRITE_CSR(sc, WXREG_XMIT_CFGW, WXTXCW_DEFAULT);
1071                 sc->wx_dcr &= ~WXDCR_SLU;
1072                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1073                 sc->ane_failed = 0;
1074         }
1075
1076         if (sc->wx_icr & WXISR_LSC) {
1077                 if (READ_CSR(sc, WXREG_DSR) & WXDSR_LU) {
1078                         IPRINTF(sc, (lup, sc->wx_name));
1079                         sc->linkup = 1;
1080                         sc->wx_dcr |= (WXDCR_SWDPIO0|WXDCR_SWDPIN0);
1081                 } else {
1082                         IPRINTF(sc, (ldn, sc->wx_name));
1083                         sc->linkup = 0;
1084                         sc->wx_dcr &= ~(WXDCR_SWDPIO0|WXDCR_SWDPIN0);
1085                 }
1086                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1087         } else {
1088                 DPRINTF(sc, (sqe, sc->wx_name));
1089         }
1090 }
1091
1092 static void
1093 wx_check_link(wx_softc_t *sc)
1094 {
1095         u_int32_t rxcw, dcr, dsr;
1096
1097         if (sc->wx_mii) {
1098                 mii_pollstat(WX_MII_FROM_SOFTC(sc));
1099                 return;
1100         }
1101
1102         rxcw = READ_CSR(sc, WXREG_RECV_CFGW);
1103         dcr = READ_CSR(sc, WXREG_DCR);
1104         dsr = READ_CSR(sc, WXREG_DSR);
1105
1106         if ((dsr & WXDSR_LU) == 0 && (dcr & WXDCR_SWDPIN1) == 0 &&
1107             (rxcw & WXRXCW_C) == 0) {
1108                 if (sc->ane_failed == 0) {
1109                         sc->ane_failed = 1;
1110                         return;
1111                 }
1112                 DPRINTF(sc, (inane, sc->wx_name));
1113                 WRITE_CSR(sc, WXREG_XMIT_CFGW, WXTXCW_DEFAULT & ~WXTXCW_ANE);
1114                 if (sc->wx_idnrev < WX_WISEMAN_2_1)
1115                         sc->wx_dcr &= ~WXDCR_TFCE;
1116                 sc->wx_dcr |= WXDCR_SLU;
1117                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1118         } else if ((rxcw & WXRXCW_C) != 0 && (dcr & WXDCR_SLU) != 0) {
1119                 DPRINTF(sc, (ane, sc->wx_name));
1120                 WRITE_CSR(sc, WXREG_XMIT_CFGW, WXTXCW_DEFAULT);
1121                 sc->wx_dcr &= ~WXDCR_SLU;
1122                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1123         }
1124 }
1125
1126 static void
1127 wx_handle_rxint(wx_softc_t *sc)
1128 {
1129         struct ether_header *eh;
1130         struct mbuf *m0, *mb, *pending[WX_MAX_RDESC];
1131         struct ifnet *ifp = &sc->wx_if;
1132         int npkts, ndesc, lidx, idx, tlen;
1133
1134         DPRINTF(sc, ("%s: wx_handle_rxint\n", sc->wx_name));
1135
1136         for (m0 = sc->rpending, tlen = ndesc = npkts = 0, idx = sc->rnxt,
1137             lidx = R_PREV_IDX(idx); ndesc < WX_MAX_RDESC;
1138             ndesc++, lidx = idx, idx = R_NXT_IDX(idx)) {
1139                 wxrd_t *rd;
1140                 rxpkt_t *rxpkt;
1141                 int length, offset, lastframe;
1142
1143                 rd = &sc->rdescriptors[idx];
1144                 /*
1145                  * XXX: DMA Flush descriptor
1146                  */
1147                 if ((rd->status & RDSTAT_DD) == 0) {
1148                         if (m0) {
1149                                 if (sc->rpending == NULL) {
1150                                         m0->m_pkthdr.len = tlen;
1151                                         sc->rpending = m0;
1152                                 } else {
1153                                         m_freem(m0);
1154                                 }
1155                                 m0 = NULL;
1156                         }
1157                         DPRINTF(sc, ("%s: WXRX: ndesc %d idx %d lidx %d\n",
1158                             sc->wx_name, ndesc, idx, lidx));
1159                         break;
1160                 }
1161
1162                 if (rd->errors != 0) {
1163                         printf("%s: packet with errors (%x)\n",
1164                             sc->wx_name, rd->errors);
1165                         rd->status = 0;
1166                         ifp->if_ierrors++;
1167                         if (m0) {
1168                                 m_freem(m0);
1169                                 m0 = NULL;
1170                                 if (sc->rpending) {
1171                                         m_freem(sc->rpending);
1172                                         sc->rpending = NULL;
1173                                 }
1174                         }
1175                         continue;
1176                 }
1177
1178
1179                 rxpkt = &sc->rbase[idx];
1180                 mb = rxpkt->dptr;
1181                 if (mb == NULL) {
1182                         printf("%s: receive descriptor with no mbuf\n",
1183                             sc->wx_name);
1184                         (void) wx_get_rbuf(sc, rxpkt);
1185                         rd->status = 0;
1186                         ifp->if_ierrors++;
1187                         if (m0) {
1188                                 m_freem(m0);
1189                                 m0 = NULL;
1190                                 if (sc->rpending) {
1191                                         m_freem(sc->rpending);
1192                                         sc->rpending = NULL;
1193                                 }
1194                         }
1195                         continue;
1196                 }
1197
1198                 /* XXX: Flush DMA for rxpkt */
1199
1200                 if (wx_get_rbuf(sc, rxpkt)) {
1201                         sc->wx_rxnobuf++;
1202                         wx_rxdma_map(sc, rxpkt, mb);
1203                         ifp->if_ierrors++;
1204                         rd->status = 0;
1205                         if (m0) {
1206                                 m_freem(m0);
1207                                 m0 = NULL;
1208                                 if (sc->rpending) {
1209                                         m_freem(sc->rpending);
1210                                         sc->rpending = NULL;
1211                                 }
1212                         }
1213                         continue;
1214                 }
1215
1216                 /*
1217                  * Save the completing packet's offset value and length
1218                  * and install the new one into the descriptor.
1219                  */
1220                 lastframe = (rd->status & RDSTAT_EOP) != 0;
1221                 length = rd->length;
1222                 offset = rd->address.lowpart & 0xff;
1223                 bzero (rd, sizeof (*rd));
1224                 rd->address.lowpart = rxpkt->dma_addr + WX_RX_OFFSET_VALUE;
1225
1226                 mb->m_len = length;
1227                 mb->m_data += offset;
1228                 mb->m_next = NULL;
1229                 if (m0 == NULL) {
1230                         m0 = mb;
1231                         tlen = length;
1232                 } else if (m0 == sc->rpending) {
1233                         /*
1234                          * Pick up where we left off before. If
1235                          * we have an offset (we're assuming the
1236                          * first frame has an offset), then we've
1237                          * lost sync somewhere along the line.
1238                          */
1239                         if (offset) {
1240                                 printf("%s: lost sync with partial packet\n",
1241                                     sc->wx_name);
1242                                 m_freem(sc->rpending);
1243                                 sc->rpending = NULL;
1244                                 m0 = mb;
1245                                 tlen = length;
1246                         } else {
1247                                 sc->rpending = NULL;
1248                                 tlen = m0->m_pkthdr.len;
1249                         }
1250                 } else {
1251                         tlen += length;
1252                 }
1253
1254                 DPRINTF(sc, ("%s: RDESC[%d] len %d off %d lastframe %d\n",
1255                     sc->wx_name, idx, mb->m_len, offset, lastframe));
1256                 if (m0 != mb)
1257                         m_cat(m0, mb);
1258                 if (lastframe == 0) {
1259                         continue;
1260                 }
1261                 m0->m_pkthdr.rcvif = ifp;
1262                 m0->m_pkthdr.len = tlen - WX_CRC_LENGTH;
1263                 mb->m_len -= WX_CRC_LENGTH;
1264
1265                 eh = mtod(m0, struct ether_header *);
1266                 /*
1267                  * No need to check for promiscous mode since
1268                  * the decision to keep or drop the packet is
1269                  * handled by ether_input()
1270                  */
1271                 pending[npkts++] = m0;
1272                 m0 = NULL;
1273                 tlen = 0;
1274         }
1275
1276         if (ndesc) {
1277                 if (IS_WISEMAN(sc)) {
1278                         WRITE_CSR(sc, WXREG_RDT0, lidx);
1279                 } else {
1280                         WRITE_CSR(sc, WXREG_RDT0_LIVENGOOD, lidx);
1281                 }
1282                 sc->rnxt = idx;
1283         }
1284
1285         if (npkts) {
1286                 sc->wx_rxintr++;
1287         }
1288
1289         for (idx = 0; idx < npkts; idx++) {
1290                 mb = pending[idx];
1291                 if (ifp->if_bpf) {
1292                         bpf_mtap(WX_BPFTAP_ARG(ifp), mb);
1293                 }
1294                 ifp->if_ipackets++;
1295                 DPRINTF(sc, ("%s: RECV packet length %d\n",
1296                     sc->wx_name, mb->m_pkthdr.len));
1297                 eh = mtod(mb, struct ether_header *);
1298                 m_adj(mb, sizeof (struct ether_header));
1299                 ether_input(ifp, eh, mb);
1300         }
1301 }
1302
1303 static void
1304 wx_gc(wx_softc_t *sc)
1305 {
1306         struct ifnet *ifp = &sc->wx_if;
1307         txpkt_t *txpkt;
1308         u_int32_t tdh;
1309
1310         WX_LOCK(sc);
1311         txpkt = sc->tbsyf;
1312         if (IS_WISEMAN(sc)) {
1313                 tdh = READ_CSR(sc, WXREG_TDH);
1314         } else {
1315                 tdh = READ_CSR(sc, WXREG_TDH_LIVENGOOD);
1316         }
1317         while (txpkt != NULL) {
1318                 u_int32_t end = txpkt->eidx, cidx = tdh;
1319
1320                 /*
1321                  * Normalize start..end indices to 2 *
1322                  * WX_MAX_TDESC range to eliminate wrap.
1323                  */
1324                 if (txpkt->eidx < txpkt->sidx) {
1325                         end += WX_MAX_TDESC;
1326                 }
1327
1328                 /*
1329                  * Normalize current chip index to 2 *
1330                  * WX_MAX_TDESC range to eliminate wrap.
1331                  */
1332                 if (cidx < txpkt->sidx) {
1333                         cidx += WX_MAX_TDESC;
1334                 }
1335
1336                 /*
1337                  * If the current chip index is between low and
1338                  * high indices for this packet, it's not finished
1339                  * transmitting yet. Because transmits are done FIFO,
1340                  * this means we're done garbage collecting too.
1341                  */
1342
1343                 if (txpkt->sidx <= cidx && cidx < txpkt->eidx) {
1344                         DPRINTF(sc, ("%s: TXGC %d..%d TDH %d\n", sc->wx_name,
1345                             txpkt->sidx, txpkt->eidx, tdh));
1346                         break;
1347                 }
1348                 ifp->if_opackets++;
1349
1350                 if (txpkt->dptr) {
1351                         (void) m_freem(txpkt->dptr);
1352                 } else {
1353                         printf("%s: null mbuf in gc\n", sc->wx_name);
1354                 }
1355
1356                 for (cidx = txpkt->sidx; cidx != txpkt->eidx;
1357                     cidx = T_NXT_IDX(cidx)) {
1358                         txpkt_t *tmp;
1359                         wxtd_t *td;
1360
1361                         td = &sc->tdescriptors[cidx];
1362                         if (td->status & TXSTS_EC) {
1363                                 IPRINTF(sc, ("%s: excess collisions\n",
1364                                     sc->wx_name));
1365                                 ifp->if_collisions++;
1366                                 ifp->if_oerrors++;
1367                         }
1368                         if (td->status & TXSTS_LC) {
1369                                 IPRINTF(sc,
1370                                     ("%s: lost carrier\n", sc->wx_name));
1371                                 ifp->if_oerrors++;
1372                         }
1373                         tmp = &sc->tbase[cidx];
1374                         DPRINTF(sc, ("%s: TXGC[%d] %p %d..%d done nact %d "
1375                             "TDH %d\n", sc->wx_name, cidx, tmp->dptr,
1376                             txpkt->sidx, txpkt->eidx, sc->tactive, tdh));
1377                         tmp->dptr = NULL;
1378                         if (sc->tactive == 0) {
1379                                 printf("%s: nactive < 0?\n", sc->wx_name);
1380                         } else {
1381                                 sc->tactive -= 1;
1382                         }
1383                         bzero(td, sizeof (*td));
1384                 }
1385                 sc->tbsyf = txpkt->next;
1386                 txpkt = sc->tbsyf;
1387         }
1388         if (sc->tactive < WX_MAX_TDESC - 1) {
1389                 ifp->if_timer = 0;
1390                 ifp->if_flags &= ~IFF_OACTIVE;
1391         }
1392
1393         /* used SW LED to indicate transmission not active */
1394         if (sc->tactive == 0 && sc->wx_mii) {
1395                 WRITE_CSR(sc, WXREG_DCR,
1396                     READ_CSR(sc, WXREG_DCR) & ~(WXDCR_SWDPIO0|WXDCR_SWDPIN0));
1397         }
1398         WX_UNLOCK(sc);
1399 }
1400
1401 /*
1402  * Periodic timer to update packet in/out/collision statistics,
1403  * and, more importantly, garbage collect completed transmissions
1404  * and to handle link status changes.
1405  */
1406 #define WX_PRT_STATS(sc, y)     printf("\t" # y " = %u\n", (sc)-> ## y )
1407 #define WX_CLR_STATS(sc, y)     (sc)-> ## y  = 0
1408
1409 static void
1410 wx_watchdog(void *arg)
1411 {
1412         wx_softc_t *sc = arg;
1413
1414         WX_LOCK(sc);
1415         if (sc->wx_needreinit) {
1416                 WX_UNLOCK(sc);
1417                 if (wx_init(sc) == 0) {
1418                         WX_LOCK(sc);
1419                         sc->wx_needreinit = 0;
1420                 } else {
1421                         WX_LOCK(sc);
1422                 }
1423         } else {
1424                 wx_gc(sc);
1425                 wx_check_link(sc);
1426         }
1427         if (wx_dump_stats == device_get_unit(sc->w.dev)) {
1428                 printf("%s: current statistics\n", sc->wx_name);
1429                 WX_PRT_STATS(sc, wx_intr);
1430                 WX_PRT_STATS(sc, wx_linkintr);
1431                 WX_PRT_STATS(sc, wx_rxintr);
1432                 WX_PRT_STATS(sc, wx_txqe);
1433                 WX_PRT_STATS(sc, wx_xmitgc);
1434                 WX_PRT_STATS(sc, wx_xmitpullup);
1435                 WX_PRT_STATS(sc, wx_xmitcluster);
1436                 WX_PRT_STATS(sc, wx_xmitputback);
1437                 WX_PRT_STATS(sc, wx_xmitwanted);
1438                 WX_PRT_STATS(sc, wx_xmitblocked);
1439                 WX_PRT_STATS(sc, wx_xmitrunt);
1440                 WX_PRT_STATS(sc, wx_rxnobuf);
1441                 WX_PRT_STATS(sc, wx_oddpkt);
1442                 wx_dump_stats = -1;
1443         }
1444         if (wx_clr_stats == device_get_unit(sc->w.dev)) {
1445                 printf("%s: statistics cleared\n", sc->wx_name);
1446                 WX_CLR_STATS(sc, wx_intr);
1447                 WX_CLR_STATS(sc, wx_linkintr);
1448                 WX_CLR_STATS(sc, wx_rxintr);
1449                 WX_CLR_STATS(sc, wx_txqe);
1450                 WX_CLR_STATS(sc, wx_xmitgc);
1451                 WX_CLR_STATS(sc, wx_xmitpullup);
1452                 WX_CLR_STATS(sc, wx_xmitcluster);
1453                 WX_CLR_STATS(sc, wx_xmitputback);
1454                 WX_CLR_STATS(sc, wx_xmitwanted);
1455                 WX_CLR_STATS(sc, wx_xmitblocked);
1456                 WX_CLR_STATS(sc, wx_xmitrunt);
1457                 WX_CLR_STATS(sc, wx_rxnobuf);
1458                 WX_CLR_STATS(sc, wx_oddpkt);
1459                 wx_clr_stats = -1;
1460         }
1461         WX_UNLOCK(sc);
1462
1463         /*
1464          * Schedule another timeout one second from now.
1465          */
1466         TIMEOUT(sc, wx_watchdog, sc, hz);
1467 }
1468
1469 /*
1470  * Stop and reinitialize the hardware
1471  */
1472 static void
1473 wx_hw_stop(wx_softc_t *sc)
1474 {
1475         u_int32_t icr;
1476         DPRINTF(sc, ("%s: wx_hw_stop\n", sc->wx_name));
1477         WX_DISABLE_INT(sc);
1478         if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1479                 wx_mwi_whackon(sc);
1480         }
1481         WRITE_CSR(sc, WXREG_DCR, WXDCR_RST);
1482         DELAY(20 * 1000);
1483         icr = READ_CSR(sc, WXREG_ICR);
1484         if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1485                 wx_mwi_unwhack(sc);
1486         }
1487 }
1488
1489 static void
1490 wx_set_addr(wx_softc_t *sc, int idx, u_int8_t *mac)
1491 {
1492         u_int32_t t0, t1;
1493         DPRINTF(sc, ("%s: wx_set_addr\n", sc->wx_name));
1494         t0 = (mac[0]) | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
1495         t1 = (mac[4] << 0) | (mac[5] << 8);
1496         t1 |= WX_RAL_AV;
1497         WRITE_CSR(sc, WXREG_RAL_LO(idx), t0);
1498         WRITE_CSR(sc, WXREG_RAL_HI(idx), t1);
1499 }
1500
1501 static int
1502 wx_hw_initialize(wx_softc_t *sc)
1503 {
1504         int i;
1505
1506         DPRINTF(sc, ("%s: wx_hw_initialize\n", sc->wx_name));
1507
1508         WRITE_CSR(sc, WXREG_VET, 0);
1509         for (i = 0; i < (WX_VLAN_TAB_SIZE << 2); i += 4) {
1510                 WRITE_CSR(sc, (WXREG_VFTA + i), 0);
1511         }
1512         if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1513                 wx_mwi_whackon(sc);
1514                 WRITE_CSR(sc, WXREG_RCTL, WXRCTL_RST);
1515                 DELAY(5 * 1000);
1516         }
1517         /*
1518          * Load the first receiver address with our MAC address,
1519          * and load as many multicast addresses as can fit into
1520          * the receive address array.
1521          */
1522         wx_set_addr(sc, 0, sc->wx_enaddr);
1523         for (i = 1; i <= sc->wx_nmca; i++) {
1524                 if (i >= WX_RAL_TAB_SIZE) {
1525                         break;
1526                 } else {
1527                         wx_set_addr(sc, i, sc->wx_mcaddr[i-1]);
1528                 }
1529         }
1530
1531         while (i < WX_RAL_TAB_SIZE) {
1532                 WRITE_CSR(sc, WXREG_RAL_LO(i), 0);
1533                 WRITE_CSR(sc, WXREG_RAL_HI(i), 0);
1534                 i++;
1535         }
1536
1537         if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1538                 WRITE_CSR(sc, WXREG_RCTL, 0);
1539                 DELAY(1 * 1000);
1540                 wx_mwi_unwhack(sc);
1541         }
1542
1543         /*
1544          * Clear out the hashed multicast table array.
1545          */
1546         for (i = 0; i < WX_MC_TAB_SIZE; i++) {
1547                 WRITE_CSR(sc, WXREG_MTA + (sizeof (u_int32_t) * 4), 0);
1548         }
1549
1550         if (IS_LIVENGOOD_CU(sc)) {
1551                 /*
1552                  * has a PHY - raise its reset line to make it operational
1553                  */
1554                 u_int32_t tmp = READ_CSR(sc, WXREG_EXCT);
1555                 tmp |= WXPHY_RESET_DIR4;
1556                 WRITE_CSR(sc, WXREG_EXCT, tmp);
1557                 DELAY(20*1000);
1558
1559                 tmp = READ_CSR(sc, WXREG_EXCT);
1560                 tmp &= ~WXPHY_RESET4;
1561                 WRITE_CSR(sc, WXREG_EXCT, tmp);
1562                 DELAY(20*1000);
1563
1564                 tmp = READ_CSR(sc, WXREG_EXCT);
1565                 tmp |= WXPHY_RESET4;
1566                 WRITE_CSR(sc, WXREG_EXCT, tmp);
1567                 DELAY(20*1000);
1568         } else if (IS_LIVENGOOD(sc)) {
1569                 u_int16_t tew;
1570
1571                 /*
1572                  * Handle link control
1573                  */
1574                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr | WXDCR_LRST);
1575                 DELAY(50 * 1000);
1576
1577                 wx_read_eeprom(sc, &tew, WX_EEPROM_CTLR2_OFF, 1);
1578                 tew = (tew & WX_EEPROM_CTLR2_SWDPIO) << WX_EEPROM_EXT_SHIFT;
1579                 WRITE_CSR(sc, WXREG_EXCT, (u_int32_t)tew);
1580         }
1581
1582         if (sc->wx_dcr & (WXDCR_RFCE|WXDCR_TFCE)) {
1583                 WRITE_CSR(sc, WXREG_FCAL, FC_FRM_CONST_LO);
1584                 WRITE_CSR(sc, WXREG_FCAH, FC_FRM_CONST_HI);
1585                 WRITE_CSR(sc, WXREG_FCT, FC_TYP_CONST);
1586         } else {
1587                 WRITE_CSR(sc, WXREG_FCAL, 0);
1588                 WRITE_CSR(sc, WXREG_FCAH, 0);
1589                 WRITE_CSR(sc, WXREG_FCT, 0);
1590         }
1591         WRITE_CSR(sc, WXREG_FLOW_XTIMER, WX_XTIMER_DFLT);
1592
1593         if (IS_WISEMAN(sc)) {
1594                 if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1595                         WRITE_CSR(sc, WXREG_FLOW_RCV_HI, 0);
1596                         WRITE_CSR(sc, WXREG_FLOW_RCV_LO, 0);
1597                         sc->wx_dcr &= ~(WXDCR_RFCE|WXDCR_TFCE);
1598                 } else {
1599                         WRITE_CSR(sc, WXREG_FLOW_RCV_HI, WX_RCV_FLOW_HI_DFLT);
1600                         WRITE_CSR(sc, WXREG_FLOW_RCV_LO, WX_RCV_FLOW_LO_DFLT);
1601                 }
1602         } else {
1603                 WRITE_CSR(sc, WXREG_FLOW_RCV_HI_LIVENGOOD, WX_RCV_FLOW_HI_DFLT);
1604                 WRITE_CSR(sc, WXREG_FLOW_RCV_LO_LIVENGOOD, WX_RCV_FLOW_LO_DFLT);
1605         }
1606
1607         if (!IS_LIVENGOOD_CU(sc))
1608                 WRITE_CSR(sc, WXREG_XMIT_CFGW, WXTXCW_DEFAULT);
1609
1610         WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1611         DELAY(50 * 1000);
1612
1613         if (!IS_LIVENGOOD_CU(sc)) {
1614                 /*
1615                  * The pin stuff is all FM from the Linux driver.
1616                  */
1617                 if ((READ_CSR(sc, WXREG_DCR) & WXDCR_SWDPIN1) == 0) {
1618                         for (i = 0; i < (WX_LINK_UP_TIMEOUT/10); i++) {
1619                                 DELAY(10 * 1000);
1620                                 if (READ_CSR(sc, WXREG_DSR) & WXDSR_LU) {
1621                                         sc->linkup = 1;
1622                                         break;
1623                                 }
1624                         }
1625                         if (sc->linkup == 0) {
1626                                 sc->ane_failed = 1;
1627                                 wx_check_link(sc);
1628                         }
1629                         sc->ane_failed = 0;
1630                 } else {
1631                         printf("%s: SWDPIO1 did not clear- check for reversed "
1632                                 "or disconnected cable\n", sc->wx_name);
1633                         /* but return okay anyway */
1634                 }
1635         }
1636
1637         sc->wx_ienable = WXIENABLE_DEFAULT;
1638         return (0);
1639 }
1640
1641 /*
1642  * Stop the interface. Cancels the statistics updater and resets the interface.
1643  */
1644 static void
1645 wx_stop(wx_softc_t *sc)
1646 {
1647         txpkt_t *txp;
1648         rxpkt_t *rxp;
1649         struct ifnet *ifp = &sc->wx_if;
1650
1651         DPRINTF(sc, ("%s: wx_stop\n", sc->wx_name));
1652         /*
1653          * Cancel stats updater.
1654          */
1655         UNTIMEOUT(wx_watchdog, sc, sc);
1656
1657         /*
1658          * Reset the chip
1659          */
1660         wx_hw_stop(sc);
1661
1662         /*
1663          * Release any xmit buffers.
1664          */
1665         for (txp = sc->tbase; txp && txp < &sc->tbase[WX_MAX_TDESC]; txp++) {
1666                 if (txp->dptr) {
1667                         m_free(txp->dptr);
1668                         txp->dptr = NULL;
1669                 }
1670         }
1671
1672         /*
1673          * Free all the receive buffers.
1674          */
1675         for (rxp = sc->rbase; rxp && rxp < &sc->rbase[WX_MAX_RDESC]; rxp++) {
1676                 if (rxp->dptr) {
1677                         m_free(rxp->dptr);
1678                         rxp->dptr = NULL;
1679                 }
1680         }
1681
1682         if (sc->rpending) {
1683                 m_freem(sc->rpending);
1684                 sc->rpending = NULL;
1685         }
1686
1687         /*
1688          * And we're outta here...
1689          */
1690
1691         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1692         ifp->if_timer = 0;
1693 }
1694
1695 /*
1696  * Transmit Watchdog
1697  */
1698 static void
1699 wx_txwatchdog(struct ifnet *ifp)
1700 {
1701         wx_softc_t *sc = SOFTC_IFP(ifp);
1702         printf("%s: device timeout\n", sc->wx_name);
1703         ifp->if_oerrors++;
1704         if (wx_init(sc)) {
1705                 printf("%s: could not re-init device\n", sc->wx_name);
1706                 sc->wx_needreinit = 1;
1707         }
1708 }
1709
1710 static int
1711 wx_init(void *xsc)
1712 {
1713         struct ifmedia *ifm;
1714         wx_softc_t *sc = xsc;
1715         struct ifnet *ifp = &sc->wx_if;
1716         rxpkt_t *rxpkt;
1717         wxrd_t *rd;
1718         size_t len;
1719         int i, bflags;
1720
1721         DPRINTF(sc, ("%s: wx_init\n", sc->wx_name));
1722         WX_LOCK(sc);
1723
1724         /*
1725          * Cancel any pending I/O by resetting things.
1726          * wx_stop will free any allocated mbufs.
1727          */
1728         wx_stop(sc);
1729
1730         /*
1731          * Reset the hardware. All network addresses loaded here, but
1732          * neither the receiver nor the transmitter are enabled.
1733          */
1734
1735         if (wx_hw_initialize(sc)) {
1736                 DPRINTF(sc, ("%s: wx_hw_initialize failed\n", sc->wx_name));
1737                 WX_UNLOCK(sc);
1738                 return (EIO);
1739         }
1740
1741         /*
1742          * Set up the receive ring stuff.
1743          */
1744         len = sizeof (wxrd_t) * WX_MAX_RDESC;
1745         bzero(sc->rdescriptors, len);
1746         for (rxpkt = sc->rbase, i = 0; rxpkt != NULL && i < WX_MAX_RDESC;
1747             i += RXINCR, rxpkt++) {
1748                 rd = &sc->rdescriptors[i];
1749                 if (wx_get_rbuf(sc, rxpkt)) {
1750                         break;
1751                 }
1752                 rd->address.lowpart = rxpkt->dma_addr + WX_RX_OFFSET_VALUE;
1753         }
1754         if (i != WX_MAX_RDESC) {
1755                 printf("%s: could not set up rbufs\n", sc->wx_name);
1756                 wx_stop(sc);
1757                 WX_UNLOCK(sc);
1758                 return (ENOMEM);
1759         }
1760
1761         /*
1762          * Set up transmit parameters and enable the transmitter.
1763          */
1764         sc->tnxtfree = sc->tactive = 0;
1765         sc->tbsyf = sc->tbsyl = NULL;
1766         WRITE_CSR(sc, WXREG_TCTL, 0);
1767         DELAY(5 * 1000);
1768         if (IS_WISEMAN(sc)) {
1769                 WRITE_CSR(sc, WXREG_TDBA_LO,
1770                         vtophys((vm_offset_t)&sc->tdescriptors[0]));
1771                 WRITE_CSR(sc, WXREG_TDBA_HI, 0);
1772                 WRITE_CSR(sc, WXREG_TDLEN, WX_MAX_TDESC * sizeof (wxtd_t));
1773                 WRITE_CSR(sc, WXREG_TDH, 0);
1774                 WRITE_CSR(sc, WXREG_TDT, 0);
1775                 WRITE_CSR(sc, WXREG_TQSA_HI, 0);
1776                 WRITE_CSR(sc, WXREG_TQSA_LO, 0);
1777                 WRITE_CSR(sc, WXREG_TIPG, WX_WISEMAN_TIPG_DFLT);
1778                 WRITE_CSR(sc, WXREG_TIDV, wx_txint_delay);
1779         } else {
1780                 WRITE_CSR(sc, WXREG_TDBA_LO_LIVENGOOD,
1781                         vtophys((vm_offset_t)&sc->tdescriptors[0]));
1782                 WRITE_CSR(sc, WXREG_TDBA_HI_LIVENGOOD, 0);
1783                 WRITE_CSR(sc, WXREG_TDLEN_LIVENGOOD,
1784                         WX_MAX_TDESC * sizeof (wxtd_t));
1785                 WRITE_CSR(sc, WXREG_TDH_LIVENGOOD, 0);
1786                 WRITE_CSR(sc, WXREG_TDT_LIVENGOOD, 0);
1787                 WRITE_CSR(sc, WXREG_TQSA_HI, 0);
1788                 WRITE_CSR(sc, WXREG_TQSA_LO, 0);
1789                 WRITE_CSR(sc, WXREG_TIPG, WX_LIVENGOOD_TIPG_DFLT);
1790                 WRITE_CSR(sc, WXREG_TIDV_LIVENGOOD, wx_txint_delay);
1791         }
1792         WRITE_CSR(sc, WXREG_TCTL, (WXTCTL_CT(WX_COLLISION_THRESHOLD) |
1793             WXTCTL_COLD(WX_FDX_COLLISION_DX) | WXTCTL_EN));
1794         /*
1795          * Set up receive parameters and enable the receiver.
1796          */
1797
1798         sc->rnxt = 0;
1799         WRITE_CSR(sc, WXREG_RCTL, 0);
1800         DELAY(5 * 1000);
1801         if (IS_WISEMAN(sc)) {
1802                 WRITE_CSR(sc, WXREG_RDTR0, WXRDTR_FPD);
1803                 WRITE_CSR(sc, WXREG_RDBA0_LO,
1804                     vtophys((vm_offset_t)&sc->rdescriptors[0]));
1805                 WRITE_CSR(sc, WXREG_RDBA0_HI, 0);
1806                 WRITE_CSR(sc, WXREG_RDLEN0, WX_MAX_RDESC * sizeof (wxrd_t));
1807                 WRITE_CSR(sc, WXREG_RDH0, 0);
1808                 WRITE_CSR(sc, WXREG_RDT0, (WX_MAX_RDESC - RXINCR));
1809         } else {
1810                 /*
1811                  * The delay should yield ~10us receive interrupt delay
1812                  */
1813                 WRITE_CSR(sc, WXREG_RDTR0_LIVENGOOD, WXRDTR_FPD | 0x40);
1814                 WRITE_CSR(sc, WXREG_RDBA0_LO_LIVENGOOD,
1815                     vtophys((vm_offset_t)&sc->rdescriptors[0]));
1816                 WRITE_CSR(sc, WXREG_RDBA0_HI_LIVENGOOD, 0);
1817                 WRITE_CSR(sc, WXREG_RDLEN0_LIVENGOOD,
1818                     WX_MAX_RDESC * sizeof (wxrd_t));
1819                 WRITE_CSR(sc, WXREG_RDH0_LIVENGOOD, 0);
1820                 WRITE_CSR(sc, WXREG_RDT0_LIVENGOOD, (WX_MAX_RDESC - RXINCR));
1821         }
1822         WRITE_CSR(sc, WXREG_RDTR1, 0);
1823         WRITE_CSR(sc, WXREG_RDBA1_LO, 0);
1824         WRITE_CSR(sc, WXREG_RDBA1_HI, 0);
1825         WRITE_CSR(sc, WXREG_RDLEN1, 0);
1826         WRITE_CSR(sc, WXREG_RDH1, 0);
1827         WRITE_CSR(sc, WXREG_RDT1, 0);
1828
1829         if (ifp->if_mtu > ETHERMTU) {
1830                 bflags = WXRCTL_EN | WXRCTL_LPE | WXRCTL_2KRBUF;
1831         } else {
1832                 bflags = WXRCTL_EN | WXRCTL_2KRBUF;
1833         }
1834
1835         WRITE_CSR(sc, WXREG_RCTL, bflags |
1836             ((ifp->if_flags & IFF_BROADCAST) ? WXRCTL_BAM : 0) |
1837             ((ifp->if_flags & IFF_PROMISC) ? WXRCTL_UPE : 0) |
1838             ((sc->all_mcasts) ? WXRCTL_MPE : 0));
1839
1840         /*
1841          * Enable Interrupts
1842          */
1843         WX_ENABLE_INT(sc);
1844
1845         if (sc->wx_mii) {
1846                 mii_mediachg(WX_MII_FROM_SOFTC(sc));
1847         } else {
1848                 ifm = &sc->wx_media;
1849                 i = ifm->ifm_media;
1850                 ifm->ifm_media = ifm->ifm_cur->ifm_media;
1851                 wx_ifmedia_upd(ifp);
1852                 ifm->ifm_media = i;
1853         }
1854
1855         /*
1856          * Mark that we're up and running...
1857          */
1858         ifp->if_flags |= IFF_RUNNING;
1859         ifp->if_flags &= ~IFF_OACTIVE;
1860
1861
1862         /*
1863          * Start stats updater.
1864          */
1865         TIMEOUT(sc, wx_watchdog, sc, hz);
1866
1867         WX_UNLOCK(sc);
1868         /*
1869          * And we're outta here...
1870          */
1871         return (0);
1872 }
1873
1874 /*
1875  * Get a receive buffer for our use (and dma map the data area).
1876  *
1877  * The Wiseman chip can have buffers be 256, 512, 1024 or 2048 bytes in size.
1878  * The LIVENGOOD chip can go higher (up to 16K), but what's the point as
1879  * we aren't doing non-MCLGET memory management.
1880  *
1881  * It wants them aligned on 256 byte boundaries, but can actually cope
1882  * with an offset in the first 255 bytes of the head of a receive frame.
1883  *
1884  * We'll allocate a MCLBYTE sized cluster but *not* adjust the data pointer
1885  * by any alignment value. Instead, we'll tell the chip to offset by any
1886  * alignment and we'll catch the alignment on the backend at interrupt time.
1887  */
1888 static void
1889 wx_rxdma_map(wx_softc_t *sc, rxpkt_t *rxpkt, struct mbuf *mb)
1890 {
1891         rxpkt->dptr = mb;
1892         rxpkt->dma_addr = vtophys(mtod(mb, vm_offset_t));
1893 }
1894
1895 static int
1896 wx_get_rbuf(wx_softc_t *sc, rxpkt_t *rxpkt)
1897 {
1898         struct mbuf *mb;
1899         MGETHDR(mb, M_DONTWAIT, MT_DATA);
1900         if (mb == NULL) {
1901                 rxpkt->dptr = NULL;
1902                 return (-1);
1903         }
1904         MCLGET(mb, M_DONTWAIT);
1905         if ((mb->m_flags & M_EXT) == 0) {
1906                 m_freem(mb);
1907                 rxpkt->dptr = NULL;
1908                 return (-1);
1909         }
1910         wx_rxdma_map(sc, rxpkt, mb);
1911         return (0);
1912 }
1913
1914 static int
1915 wx_ioctl(struct ifnet *ifp, IOCTL_CMD_TYPE command, caddr_t data)
1916 {
1917         wx_softc_t *sc = SOFTC_IFP(ifp);
1918         struct ifreq *ifr = (struct ifreq *) data;
1919         int error = 0;
1920
1921         WX_LOCK(sc);
1922         switch (command) {
1923         case SIOCSIFADDR:
1924         case SIOCGIFADDR:
1925                 error = ether_ioctl(ifp, command, data);
1926                 break;
1927         case SIOCSIFMTU:
1928                 if (ifr->ifr_mtu > WX_MAXMTU || ifr->ifr_mtu < ETHERMIN) {
1929                         error = EINVAL;
1930                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
1931                         ifp->if_mtu = ifr->ifr_mtu;
1932                         error = wx_init(sc);
1933                 }
1934                 break;
1935         case SIOCSIFFLAGS:
1936                 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0;
1937
1938                 /*
1939                  * If interface is marked up and not running, then start it.
1940                  * If it is marked down and running, stop it.
1941                  * If it's up then re-initialize it. This is so flags
1942                  * such as IFF_PROMISC are handled.
1943                  */
1944                 if (ifp->if_flags & IFF_UP) {
1945                         if ((ifp->if_flags & IFF_RUNNING) == 0) {
1946                                 error = wx_init(sc);
1947                         }
1948                 } else {
1949                         if (ifp->if_flags & IFF_RUNNING) {
1950                                 wx_stop(sc);
1951                         }
1952                 }
1953                 break;
1954
1955         case SIOCADDMULTI:
1956         case SIOCDELMULTI:
1957                 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0;
1958                 error = wx_mc_setup(sc);
1959                 break;
1960         case SIOCGIFMEDIA:
1961         case SIOCSIFMEDIA:
1962                 DPRINTF(sc, ("%s: ioctl SIOC[GS]IFMEDIA: command=%#lx\n",
1963                     sc->wx_name, command));
1964                 if (sc->wx_mii) {
1965                         mii_data_t *mii = WX_MII_FROM_SOFTC(sc);
1966                         error = ifmedia_ioctl(ifp, ifr,
1967                             &mii->mii_media, command);
1968                 } else {
1969                         error = ifmedia_ioctl(ifp, ifr, &sc->wx_media, command);
1970                 }
1971
1972                 break;
1973         default:
1974                 error = EINVAL;
1975         }
1976
1977         WX_UNLOCK(sc);
1978         return (error);
1979 }
1980
1981 static int
1982 wx_ifmedia_upd(struct ifnet *ifp)
1983 {
1984         struct wx_softc *sc = SOFTC_IFP(ifp);
1985         struct ifmedia *ifm;
1986
1987         DPRINTF(sc, ("%s: ifmedia_upd\n", sc->wx_name));
1988
1989         if (sc->wx_mii) {
1990                 mii_mediachg(WX_MII_FROM_SOFTC(sc));
1991                 return 0;
1992         }
1993
1994         ifm = &sc->wx_media;
1995
1996         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1997                 return (EINVAL);
1998         }
1999
2000         return (0);
2001 }
2002
2003 static void
2004 wx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2005 {
2006         u_int32_t dsr;
2007         struct wx_softc *sc = SOFTC_IFP(ifp);
2008
2009         DPRINTF(sc, ("%s: ifmedia_sts: ", sc->wx_name));
2010
2011         if (sc->wx_mii) {
2012                 mii_data_t *mii = WX_MII_FROM_SOFTC(sc);
2013                 mii_pollstat(mii);
2014                 ifmr->ifm_active = mii->mii_media_active;
2015                 ifmr->ifm_status = mii->mii_media_status;
2016                 DPRINTF(sc, ("active=%#x status=%#x\n",
2017                     ifmr->ifm_active, ifmr->ifm_status));
2018                 return;
2019         }
2020
2021         DPRINTF(sc, ("\n"));
2022         ifmr->ifm_status = IFM_AVALID;
2023         ifmr->ifm_active = IFM_ETHER;
2024
2025         if (sc->linkup == 0)
2026                 return;
2027
2028         ifmr->ifm_status |= IFM_ACTIVE;
2029         dsr = READ_CSR(sc, WXREG_DSR);
2030         if (IS_LIVENGOOD(sc)) {
2031                 if (dsr &  WXDSR_1000BT) {
2032                         if (IS_LIVENGOOD_CU(sc)) {
2033                                 ifmr->ifm_status |= IFM_1000_TX;
2034                         }
2035                         else {
2036                                 ifmr->ifm_status |= IFM_1000_SX;
2037                         }
2038                 } else if (dsr & WXDSR_100BT) {
2039                         ifmr->ifm_status |= IFM_100_FX; /* ?? */
2040                 } else {
2041                         ifmr->ifm_status |= IFM_10_T;   /* ?? */
2042                 }
2043         } else {
2044                 ifmr->ifm_status |= IFM_1000_SX;
2045         }
2046         if (dsr & WXDSR_FD) {
2047                 ifmr->ifm_active |= IFM_FDX;
2048         }
2049 }
2050
2051
2052 #define RAISE_CLOCK(sc, dcr)    \
2053                 WRITE_CSR(sc, WXREG_DCR, (dcr) | WXPHY_MDC), DELAY(2)
2054
2055 #define LOWER_CLOCK(sc, dcr)    \
2056                 WRITE_CSR(sc, WXREG_DCR, (dcr) & ~WXPHY_MDC), DELAY(2)
2057
2058 static u_int32_t
2059 wx_mii_shift_in(wx_softc_t *sc)
2060 {
2061         u_int32_t dcr, i;
2062         u_int32_t data = 0;
2063
2064         dcr = READ_CSR(sc, WXREG_DCR);
2065         dcr &= ~(WXPHY_MDIO_DIR | WXPHY_MDIO);
2066         WRITE_CSR(sc, WXREG_DCR, dcr);
2067         RAISE_CLOCK(sc, dcr);
2068         LOWER_CLOCK(sc, dcr);
2069
2070         for (i = 0; i < 16; i++) {
2071                 data <<= 1;
2072                 RAISE_CLOCK(sc, dcr);
2073                 dcr = READ_CSR(sc, WXREG_DCR);
2074
2075                 if (dcr & WXPHY_MDIO)
2076                         data |= 1;
2077
2078                 LOWER_CLOCK(sc, dcr);
2079         }
2080
2081         RAISE_CLOCK(sc, dcr);
2082         LOWER_CLOCK(sc, dcr);
2083         return (data);
2084 }
2085
2086 static void
2087 wx_mii_shift_out(wx_softc_t *sc, u_int32_t data, u_int32_t count)
2088 {
2089         u_int32_t dcr, mask;
2090
2091         dcr = READ_CSR(sc, WXREG_DCR);
2092         dcr |= WXPHY_MDIO_DIR | WXPHY_MDC_DIR;
2093
2094         for (mask = (1 << (count - 1)); mask; mask >>= 1) {
2095                 if (data & mask)
2096                         dcr |= WXPHY_MDIO;
2097                 else
2098                         dcr &= ~WXPHY_MDIO;
2099
2100                 WRITE_CSR(sc, WXREG_DCR, dcr);
2101                 DELAY(2);
2102                 RAISE_CLOCK(sc, dcr);
2103                 LOWER_CLOCK(sc, dcr);
2104         }
2105 }
2106
2107 static int
2108 wx_miibus_readreg(void *arg, int phy, int reg)
2109 {
2110         wx_softc_t *sc = WX_SOFTC_FROM_MII_ARG(arg);
2111         unsigned int data = 0;
2112
2113         if (!IS_LIVENGOOD_CU(sc)) {
2114                 return 0;
2115         }
2116         wx_mii_shift_out(sc, WXPHYC_PREAMBLE, WXPHYC_PREAMBLE_LEN);
2117         wx_mii_shift_out(sc, reg | (phy << 5) | (WXPHYC_READ << 10) |
2118             (WXPHYC_SOF << 12), 14);
2119         data = wx_mii_shift_in(sc);
2120         return (data & WXMDIC_DATA_MASK);
2121 }
2122
2123 static int
2124 wx_miibus_writereg(void *arg, int phy, int reg, int data)
2125 {
2126         wx_softc_t *sc = WX_SOFTC_FROM_MII_ARG(arg);
2127         if (!IS_LIVENGOOD_CU(sc)) {
2128                 return 0;
2129         }
2130         wx_mii_shift_out(sc, WXPHYC_PREAMBLE, WXPHYC_PREAMBLE_LEN);
2131         wx_mii_shift_out(sc, (u_int32_t)data | (WXPHYC_TURNAROUND << 16) |
2132             (reg << 18) | (phy << 23) | (WXPHYC_WRITE << 28) |
2133             (WXPHYC_SOF << 30), 32);
2134         return (0);
2135 }
2136
2137 static void
2138 wx_miibus_statchg(void *arg)
2139 {
2140         wx_softc_t *sc = WX_SOFTC_FROM_MII_ARG(arg);
2141         mii_data_t *mii = WX_MII_FROM_SOFTC(sc);
2142         u_int32_t dcr, tctl;
2143
2144         if (mii == NULL)
2145                 return;
2146
2147         dcr = sc->wx_dcr;
2148         tctl = READ_CSR(sc, WXREG_TCTL);
2149         DPRINTF(sc, ("%s: statchg dcr=%#x tctl=%#x", sc->wx_name, dcr, tctl));
2150
2151         dcr |= WXDCR_FRCSPD | WXDCR_FRCDPX | WXDCR_SLU;
2152         dcr &= ~(WXDCR_SPEED_MASK | WXDCR_ASDE /* | WXDCR_ILOS */);
2153
2154         if (mii->mii_media_status & IFM_ACTIVE) {
2155                 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE) {
2156                         DPRINTF(sc, (" link-down\n"));
2157                         sc->linkup = 0;
2158                         return;
2159                 }
2160
2161                 sc->linkup = 1;
2162         }
2163
2164         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) {
2165                 DPRINTF(sc, (" 1000TX"));
2166                 dcr |= WXDCR_1000BT;
2167         } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
2168                 DPRINTF(sc, (" 100TX"));
2169                 dcr |= WXDCR_100BT;
2170         } else  /* assume IFM_10_TX */ {
2171                 DPRINTF(sc, (" 10TX"));
2172                 dcr |= WXDCR_10BT;
2173         }
2174
2175         if (mii->mii_media_active & IFM_FDX) {
2176                 DPRINTF(sc, ("-FD"));
2177                 tctl = WXTCTL_CT(WX_COLLISION_THRESHOLD) |
2178                     WXTCTL_COLD(WX_FDX_COLLISION_DX) | WXTCTL_EN;
2179                 dcr |= WXDCR_FD;
2180         } else {
2181                 DPRINTF(sc, ("-HD"));
2182                 tctl = WXTCTL_CT(WX_COLLISION_THRESHOLD) |
2183                     WXTCTL_COLD(WX_HDX_COLLISION_DX) | WXTCTL_EN;
2184                 dcr &= ~WXDCR_FD;
2185         }
2186
2187         /* FLAG0==rx-flow-control FLAG1==tx-flow-control */
2188         if (mii->mii_media_active & IFM_FLAG0) {
2189                 dcr |= WXDCR_RFCE;
2190         } else {
2191                 dcr &= ~WXDCR_RFCE;
2192         }
2193
2194         if (mii->mii_media_active & IFM_FLAG1) {
2195                 dcr |= WXDCR_TFCE;
2196         } else {
2197                 dcr &= ~WXDCR_TFCE;
2198         }
2199
2200         if (dcr & (WXDCR_RFCE|WXDCR_TFCE)) {
2201                 WRITE_CSR(sc, WXREG_FCAL, FC_FRM_CONST_LO);
2202                 WRITE_CSR(sc, WXREG_FCAH, FC_FRM_CONST_HI);
2203                 WRITE_CSR(sc, WXREG_FCT, FC_TYP_CONST);
2204         } else {
2205                 WRITE_CSR(sc, WXREG_FCAL, 0);
2206                 WRITE_CSR(sc, WXREG_FCAH, 0);
2207                 WRITE_CSR(sc, WXREG_FCT, 0);
2208         }
2209
2210         DPRINTF(sc, (" dcr=%#x tctl=%#x\n", dcr, tctl));
2211         WRITE_CSR(sc, WXREG_TCTL, tctl);
2212         sc->wx_dcr = dcr;
2213         WRITE_CSR(sc, WXREG_DCR, dcr);
2214 }
2215
2216 static void
2217 wx_miibus_mediainit(void *arg)
2218 {
2219 }