2 * Copyright 1996 Massachusetts Institute of Technology
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5 * its documentation for any purpose and without fee is hereby
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29 * $FreeBSD: src/sys/i386/i386/perfmon.c,v 1.21 1999/09/25 18:24:04 phk Exp $
30 * $DragonFly: src/sys/i386/i386/Attic/perfmon.c,v 1.6 2003/07/21 05:50:39 dillon Exp $
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/fcntl.h>
40 #include <machine/cputypes.h>
42 #include <machine/clock.h>
43 #include <machine/perfmon.h>
45 static int perfmon_inuse;
46 static int perfmon_cpuok;
48 static int msr_ctl[NPMC];
50 static int msr_pmc[NPMC];
51 static unsigned int ctl_shadow[NPMC];
52 static quad_t pmc_shadow[NPMC]; /* used when ctr is stopped on P5 */
53 static int (*writectl)(int);
55 static int writectl5(int);
56 static int writectl6(int);
59 static d_close_t perfmon_close;
60 static d_open_t perfmon_open;
61 static d_ioctl_t perfmon_ioctl;
63 #define CDEV_MAJOR 2 /* We're really a minor of mem.c */
64 static struct cdevsw perfmon_cdevsw = {
71 /* open */ perfmon_open,
72 /* close */ perfmon_close,
75 /* ioctl */ perfmon_ioctl,
78 /* strategy */ nostrategy,
84 * Must be called after cpu_class is set up.
105 writectl = writectl6;
113 make_dev(&perfmon_cdevsw, 32, UID_ROOT, GID_KMEM, 0640, "perfmon");
119 return perfmon_cpuok;
123 perfmon_setup(int pmc, unsigned int control)
125 if (pmc < 0 || pmc >= NPMC)
128 perfmon_inuse |= (1 << pmc);
129 control &= ~(PMCF_SYS_FLAGS << 16);
130 mpintr_lock(); /* doesn't have to be mpintr_lock YYY */
131 ctl_shadow[pmc] = control;
133 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
139 perfmon_get(int pmc, unsigned int *control)
141 if (pmc < 0 || pmc >= NPMC)
144 if (perfmon_inuse & (1 << pmc)) {
145 *control = ctl_shadow[pmc];
148 return EBUSY; /* XXX reversed sense */
152 perfmon_fini(int pmc)
154 if (pmc < 0 || pmc >= NPMC)
157 if (perfmon_inuse & (1 << pmc)) {
160 perfmon_inuse &= ~(1 << pmc);
163 return EBUSY; /* XXX reversed sense */
167 perfmon_start(int pmc)
169 if (pmc < 0 || pmc >= NPMC)
172 if (perfmon_inuse & (1 << pmc)) {
173 mpintr_lock(); /* doesn't have to be mpintr YYY */
174 ctl_shadow[pmc] |= (PMCF_EN << 16);
175 wrmsr(msr_pmc[pmc], pmc_shadow[pmc]);
184 perfmon_stop(int pmc)
186 if (pmc < 0 || pmc >= NPMC)
189 if (perfmon_inuse & (1 << pmc)) {
191 pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
192 ctl_shadow[pmc] &= ~(PMCF_EN << 16);
201 perfmon_read(int pmc, quad_t *val)
203 if (pmc < 0 || pmc >= NPMC)
206 if (perfmon_inuse & (1 << pmc)) {
207 if (ctl_shadow[pmc] & (PMCF_EN << 16))
208 *val = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
210 *val = pmc_shadow[pmc];
218 perfmon_reset(int pmc)
220 if (pmc < 0 || pmc >= NPMC)
223 if (perfmon_inuse & (1 << pmc)) {
224 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
232 * Unfortunately, the performance-monitoring registers are laid out
233 * differently in the P5 and P6. We keep everything in P6 format
234 * internally (except for the event code), and convert to P5
235 * format as needed on those CPUs. The writectl function pointer
236 * is set up to point to one of these functions by perfmon_init().
241 if (pmc > 0 && !(ctl_shadow[pmc] & (PMCF_EN << 16))) {
242 wrmsr(msr_ctl[pmc], 0);
244 wrmsr(msr_ctl[pmc], ctl_shadow[pmc]);
249 #define P5FLAG_P 0x200
250 #define P5FLAG_E 0x100
251 #define P5FLAG_USR 0x80
252 #define P5FLAG_OS 0x40
259 if (ctl_shadow[1] & (PMCF_EN << 16)) {
260 if (ctl_shadow[1] & (PMCF_USR << 16))
261 newval |= P5FLAG_USR << 16;
262 if (ctl_shadow[1] & (PMCF_OS << 16))
263 newval |= P5FLAG_OS << 16;
264 if (!(ctl_shadow[1] & (PMCF_E << 16)))
265 newval |= P5FLAG_E << 16;
266 newval |= (ctl_shadow[1] & 0x3f) << 16;
268 if (ctl_shadow[0] & (PMCF_EN << 16)) {
269 if (ctl_shadow[0] & (PMCF_USR << 16))
270 newval |= P5FLAG_USR;
271 if (ctl_shadow[0] & (PMCF_OS << 16))
273 if (!(ctl_shadow[0] & (PMCF_E << 16)))
275 newval |= ctl_shadow[0] & 0x3f;
278 wrmsr(msr_ctl[0], newval);
279 return 0; /* XXX should check for unimplemented bits */
284 * Now the user-mode interface, called from a subdevice of mem.c.
287 static int writerpmc;
290 perfmon_open(dev_t dev, int flags, int fmt, struct thread *td)
295 if (flags & FWRITE) {
307 perfmon_close(dev_t dev, int flags, int fmt, struct thread *td)
309 if (flags & FWRITE) {
312 for (i = 0; i < NPMC; i++) {
313 if (writerpmc & (1 << i))
322 perfmon_ioctl(dev_t dev, u_long cmd, caddr_t param, int flags, struct thread *td)
325 struct pmc_data *pmcd;
326 struct pmc_tstamp *pmct;
332 if (!(flags & FWRITE))
334 pmc = (struct pmc *)param;
336 rv = perfmon_setup(pmc->pmc_num, pmc->pmc_val);
338 writerpmc |= (1 << pmc->pmc_num);
343 pmc = (struct pmc *)param;
344 rv = perfmon_get(pmc->pmc_num, &pmc->pmc_val);
348 if (!(flags & FWRITE))
352 rv = perfmon_start(*ip);
356 if (!(flags & FWRITE))
360 rv = perfmon_stop(*ip);
364 if (!(flags & FWRITE))
368 rv = perfmon_reset(*ip);
372 pmcd = (struct pmc_data *)param;
373 rv = perfmon_read(pmcd->pmcd_num, &pmcd->pmcd_value);
381 pmct = (struct pmc_tstamp *)param;
382 /* XXX interface loses precision. */
383 pmct->pmct_rate = tsc_freq / 1000000;
384 pmct->pmct_value = rdtsc();