2 * Copyright (c) 2004, 2005 David Young. All rights reserved.
4 * Programmed for NetBSD by David Young.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of David Young may not be used to endorse or promote
15 * products derived from this software without specific prior
18 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
19 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
20 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
21 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
22 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
23 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
24 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
31 * $NetBSD: rtwphy.c,v 1.9 2006/03/08 00:24:06 dyoung Exp $
32 * $DragonFly: src/sys/dev/netif/rtw/rtwphy.c,v 1.3 2006/10/25 20:55:58 dillon Exp $
36 * Control the Philips SA2400 RF front-end and the baseband processor
37 * built into the Realtek RTL8180.
40 #include <sys/param.h>
42 #include <sys/socket.h>
45 #include <net/if_arp.h>
46 #include <net/if_media.h>
48 #include <netproto/802_11/ieee80211_var.h>
49 #include <netproto/802_11/ieee80211_radiotap.h>
53 #include "max2820reg.h"
54 #include "sa2400reg.h"
59 static int rtw_max2820_pwrstate(struct rtw_rf *, enum rtw_pwrstate);
60 static int rtw_sa2400_pwrstate(struct rtw_rf *, enum rtw_pwrstate);
62 #define GCT_WRITE(__gr, __addr, __val, __label) \
64 if (rtw_rfbus_write(&(__gr)->gr_bus, RTW_RFCHIPID_GCT, \
65 (__addr), (__val)) == -1) \
70 rtw_bbp_preinit(struct rtw_regs *regs, u_int antatten0, int dflantb, u_int freq)
72 u_int antatten = antatten0;
75 antatten |= RTW_BBP_ANTATTEN_DFLANTB;
76 if (freq == 2484) /* channel 14 */
77 antatten |= RTW_BBP_ANTATTEN_CHAN14;
78 return rtw_bbp_write(regs, RTW_BBP_ANTATTEN, antatten);
82 rtw_bbp_init(struct rtw_regs *regs, struct rtw_bbpset *bb, int antdiv,
83 int dflantb, uint8_t cs_threshold, u_int freq)
90 sys2 |= RTW_BBP_SYS2_ANTDIV;
91 sys3 = bb->bb_sys3 | SHIFTIN(cs_threshold, RTW_BBP_SYS3_CSTHRESH_MASK);
93 #define RTW_BBP_WRITE_OR_RETURN(reg, val) \
94 if ((rc = rtw_bbp_write(regs, reg, val)) != 0) \
97 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS1, bb->bb_sys1);
98 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TXAGC, bb->bb_txagc);
99 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_LNADET, bb->bb_lnadet);
100 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCINI, bb->bb_ifagcini);
101 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCLIMIT, bb->bb_ifagclimit);
102 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCDET, bb->bb_ifagcdet);
104 if ((rc = rtw_bbp_preinit(regs, bb->bb_antatten, dflantb, freq)) != 0)
107 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TRL, bb->bb_trl);
108 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS2, sys2);
109 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS3, sys3);
110 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHESTLIM, bb->bb_chestlim);
111 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHSQLIM, bb->bb_chsqlim);
116 rtw_sa2400_txpower(struct rtw_rf *rf, uint8_t opaque_txpower)
118 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
119 struct rtw_rfbus *bus = &sa->sa_bus;
121 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_TX,
125 /* make sure we're using the same settings as the reference driver */
127 verify_syna(u_int freq, uint32_t val)
129 uint32_t expected_val = ~val;
133 expected_val = 0x0000096c; /* ch 1 */
136 expected_val = 0x00080970; /* ch 2 */
139 expected_val = 0x00100974; /* ch 3 */
142 expected_val = 0x00180978; /* ch 4 */
145 expected_val = 0x00000980; /* ch 5 */
148 expected_val = 0x00080984; /* ch 6 */
151 expected_val = 0x00100988; /* ch 7 */
154 expected_val = 0x0018098c; /* ch 8 */
157 expected_val = 0x00000994; /* ch 9 */
160 expected_val = 0x00080998; /* ch 10 */
163 expected_val = 0x0010099c; /* ch 11 */
166 expected_val = 0x001809a0; /* ch 12 */
169 expected_val = 0x000009a8; /* ch 13 */
172 expected_val = 0x000009b4; /* ch 14 */
175 KKASSERT(val == expected_val);
180 rtw_sa2400_tune(struct rtw_rf *rf, u_int freq)
182 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
183 struct rtw_rfbus *bus = &sa->sa_bus;
185 uint32_t syna, synb, sync;
189 * XO = 44MHz, R = 11, hence N is in units of XO / R = 4MHz.
191 * The channel spacing (5MHz) is not divisible by 4MHz, so
192 * we set the fractional part of N to compensate.
197 syna = SHIFTIN(nf, SA2400_SYNA_NF_MASK) |
198 SHIFTIN(n, SA2400_SYNA_N_MASK);
199 verify_syna(freq, syna);
202 * Divide the 44MHz crystal down to 4MHz. Set the fractional
203 * compensation charge pump value to agree with the fractional
206 synb = SHIFTIN(11, SA2400_SYNB_R_MASK) | SA2400_SYNB_L_NORMAL |
207 SA2400_SYNB_ON | SA2400_SYNB_ONE |
208 SHIFTIN(80, SA2400_SYNB_FC_MASK); /* agrees w/ SA2400_SYNA_FM = 0 */
210 sync = SA2400_SYNC_CP_NORMAL;
212 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNA, syna);
216 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNB, synb);
220 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNC, sync);
224 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYND, 0x0);
228 rtw_sa2400_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power)
230 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
231 struct rtw_rfbus *bus = &sa->sa_bus;
234 opmode = SA2400_OPMODE_DEFAULTS;
237 opmode |= SA2400_OPMODE_MODE_TXRX;
240 opmode |= SA2400_OPMODE_MODE_WAIT;
243 opmode |= SA2400_OPMODE_MODE_SLEEP;
248 opmode |= SA2400_OPMODE_DIGIN;
250 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
255 rtw_sa2400_manrx_init(struct rtw_sa2400 *sa)
260 * XXX we are not supposed to be in RXMGC mode when we do this?
262 manrx = SA2400_MANRX_AHSN;
263 manrx |= SA2400_MANRX_TEN;
264 manrx |= SHIFTIN(1023, SA2400_MANRX_RXGAIN_MASK);
266 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_MANRX,
271 rtw_sa2400_vcocal_start(struct rtw_sa2400 *sa, int start)
275 opmode = SA2400_OPMODE_DEFAULTS;
277 opmode |= SA2400_OPMODE_MODE_VCOCALIB;
279 opmode |= SA2400_OPMODE_MODE_SLEEP;
282 opmode |= SA2400_OPMODE_DIGIN;
284 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
289 rtw_sa2400_vco_calibration(struct rtw_sa2400 *sa)
294 if ((rc = rtw_sa2400_vcocal_start(sa, 1)) != 0)
296 DELAY(2200); /* 2.2 milliseconds */
297 /* XXX superfluous: SA2400 automatically entered SLEEP mode. */
298 return rtw_sa2400_vcocal_start(sa, 0);
302 rtw_sa2400_filter_calibration(struct rtw_sa2400 *sa)
306 opmode = SA2400_OPMODE_DEFAULTS | SA2400_OPMODE_MODE_FCALIB;
308 opmode |= SA2400_OPMODE_DIGIN;
310 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
315 rtw_sa2400_dc_calibration(struct rtw_sa2400 *sa)
317 struct rtw_rf *rf = &sa->sa_rf;
321 rf->rf_continuous_tx_cb(rf->rf_continuous_tx_arg, 1);
323 dccal = SA2400_OPMODE_DEFAULTS | SA2400_OPMODE_MODE_TXRX;
325 rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
331 * DCALIB after being in Tx mode for 5 microseconds
335 dccal &= ~SA2400_OPMODE_MODE_MASK;
336 dccal |= SA2400_OPMODE_MODE_DCALIB;
338 rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
343 DELAY(20); /* calibration takes at most 20 microseconds */
345 rf->rf_continuous_tx_cb(rf->rf_continuous_tx_arg, 0);
350 rtw_sa2400_agc_init(struct rtw_sa2400 *sa)
354 agc = SHIFTIN(25, SA2400_AGC_MAXGAIN_MASK);
355 agc |= SHIFTIN(7, SA2400_AGC_BBPDELAY_MASK);
356 agc |= SHIFTIN(15, SA2400_AGC_LNADELAY_MASK);
357 agc |= SHIFTIN(27, SA2400_AGC_RXONDELAY_MASK);
359 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_AGC,
364 rtw_sa2400_destroy(struct rtw_rf *rf)
366 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
368 memset(sa, 0, sizeof(*sa));
373 rtw_sa2400_calibrate(struct rtw_rf *rf, u_int freq)
375 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
378 /* XXX reference driver calibrates VCO twice. Is it a bug? */
379 for (i = 0; i < 2; i++) {
380 if ((rc = rtw_sa2400_vco_calibration(sa)) != 0)
383 /* VCO calibration erases synthesizer registers, so re-tune */
384 if ((rc = rtw_sa2400_tune(rf, freq)) != 0)
386 if ((rc = rtw_sa2400_filter_calibration(sa)) != 0)
388 /* analog PHY needs DC calibration */
390 return rtw_sa2400_dc_calibration(sa);
395 rtw_sa2400_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower,
396 enum rtw_pwrstate power)
398 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
401 if ((rc = rtw_sa2400_txpower(rf, opaque_txpower)) != 0)
404 /* skip configuration if it's time to sleep or to power-down. */
405 if (power == RTW_SLEEP || power == RTW_OFF)
406 return rtw_sa2400_pwrstate(rf, power);
408 /* go to sleep for configuration */
409 if ((rc = rtw_sa2400_pwrstate(rf, RTW_SLEEP)) != 0)
412 if ((rc = rtw_sa2400_tune(rf, freq)) != 0)
414 if ((rc = rtw_sa2400_agc_init(sa)) != 0)
416 if ((rc = rtw_sa2400_manrx_init(sa)) != 0)
418 if ((rc = rtw_sa2400_calibrate(rf, freq)) != 0)
421 /* enter Tx/Rx mode */
422 return rtw_sa2400_pwrstate(rf, power);
426 rtw_sa2400_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int digphy)
428 struct rtw_sa2400 *sa;
429 struct rtw_rfbus *bus;
431 struct rtw_bbpset *bb;
433 sa = kmalloc(sizeof(*sa), M_DEVBUF, M_WAITOK | M_ZERO);
435 sa->sa_digphy = digphy;
440 rf->rf_init = rtw_sa2400_init;
441 rf->rf_destroy = rtw_sa2400_destroy;
442 rf->rf_txpower = rtw_sa2400_txpower;
443 rf->rf_tune = rtw_sa2400_tune;
444 rf->rf_pwrstate = rtw_sa2400_pwrstate;
448 bb->bb_antatten = RTW_BBP_ANTATTEN_PHILIPS_MAGIC;
449 bb->bb_chestlim = 0x00;
450 bb->bb_chsqlim = 0xa0;
451 bb->bb_ifagcdet = 0x64;
452 bb->bb_ifagcini = 0x90;
453 bb->bb_ifagclimit = 0x1a;
454 bb->bb_lnadet = 0xe0;
462 bus->b_write = rf_write;
468 rtw_grf5101_txpower(struct rtw_rf *rf, uint8_t opaque_txpower)
470 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf;
472 GCT_WRITE(gr, 0x15, 0, err);
473 GCT_WRITE(gr, 0x06, opaque_txpower, err);
474 GCT_WRITE(gr, 0x15, 0x10, err);
475 GCT_WRITE(gr, 0x15, 0x00, err);
482 rtw_grf5101_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power)
484 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf;
489 GCT_WRITE(gr, 0x07, 0x0000, err);
490 GCT_WRITE(gr, 0x1f, 0x0045, err);
491 GCT_WRITE(gr, 0x1f, 0x0005, err);
492 GCT_WRITE(gr, 0x00, 0x08e4, err);
496 GCT_WRITE(gr, 0x1f, 0x0001, err);
498 GCT_WRITE(gr, 0x1f, 0x0001, err);
500 GCT_WRITE(gr, 0x1f, 0x0041, err);
502 GCT_WRITE(gr, 0x1f, 0x0061, err);
504 GCT_WRITE(gr, 0x00, 0x0ae4, err);
506 GCT_WRITE(gr, 0x07, 0x1000, err);
517 rtw_grf5101_tune(struct rtw_rf *rf, u_int freq)
520 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf;
524 } else if ((channel = (freq - 2412) / 5 + 1) < 1 || channel > 13) {
525 RTW_DPRINTF(RTW_DEBUG_PHY,
526 ("%s: invalid channel %d (freq %d)\n", __func__, channel,
531 GCT_WRITE(gr, 0x07, 0, err);
532 GCT_WRITE(gr, 0x0b, channel - 1, err);
533 GCT_WRITE(gr, 0x07, 0x1000, err);
540 rtw_grf5101_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower,
541 enum rtw_pwrstate power)
544 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf;
547 * These values have been derived from the rtl8180-sa2400
548 * Linux driver. It is unknown what they all do, GCT refuse
549 * to release any documentation so these are more than
550 * likely sub optimal settings
553 GCT_WRITE(gr, 0x01, 0x1a23, err);
554 GCT_WRITE(gr, 0x02, 0x4971, err);
555 GCT_WRITE(gr, 0x03, 0x41de, err);
556 GCT_WRITE(gr, 0x04, 0x2d80, err);
558 GCT_WRITE(gr, 0x05, 0x61ff, err);
560 GCT_WRITE(gr, 0x06, 0x0, err);
562 GCT_WRITE(gr, 0x08, 0x7533, err);
563 GCT_WRITE(gr, 0x09, 0xc401, err);
564 GCT_WRITE(gr, 0x0a, 0x0, err);
565 GCT_WRITE(gr, 0x0c, 0x1c7, err);
566 GCT_WRITE(gr, 0x0d, 0x29d3, err);
567 GCT_WRITE(gr, 0x0e, 0x2e8, err);
568 GCT_WRITE(gr, 0x10, 0x192, err);
569 GCT_WRITE(gr, 0x11, 0x248, err);
570 GCT_WRITE(gr, 0x12, 0x0, err);
571 GCT_WRITE(gr, 0x13, 0x20c4, err);
572 GCT_WRITE(gr, 0x14, 0xf4fc, err);
573 GCT_WRITE(gr, 0x15, 0x0, err);
574 GCT_WRITE(gr, 0x16, 0x1500, err);
576 if ((rc = rtw_grf5101_txpower(rf, opaque_txpower)) != 0)
579 if ((rc = rtw_grf5101_tune(rf, freq)) != 0)
588 rtw_grf5101_destroy(struct rtw_rf *rf)
590 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf;
592 memset(gr, 0, sizeof(*gr));
597 rtw_grf5101_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int digphy)
599 struct rtw_grf5101 *gr;
600 struct rtw_rfbus *bus;
602 struct rtw_bbpset *bb;
604 gr = kmalloc(sizeof(*gr), M_DEVBUF, M_WAITOK | M_ZERO);
609 rf->rf_init = rtw_grf5101_init;
610 rf->rf_destroy = rtw_grf5101_destroy;
611 rf->rf_txpower = rtw_grf5101_txpower;
612 rf->rf_tune = rtw_grf5101_tune;
613 rf->rf_pwrstate = rtw_grf5101_pwrstate;
617 bb->bb_antatten = RTW_BBP_ANTATTEN_GCT_MAGIC;
618 bb->bb_chestlim = 0x00;
619 bb->bb_chsqlim = 0xa0;
620 bb->bb_ifagcdet = 0x64;
621 bb->bb_ifagcini = 0x90;
622 bb->bb_ifagclimit = 0x1e;
623 bb->bb_lnadet = 0xc0;
631 bus->b_write = rf_write;
638 rtw_max2820_tune(struct rtw_rf *rf, u_int freq)
640 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf;
641 struct rtw_rfbus *bus = &mx->mx_bus;
643 if (freq < 2400 || freq > 2499)
646 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_CHANNEL,
647 SHIFTIN(freq - 2400, MAX2820_CHANNEL_CF_MASK));
651 rtw_max2820_destroy(struct rtw_rf *rf)
653 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf;
655 memset(mx, 0, sizeof(*mx));
660 rtw_max2820_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower,
661 enum rtw_pwrstate power)
663 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf;
664 struct rtw_rfbus *bus = &mx->mx_bus;
667 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TEST,
668 MAX2820_TEST_DEFAULT);
672 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE,
673 MAX2820_ENABLE_DEFAULT);
677 /* skip configuration if it's time to sleep or to power-down. */
678 if ((rc = rtw_max2820_pwrstate(rf, power)) != 0)
680 else if (power == RTW_OFF || power == RTW_SLEEP)
683 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_SYNTH,
684 MAX2820_SYNTH_R_44MHZ);
688 if ((rc = rtw_max2820_tune(rf, freq)) != 0)
692 * XXX The MAX2820 datasheet indicates that 1C and 2C should not
693 * be changed from 7, however, the reference driver sets them
694 * to 4 and 1, respectively.
696 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_RECEIVE,
697 MAX2820_RECEIVE_DL_DEFAULT |
698 SHIFTIN(4, MAX2820A_RECEIVE_1C_MASK) |
699 SHIFTIN(1, MAX2820A_RECEIVE_2C_MASK));
703 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TRANSMIT,
704 MAX2820_TRANSMIT_PA_DEFAULT);
708 rtw_max2820_txpower(struct rtw_rf *rf, uint8_t opaque_txpower)
715 rtw_max2820_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power)
718 struct rtw_max2820 *mx;
719 struct rtw_rfbus *bus;
721 mx = (struct rtw_max2820 *)rf;
731 enable = MAX2820_ENABLE_DEFAULT;
734 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE, enable);
738 rtw_max2820_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int is_a)
740 struct rtw_max2820 *mx;
741 struct rtw_rfbus *bus;
743 struct rtw_bbpset *bb;
745 mx = kmalloc(sizeof(*mx), M_DEVBUF, M_WAITOK | M_ZERO);
752 rf->rf_init = rtw_max2820_init;
753 rf->rf_destroy = rtw_max2820_destroy;
754 rf->rf_txpower = rtw_max2820_txpower;
755 rf->rf_tune = rtw_max2820_tune;
756 rf->rf_pwrstate = rtw_max2820_pwrstate;
760 bb->bb_antatten = RTW_BBP_ANTATTEN_MAXIM_MAGIC;
762 bb->bb_chsqlim = 159;
763 bb->bb_ifagcdet = 100;
764 bb->bb_ifagcini = 144;
765 bb->bb_ifagclimit = 26;
774 bus->b_write = rf_write;
781 rtw_phy_init(struct rtw_regs *regs, struct rtw_rf *rf, uint8_t opaque_txpower,
782 uint8_t cs_threshold, u_int freq, int antdiv, int dflantb,
783 enum rtw_pwrstate power)
786 RTW_DPRINTF(RTW_DEBUG_PHY,
787 ("%s: txpower %u csthresh %u freq %u antdiv %u dflantb %u "
788 "pwrstate %s\n", __func__, opaque_txpower, cs_threshold, freq,
789 antdiv, dflantb, rtw_pwrstate_string(power)));
791 /* XXX is this really necessary? */
792 if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0)
795 rc = rtw_bbp_preinit(regs, rf->rf_bbpset.bb_antatten, dflantb, freq);
799 if ((rc = rtw_rf_tune(rf, freq)) != 0)
803 if ((rc = rtw_rf_init(rf, freq, opaque_txpower, power)) != 0)
805 #if 0 /* what is this redundant tx power setting here for? */
806 if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0)
809 return rtw_bbp_init(regs, &rf->rf_bbpset, antdiv, dflantb, cs_threshold, freq);