2 * Copyright (c) 2003 Matthew Dillon <dillon@backplane.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $DragonFly: src/sys/i386/i386/Attic/pmap_inval.c,v 1.1 2004/02/17 19:38:53 dillon Exp $
30 * pmap invalidation support code. Certain hardware requirements must
31 * be dealt with when manipulating page table entries and page directory
32 * entries within a pmap. In particular, we cannot safely manipulate
33 * page tables which are in active use by another cpu (even if it is
34 * running in userland) for two reasons: First, TLB writebacks will
35 * race against our own modifications and tests. Second, even if we
36 * were to use bus-locked instruction we can still screw up the
37 * target cpu's instruction pipeline due to Intel cpu errata.
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
44 #include <sys/vmmeter.h>
45 #include <sys/thread2.h>
49 #include <vm/vm_object.h>
51 #include <machine/cputypes.h>
52 #include <machine/md_var.h>
53 #include <machine/specialreg.h>
54 #if defined(SMP) || defined(APIC_IO)
55 #include <machine/smp.h>
56 #include <machine/apic.h>
57 #endif /* SMP || APIC_IO */
58 #include <machine/globaldata.h>
59 #include <machine/pmap.h>
60 #include <machine/pmap_inval.h>
65 _cpu_invltlb(void *dummy)
71 _cpu_invl1pg(void *data)
79 * Initialize for add or flush
82 pmap_inval_init(pmap_inval_info_t info)
88 * Add a (pmap, va) pair to the invalidation list and protect access
92 pmap_inval_add(pmap_inval_info_t info, pmap_t pmap, vm_offset_t va)
95 if ((info->pir_flags & PIRF_CPUSYNC) == 0) {
96 info->pir_flags |= PIRF_CPUSYNC;
97 info->pir_cpusync.cs_run_func = NULL;
98 info->pir_cpusync.cs_fin1_func = NULL;
99 info->pir_cpusync.cs_fin2_func = NULL;
100 lwkt_cpusync_start(pmap->pm_active, &info->pir_cpusync);
101 } else if (pmap->pm_active & ~info->pir_cpusync.cs_mask) {
102 lwkt_cpusync_add(pmap->pm_active, &info->pir_cpusync);
105 if (pmap->pm_active == 0)
108 if ((info->pir_flags & (PIRF_INVLTLB|PIRF_INVL1PG)) == 0) {
109 if (va == (vm_offset_t)-1) {
110 info->pir_flags |= PIRF_INVLTLB;
112 info->pir_cpusync.cs_fin2_func = _cpu_invltlb;
115 info->pir_flags |= PIRF_INVL1PG;
116 info->pir_cpusync.cs_data = (void *)va;
118 info->pir_cpusync.cs_fin2_func = _cpu_invl1pg;
122 info->pir_flags |= PIRF_INVLTLB;
124 info->pir_cpusync.cs_fin2_func = _cpu_invltlb;
130 * Synchronize changes with target cpus.
133 pmap_inval_flush(pmap_inval_info_t info)
136 if (info->pir_flags & PIRF_CPUSYNC)
137 lwkt_cpusync_finish(&info->pir_cpusync);
139 if (info->pir_flags & PIRF_INVLTLB)
141 else if (info->pir_flags & PIRF_INVL1PG)
142 cpu_invlpg(info->pir_cpusync.cs_data);