2209d9297278ca7b90c1f0bf9d49d6101cc9e982
[dragonfly.git] / sys / dev / drm / i915 / i915_gem_gtt.c
1 /*
2  * Copyright © 2010 Daniel Vetter
3  * Copyright © 2011-2014 Intel Corporation
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22  * IN THE SOFTWARE.
23  *
24  */
25
26 #include <linux/seq_file.h>
27 #include <drm/drmP.h>
28 #include <drm/i915_drm.h>
29 #include "i915_drv.h"
30 #include "i915_vgpu.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33
34 #include <linux/bitmap.h>
35 #include <linux/highmem.h>
36
37 /**
38  * DOC: Global GTT views
39  *
40  * Background and previous state
41  *
42  * Historically objects could exists (be bound) in global GTT space only as
43  * singular instances with a view representing all of the object's backing pages
44  * in a linear fashion. This view will be called a normal view.
45  *
46  * To support multiple views of the same object, where the number of mapped
47  * pages is not equal to the backing store, or where the layout of the pages
48  * is not linear, concept of a GGTT view was added.
49  *
50  * One example of an alternative view is a stereo display driven by a single
51  * image. In this case we would have a framebuffer looking like this
52  * (2x2 pages):
53  *
54  *    12
55  *    34
56  *
57  * Above would represent a normal GGTT view as normally mapped for GPU or CPU
58  * rendering. In contrast, fed to the display engine would be an alternative
59  * view which could look something like this:
60  *
61  *   1212
62  *   3434
63  *
64  * In this example both the size and layout of pages in the alternative view is
65  * different from the normal view.
66  *
67  * Implementation and usage
68  *
69  * GGTT views are implemented using VMAs and are distinguished via enum
70  * i915_ggtt_view_type and struct i915_ggtt_view.
71  *
72  * A new flavour of core GEM functions which work with GGTT bound objects were
73  * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
74  * renaming  in large amounts of code. They take the struct i915_ggtt_view
75  * parameter encapsulating all metadata required to implement a view.
76  *
77  * As a helper for callers which are only interested in the normal view,
78  * globally const i915_ggtt_view_normal singleton instance exists. All old core
79  * GEM API functions, the ones not taking the view parameter, are operating on,
80  * or with the normal GGTT view.
81  *
82  * Code wanting to add or use a new GGTT view needs to:
83  *
84  * 1. Add a new enum with a suitable name.
85  * 2. Extend the metadata in the i915_ggtt_view structure if required.
86  * 3. Add support to i915_get_vma_pages().
87  *
88  * New views are required to build a scatter-gather table from within the
89  * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
90  * exists for the lifetime of an VMA.
91  *
92  * Core API is designed to have copy semantics which means that passed in
93  * struct i915_ggtt_view does not need to be persistent (left around after
94  * calling the core API functions).
95  *
96  */
97
98 static int
99 i915_get_ggtt_vma_pages(struct i915_vma *vma);
100
101 const struct i915_ggtt_view i915_ggtt_view_normal;
102 const struct i915_ggtt_view i915_ggtt_view_rotated = {
103         .type = I915_GGTT_VIEW_ROTATED
104 };
105
106 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
107 {
108         bool has_aliasing_ppgtt;
109         bool has_full_ppgtt;
110
111         has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
112         has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
113
114         if (intel_vgpu_active(dev))
115                 has_full_ppgtt = false; /* emulation is too hard */
116
117         /*
118          * We don't allow disabling PPGTT for gen9+ as it's a requirement for
119          * execlists, the sole mechanism available to submit work.
120          */
121         if (INTEL_INFO(dev)->gen < 9 &&
122             (enable_ppgtt == 0 || !has_aliasing_ppgtt))
123                 return 0;
124
125         if (enable_ppgtt == 1)
126                 return 1;
127
128         if (enable_ppgtt == 2 && has_full_ppgtt)
129                 return 2;
130
131 #ifdef CONFIG_INTEL_IOMMU
132         /* Disable ppgtt on SNB if VT-d is on. */
133         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
134                 DRM_INFO("Disabling PPGTT because VT-d is on\n");
135                 return 0;
136         }
137 #endif
138
139         /* Early VLV doesn't have this */
140         if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
141             dev->pdev->revision < 0xb) {
142                 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
143                 return 0;
144         }
145
146         if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
147                 return 2;
148         else
149                 return has_aliasing_ppgtt ? 1 : 0;
150 }
151
152 static int ppgtt_bind_vma(struct i915_vma *vma,
153                           enum i915_cache_level cache_level,
154                           u32 unused)
155 {
156         u32 pte_flags = 0;
157
158         /* Currently applicable only to VLV */
159         if (vma->obj->gt_ro)
160                 pte_flags |= PTE_READ_ONLY;
161
162         vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
163                                 cache_level, pte_flags);
164
165         return 0;
166 }
167
168 static void ppgtt_unbind_vma(struct i915_vma *vma)
169 {
170         vma->vm->clear_range(vma->vm,
171                              vma->node.start,
172                              vma->obj->base.size,
173                              true);
174 }
175
176 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
177                                   enum i915_cache_level level,
178                                   bool valid)
179 {
180         gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
181         pte |= addr;
182
183         switch (level) {
184         case I915_CACHE_NONE:
185                 pte |= PPAT_UNCACHED_INDEX;
186                 break;
187         case I915_CACHE_WT:
188                 pte |= PPAT_DISPLAY_ELLC_INDEX;
189                 break;
190         default:
191                 pte |= PPAT_CACHED_INDEX;
192                 break;
193         }
194
195         return pte;
196 }
197
198 static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
199                                   const enum i915_cache_level level)
200 {
201         gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
202         pde |= addr;
203         if (level != I915_CACHE_NONE)
204                 pde |= PPAT_CACHED_PDE_INDEX;
205         else
206                 pde |= PPAT_UNCACHED_INDEX;
207         return pde;
208 }
209
210 #define gen8_pdpe_encode gen8_pde_encode
211 #define gen8_pml4e_encode gen8_pde_encode
212
213 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
214                                  enum i915_cache_level level,
215                                  bool valid, u32 unused)
216 {
217         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
218         pte |= GEN6_PTE_ADDR_ENCODE(addr);
219
220         switch (level) {
221         case I915_CACHE_L3_LLC:
222         case I915_CACHE_LLC:
223                 pte |= GEN6_PTE_CACHE_LLC;
224                 break;
225         case I915_CACHE_NONE:
226                 pte |= GEN6_PTE_UNCACHED;
227                 break;
228         default:
229                 MISSING_CASE(level);
230         }
231
232         return pte;
233 }
234
235 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
236                                  enum i915_cache_level level,
237                                  bool valid, u32 unused)
238 {
239         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
240         pte |= GEN6_PTE_ADDR_ENCODE(addr);
241
242         switch (level) {
243         case I915_CACHE_L3_LLC:
244                 pte |= GEN7_PTE_CACHE_L3_LLC;
245                 break;
246         case I915_CACHE_LLC:
247                 pte |= GEN6_PTE_CACHE_LLC;
248                 break;
249         case I915_CACHE_NONE:
250                 pte |= GEN6_PTE_UNCACHED;
251                 break;
252         default:
253                 MISSING_CASE(level);
254         }
255
256         return pte;
257 }
258
259 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
260                                  enum i915_cache_level level,
261                                  bool valid, u32 flags)
262 {
263         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
264         pte |= GEN6_PTE_ADDR_ENCODE(addr);
265
266         if (!(flags & PTE_READ_ONLY))
267                 pte |= BYT_PTE_WRITEABLE;
268
269         if (level != I915_CACHE_NONE)
270                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
271
272         return pte;
273 }
274
275 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
276                                  enum i915_cache_level level,
277                                  bool valid, u32 unused)
278 {
279         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
280         pte |= HSW_PTE_ADDR_ENCODE(addr);
281
282         if (level != I915_CACHE_NONE)
283                 pte |= HSW_WB_LLC_AGE3;
284
285         return pte;
286 }
287
288 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
289                                   enum i915_cache_level level,
290                                   bool valid, u32 unused)
291 {
292         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
293         pte |= HSW_PTE_ADDR_ENCODE(addr);
294
295         switch (level) {
296         case I915_CACHE_NONE:
297                 break;
298         case I915_CACHE_WT:
299                 pte |= HSW_WT_ELLC_LLC_AGE3;
300                 break;
301         default:
302                 pte |= HSW_WB_ELLC_LLC_AGE3;
303                 break;
304         }
305
306         return pte;
307 }
308
309 static int __setup_page_dma(struct drm_device *dev,
310                             struct i915_page_dma *p, gfp_t flags)
311 {
312         struct device *device = dev->pdev->dev;
313
314         p->page = alloc_page(flags);
315         if (!p->page)
316                 return -ENOMEM;
317
318         p->daddr = dma_map_page(device,
319                                 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
320
321         if (dma_mapping_error(device, p->daddr)) {
322                 __free_page(p->page);
323                 return -EINVAL;
324         }
325
326         return 0;
327 }
328
329 static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
330 {
331         return __setup_page_dma(dev, p, GFP_KERNEL);
332 }
333
334 static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
335 {
336         if (WARN_ON(!p->page))
337                 return;
338
339         dma_unmap_page(dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
340         __free_page(p->page);
341         memset(p, 0, sizeof(*p));
342 }
343
344 static void *kmap_page_dma(struct i915_page_dma *p)
345 {
346         return kmap_atomic(p->page);
347 }
348
349 /* We use the flushing unmap only with ppgtt structures:
350  * page directories, page tables and scratch pages.
351  */
352 static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
353 {
354         /* There are only few exceptions for gen >=6. chv and bxt.
355          * And we are not sure about the latter so play safe for now.
356          */
357         if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
358                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
359
360         kunmap_atomic(vaddr);
361 }
362
363 #define kmap_px(px) kmap_page_dma(px_base(px))
364 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
365
366 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
367 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
368 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
369 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
370
371 static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
372                           const uint64_t val)
373 {
374         int i;
375         uint64_t * const vaddr = kmap_page_dma(p);
376
377         for (i = 0; i < 512; i++)
378                 vaddr[i] = val;
379
380         kunmap_page_dma(dev, vaddr);
381 }
382
383 static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
384                              const uint32_t val32)
385 {
386         uint64_t v = val32;
387
388         v = v << 32 | val32;
389
390         fill_page_dma(dev, p, v);
391 }
392
393 static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
394 {
395         struct i915_page_scratch *sp;
396         int ret;
397
398         sp = kzalloc(sizeof(*sp), GFP_KERNEL);
399         if (sp == NULL)
400                 return ERR_PTR(-ENOMEM);
401
402         ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
403         if (ret) {
404                 kfree(sp);
405                 return ERR_PTR(ret);
406         }
407
408         set_pages_uc(px_page(sp), 1);
409
410         return sp;
411 }
412
413 static void free_scratch_page(struct drm_device *dev,
414                               struct i915_page_scratch *sp)
415 {
416         set_pages_wb(px_page(sp), 1);
417
418         cleanup_px(dev, sp);
419         kfree(sp);
420 }
421
422 static struct i915_page_table *alloc_pt(struct drm_device *dev)
423 {
424         struct i915_page_table *pt;
425         const size_t count = INTEL_INFO(dev)->gen >= 8 ?
426                 GEN8_PTES : GEN6_PTES;
427         int ret = -ENOMEM;
428
429         pt = kzalloc(sizeof(*pt), GFP_KERNEL);
430         if (!pt)
431                 return ERR_PTR(-ENOMEM);
432
433         pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
434                                 GFP_KERNEL);
435
436         if (!pt->used_ptes)
437                 goto fail_bitmap;
438
439         ret = setup_px(dev, pt);
440         if (ret)
441                 goto fail_page_m;
442
443         return pt;
444
445 fail_page_m:
446         kfree(pt->used_ptes);
447 fail_bitmap:
448         kfree(pt);
449
450         return ERR_PTR(ret);
451 }
452
453 static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
454 {
455         cleanup_px(dev, pt);
456         kfree(pt->used_ptes);
457         kfree(pt);
458 }
459
460 /**
461  * alloc_pt_range() - Allocate a multiple page tables
462  * @pd:         The page directory which will have at least @count entries
463  *              available to point to the allocated page tables.
464  * @pde:        First page directory entry for which we are allocating.
465  * @count:      Number of pages to allocate.
466  * @dev:        DRM device.
467  *
468  * Allocates multiple page table pages and sets the appropriate entries in the
469  * page table structure within the page directory. Function cleans up after
470  * itself on any failures.
471  *
472  * Return: 0 if allocation succeeded.
473  */
474 static int alloc_pt_range(struct i915_page_directory *pd, uint16_t pde, size_t count,
475                           struct drm_device *dev)
476 {
477         int i, ret;
478
479         /* 512 is the max page tables per page_directory on any platform. */
480         if (WARN_ON(pde + count > I915_PDES))
481                 return -EINVAL;
482
483         for (i = pde; i < pde + count; i++) {
484                 struct i915_page_table *pt = alloc_pt(dev);
485
486                 if (IS_ERR(pt)) {
487                         ret = PTR_ERR(pt);
488                         goto err_out;
489                 }
490                 WARN(pd->page_table[i],
491                      "Leaking page directory entry %d (%p)\n",
492                      i, pd->page_table[i]);
493                 pd->page_table[i] = pt;
494         }
495
496         return 0;
497
498 err_out:
499         while (i-- > pde)
500                 free_pt(dev, pd->page_table[i]);
501         return ret;
502 }
503
504 static void gen8_initialize_pt(struct i915_address_space *vm,
505                                struct i915_page_table *pt)
506 {
507         gen8_pte_t scratch_pte;
508
509         scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
510                                       I915_CACHE_LLC, true);
511
512         fill_px(vm->dev, pt, scratch_pte);
513 }
514
515 static void gen6_initialize_pt(struct i915_address_space *vm,
516                                struct i915_page_table *pt)
517 {
518         gen6_pte_t scratch_pte;
519
520         WARN_ON(px_dma(vm->scratch_page) == 0);
521
522         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
523                                      I915_CACHE_LLC, true, 0);
524
525         fill32_px(vm->dev, pt, scratch_pte);
526 }
527
528 static struct i915_page_directory *alloc_pd(struct drm_device *dev)
529 {
530         struct i915_page_directory *pd;
531         int ret = -ENOMEM;
532
533         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
534         if (!pd)
535                 return ERR_PTR(-ENOMEM);
536
537         pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
538                                 sizeof(*pd->used_pdes), GFP_KERNEL);
539         if (!pd->used_pdes)
540                 goto fail_bitmap;
541
542         ret = setup_px(dev, pd);
543         if (ret)
544                 goto fail_page_m;
545
546         return pd;
547
548 fail_page_m:
549         kfree(pd->used_pdes);
550 fail_bitmap:
551         kfree(pd);
552
553         return ERR_PTR(ret);
554 }
555
556 static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
557 {
558         if (px_page(pd)) {
559                 cleanup_px(dev, pd);
560                 kfree(pd->used_pdes);
561                 kfree(pd);
562         }
563 }
564
565 static void gen8_initialize_pd(struct i915_address_space *vm,
566                                struct i915_page_directory *pd)
567 {
568         gen8_pde_t scratch_pde;
569
570         scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
571
572         fill_px(vm->dev, pd, scratch_pde);
573 }
574
575 static int __pdp_init(struct drm_device *dev,
576                       struct i915_page_directory_pointer *pdp)
577 {
578         size_t pdpes = I915_PDPES_PER_PDP(dev);
579
580         pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
581                                   sizeof(unsigned long),
582                                   GFP_KERNEL);
583         if (!pdp->used_pdpes)
584                 return -ENOMEM;
585
586         pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
587                                       GFP_KERNEL);
588         if (!pdp->page_directory) {
589                 kfree(pdp->used_pdpes);
590                 /* the PDP might be the statically allocated top level. Keep it
591                  * as clean as possible */
592                 pdp->used_pdpes = NULL;
593                 return -ENOMEM;
594         }
595
596         return 0;
597 }
598
599 static void __pdp_fini(struct i915_page_directory_pointer *pdp)
600 {
601         kfree(pdp->used_pdpes);
602         kfree(pdp->page_directory);
603         pdp->page_directory = NULL;
604 }
605
606 static struct
607 i915_page_directory_pointer *alloc_pdp(struct drm_device *dev)
608 {
609         struct i915_page_directory_pointer *pdp;
610         int ret = -ENOMEM;
611
612         WARN_ON(!USES_FULL_48BIT_PPGTT(dev));
613
614         pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
615         if (!pdp)
616                 return ERR_PTR(-ENOMEM);
617
618         ret = __pdp_init(dev, pdp);
619         if (ret)
620                 goto fail_bitmap;
621
622         ret = setup_px(dev, pdp);
623         if (ret)
624                 goto fail_page_m;
625
626         return pdp;
627
628 fail_page_m:
629         __pdp_fini(pdp);
630 fail_bitmap:
631         kfree(pdp);
632
633         return ERR_PTR(ret);
634 }
635
636 static void free_pdp(struct drm_device *dev,
637                      struct i915_page_directory_pointer *pdp)
638 {
639         __pdp_fini(pdp);
640         if (USES_FULL_48BIT_PPGTT(dev)) {
641                 cleanup_px(dev, pdp);
642                 kfree(pdp);
643         }
644 }
645
646 static void gen8_initialize_pdp(struct i915_address_space *vm,
647                                 struct i915_page_directory_pointer *pdp)
648 {
649         gen8_ppgtt_pdpe_t scratch_pdpe;
650
651         scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
652
653         fill_px(vm->dev, pdp, scratch_pdpe);
654 }
655
656 static void gen8_initialize_pml4(struct i915_address_space *vm,
657                                  struct i915_pml4 *pml4)
658 {
659         gen8_ppgtt_pml4e_t scratch_pml4e;
660
661         scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
662                                           I915_CACHE_LLC);
663
664         fill_px(vm->dev, pml4, scratch_pml4e);
665 }
666
667 static void
668 gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt,
669                           struct i915_page_directory_pointer *pdp,
670                           struct i915_page_directory *pd,
671                           int index)
672 {
673         gen8_ppgtt_pdpe_t *page_directorypo;
674
675         if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
676                 return;
677
678         page_directorypo = kmap_px(pdp);
679         page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
680         kunmap_px(ppgtt, page_directorypo);
681 }
682
683 static void
684 gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt,
685                                   struct i915_pml4 *pml4,
686                                   struct i915_page_directory_pointer *pdp,
687                                   int index)
688 {
689         gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4);
690
691         WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev));
692         pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
693         kunmap_px(ppgtt, pagemap);
694 }
695
696 /* Broadwell Page Directory Pointer Descriptors */
697 static int gen8_write_pdp(struct drm_i915_gem_request *req,
698                           unsigned entry,
699                           dma_addr_t addr)
700 {
701         struct intel_engine_cs *ring = req->ring;
702         int ret;
703
704         BUG_ON(entry >= 4);
705
706         ret = intel_ring_begin(req, 6);
707         if (ret)
708                 return ret;
709
710         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
711         intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
712         intel_ring_emit(ring, upper_32_bits(addr));
713         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
714         intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
715         intel_ring_emit(ring, lower_32_bits(addr));
716         intel_ring_advance(ring);
717
718         return 0;
719 }
720
721 static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt,
722                                  struct drm_i915_gem_request *req)
723 {
724         int i, ret;
725
726         for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
727                 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
728
729                 ret = gen8_write_pdp(req, i, pd_daddr);
730                 if (ret)
731                         return ret;
732         }
733
734         return 0;
735 }
736
737 static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
738                               struct drm_i915_gem_request *req)
739 {
740         return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
741 }
742
743 static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
744                                        struct i915_page_directory_pointer *pdp,
745                                        uint64_t start,
746                                        uint64_t length,
747                                        gen8_pte_t scratch_pte)
748 {
749         struct i915_hw_ppgtt *ppgtt =
750                 container_of(vm, struct i915_hw_ppgtt, base);
751         gen8_pte_t *pt_vaddr;
752         unsigned pdpe = gen8_pdpe_index(start);
753         unsigned pde = gen8_pde_index(start);
754         unsigned pte = gen8_pte_index(start);
755         unsigned num_entries = length >> PAGE_SHIFT;
756         unsigned last_pte, i;
757
758         if (WARN_ON(!pdp))
759                 return;
760
761         while (num_entries) {
762                 struct i915_page_directory *pd;
763                 struct i915_page_table *pt;
764
765                 if (WARN_ON(!pdp->page_directory[pdpe]))
766                         break;
767
768                 pd = pdp->page_directory[pdpe];
769
770                 if (WARN_ON(!pd->page_table[pde]))
771                         break;
772
773                 pt = pd->page_table[pde];
774
775                 if (WARN_ON(!px_page(pt)))
776                         break;
777
778                 last_pte = pte + num_entries;
779                 if (last_pte > GEN8_PTES)
780                         last_pte = GEN8_PTES;
781
782                 pt_vaddr = kmap_px(pt);
783
784                 for (i = pte; i < last_pte; i++) {
785                         pt_vaddr[i] = scratch_pte;
786                         num_entries--;
787                 }
788
789                 kunmap_px(ppgtt, pt_vaddr);     /* XXX dillon, out of order
790                                                  * patch from linux
791                                                  * 44a71024 12-Apr-2016
792                                                  */
793
794                 pte = 0;
795                 if (++pde == I915_PDES) {
796                         if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
797                                 break;
798                         pde = 0;
799                 }
800         }
801 }
802
803 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
804                                    uint64_t start,
805                                    uint64_t length,
806                                    bool use_scratch)
807 {
808         struct i915_hw_ppgtt *ppgtt =
809                 container_of(vm, struct i915_hw_ppgtt, base);
810         gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
811                                                  I915_CACHE_LLC, use_scratch);
812
813         if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
814                 gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length,
815                                            scratch_pte);
816         } else {
817                 uint64_t templ4, pml4e;
818                 struct i915_page_directory_pointer *pdp;
819
820                 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
821                         gen8_ppgtt_clear_pte_range(vm, pdp, start, length,
822                                                    scratch_pte);
823                 }
824         }
825 }
826
827 static void
828 gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
829                               struct i915_page_directory_pointer *pdp,
830                               struct sg_page_iter *sg_iter,
831                               uint64_t start,
832                               enum i915_cache_level cache_level)
833 {
834         struct i915_hw_ppgtt *ppgtt =
835                 container_of(vm, struct i915_hw_ppgtt, base);
836         gen8_pte_t *pt_vaddr;
837         unsigned pdpe = gen8_pdpe_index(start);
838         unsigned pde = gen8_pde_index(start);
839         unsigned pte = gen8_pte_index(start);
840
841         pt_vaddr = NULL;
842
843         while (__sg_page_iter_next(sg_iter)) {
844                 if (pt_vaddr == NULL) {
845                         struct i915_page_directory *pd = pdp->page_directory[pdpe];
846                         while (pd == NULL) {
847                                 kprintf("PD NULL pdp %p pdpe %u\n", pdp, pdpe);
848                                 tsleep(&pd, 0, "froze", hz);
849                         }
850                         struct i915_page_table *pt = pd->page_table[pde];
851                         while (pt == NULL) {
852                                 kprintf("PT NULL pdp %p pdpe %u\n", pd, pde);
853                                 tsleep(&pd, 0, "froze", hz);
854                         }
855
856                         pt_vaddr = kmap_px(pt);
857                 }
858
859                 pt_vaddr[pte] =
860                         gen8_pte_encode(sg_page_iter_dma_address(sg_iter),
861                                         cache_level, true);
862                 if (++pte == GEN8_PTES) {
863                         kunmap_px(ppgtt, pt_vaddr);
864                         pt_vaddr = NULL;
865                         if (++pde == I915_PDES) {
866                                 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
867                                         break;
868                                 pde = 0;
869                         }
870                         pte = 0;
871                 }
872         }
873
874         if (pt_vaddr)
875                 kunmap_px(ppgtt, pt_vaddr);
876 }
877
878 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
879                                       struct sg_table *pages,
880                                       uint64_t start,
881                                       enum i915_cache_level cache_level,
882                                       u32 unused)
883 {
884         struct i915_hw_ppgtt *ppgtt =
885                 container_of(vm, struct i915_hw_ppgtt, base);
886         struct sg_page_iter sg_iter;
887
888         __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
889
890         if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
891                 gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start,
892                                               cache_level);
893         } else {
894                 struct i915_page_directory_pointer *pdp;
895                 uint64_t templ4, pml4e;
896                 uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT;
897
898                 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
899                         gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter,
900                                                       start, cache_level);
901                 }
902         }
903 }
904
905 static void gen8_free_page_tables(struct drm_device *dev,
906                                   struct i915_page_directory *pd)
907 {
908         int i;
909
910         if (!px_page(pd))
911                 return;
912
913         for_each_set_bit(i, pd->used_pdes, I915_PDES) {
914                 if (WARN_ON(!pd->page_table[i]))
915                         continue;
916
917                 free_pt(dev, pd->page_table[i]);
918                 pd->page_table[i] = NULL;
919         }
920 }
921
922 static int gen8_init_scratch(struct i915_address_space *vm)
923 {
924         struct drm_device *dev = vm->dev;
925
926         vm->scratch_page = alloc_scratch_page(dev);
927         if (IS_ERR(vm->scratch_page))
928                 return PTR_ERR(vm->scratch_page);
929
930         vm->scratch_pt = alloc_pt(dev);
931         if (IS_ERR(vm->scratch_pt)) {
932                 free_scratch_page(dev, vm->scratch_page);
933                 return PTR_ERR(vm->scratch_pt);
934         }
935
936         vm->scratch_pd = alloc_pd(dev);
937         if (IS_ERR(vm->scratch_pd)) {
938                 free_pt(dev, vm->scratch_pt);
939                 free_scratch_page(dev, vm->scratch_page);
940                 return PTR_ERR(vm->scratch_pd);
941         }
942
943         if (USES_FULL_48BIT_PPGTT(dev)) {
944                 vm->scratch_pdp = alloc_pdp(dev);
945                 if (IS_ERR(vm->scratch_pdp)) {
946                         free_pd(dev, vm->scratch_pd);
947                         free_pt(dev, vm->scratch_pt);
948                         free_scratch_page(dev, vm->scratch_page);
949                         return PTR_ERR(vm->scratch_pdp);
950                 }
951         }
952
953         gen8_initialize_pt(vm, vm->scratch_pt);
954         gen8_initialize_pd(vm, vm->scratch_pd);
955         if (USES_FULL_48BIT_PPGTT(dev))
956                 gen8_initialize_pdp(vm, vm->scratch_pdp);
957
958         return 0;
959 }
960
961 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
962 {
963         enum vgt_g2v_type msg;
964         struct drm_device *dev = ppgtt->base.dev;
965         struct drm_i915_private *dev_priv = dev->dev_private;
966         unsigned int offset = vgtif_reg(pdp0_lo);
967         int i;
968
969         if (USES_FULL_48BIT_PPGTT(dev)) {
970                 u64 daddr = px_dma(&ppgtt->pml4);
971
972                 I915_WRITE(offset, lower_32_bits(daddr));
973                 I915_WRITE(offset + 4, upper_32_bits(daddr));
974
975                 msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
976                                 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
977         } else {
978                 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
979                         u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
980
981                         I915_WRITE(offset, lower_32_bits(daddr));
982                         I915_WRITE(offset + 4, upper_32_bits(daddr));
983
984                         offset += 8;
985                 }
986
987                 msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
988                                 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
989         }
990
991         I915_WRITE(vgtif_reg(g2v_notify), msg);
992
993         return 0;
994 }
995
996 static void gen8_free_scratch(struct i915_address_space *vm)
997 {
998         struct drm_device *dev = vm->dev;
999
1000         if (USES_FULL_48BIT_PPGTT(dev))
1001                 free_pdp(dev, vm->scratch_pdp);
1002         free_pd(dev, vm->scratch_pd);
1003         free_pt(dev, vm->scratch_pt);
1004         free_scratch_page(dev, vm->scratch_page);
1005 }
1006
1007 static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev,
1008                                     struct i915_page_directory_pointer *pdp)
1009 {
1010         int i;
1011
1012         for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
1013                 if (WARN_ON(!pdp->page_directory[i]))
1014                         continue;
1015
1016                 gen8_free_page_tables(dev, pdp->page_directory[i]);
1017                 free_pd(dev, pdp->page_directory[i]);
1018         }
1019
1020         free_pdp(dev, pdp);
1021 }
1022
1023 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
1024 {
1025         int i;
1026
1027         for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) {
1028                 if (WARN_ON(!ppgtt->pml4.pdps[i]))
1029                         continue;
1030
1031                 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]);
1032         }
1033
1034         cleanup_px(ppgtt->base.dev, &ppgtt->pml4);
1035 }
1036
1037 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
1038 {
1039         struct i915_hw_ppgtt *ppgtt =
1040                 container_of(vm, struct i915_hw_ppgtt, base);
1041
1042         if (intel_vgpu_active(vm->dev))
1043                 gen8_ppgtt_notify_vgt(ppgtt, false);
1044
1045         if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
1046                 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp);
1047         else
1048                 gen8_ppgtt_cleanup_4lvl(ppgtt);
1049
1050         gen8_free_scratch(vm);
1051 }
1052
1053 /**
1054  * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
1055  * @vm: Master vm structure.
1056  * @pd: Page directory for this address range.
1057  * @start:      Starting virtual address to begin allocations.
1058  * @length:     Size of the allocations.
1059  * @new_pts:    Bitmap set by function with new allocations. Likely used by the
1060  *              caller to free on error.
1061  *
1062  * Allocate the required number of page tables. Extremely similar to
1063  * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1064  * the page directory boundary (instead of the page directory pointer). That
1065  * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1066  * possible, and likely that the caller will need to use multiple calls of this
1067  * function to achieve the appropriate allocation.
1068  *
1069  * Return: 0 if success; negative error code otherwise.
1070  */
1071 static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
1072                                      struct i915_page_directory *pd,
1073                                      uint64_t start,
1074                                      uint64_t length,
1075                                      unsigned long *new_pts)
1076 {
1077         struct drm_device *dev = vm->dev;
1078         struct i915_page_table *pt;
1079         uint64_t temp;
1080         uint32_t pde;
1081
1082         gen8_for_each_pde(pt, pd, start, length, temp, pde) {
1083                 /* Don't reallocate page tables */
1084                 if (test_bit(pde, pd->used_pdes)) {
1085                         /* Scratch is never allocated this way */
1086                         WARN_ON(pt == vm->scratch_pt);
1087                         continue;
1088                 }
1089
1090                 pt = alloc_pt(dev);
1091                 if (IS_ERR(pt))
1092                         goto unwind_out;
1093
1094                 gen8_initialize_pt(vm, pt);
1095                 pd->page_table[pde] = pt;
1096                 __set_bit(pde, new_pts);
1097                 trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT);
1098         }
1099
1100         return 0;
1101
1102 unwind_out:
1103         for_each_set_bit(pde, new_pts, I915_PDES)
1104                 free_pt(dev, pd->page_table[pde]);
1105
1106         return -ENOMEM;
1107 }
1108
1109 /**
1110  * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
1111  * @vm: Master vm structure.
1112  * @pdp:        Page directory pointer for this address range.
1113  * @start:      Starting virtual address to begin allocations.
1114  * @length:     Size of the allocations.
1115  * @new_pds:    Bitmap set by function with new allocations. Likely used by the
1116  *              caller to free on error.
1117  *
1118  * Allocate the required number of page directories starting at the pde index of
1119  * @start, and ending at the pde index @start + @length. This function will skip
1120  * over already allocated page directories within the range, and only allocate
1121  * new ones, setting the appropriate pointer within the pdp as well as the
1122  * correct position in the bitmap @new_pds.
1123  *
1124  * The function will only allocate the pages within the range for a give page
1125  * directory pointer. In other words, if @start + @length straddles a virtually
1126  * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1127  * required by the caller, This is not currently possible, and the BUG in the
1128  * code will prevent it.
1129  *
1130  * Return: 0 if success; negative error code otherwise.
1131  */
1132 static int
1133 gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
1134                                   struct i915_page_directory_pointer *pdp,
1135                                   uint64_t start,
1136                                   uint64_t length,
1137                                   unsigned long *new_pds)
1138 {
1139         struct drm_device *dev = vm->dev;
1140         struct i915_page_directory *pd;
1141         uint64_t temp;
1142         uint32_t pdpe;
1143         uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1144
1145         WARN_ON(!bitmap_empty(new_pds, pdpes));
1146
1147         gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1148                 if (test_bit(pdpe, pdp->used_pdpes))
1149                         continue;
1150
1151                 pd = alloc_pd(dev);
1152                 if (IS_ERR(pd))
1153                         goto unwind_out;
1154
1155                 gen8_initialize_pd(vm, pd);
1156                 pdp->page_directory[pdpe] = pd;
1157                 __set_bit(pdpe, new_pds);
1158                 trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT);
1159         }
1160
1161         return 0;
1162
1163 unwind_out:
1164         for_each_set_bit(pdpe, new_pds, pdpes)
1165                 free_pd(dev, pdp->page_directory[pdpe]);
1166
1167         return -ENOMEM;
1168 }
1169
1170 /**
1171  * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1172  * @vm: Master vm structure.
1173  * @pml4:       Page map level 4 for this address range.
1174  * @start:      Starting virtual address to begin allocations.
1175  * @length:     Size of the allocations.
1176  * @new_pdps:   Bitmap set by function with new allocations. Likely used by the
1177  *              caller to free on error.
1178  *
1179  * Allocate the required number of page directory pointers. Extremely similar to
1180  * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1181  * The main difference is here we are limited by the pml4 boundary (instead of
1182  * the page directory pointer).
1183  *
1184  * Return: 0 if success; negative error code otherwise.
1185  */
1186 static int
1187 gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm,
1188                                   struct i915_pml4 *pml4,
1189                                   uint64_t start,
1190                                   uint64_t length,
1191                                   unsigned long *new_pdps)
1192 {
1193         struct drm_device *dev = vm->dev;
1194         struct i915_page_directory_pointer *pdp;
1195         uint64_t temp;
1196         uint32_t pml4e;
1197
1198         WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4));
1199
1200         gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) {
1201                 if (!test_bit(pml4e, pml4->used_pml4es)) {
1202                         pdp = alloc_pdp(dev);
1203                         if (IS_ERR(pdp))
1204                                 goto unwind_out;
1205
1206                         gen8_initialize_pdp(vm, pdp);
1207                         pml4->pdps[pml4e] = pdp;
1208                         __set_bit(pml4e, new_pdps);
1209                         trace_i915_page_directory_pointer_entry_alloc(vm,
1210                                                                       pml4e,
1211                                                                       start,
1212                                                                       GEN8_PML4E_SHIFT);
1213                 }
1214         }
1215
1216         return 0;
1217
1218 unwind_out:
1219         for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1220                 free_pdp(dev, pml4->pdps[pml4e]);
1221
1222         return -ENOMEM;
1223 }
1224
1225 static void
1226 free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts)
1227 {
1228         kfree(new_pts);
1229         kfree(new_pds);
1230 }
1231
1232 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1233  * of these are based on the number of PDPEs in the system.
1234  */
1235 static
1236 int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
1237                                          unsigned long **new_pts,
1238                                          uint32_t pdpes)
1239 {
1240         unsigned long *pds;
1241         unsigned long *pts;
1242
1243         pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY);
1244         if (!pds)
1245                 return -ENOMEM;
1246
1247         pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long),
1248                       GFP_TEMPORARY);
1249         if (!pts)
1250                 goto err_out;
1251
1252         *new_pds = pds;
1253         *new_pts = pts;
1254
1255         return 0;
1256
1257 err_out:
1258         free_gen8_temp_bitmaps(pds, pts);
1259         return -ENOMEM;
1260 }
1261
1262 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1263  * the page table structures, we mark them dirty so that
1264  * context switching/execlist queuing code takes extra steps
1265  * to ensure that tlbs are flushed.
1266  */
1267 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
1268 {
1269         ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
1270 }
1271
1272 static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm,
1273                                     struct i915_page_directory_pointer *pdp,
1274                                     uint64_t start,
1275                                     uint64_t length)
1276 {
1277         struct i915_hw_ppgtt *ppgtt =
1278                 container_of(vm, struct i915_hw_ppgtt, base);
1279         unsigned long *new_page_dirs, *new_page_tables;
1280         struct drm_device *dev = vm->dev;
1281         struct i915_page_directory *pd;
1282         const uint64_t orig_start = start;
1283         const uint64_t orig_length = length;
1284         uint64_t temp;
1285         uint32_t pdpe;
1286         uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1287         int ret;
1288
1289         /* Wrap is never okay since we can only represent 48b, and we don't
1290          * actually use the other side of the canonical address space.
1291          */
1292         if (WARN_ON(start + length < start))
1293                 return -ENODEV;
1294
1295         if (WARN_ON(start + length > vm->total))
1296                 return -ENODEV;
1297
1298         ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1299         if (ret)
1300                 return ret;
1301
1302         /* Do the allocations first so we can easily bail out */
1303         ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
1304                                                 new_page_dirs);
1305         if (ret) {
1306                 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1307                 return ret;
1308         }
1309
1310         /* For every page directory referenced, allocate page tables */
1311         gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1312                 ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
1313                                                 new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES));
1314                 if (ret)
1315                         goto err_out;
1316         }
1317
1318         start = orig_start;
1319         length = orig_length;
1320
1321         /* Allocations have completed successfully, so set the bitmaps, and do
1322          * the mappings. */
1323         gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1324                 gen8_pde_t *const page_directory = kmap_px(pd);
1325                 struct i915_page_table *pt;
1326                 uint64_t pd_len = length;
1327                 uint64_t pd_start = start;
1328                 uint32_t pde;
1329
1330                 /* Every pd should be allocated, we just did that above. */
1331                 WARN_ON(!pd);
1332
1333                 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
1334                         /* Same reasoning as pd */
1335                         WARN_ON(!pt);
1336                         if (pt == NULL)         /* XXX dillon hack */
1337                                 continue;       /* XXX dillon hack */
1338                         WARN_ON(!pd_len);
1339                         WARN_ON(!gen8_pte_count(pd_start, pd_len));
1340
1341                         /* Set our used ptes within the page table */
1342                         bitmap_set(pt->used_ptes,
1343                                    gen8_pte_index(pd_start),
1344                                    gen8_pte_count(pd_start, pd_len));
1345
1346                         /* Our pde is now pointing to the pagetable, pt */
1347                         __set_bit(pde, pd->used_pdes);
1348
1349                         /* Map the PDE to the page table */
1350                         page_directory[pde] = gen8_pde_encode(px_dma(pt),
1351                                                               I915_CACHE_LLC);
1352                         trace_i915_page_table_entry_map(&ppgtt->base, pde, pt,
1353                                                         gen8_pte_index(start),
1354                                                         gen8_pte_count(start, length),
1355                                                         GEN8_PTES);
1356
1357                         /* NB: We haven't yet mapped ptes to pages. At this
1358                          * point we're still relying on insert_entries() */
1359                 }
1360
1361                 kunmap_px(ppgtt, page_directory);
1362                 __set_bit(pdpe, pdp->used_pdpes);
1363                 gen8_setup_page_directory(ppgtt, pdp, pd, pdpe);
1364         }
1365
1366         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1367         mark_tlbs_dirty(ppgtt);
1368         return 0;
1369
1370 err_out:
1371         while (pdpe--) {
1372                 for_each_set_bit(temp, new_page_tables + pdpe *
1373                                 BITS_TO_LONGS(I915_PDES), I915_PDES)
1374                         free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
1375         }
1376
1377         for_each_set_bit(pdpe, new_page_dirs, pdpes)
1378                 free_pd(dev, pdp->page_directory[pdpe]);
1379
1380         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1381         mark_tlbs_dirty(ppgtt);
1382         return ret;
1383 }
1384
1385 static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm,
1386                                     struct i915_pml4 *pml4,
1387                                     uint64_t start,
1388                                     uint64_t length)
1389 {
1390         DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4);
1391         struct i915_hw_ppgtt *ppgtt =
1392                         container_of(vm, struct i915_hw_ppgtt, base);
1393         struct i915_page_directory_pointer *pdp;
1394         uint64_t temp, pml4e;
1395         int ret = 0;
1396
1397         /* Do the pml4 allocations first, so we don't need to track the newly
1398          * allocated tables below the pdp */
1399         bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4);
1400
1401         /* The pagedirectory and pagetable allocations are done in the shared 3
1402          * and 4 level code. Just allocate the pdps.
1403          */
1404         ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length,
1405                                                 new_pdps);
1406         if (ret)
1407                 return ret;
1408
1409         WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2,
1410              "The allocation has spanned more than 512GB. "
1411              "It is highly likely this is incorrect.");
1412
1413         gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) {
1414                 WARN_ON(!pdp);
1415
1416                 ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length);
1417                 if (ret)
1418                         goto err_out;
1419
1420                 gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e);
1421         }
1422
1423         bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es,
1424                   GEN8_PML4ES_PER_PML4);
1425
1426         return 0;
1427
1428 err_out:
1429         for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1430                 gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]);
1431
1432         return ret;
1433 }
1434
1435 static int gen8_alloc_va_range(struct i915_address_space *vm,
1436                                uint64_t start, uint64_t length)
1437 {
1438         struct i915_hw_ppgtt *ppgtt =
1439                 container_of(vm, struct i915_hw_ppgtt, base);
1440
1441         if (USES_FULL_48BIT_PPGTT(vm->dev))
1442                 return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length);
1443         else
1444                 return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length);
1445 }
1446
1447 static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp,
1448                           uint64_t start, uint64_t length,
1449                           gen8_pte_t scratch_pte,
1450                           struct seq_file *m)
1451 {
1452         struct i915_page_directory *pd;
1453         uint64_t temp;
1454         uint32_t pdpe;
1455
1456         gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1457                 struct i915_page_table *pt;
1458                 uint64_t pd_len = length;
1459                 uint64_t pd_start = start;
1460                 uint32_t pde;
1461
1462                 if (!test_bit(pdpe, pdp->used_pdpes))
1463                         continue;
1464
1465                 seq_printf(m, "\tPDPE #%d\n", pdpe);
1466                 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
1467                         uint32_t  pte;
1468                         gen8_pte_t *pt_vaddr;
1469
1470                         if (!test_bit(pde, pd->used_pdes))
1471                                 continue;
1472
1473                         pt_vaddr = kmap_px(pt);
1474                         for (pte = 0; pte < GEN8_PTES; pte += 4) {
1475                                 uint64_t va =
1476                                         (pdpe << GEN8_PDPE_SHIFT) |
1477                                         (pde << GEN8_PDE_SHIFT) |
1478                                         (pte << GEN8_PTE_SHIFT);
1479                                 int i;
1480                                 bool found = false;
1481
1482                                 for (i = 0; i < 4; i++)
1483                                         if (pt_vaddr[pte + i] != scratch_pte)
1484                                                 found = true;
1485                                 if (!found)
1486                                         continue;
1487
1488                                 seq_printf(m, "\t\t0x%lx [%03d,%03d,%04d]: =", va, pdpe, pde, pte);
1489                                 for (i = 0; i < 4; i++) {
1490                                         if (pt_vaddr[pte + i] != scratch_pte)
1491                                                 seq_printf(m, " %lx", pt_vaddr[pte + i]);
1492                                         else
1493                                                 seq_puts(m, "  SCRATCH ");
1494                                 }
1495                                 seq_puts(m, "\n");
1496                         }
1497                         /* don't use kunmap_px, it could trigger
1498                          * an unnecessary flush.
1499                          */
1500                         kunmap_atomic(pt_vaddr);
1501                 }
1502         }
1503 }
1504
1505 static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1506 {
1507         struct i915_address_space *vm = &ppgtt->base;
1508         uint64_t start = ppgtt->base.start;
1509         uint64_t length = ppgtt->base.total;
1510         gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
1511                                                  I915_CACHE_LLC, true);
1512
1513         if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
1514                 gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m);
1515         } else {
1516                 uint64_t templ4, pml4e;
1517                 struct i915_pml4 *pml4 = &ppgtt->pml4;
1518                 struct i915_page_directory_pointer *pdp;
1519
1520                 gen8_for_each_pml4e(pdp, pml4, start, length, templ4, pml4e) {
1521                         if (!test_bit(pml4e, pml4->used_pml4es))
1522                                 continue;
1523
1524                         seq_printf(m, "    PML4E #%lu\n", pml4e);
1525                         gen8_dump_pdp(pdp, start, length, scratch_pte, m);
1526                 }
1527         }
1528 }
1529
1530 static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt)
1531 {
1532         unsigned long *new_page_dirs, *new_page_tables;
1533         uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1534         int ret;
1535
1536         /* We allocate temp bitmap for page tables for no gain
1537          * but as this is for init only, lets keep the things simple
1538          */
1539         ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1540         if (ret)
1541                 return ret;
1542
1543         /* Allocate for all pdps regardless of how the ppgtt
1544          * was defined.
1545          */
1546         ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp,
1547                                                 0, 1ULL << 32,
1548                                                 new_page_dirs);
1549         if (!ret)
1550                 *ppgtt->pdp.used_pdpes = *new_page_dirs;
1551
1552         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1553
1554         return ret;
1555 }
1556
1557 /*
1558  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1559  * with a net effect resembling a 2-level page table in normal x86 terms. Each
1560  * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1561  * space.
1562  *
1563  */
1564 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1565 {
1566         int ret;
1567
1568         ret = gen8_init_scratch(&ppgtt->base);
1569         if (ret)
1570                 return ret;
1571
1572         ppgtt->base.start = 0;
1573         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
1574         ppgtt->base.allocate_va_range = gen8_alloc_va_range;
1575         ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
1576         ppgtt->base.clear_range = gen8_ppgtt_clear_range;
1577         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1578         ppgtt->base.bind_vma = ppgtt_bind_vma;
1579         ppgtt->debug_dump = gen8_dump_ppgtt;
1580
1581         if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
1582                 ret = setup_px(ppgtt->base.dev, &ppgtt->pml4);
1583                 if (ret)
1584                         goto free_scratch;
1585
1586                 gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4);
1587
1588                 ppgtt->base.total = 1ULL << 48;
1589                 ppgtt->switch_mm = gen8_48b_mm_switch;
1590         } else {
1591                 ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp);
1592                 if (ret)
1593                         goto free_scratch;
1594
1595 #define CONFIG_X86_32   0
1596                 ppgtt->base.total = 1ULL << 32;
1597                 ppgtt->switch_mm = gen8_legacy_mm_switch;
1598                 trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base,
1599                                                               0, 0,
1600                                                               GEN8_PML4E_SHIFT);
1601
1602                 if (intel_vgpu_active(ppgtt->base.dev)) {
1603                         ret = gen8_preallocate_top_level_pdps(ppgtt);
1604                         if (ret)
1605                                 goto free_scratch;
1606                 }
1607         }
1608
1609         if (intel_vgpu_active(ppgtt->base.dev))
1610                 gen8_ppgtt_notify_vgt(ppgtt, true);
1611
1612         return 0;
1613
1614 free_scratch:
1615         gen8_free_scratch(&ppgtt->base);
1616         return ret;
1617 }
1618
1619 static int gen8_aliasing_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1620 {
1621         struct drm_device *dev = ppgtt->base.dev;
1622         struct drm_i915_private *dev_priv = dev->dev_private;
1623         uint64_t start = 0, size = dev_priv->gtt.base.total;
1624         int ret;
1625
1626         ret = gen8_ppgtt_init(ppgtt);
1627         if (ret)
1628                 return ret;
1629
1630         /* Aliasing PPGTT has to always work and be mapped because of the way we
1631          * use RESTORE_INHIBIT in the context switch. This will be fixed
1632          * eventually. */
1633         ret = gen8_alloc_va_range(&ppgtt->base, start, size);
1634         if (ret) {
1635                 free_pd(ppgtt->base.dev, ppgtt->base.scratch_pd);
1636                 free_pt(ppgtt->base.dev, ppgtt->base.scratch_pt);
1637                 return ret;
1638         }
1639
1640         ppgtt->base.allocate_va_range = NULL;
1641         ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
1642
1643         return 0;
1644 }
1645
1646 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1647 {
1648         struct i915_address_space *vm = &ppgtt->base;
1649         struct i915_page_table *unused;
1650         gen6_pte_t scratch_pte;
1651         uint32_t pd_entry;
1652         uint32_t  pte, pde, temp;
1653         uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
1654
1655         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1656                                      I915_CACHE_LLC, true, 0);
1657
1658         gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
1659                 u32 expected;
1660                 gen6_pte_t *pt_vaddr;
1661                 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
1662                 pd_entry = readl(ppgtt->pd_addr + pde);
1663                 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1664
1665                 if (pd_entry != expected)
1666                         seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1667                                    pde,
1668                                    pd_entry,
1669                                    expected);
1670                 seq_printf(m, "\tPDE: %x\n", pd_entry);
1671
1672                 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1673
1674                 for (pte = 0; pte < GEN6_PTES; pte+=4) {
1675                         unsigned long va =
1676                                 (pde * PAGE_SIZE * GEN6_PTES) +
1677                                 (pte * PAGE_SIZE);
1678                         int i;
1679                         bool found = false;
1680                         for (i = 0; i < 4; i++)
1681                                 if (pt_vaddr[pte + i] != scratch_pte)
1682                                         found = true;
1683                         if (!found)
1684                                 continue;
1685
1686                         seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1687                         for (i = 0; i < 4; i++) {
1688                                 if (pt_vaddr[pte + i] != scratch_pte)
1689                                         seq_printf(m, " %08x", pt_vaddr[pte + i]);
1690                                 else
1691                                         seq_puts(m, "  SCRATCH ");
1692                         }
1693                         seq_puts(m, "\n");
1694                 }
1695                 kunmap_px(ppgtt, pt_vaddr);
1696         }
1697 }
1698
1699 /* Write pde (index) from the page directory @pd to the page table @pt */
1700 static void gen6_write_pde(struct i915_page_directory *pd,
1701                             const int pde, struct i915_page_table *pt)
1702 {
1703         /* Caller needs to make sure the write completes if necessary */
1704         struct i915_hw_ppgtt *ppgtt =
1705                 container_of(pd, struct i915_hw_ppgtt, pd);
1706         u32 pd_entry;
1707
1708         pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
1709         pd_entry |= GEN6_PDE_VALID;
1710
1711         writel(pd_entry, ppgtt->pd_addr + pde);
1712 }
1713
1714 /* Write all the page tables found in the ppgtt structure to incrementing page
1715  * directories. */
1716 static void gen6_write_page_range(struct drm_i915_private *dev_priv,
1717                                   struct i915_page_directory *pd,
1718                                   uint32_t start, uint32_t length)
1719 {
1720         struct i915_page_table *pt;
1721         uint32_t pde, temp;
1722
1723         gen6_for_each_pde(pt, pd, start, length, temp, pde)
1724                 gen6_write_pde(pd, pde, pt);
1725
1726         /* Make sure write is complete before other code can use this page
1727          * table. Also require for WC mapped PTEs */
1728         readl(dev_priv->gtt.gsm);
1729 }
1730
1731 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
1732 {
1733         BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
1734
1735         return (ppgtt->pd.base.ggtt_offset / 64) << 16;
1736 }
1737
1738 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
1739                          struct drm_i915_gem_request *req)
1740 {
1741         struct intel_engine_cs *ring = req->ring;
1742         int ret;
1743
1744         /* NB: TLBs must be flushed and invalidated before a switch */
1745         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1746         if (ret)
1747                 return ret;
1748
1749         ret = intel_ring_begin(req, 6);
1750         if (ret)
1751                 return ret;
1752
1753         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1754         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1755         intel_ring_emit(ring, PP_DIR_DCLV_2G);
1756         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1757         intel_ring_emit(ring, get_pd_offset(ppgtt));
1758         intel_ring_emit(ring, MI_NOOP);
1759         intel_ring_advance(ring);
1760
1761         return 0;
1762 }
1763
1764 static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
1765                           struct drm_i915_gem_request *req)
1766 {
1767         struct intel_engine_cs *ring = req->ring;
1768         struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1769
1770         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1771         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1772         return 0;
1773 }
1774
1775 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
1776                           struct drm_i915_gem_request *req)
1777 {
1778         struct intel_engine_cs *ring = req->ring;
1779         int ret;
1780
1781         /* NB: TLBs must be flushed and invalidated before a switch */
1782         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1783         if (ret)
1784                 return ret;
1785
1786         ret = intel_ring_begin(req, 6);
1787         if (ret)
1788                 return ret;
1789
1790         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1791         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1792         intel_ring_emit(ring, PP_DIR_DCLV_2G);
1793         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1794         intel_ring_emit(ring, get_pd_offset(ppgtt));
1795         intel_ring_emit(ring, MI_NOOP);
1796         intel_ring_advance(ring);
1797
1798         /* XXX: RCS is the only one to auto invalidate the TLBs? */
1799         if (ring->id != RCS) {
1800                 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1801                 if (ret)
1802                         return ret;
1803         }
1804
1805         return 0;
1806 }
1807
1808 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
1809                           struct drm_i915_gem_request *req)
1810 {
1811         struct intel_engine_cs *ring = req->ring;
1812         struct drm_device *dev = ppgtt->base.dev;
1813         struct drm_i915_private *dev_priv = dev->dev_private;
1814
1815
1816         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1817         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1818
1819         POSTING_READ(RING_PP_DIR_DCLV(ring));
1820
1821         return 0;
1822 }
1823
1824 static void gen8_ppgtt_enable(struct drm_device *dev)
1825 {
1826         struct drm_i915_private *dev_priv = dev->dev_private;
1827         struct intel_engine_cs *ring;
1828         int j;
1829
1830         for_each_ring(ring, dev_priv, j) {
1831                 u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0;
1832                 I915_WRITE(RING_MODE_GEN7(ring),
1833                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
1834         }
1835 }
1836
1837 static void gen7_ppgtt_enable(struct drm_device *dev)
1838 {
1839         struct drm_i915_private *dev_priv = dev->dev_private;
1840         struct intel_engine_cs *ring;
1841         uint32_t ecochk, ecobits;
1842         int i;
1843
1844         ecobits = I915_READ(GAC_ECO_BITS);
1845         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1846
1847         ecochk = I915_READ(GAM_ECOCHK);
1848         if (IS_HASWELL(dev)) {
1849                 ecochk |= ECOCHK_PPGTT_WB_HSW;
1850         } else {
1851                 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1852                 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1853         }
1854         I915_WRITE(GAM_ECOCHK, ecochk);
1855
1856         for_each_ring(ring, dev_priv, i) {
1857                 /* GFX_MODE is per-ring on gen7+ */
1858                 I915_WRITE(RING_MODE_GEN7(ring),
1859                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1860         }
1861 }
1862
1863 static void gen6_ppgtt_enable(struct drm_device *dev)
1864 {
1865         struct drm_i915_private *dev_priv = dev->dev_private;
1866         uint32_t ecochk, gab_ctl, ecobits;
1867
1868         ecobits = I915_READ(GAC_ECO_BITS);
1869         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1870                    ECOBITS_PPGTT_CACHE64B);
1871
1872         gab_ctl = I915_READ(GAB_CTL);
1873         I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1874
1875         ecochk = I915_READ(GAM_ECOCHK);
1876         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1877
1878         I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1879 }
1880
1881 /* PPGTT support for Sandybdrige/Gen6 and later */
1882 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1883                                    uint64_t start,
1884                                    uint64_t length,
1885                                    bool use_scratch)
1886 {
1887         struct i915_hw_ppgtt *ppgtt =
1888                 container_of(vm, struct i915_hw_ppgtt, base);
1889         gen6_pte_t *pt_vaddr, scratch_pte;
1890         unsigned first_entry = start >> PAGE_SHIFT;
1891         unsigned num_entries = length >> PAGE_SHIFT;
1892         unsigned act_pt = first_entry / GEN6_PTES;
1893         unsigned first_pte = first_entry % GEN6_PTES;
1894         unsigned last_pte, i;
1895
1896         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1897                                      I915_CACHE_LLC, true, 0);
1898
1899         while (num_entries) {
1900                 last_pte = first_pte + num_entries;
1901                 if (last_pte > GEN6_PTES)
1902                         last_pte = GEN6_PTES;
1903
1904                 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1905
1906                 for (i = first_pte; i < last_pte; i++)
1907                         pt_vaddr[i] = scratch_pte;
1908
1909                 kunmap_px(ppgtt, pt_vaddr);
1910
1911                 num_entries -= last_pte - first_pte;
1912                 first_pte = 0;
1913                 act_pt++;
1914         }
1915 }
1916
1917 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1918                                       struct sg_table *pages,
1919                                       uint64_t start,
1920                                       enum i915_cache_level cache_level, u32 flags)
1921 {
1922         struct i915_hw_ppgtt *ppgtt =
1923                 container_of(vm, struct i915_hw_ppgtt, base);
1924         gen6_pte_t *pt_vaddr;
1925         unsigned first_entry = start >> PAGE_SHIFT;
1926         unsigned act_pt = first_entry / GEN6_PTES;
1927         unsigned act_pte = first_entry % GEN6_PTES;
1928         struct sg_page_iter sg_iter;
1929
1930         pt_vaddr = NULL;
1931         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
1932                 if (pt_vaddr == NULL)
1933                         pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1934
1935                 pt_vaddr[act_pte] =
1936                         vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
1937                                        cache_level, true, flags);
1938
1939                 if (++act_pte == GEN6_PTES) {
1940                         kunmap_px(ppgtt, pt_vaddr);
1941                         pt_vaddr = NULL;
1942                         act_pt++;
1943                         act_pte = 0;
1944                 }
1945         }
1946         if (pt_vaddr)
1947                 kunmap_px(ppgtt, pt_vaddr);
1948 }
1949
1950 static int gen6_alloc_va_range(struct i915_address_space *vm,
1951                                uint64_t start_in, uint64_t length_in)
1952 {
1953         DECLARE_BITMAP(new_page_tables, I915_PDES);
1954         struct drm_device *dev = vm->dev;
1955         struct drm_i915_private *dev_priv = dev->dev_private;
1956         struct i915_hw_ppgtt *ppgtt =
1957                                 container_of(vm, struct i915_hw_ppgtt, base);
1958         struct i915_page_table *pt;
1959         uint32_t start, length, start_save, length_save;
1960         uint32_t pde, temp;
1961         int ret;
1962
1963         if (WARN_ON(start_in + length_in > ppgtt->base.total))
1964                 return -ENODEV;
1965
1966         start = start_save = start_in;
1967         length = length_save = length_in;
1968
1969         bitmap_zero(new_page_tables, I915_PDES);
1970
1971         /* The allocation is done in two stages so that we can bail out with
1972          * minimal amount of pain. The first stage finds new page tables that
1973          * need allocation. The second stage marks use ptes within the page
1974          * tables.
1975          */
1976         gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1977                 if (pt != vm->scratch_pt) {
1978 //                      WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1979                         continue;
1980                 }
1981
1982                 /* We've already allocated a page table */
1983                 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1984
1985                 pt = alloc_pt(dev);
1986                 if (IS_ERR(pt)) {
1987                         ret = PTR_ERR(pt);
1988                         goto unwind_out;
1989                 }
1990
1991                 gen6_initialize_pt(vm, pt);
1992
1993                 ppgtt->pd.page_table[pde] = pt;
1994                 __set_bit(pde, new_page_tables);
1995                 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
1996         }
1997
1998         start = start_save;
1999         length = length_save;
2000
2001         gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
2002                 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
2003
2004                 bitmap_zero(tmp_bitmap, GEN6_PTES);
2005                 bitmap_set(tmp_bitmap, gen6_pte_index(start),
2006                            gen6_pte_count(start, length));
2007
2008                 if (__test_and_clear_bit(pde, new_page_tables))
2009                         gen6_write_pde(&ppgtt->pd, pde, pt);
2010
2011                 trace_i915_page_table_entry_map(vm, pde, pt,
2012                                          gen6_pte_index(start),
2013                                          gen6_pte_count(start, length),
2014                                          GEN6_PTES);
2015                 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
2016                                 GEN6_PTES);
2017         }
2018
2019         WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
2020
2021         /* Make sure write is complete before other code can use this page
2022          * table. Also require for WC mapped PTEs */
2023         readl(dev_priv->gtt.gsm);
2024
2025         mark_tlbs_dirty(ppgtt);
2026         return 0;
2027
2028 unwind_out:
2029         for_each_set_bit(pde, new_page_tables, I915_PDES) {
2030                 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
2031
2032                 ppgtt->pd.page_table[pde] = vm->scratch_pt;
2033                 free_pt(vm->dev, pt);
2034         }
2035
2036         mark_tlbs_dirty(ppgtt);
2037         return ret;
2038 }
2039
2040 static int gen6_init_scratch(struct i915_address_space *vm)
2041 {
2042         struct drm_device *dev = vm->dev;
2043
2044         vm->scratch_page = alloc_scratch_page(dev);
2045         if (IS_ERR(vm->scratch_page))
2046                 return PTR_ERR(vm->scratch_page);
2047
2048         vm->scratch_pt = alloc_pt(dev);
2049         if (IS_ERR(vm->scratch_pt)) {
2050                 free_scratch_page(dev, vm->scratch_page);
2051                 return PTR_ERR(vm->scratch_pt);
2052         }
2053
2054         gen6_initialize_pt(vm, vm->scratch_pt);
2055
2056         return 0;
2057 }
2058
2059 static void gen6_free_scratch(struct i915_address_space *vm)
2060 {
2061         struct drm_device *dev = vm->dev;
2062
2063         free_pt(dev, vm->scratch_pt);
2064         free_scratch_page(dev, vm->scratch_page);
2065 }
2066
2067 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
2068 {
2069         struct i915_hw_ppgtt *ppgtt =
2070                 container_of(vm, struct i915_hw_ppgtt, base);
2071         struct i915_page_table *pt;
2072         uint32_t pde;
2073
2074         drm_mm_remove_node(&ppgtt->node);
2075
2076         gen6_for_all_pdes(pt, ppgtt, pde) {
2077                 if (pt != vm->scratch_pt)
2078                         free_pt(ppgtt->base.dev, pt);
2079         }
2080
2081         gen6_free_scratch(vm);
2082 }
2083
2084 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
2085 {
2086         struct i915_address_space *vm = &ppgtt->base;
2087         struct drm_device *dev = ppgtt->base.dev;
2088         struct drm_i915_private *dev_priv = dev->dev_private;
2089         bool retried = false;
2090         int ret;
2091
2092         /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
2093          * allocator works in address space sizes, so it's multiplied by page
2094          * size. We allocate at the top of the GTT to avoid fragmentation.
2095          */
2096         BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
2097
2098         ret = gen6_init_scratch(vm);
2099         if (ret)
2100                 return ret;
2101
2102 alloc:
2103         ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
2104                                                   &ppgtt->node, GEN6_PD_SIZE,
2105                                                   GEN6_PD_ALIGN, 0,
2106                                                   0, dev_priv->gtt.base.total,
2107                                                   DRM_MM_TOPDOWN);
2108         if (ret == -ENOSPC && !retried) {
2109                 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
2110                                                GEN6_PD_SIZE, GEN6_PD_ALIGN,
2111                                                I915_CACHE_NONE,
2112                                                0, dev_priv->gtt.base.total,
2113                                                0);
2114                 if (ret)
2115                         goto err_out;
2116
2117                 retried = true;
2118                 goto alloc;
2119         }
2120
2121         if (ret)
2122                 goto err_out;
2123
2124
2125         if (ppgtt->node.start < dev_priv->gtt.mappable_end)
2126                 DRM_DEBUG("Forced to use aperture for PDEs\n");
2127
2128         return 0;
2129
2130 err_out:
2131         gen6_free_scratch(vm);
2132         return ret;
2133 }
2134
2135 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
2136 {
2137         return gen6_ppgtt_allocate_page_directories(ppgtt);
2138 }
2139
2140 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
2141                                   uint64_t start, uint64_t length)
2142 {
2143         struct i915_page_table *unused;
2144         uint32_t pde, temp;
2145
2146         gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
2147                 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
2148 }
2149
2150 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt, bool aliasing)
2151 {
2152         struct drm_device *dev = ppgtt->base.dev;
2153         struct drm_i915_private *dev_priv = dev->dev_private;
2154         int ret;
2155
2156         ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
2157         if (IS_GEN6(dev)) {
2158                 ppgtt->switch_mm = gen6_mm_switch;
2159         } else if (IS_HASWELL(dev)) {
2160                 ppgtt->switch_mm = hsw_mm_switch;
2161         } else if (IS_GEN7(dev)) {
2162                 ppgtt->switch_mm = gen7_mm_switch;
2163         } else
2164                 BUG();
2165
2166         if (intel_vgpu_active(dev))
2167                 ppgtt->switch_mm = vgpu_mm_switch;
2168
2169         ret = gen6_ppgtt_alloc(ppgtt);
2170         if (ret)
2171                 return ret;
2172
2173         if (aliasing) {
2174                 /* preallocate all pts */
2175                 ret = alloc_pt_range(&ppgtt->pd, 0, I915_PDES,
2176                                 ppgtt->base.dev);
2177
2178                 if (ret) {
2179                         gen6_ppgtt_cleanup(&ppgtt->base);
2180                         return ret;
2181                 }
2182         }
2183
2184         ppgtt->base.allocate_va_range = gen6_alloc_va_range;
2185         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
2186         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
2187         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
2188         ppgtt->base.bind_vma = ppgtt_bind_vma;
2189         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
2190         ppgtt->base.start = 0;
2191         ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
2192         ppgtt->debug_dump = gen6_dump_ppgtt;
2193
2194         ppgtt->pd.base.ggtt_offset =
2195                 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
2196
2197         ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
2198                 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
2199
2200         if (aliasing)
2201                 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
2202         else
2203                 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
2204
2205         gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
2206
2207         DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
2208                          ppgtt->node.size >> 20,
2209                          ppgtt->node.start / PAGE_SIZE);
2210
2211         DRM_DEBUG("Adding PPGTT at offset %x\n",
2212                   ppgtt->pd.base.ggtt_offset << 10);
2213
2214         return 0;
2215 }
2216
2217 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt,
2218                 bool aliasing)
2219 {
2220         ppgtt->base.dev = dev;
2221
2222         if (INTEL_INFO(dev)->gen < 8)
2223                 return gen6_ppgtt_init(ppgtt, aliasing);
2224         else if (aliasing)
2225                 return gen8_aliasing_ppgtt_init(ppgtt);
2226         else
2227                 return gen8_ppgtt_init(ppgtt);
2228 }
2229
2230 static void i915_address_space_init(struct i915_address_space *vm,
2231                                     struct drm_i915_private *dev_priv)
2232 {
2233         drm_mm_init(&vm->mm, vm->start, vm->total);
2234         vm->dev = dev_priv->dev;
2235         INIT_LIST_HEAD(&vm->active_list);
2236         INIT_LIST_HEAD(&vm->inactive_list);
2237         list_add_tail(&vm->global_link, &dev_priv->vm_list);
2238 }
2239
2240 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
2241 {
2242         struct drm_i915_private *dev_priv = dev->dev_private;
2243         int ret = 0;
2244
2245         ret = __hw_ppgtt_init(dev, ppgtt, false);
2246         if (ret == 0) {
2247                 kref_init(&ppgtt->ref);
2248                 i915_address_space_init(&ppgtt->base, dev_priv);
2249         }
2250
2251         return ret;
2252 }
2253
2254 int i915_ppgtt_init_hw(struct drm_device *dev)
2255 {
2256         /* In the case of execlists, PPGTT is enabled by the context descriptor
2257          * and the PDPs are contained within the context itself.  We don't
2258          * need to do anything here. */
2259         if (i915.enable_execlists)
2260                 return 0;
2261
2262         if (!USES_PPGTT(dev))
2263                 return 0;
2264
2265         if (IS_GEN6(dev))
2266                 gen6_ppgtt_enable(dev);
2267         else if (IS_GEN7(dev))
2268                 gen7_ppgtt_enable(dev);
2269         else if (INTEL_INFO(dev)->gen >= 8)
2270                 gen8_ppgtt_enable(dev);
2271         else
2272                 MISSING_CASE(INTEL_INFO(dev)->gen);
2273
2274         return 0;
2275 }
2276
2277 int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
2278 {
2279         struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
2280         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2281
2282         if (i915.enable_execlists)
2283                 return 0;
2284
2285         if (!ppgtt)
2286                 return 0;
2287
2288         return ppgtt->switch_mm(ppgtt, req);
2289 }
2290
2291 struct i915_hw_ppgtt *
2292 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
2293 {
2294         struct i915_hw_ppgtt *ppgtt;
2295         int ret;
2296
2297         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2298         if (!ppgtt)
2299                 return ERR_PTR(-ENOMEM);
2300
2301         ret = i915_ppgtt_init(dev, ppgtt);
2302         if (ret) {
2303                 kfree(ppgtt);
2304                 return ERR_PTR(ret);
2305         }
2306
2307         ppgtt->file_priv = fpriv;
2308
2309         trace_i915_ppgtt_create(&ppgtt->base);
2310
2311         return ppgtt;
2312 }
2313
2314 void  i915_ppgtt_release(struct kref *kref)
2315 {
2316         struct i915_hw_ppgtt *ppgtt =
2317                 container_of(kref, struct i915_hw_ppgtt, ref);
2318
2319         trace_i915_ppgtt_release(&ppgtt->base);
2320
2321         /* vmas should already be unbound */
2322         WARN_ON(!list_empty(&ppgtt->base.active_list));
2323         WARN_ON(!list_empty(&ppgtt->base.inactive_list));
2324
2325         list_del(&ppgtt->base.global_link);
2326         drm_mm_takedown(&ppgtt->base.mm);
2327
2328         ppgtt->base.cleanup(&ppgtt->base);
2329         kfree(ppgtt);
2330 }
2331
2332 extern int intel_iommu_gfx_mapped;
2333 /* Certain Gen5 chipsets require require idling the GPU before
2334  * unmapping anything from the GTT when VT-d is enabled.
2335  */
2336 static bool needs_idle_maps(struct drm_device *dev)
2337 {
2338 #ifdef CONFIG_INTEL_IOMMU
2339         /* Query intel_iommu to see if we need the workaround. Presumably that
2340          * was loaded first.
2341          */
2342         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
2343                 return true;
2344 #endif
2345         return false;
2346 }
2347
2348 static bool do_idling(struct drm_i915_private *dev_priv)
2349 {
2350         bool ret = dev_priv->mm.interruptible;
2351
2352         if (unlikely(dev_priv->gtt.do_idle_maps)) {
2353                 dev_priv->mm.interruptible = false;
2354                 if (i915_gpu_idle(dev_priv->dev)) {
2355                         DRM_ERROR("Couldn't idle GPU\n");
2356                         /* Wait a bit, in hopes it avoids the hang */
2357                         udelay(10);
2358                 }
2359         }
2360
2361         return ret;
2362 }
2363
2364 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
2365 {
2366         if (unlikely(dev_priv->gtt.do_idle_maps))
2367                 dev_priv->mm.interruptible = interruptible;
2368 }
2369
2370 void i915_check_and_clear_faults(struct drm_device *dev)
2371 {
2372         struct drm_i915_private *dev_priv = dev->dev_private;
2373         struct intel_engine_cs *ring;
2374         int i;
2375
2376         if (INTEL_INFO(dev)->gen < 6)
2377                 return;
2378
2379         for_each_ring(ring, dev_priv, i) {
2380                 u32 fault_reg;
2381                 fault_reg = I915_READ(RING_FAULT_REG(ring));
2382                 if (fault_reg & RING_FAULT_VALID) {
2383 #if 0
2384                         DRM_DEBUG_DRIVER("Unexpected fault\n"
2385                                          "\tAddr: 0x%08lx\n"
2386                                          "\tAddress space: %s\n"
2387                                          "\tSource ID: %d\n"
2388                                          "\tType: %d\n",
2389                                          fault_reg & PAGE_MASK,
2390                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
2391                                          RING_FAULT_SRCID(fault_reg),
2392                                          RING_FAULT_FAULT_TYPE(fault_reg));
2393 #endif
2394                         I915_WRITE(RING_FAULT_REG(ring),
2395                                    fault_reg & ~RING_FAULT_VALID);
2396                 }
2397         }
2398         POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
2399 }
2400
2401 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
2402 {
2403         if (INTEL_INFO(dev_priv->dev)->gen < 6) {
2404                 intel_gtt_chipset_flush();
2405         } else {
2406                 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2407                 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2408         }
2409 }
2410
2411 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
2412 {
2413         struct drm_i915_private *dev_priv = dev->dev_private;
2414
2415         /* Don't bother messing with faults pre GEN6 as we have little
2416          * documentation supporting that it's a good idea.
2417          */
2418         if (INTEL_INFO(dev)->gen < 6)
2419                 return;
2420
2421         i915_check_and_clear_faults(dev);
2422
2423         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2424                                        dev_priv->gtt.base.start,
2425                                        dev_priv->gtt.base.total,
2426                                        true);
2427
2428         i915_ggtt_flush(dev_priv);
2429 }
2430
2431 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
2432 {
2433         if (!dma_map_sg(obj->base.dev->pdev->dev,
2434                         obj->pages->sgl, obj->pages->nents,
2435                         PCI_DMA_BIDIRECTIONAL))
2436                 return -ENOSPC;
2437
2438         return 0;
2439 }
2440
2441 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
2442 {
2443 #if 0
2444         writeq(pte, addr);
2445 #else
2446         iowrite32((u32)pte, addr);
2447         iowrite32(pte >> 32, addr + 4);
2448 #endif
2449 }
2450
2451 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
2452                                      struct sg_table *st,
2453                                      uint64_t start,
2454                                      enum i915_cache_level level, u32 unused)
2455 {
2456         struct drm_i915_private *dev_priv = vm->dev->dev_private;
2457         unsigned first_entry = start >> PAGE_SHIFT;
2458         gen8_pte_t __iomem *gtt_entries =
2459                 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
2460         int i = 0;
2461         struct sg_page_iter sg_iter;
2462         dma_addr_t addr = 0; /* shut up gcc */
2463
2464         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2465                 addr = sg_dma_address(sg_iter.sg) +
2466                         (sg_iter.sg_pgoffset << PAGE_SHIFT);
2467                 gen8_set_pte(&gtt_entries[i],
2468                              gen8_pte_encode(addr, level, true));
2469                 i++;
2470         }
2471
2472         /*
2473          * XXX: This serves as a posting read to make sure that the PTE has
2474          * actually been updated. There is some concern that even though
2475          * registers and PTEs are within the same BAR that they are potentially
2476          * of NUMA access patterns. Therefore, even with the way we assume
2477          * hardware should work, we must keep this posting read for paranoia.
2478          */
2479         if (i != 0)
2480                 WARN_ON(readq(&gtt_entries[i-1])
2481                         != gen8_pte_encode(addr, level, true));
2482
2483         /* This next bit makes the above posting read even more important. We
2484          * want to flush the TLBs only after we're certain all the PTE updates
2485          * have finished.
2486          */
2487         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2488         POSTING_READ(GFX_FLSH_CNTL_GEN6);
2489 }
2490
2491 /*
2492  * Binds an object into the global gtt with the specified cache level. The object
2493  * will be accessible to the GPU via commands whose operands reference offsets
2494  * within the global GTT as well as accessible by the GPU through the GMADR
2495  * mapped BAR (dev_priv->mm.gtt->gtt).
2496  */
2497 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
2498                                      struct sg_table *st,
2499                                      uint64_t start,
2500                                      enum i915_cache_level level, u32 flags)
2501 {
2502         struct drm_i915_private *dev_priv = vm->dev->dev_private;
2503         unsigned first_entry = start >> PAGE_SHIFT;
2504         gen6_pte_t __iomem *gtt_entries =
2505                 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
2506         int i = 0;
2507         struct sg_page_iter sg_iter;
2508         dma_addr_t addr = 0;
2509
2510         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2511                 addr = sg_page_iter_dma_address(&sg_iter);
2512                 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
2513                 i++;
2514         }
2515
2516         /* XXX: This serves as a posting read to make sure that the PTE has
2517          * actually been updated. There is some concern that even though
2518          * registers and PTEs are within the same BAR that they are potentially
2519          * of NUMA access patterns. Therefore, even with the way we assume
2520          * hardware should work, we must keep this posting read for paranoia.
2521          */
2522         if (i != 0) {
2523                 unsigned long gtt = readl(&gtt_entries[i-1]);
2524                 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
2525         }
2526
2527         /* This next bit makes the above posting read even more important. We
2528          * want to flush the TLBs only after we're certain all the PTE updates
2529          * have finished.
2530          */
2531         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2532         POSTING_READ(GFX_FLSH_CNTL_GEN6);
2533 }
2534
2535 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
2536                                   uint64_t start,
2537                                   uint64_t length,
2538                                   bool use_scratch)
2539 {
2540         struct drm_i915_private *dev_priv = vm->dev->dev_private;
2541         unsigned first_entry = start >> PAGE_SHIFT;
2542         unsigned num_entries = length >> PAGE_SHIFT;
2543         gen8_pte_t scratch_pte, __iomem *gtt_base =
2544                 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
2545         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
2546         int i;
2547
2548         if (WARN(num_entries > max_entries,
2549                  "First entry = %d; Num entries = %d (max=%d)\n",
2550                  first_entry, num_entries, max_entries))
2551                 num_entries = max_entries;
2552
2553         scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
2554                                       I915_CACHE_LLC,
2555                                       use_scratch);
2556         for (i = 0; i < num_entries; i++)
2557                 gen8_set_pte(&gtt_base[i], scratch_pte);
2558         readl(gtt_base);
2559 }
2560
2561 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
2562                                   uint64_t start,
2563                                   uint64_t length,
2564                                   bool use_scratch)
2565 {
2566         struct drm_i915_private *dev_priv = vm->dev->dev_private;
2567         unsigned first_entry = start >> PAGE_SHIFT;
2568         unsigned num_entries = length >> PAGE_SHIFT;
2569         gen6_pte_t scratch_pte, __iomem *gtt_base =
2570                 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
2571         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
2572         int i;
2573
2574         if (WARN(num_entries > max_entries,
2575                  "First entry = %d; Num entries = %d (max=%d)\n",
2576                  first_entry, num_entries, max_entries))
2577                 num_entries = max_entries;
2578
2579         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
2580                                      I915_CACHE_LLC, use_scratch, 0);
2581
2582         for (i = 0; i < num_entries; i++)
2583                 iowrite32(scratch_pte, &gtt_base[i]);
2584         readl(gtt_base);
2585 }
2586
2587 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2588                                      struct sg_table *pages,
2589                                      uint64_t start,
2590                                      enum i915_cache_level cache_level, u32 unused)
2591 {
2592         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2593                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2594
2595         intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
2596 }
2597
2598 static void i915_ggtt_clear_range(struct i915_address_space *vm,
2599                                   uint64_t start,
2600                                   uint64_t length,
2601                                   bool unused)
2602 {
2603         unsigned first_entry = start >> PAGE_SHIFT;
2604         unsigned num_entries = length >> PAGE_SHIFT;
2605         intel_gtt_clear_range(first_entry, num_entries);
2606 }
2607
2608 static int ggtt_bind_vma(struct i915_vma *vma,
2609                          enum i915_cache_level cache_level,
2610                          u32 flags)
2611 {
2612         struct drm_i915_gem_object *obj = vma->obj;
2613         u32 pte_flags = 0;
2614         int ret;
2615
2616         ret = i915_get_ggtt_vma_pages(vma);
2617         if (ret)
2618                 return ret;
2619
2620         /* Currently applicable only to VLV */
2621         if (obj->gt_ro)
2622                 pte_flags |= PTE_READ_ONLY;
2623
2624         vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages,
2625                                 vma->node.start,
2626                                 cache_level, pte_flags);
2627
2628         /*
2629          * Without aliasing PPGTT there's no difference between
2630          * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2631          * upgrade to both bound if we bind either to avoid double-binding.
2632          */
2633         vma->bound |= GLOBAL_BIND | LOCAL_BIND;
2634
2635         return 0;
2636 }
2637
2638 static int aliasing_gtt_bind_vma(struct i915_vma *vma,
2639                                  enum i915_cache_level cache_level,
2640                                  u32 flags)
2641 {
2642         struct drm_device *dev = vma->vm->dev;
2643         struct drm_i915_private *dev_priv = dev->dev_private;
2644         struct drm_i915_gem_object *obj = vma->obj;
2645         struct sg_table *pages = obj->pages;
2646         u32 pte_flags = 0;
2647         int ret;
2648
2649         ret = i915_get_ggtt_vma_pages(vma);
2650         if (ret)
2651                 return ret;
2652         pages = vma->ggtt_view.pages;
2653
2654         /* Currently applicable only to VLV */
2655         if (obj->gt_ro)
2656                 pte_flags |= PTE_READ_ONLY;
2657
2658
2659         if (flags & GLOBAL_BIND) {
2660                 vma->vm->insert_entries(vma->vm, pages,
2661                                         vma->node.start,
2662                                         cache_level, pte_flags);
2663         }
2664
2665         if (flags & LOCAL_BIND) {
2666                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
2667                 appgtt->base.insert_entries(&appgtt->base, pages,
2668                                             vma->node.start,
2669                                             cache_level, pte_flags);
2670         }
2671
2672         return 0;
2673 }
2674
2675 static void ggtt_unbind_vma(struct i915_vma *vma)
2676 {
2677         struct drm_device *dev = vma->vm->dev;
2678         struct drm_i915_private *dev_priv = dev->dev_private;
2679         struct drm_i915_gem_object *obj = vma->obj;
2680         const uint64_t size = min_t(uint64_t,
2681                                     obj->base.size,
2682                                     vma->node.size);
2683
2684         if (vma->bound & GLOBAL_BIND) {
2685                 vma->vm->clear_range(vma->vm,
2686                                      vma->node.start,
2687                                      size,
2688                                      true);
2689         }
2690
2691         if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
2692                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
2693
2694                 appgtt->base.clear_range(&appgtt->base,
2695                                          vma->node.start,
2696                                          size,
2697                                          true);
2698         }
2699 }
2700
2701 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
2702 {
2703         struct drm_device *dev = obj->base.dev;
2704         struct drm_i915_private *dev_priv = dev->dev_private;
2705         bool interruptible;
2706
2707         interruptible = do_idling(dev_priv);
2708
2709         dma_unmap_sg(dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
2710                      PCI_DMA_BIDIRECTIONAL);
2711
2712         undo_idling(dev_priv, interruptible);
2713 }
2714
2715 static void i915_gtt_color_adjust(struct drm_mm_node *node,
2716                                   unsigned long color,
2717                                   u64 *start,
2718                                   u64 *end)
2719 {
2720         if (node->color != color)
2721                 *start += 4096;
2722
2723         if (!list_empty(&node->node_list)) {
2724                 node = list_entry(node->node_list.next,
2725                                   struct drm_mm_node,
2726                                   node_list);
2727                 if (node->allocated && node->color != color)
2728                         *end -= 4096;
2729         }
2730 }
2731
2732 static int i915_gem_setup_global_gtt(struct drm_device *dev,
2733                                      u64 start,
2734                                      u64 mappable_end,
2735                                      u64 end)
2736 {
2737         /* Let GEM Manage all of the aperture.
2738          *
2739          * However, leave one page at the end still bound to the scratch page.
2740          * There are a number of places where the hardware apparently prefetches
2741          * past the end of the object, and we've seen multiple hangs with the
2742          * GPU head pointer stuck in a batchbuffer bound at the last page of the
2743          * aperture.  One page should be enough to keep any prefetching inside
2744          * of the aperture.
2745          */
2746         struct drm_i915_private *dev_priv = dev->dev_private;
2747         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
2748         unsigned long mappable;
2749         int error;
2750         struct drm_mm_node *entry;
2751         struct drm_i915_gem_object *obj;
2752         unsigned long hole_start, hole_end;
2753         int ret;
2754
2755         mappable = min(end, mappable_end) - start;
2756         BUG_ON(mappable_end > end);
2757
2758         ggtt_vm->start = start;
2759
2760         /* Subtract the guard page before address space initialization to
2761          * shrink the range used by drm_mm */
2762         ggtt_vm->total = end - start - PAGE_SIZE;
2763         i915_address_space_init(ggtt_vm, dev_priv);
2764         ggtt_vm->total += PAGE_SIZE;
2765
2766         if (intel_vgpu_active(dev)) {
2767                 ret = intel_vgt_balloon(dev);
2768                 if (ret)
2769                         return ret;
2770         }
2771
2772         if (!HAS_LLC(dev))
2773                 ggtt_vm->mm.color_adjust = i915_gtt_color_adjust;
2774
2775         /* Mark any preallocated objects as occupied */
2776         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2777                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
2778
2779                 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
2780                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
2781
2782                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
2783                 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
2784                 if (ret) {
2785                         DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2786                         return ret;
2787                 }
2788                 vma->bound |= GLOBAL_BIND;
2789                 __i915_vma_set_map_and_fenceable(vma);
2790                 list_add_tail(&vma->mm_list, &ggtt_vm->inactive_list);
2791         }
2792
2793         /* Clear any non-preallocated blocks */
2794         drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
2795                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2796                               hole_start, hole_end);
2797                 ggtt_vm->clear_range(ggtt_vm, hole_start,
2798                                      hole_end - hole_start, true);
2799         }
2800
2801 #ifdef __DragonFly__
2802         device_printf(dev->dev,
2803             "taking over the fictitious range 0x%lx-0x%lx\n",
2804             dev_priv->gtt.mappable_base + start, dev_priv->gtt.mappable_base + start + mappable);
2805         error = -vm_phys_fictitious_reg_range(dev_priv->gtt.mappable_base + start,
2806             dev_priv->gtt.mappable_base + start + mappable, VM_MEMATTR_WRITE_COMBINING);
2807 #endif
2808
2809         /* And finally clear the reserved guard page */
2810         ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
2811
2812         if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2813                 struct i915_hw_ppgtt *ppgtt;
2814
2815                 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2816                 if (!ppgtt)
2817                         return -ENOMEM;
2818
2819                 ret = __hw_ppgtt_init(dev, ppgtt, true);
2820                 if (ret) {
2821                         ppgtt->base.cleanup(&ppgtt->base);
2822                         kfree(ppgtt);
2823                         return ret;
2824                 }
2825
2826                 if (ppgtt->base.allocate_va_range)
2827                         ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2828                                                             ppgtt->base.total);
2829                 if (ret) {
2830                         ppgtt->base.cleanup(&ppgtt->base);
2831                         kfree(ppgtt);
2832                         return ret;
2833                 }
2834
2835                 ppgtt->base.clear_range(&ppgtt->base,
2836                                         ppgtt->base.start,
2837                                         ppgtt->base.total,
2838                                         true);
2839
2840                 dev_priv->mm.aliasing_ppgtt = ppgtt;
2841                 WARN_ON(dev_priv->gtt.base.bind_vma != ggtt_bind_vma);
2842                 dev_priv->gtt.base.bind_vma = aliasing_gtt_bind_vma;
2843         }
2844
2845         return 0;
2846 }
2847
2848 void i915_gem_init_global_gtt(struct drm_device *dev)
2849 {
2850         struct drm_i915_private *dev_priv = dev->dev_private;
2851         u64 gtt_size, mappable_size;
2852
2853         gtt_size = dev_priv->gtt.base.total;
2854         mappable_size = dev_priv->gtt.mappable_end;
2855
2856         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
2857 }
2858
2859 void i915_global_gtt_cleanup(struct drm_device *dev)
2860 {
2861         struct drm_i915_private *dev_priv = dev->dev_private;
2862         struct i915_address_space *vm = &dev_priv->gtt.base;
2863
2864         if (dev_priv->mm.aliasing_ppgtt) {
2865                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2866
2867                 ppgtt->base.cleanup(&ppgtt->base);
2868         }
2869
2870         if (drm_mm_initialized(&vm->mm)) {
2871                 if (intel_vgpu_active(dev))
2872                         intel_vgt_deballoon();
2873
2874                 drm_mm_takedown(&vm->mm);
2875                 list_del(&vm->global_link);
2876         }
2877
2878         vm->cleanup(vm);
2879 }
2880
2881 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2882 {
2883         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2884         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2885         return snb_gmch_ctl << 20;
2886 }
2887
2888 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2889 {
2890         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2891         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2892         if (bdw_gmch_ctl)
2893                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2894
2895 #ifdef CONFIG_X86_32
2896         /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2897         if (bdw_gmch_ctl > 4)
2898                 bdw_gmch_ctl = 4;
2899 #endif
2900
2901         return bdw_gmch_ctl << 20;
2902 }
2903
2904 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2905 {
2906         gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2907         gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2908
2909         if (gmch_ctrl)
2910                 return 1 << (20 + gmch_ctrl);
2911
2912         return 0;
2913 }
2914
2915 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2916 {
2917         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2918         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2919         return snb_gmch_ctl << 25; /* 32 MB units */
2920 }
2921
2922 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2923 {
2924         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2925         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2926         return bdw_gmch_ctl << 25; /* 32 MB units */
2927 }
2928
2929 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2930 {
2931         gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2932         gmch_ctrl &= SNB_GMCH_GMS_MASK;
2933
2934         /*
2935          * 0x0  to 0x10: 32MB increments starting at 0MB
2936          * 0x11 to 0x16: 4MB increments starting at 8MB
2937          * 0x17 to 0x1d: 4MB increments start at 36MB
2938          */
2939         if (gmch_ctrl < 0x11)
2940                 return gmch_ctrl << 25;
2941         else if (gmch_ctrl < 0x17)
2942                 return (gmch_ctrl - 0x11 + 2) << 22;
2943         else
2944                 return (gmch_ctrl - 0x17 + 9) << 22;
2945 }
2946
2947 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2948 {
2949         gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2950         gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2951
2952         if (gen9_gmch_ctl < 0xf0)
2953                 return gen9_gmch_ctl << 25; /* 32 MB units */
2954         else
2955                 /* 4MB increments starting at 0xf0 for 4MB */
2956                 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2957 }
2958
2959 static int ggtt_probe_common(struct drm_device *dev,
2960                              size_t gtt_size)
2961 {
2962         struct drm_i915_private *dev_priv = dev->dev_private;
2963         struct i915_page_scratch *scratch_page;
2964         phys_addr_t gtt_phys_addr;
2965
2966         /* For Modern GENs the PTEs and register space are split in the BAR */
2967         gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
2968                 (pci_resource_len(dev->pdev, 0) / 2);
2969
2970         /*
2971          * On BXT writes larger than 64 bit to the GTT pagetable range will be
2972          * dropped. For WC mappings in general we have 64 byte burst writes
2973          * when the WC buffer is flushed, so we can't use it, but have to
2974          * resort to an uncached mapping. The WC issue is easily caught by the
2975          * readback check when writing GTT PTE entries.
2976          */
2977         if (IS_BROXTON(dev))
2978                 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2979         else
2980                 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
2981         if (!dev_priv->gtt.gsm) {
2982                 DRM_ERROR("Failed to map the gtt page table\n");
2983                 return -ENOMEM;
2984         }
2985
2986         scratch_page = alloc_scratch_page(dev);
2987         if (IS_ERR(scratch_page)) {
2988                 DRM_ERROR("Scratch setup failed\n");
2989                 /* iounmap will also get called at remove, but meh */
2990                 iounmap(dev_priv->gtt.gsm);
2991                 return PTR_ERR(scratch_page);
2992         }
2993
2994         dev_priv->gtt.base.scratch_page = scratch_page;
2995
2996         return 0;
2997 }
2998
2999 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
3000  * bits. When using advanced contexts each context stores its own PAT, but
3001  * writing this data shouldn't be harmful even in those cases. */
3002 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
3003 {
3004         uint64_t pat;
3005
3006         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
3007               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
3008               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
3009               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
3010               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
3011               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
3012               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
3013               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
3014
3015         if (!USES_PPGTT(dev_priv->dev))
3016                 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
3017                  * so RTL will always use the value corresponding to
3018                  * pat_sel = 000".
3019                  * So let's disable cache for GGTT to avoid screen corruptions.
3020                  * MOCS still can be used though.
3021                  * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
3022                  * before this patch, i.e. the same uncached + snooping access
3023                  * like on gen6/7 seems to be in effect.
3024                  * - So this just fixes blitter/render access. Again it looks
3025                  * like it's not just uncached access, but uncached + snooping.
3026                  * So we can still hold onto all our assumptions wrt cpu
3027                  * clflushing on LLC machines.
3028                  */
3029                 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
3030
3031         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
3032          * write would work. */
3033         I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
3034         I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
3035 }
3036
3037 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
3038 {
3039         uint64_t pat;
3040
3041         /*
3042          * Map WB on BDW to snooped on CHV.
3043          *
3044          * Only the snoop bit has meaning for CHV, the rest is
3045          * ignored.
3046          *
3047          * The hardware will never snoop for certain types of accesses:
3048          * - CPU GTT (GMADR->GGTT->no snoop->memory)
3049          * - PPGTT page tables
3050          * - some other special cycles
3051          *
3052          * As with BDW, we also need to consider the following for GT accesses:
3053          * "For GGTT, there is NO pat_sel[2:0] from the entry,
3054          * so RTL will always use the value corresponding to
3055          * pat_sel = 000".
3056          * Which means we must set the snoop bit in PAT entry 0
3057          * in order to keep the global status page working.
3058          */
3059         pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
3060               GEN8_PPAT(1, 0) |
3061               GEN8_PPAT(2, 0) |
3062               GEN8_PPAT(3, 0) |
3063               GEN8_PPAT(4, CHV_PPAT_SNOOP) |
3064               GEN8_PPAT(5, CHV_PPAT_SNOOP) |
3065               GEN8_PPAT(6, CHV_PPAT_SNOOP) |
3066               GEN8_PPAT(7, CHV_PPAT_SNOOP);
3067
3068         I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
3069         I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
3070 }
3071
3072 static int gen8_gmch_probe(struct drm_device *dev,
3073                            u64 *gtt_total,
3074                            size_t *stolen,
3075                            phys_addr_t *mappable_base,
3076                            u64 *mappable_end)
3077 {
3078         struct drm_i915_private *dev_priv = dev->dev_private;
3079         u64 gtt_size;
3080         u16 snb_gmch_ctl;
3081         int ret;
3082
3083         /* TODO: We're not aware of mappable constraints on gen8 yet */
3084         *mappable_base = pci_resource_start(dev->pdev, 2);
3085         *mappable_end = pci_resource_len(dev->pdev, 2);
3086
3087 #if 0
3088         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
3089                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
3090 #endif
3091
3092         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
3093
3094         if (INTEL_INFO(dev)->gen >= 9) {
3095                 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
3096                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
3097         } else if (IS_CHERRYVIEW(dev)) {
3098                 *stolen = chv_get_stolen_size(snb_gmch_ctl);
3099                 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
3100         } else {
3101                 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
3102                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
3103         }
3104
3105         *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
3106
3107         if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
3108                 chv_setup_private_ppat(dev_priv);
3109         else
3110                 bdw_setup_private_ppat(dev_priv);
3111
3112         ret = ggtt_probe_common(dev, gtt_size);
3113
3114         dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
3115         dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
3116         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
3117         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
3118
3119         return ret;
3120 }
3121
3122 static int gen6_gmch_probe(struct drm_device *dev,
3123                            u64 *gtt_total,
3124                            size_t *stolen,
3125                            phys_addr_t *mappable_base,
3126                            u64 *mappable_end)
3127 {
3128         struct drm_i915_private *dev_priv = dev->dev_private;
3129         unsigned int gtt_size;
3130         u16 snb_gmch_ctl;
3131         int ret;
3132
3133         *mappable_base = pci_resource_start(dev->pdev, 2);
3134         *mappable_end = pci_resource_len(dev->pdev, 2);
3135
3136         /* 64/512MB is the current min/max we actually know of, but this is just
3137          * a coarse sanity check.
3138          */
3139         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
3140                 DRM_ERROR("Unknown GMADR size (%lx)\n",
3141                           dev_priv->gtt.mappable_end);
3142                 return -ENXIO;
3143         }
3144
3145 #if 0
3146         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
3147                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
3148 #endif
3149         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
3150
3151         *stolen = gen6_get_stolen_size(snb_gmch_ctl);
3152
3153         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
3154         *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
3155
3156         ret = ggtt_probe_common(dev, gtt_size);
3157
3158         dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
3159         dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
3160         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
3161         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
3162
3163         return ret;
3164 }
3165
3166 static void gen6_gmch_remove(struct i915_address_space *vm)
3167 {
3168         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
3169
3170         iounmap(gtt->gsm);
3171         free_scratch_page(vm->dev, vm->scratch_page);
3172 }
3173
3174 static int i915_gmch_probe(struct drm_device *dev,
3175                            u64 *gtt_total,
3176                            size_t *stolen,
3177                            phys_addr_t *mappable_base,
3178                            u64 *mappable_end)
3179 {
3180         struct drm_i915_private *dev_priv = dev->dev_private;
3181 #if 0
3182         int ret;
3183
3184         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
3185         if (!ret) {
3186                 DRM_ERROR("failed to set up gmch\n");
3187                 return -EIO;
3188         }
3189 #endif
3190
3191         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
3192
3193         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
3194         dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
3195         dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
3196         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
3197         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
3198
3199         if (unlikely(dev_priv->gtt.do_idle_maps))
3200                 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3201
3202         return 0;
3203 }
3204
3205 static void i915_gmch_remove(struct i915_address_space *vm)
3206 {
3207         intel_gmch_remove();
3208 }
3209
3210 int i915_gem_gtt_init(struct drm_device *dev)
3211 {
3212         struct drm_i915_private *dev_priv = dev->dev_private;
3213         struct i915_gtt *gtt = &dev_priv->gtt;
3214         int ret;
3215
3216         if (INTEL_INFO(dev)->gen <= 5) {
3217                 gtt->gtt_probe = i915_gmch_probe;
3218                 gtt->base.cleanup = i915_gmch_remove;
3219         } else if (INTEL_INFO(dev)->gen < 8) {
3220                 gtt->gtt_probe = gen6_gmch_probe;
3221                 gtt->base.cleanup = gen6_gmch_remove;
3222                 if (IS_HASWELL(dev) && dev_priv->ellc_size)
3223                         gtt->base.pte_encode = iris_pte_encode;
3224                 else if (IS_HASWELL(dev))
3225                         gtt->base.pte_encode = hsw_pte_encode;
3226                 else if (IS_VALLEYVIEW(dev))
3227                         gtt->base.pte_encode = byt_pte_encode;
3228                 else if (INTEL_INFO(dev)->gen >= 7)
3229                         gtt->base.pte_encode = ivb_pte_encode;
3230                 else
3231                         gtt->base.pte_encode = snb_pte_encode;
3232         } else {
3233                 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
3234                 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
3235         }
3236
3237         gtt->base.dev = dev;
3238
3239         ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
3240                              &gtt->mappable_base, &gtt->mappable_end);
3241         if (ret)
3242                 return ret;
3243
3244         /* GMADR is the PCI mmio aperture into the global GTT. */
3245         DRM_INFO("Memory usable by graphics device = %luM\n",
3246                  gtt->base.total >> 20);
3247         DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
3248         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
3249 #ifdef CONFIG_INTEL_IOMMU
3250         if (intel_iommu_gfx_mapped)
3251                 DRM_INFO("VT-d active for gfx access\n");
3252 #endif
3253         /*
3254          * i915.enable_ppgtt is read-only, so do an early pass to validate the
3255          * user's requested state against the hardware/driver capabilities.  We
3256          * do this now so that we can print out any log messages once rather
3257          * than every time we check intel_enable_ppgtt().
3258          */
3259         i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
3260         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
3261
3262         return 0;
3263 }
3264
3265 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
3266 {
3267         struct drm_i915_private *dev_priv = dev->dev_private;
3268         struct drm_i915_gem_object *obj;
3269         struct i915_address_space *vm;
3270
3271         i915_check_and_clear_faults(dev);
3272
3273         /* First fill our portion of the GTT with scratch pages */
3274         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
3275                                        dev_priv->gtt.base.start,
3276                                        dev_priv->gtt.base.total,
3277                                        true);
3278
3279         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
3280                 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
3281                                                            &dev_priv->gtt.base);
3282                 if (!vma)
3283                         continue;
3284
3285                 i915_gem_clflush_object(obj, obj->pin_display);
3286                 WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE));
3287         }
3288
3289
3290         if (INTEL_INFO(dev)->gen >= 8) {
3291                 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
3292                         chv_setup_private_ppat(dev_priv);
3293                 else
3294                         bdw_setup_private_ppat(dev_priv);
3295
3296                 return;
3297         }
3298
3299         if (USES_PPGTT(dev)) {
3300                 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3301                         /* TODO: Perhaps it shouldn't be gen6 specific */
3302
3303                         struct i915_hw_ppgtt *ppgtt =
3304                                         container_of(vm, struct i915_hw_ppgtt,
3305                                                      base);
3306
3307                         if (i915_is_ggtt(vm))
3308                                 ppgtt = dev_priv->mm.aliasing_ppgtt;
3309
3310                         gen6_write_page_range(dev_priv, &ppgtt->pd,
3311                                               0, ppgtt->base.total);
3312                 }
3313         }
3314
3315         i915_ggtt_flush(dev_priv);
3316 }
3317
3318 static struct i915_vma *
3319 __i915_gem_vma_create(struct drm_i915_gem_object *obj,
3320                       struct i915_address_space *vm,
3321                       const struct i915_ggtt_view *ggtt_view)
3322 {
3323         struct i915_vma *vma;
3324
3325         if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
3326                 return ERR_PTR(-EINVAL);
3327
3328         vma = kzalloc(sizeof(*vma), GFP_KERNEL);
3329         if (vma == NULL)
3330                 return ERR_PTR(-ENOMEM);
3331
3332         INIT_LIST_HEAD(&vma->vma_link);
3333         INIT_LIST_HEAD(&vma->mm_list);
3334         INIT_LIST_HEAD(&vma->exec_list);
3335         vma->vm = vm;
3336         vma->obj = obj;
3337
3338         if (i915_is_ggtt(vm))
3339                 vma->ggtt_view = *ggtt_view;
3340
3341         list_add_tail(&vma->vma_link, &obj->vma_list);
3342         if (!i915_is_ggtt(vm))
3343                 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
3344
3345         return vma;
3346 }
3347
3348 struct i915_vma *
3349 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3350                                   struct i915_address_space *vm)
3351 {
3352         struct i915_vma *vma;
3353
3354         vma = i915_gem_obj_to_vma(obj, vm);
3355         if (!vma)
3356                 vma = __i915_gem_vma_create(obj, vm,
3357                                             i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
3358
3359         return vma;
3360 }
3361
3362 struct i915_vma *
3363 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3364                                        const struct i915_ggtt_view *view)
3365 {
3366         struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
3367         struct i915_vma *vma;
3368
3369         if (WARN_ON(!view))
3370                 return ERR_PTR(-EINVAL);
3371
3372         vma = i915_gem_obj_to_ggtt_view(obj, view);
3373
3374         if (IS_ERR(vma))
3375                 return vma;
3376
3377         if (!vma)
3378                 vma = __i915_gem_vma_create(obj, ggtt, view);
3379
3380         return vma;
3381
3382 }
3383
3384 static struct scatterlist *
3385 rotate_pages(dma_addr_t *in, unsigned int offset,
3386              unsigned int width, unsigned int height,
3387              struct sg_table *st, struct scatterlist *sg)
3388 {
3389         unsigned int column, row;
3390         unsigned int src_idx;
3391
3392         if (!sg) {
3393                 st->nents = 0;
3394                 sg = st->sgl;
3395         }
3396
3397         for (column = 0; column < width; column++) {
3398                 src_idx = width * (height - 1) + column;
3399                 for (row = 0; row < height; row++) {
3400                         st->nents++;
3401                         /* We don't need the pages, but need to initialize
3402                          * the entries so the sg list can be happily traversed.
3403                          * The only thing we need are DMA addresses.
3404                          */
3405                         sg_set_page(sg, NULL, PAGE_SIZE, 0);
3406                         sg_dma_address(sg) = in[offset + src_idx];
3407                         sg_dma_len(sg) = PAGE_SIZE;
3408                         sg = sg_next(sg);
3409                         src_idx -= width;
3410                 }
3411         }
3412
3413         return sg;
3414 }
3415
3416 static struct sg_table *
3417 intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
3418                           struct drm_i915_gem_object *obj)
3419 {
3420         struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
3421         unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
3422         unsigned int size_pages_uv;
3423         struct sg_page_iter sg_iter;
3424         unsigned long i;
3425         dma_addr_t *page_addr_list;
3426         struct sg_table *st;
3427         unsigned int uv_start_page;
3428         struct scatterlist *sg;
3429         int ret = -ENOMEM;
3430
3431         /* Allocate a temporary list of source pages for random access. */
3432         page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
3433                                        sizeof(dma_addr_t));
3434         if (!page_addr_list)
3435                 return ERR_PTR(ret);
3436
3437         /* Account for UV plane with NV12. */
3438         if (rot_info->pixel_format == DRM_FORMAT_NV12)
3439                 size_pages_uv = rot_info->size_uv >> PAGE_SHIFT;
3440         else
3441                 size_pages_uv = 0;
3442
3443         /* Allocate target SG list. */
3444         st = kmalloc(sizeof(*st), M_DRM, M_WAITOK);
3445         if (!st)
3446                 goto err_st_alloc;
3447
3448         ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL);
3449         if (ret)
3450                 goto err_sg_alloc;
3451
3452         /* Populate source page list from the object. */
3453         i = 0;
3454         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
3455                 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
3456                 i++;
3457         }
3458
3459         /* Rotate the pages. */
3460         sg = rotate_pages(page_addr_list, 0,
3461                      rot_info->width_pages, rot_info->height_pages,
3462                      st, NULL);
3463
3464         /* Append the UV plane if NV12. */
3465         if (rot_info->pixel_format == DRM_FORMAT_NV12) {
3466                 uv_start_page = size_pages;
3467
3468                 /* Check for tile-row un-alignment. */
3469                 if (offset_in_page(rot_info->uv_offset))
3470                         uv_start_page--;
3471
3472                 rot_info->uv_start_page = uv_start_page;
3473
3474                 rotate_pages(page_addr_list, uv_start_page,
3475                              rot_info->width_pages_uv,
3476                              rot_info->height_pages_uv,
3477                              st, sg);
3478         }
3479
3480         DRM_DEBUG_KMS(
3481                       "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0)).\n",
3482                       obj->base.size, rot_info->pitch, rot_info->height,
3483                       rot_info->pixel_format, rot_info->width_pages,
3484                       rot_info->height_pages, size_pages + size_pages_uv,
3485                       size_pages);
3486
3487         drm_free_large(page_addr_list);
3488
3489         return st;
3490
3491 err_sg_alloc:
3492         kfree(st);
3493 err_st_alloc:
3494         drm_free_large(page_addr_list);
3495
3496         DRM_DEBUG_KMS(
3497                       "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0))\n",
3498                       obj->base.size, ret, rot_info->pitch, rot_info->height,
3499                       rot_info->pixel_format, rot_info->width_pages,
3500                       rot_info->height_pages, size_pages + size_pages_uv,
3501                       size_pages);
3502         return ERR_PTR(ret);
3503 }
3504
3505 static struct sg_table *
3506 intel_partial_pages(const struct i915_ggtt_view *view,
3507                     struct drm_i915_gem_object *obj)
3508 {
3509         struct sg_table *st;
3510         struct scatterlist *sg;
3511         struct sg_page_iter obj_sg_iter;
3512         int ret = -ENOMEM;
3513
3514         st = kmalloc(sizeof(*st), M_DRM, M_WAITOK);
3515         if (!st)
3516                 goto err_st_alloc;
3517
3518         ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
3519         if (ret)
3520                 goto err_sg_alloc;
3521
3522         sg = st->sgl;
3523         st->nents = 0;
3524         for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
3525                 view->params.partial.offset)
3526         {
3527                 if (st->nents >= view->params.partial.size)
3528                         break;
3529
3530                 sg_set_page(sg, NULL, PAGE_SIZE, 0);
3531                 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
3532                 sg_dma_len(sg) = PAGE_SIZE;
3533
3534                 sg = sg_next(sg);
3535                 st->nents++;
3536         }
3537
3538         return st;
3539
3540 err_sg_alloc:
3541         kfree(st);
3542 err_st_alloc:
3543         return ERR_PTR(ret);
3544 }
3545
3546 static int
3547 i915_get_ggtt_vma_pages(struct i915_vma *vma)
3548 {
3549         int ret = 0;
3550
3551         if (vma->ggtt_view.pages)
3552                 return 0;
3553
3554         if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
3555                 vma->ggtt_view.pages = vma->obj->pages;
3556         else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
3557                 vma->ggtt_view.pages =
3558                         intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
3559         else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
3560                 vma->ggtt_view.pages =
3561                         intel_partial_pages(&vma->ggtt_view, vma->obj);
3562         else
3563                 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3564                           vma->ggtt_view.type);
3565
3566         if (!vma->ggtt_view.pages) {
3567                 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
3568                           vma->ggtt_view.type);
3569                 ret = -EINVAL;
3570         } else if (IS_ERR(vma->ggtt_view.pages)) {
3571                 ret = PTR_ERR(vma->ggtt_view.pages);
3572                 vma->ggtt_view.pages = NULL;
3573                 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3574                           vma->ggtt_view.type, ret);
3575         }
3576
3577         return ret;
3578 }
3579
3580 /**
3581  * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3582  * @vma: VMA to map
3583  * @cache_level: mapping cache level
3584  * @flags: flags like global or local mapping
3585  *
3586  * DMA addresses are taken from the scatter-gather table of this object (or of
3587  * this VMA in case of non-default GGTT views) and PTE entries set up.
3588  * Note that DMA addresses are also the only part of the SG table we care about.
3589  */
3590 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3591                   u32 flags)
3592 {
3593         int ret;
3594         u32 bind_flags;
3595
3596         if (WARN_ON(flags == 0))
3597                 return -EINVAL;
3598
3599         bind_flags = 0;
3600         if (flags & PIN_GLOBAL)
3601                 bind_flags |= GLOBAL_BIND;
3602         if (flags & PIN_USER)
3603                 bind_flags |= LOCAL_BIND;
3604
3605         if (flags & PIN_UPDATE)
3606                 bind_flags |= vma->bound;
3607         else
3608                 bind_flags &= ~vma->bound;
3609
3610         if (bind_flags == 0)
3611                 return 0;
3612
3613         if (vma->bound == 0 && vma->vm->allocate_va_range) {
3614                 trace_i915_va_alloc(vma->vm,
3615                                     vma->node.start,
3616                                     vma->node.size,
3617                                     VM_TO_TRACE_NAME(vma->vm));
3618
3619                 /* XXX: i915_vma_pin() will fix this +- hack */
3620                 vma->pin_count++;
3621                 ret = vma->vm->allocate_va_range(vma->vm,
3622                                                  vma->node.start,
3623                                                  vma->node.size);
3624                 vma->pin_count--;
3625                 if (ret)
3626                         return ret;
3627         }
3628
3629         ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
3630         if (ret)
3631                 return ret;
3632
3633         vma->bound |= bind_flags;
3634
3635         return 0;
3636 }
3637
3638 /**
3639  * i915_ggtt_view_size - Get the size of a GGTT view.
3640  * @obj: Object the view is of.
3641  * @view: The view in question.
3642  *
3643  * @return The size of the GGTT view in bytes.
3644  */
3645 size_t
3646 i915_ggtt_view_size(struct drm_i915_gem_object *obj,
3647                     const struct i915_ggtt_view *view)
3648 {
3649         if (view->type == I915_GGTT_VIEW_NORMAL) {
3650                 return obj->base.size;
3651         } else if (view->type == I915_GGTT_VIEW_ROTATED) {
3652                 return view->rotation_info.size;
3653         } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
3654                 return view->params.partial.size << PAGE_SHIFT;
3655         } else {
3656                 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
3657                 return obj->base.size;
3658         }
3659 }