2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $
33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.24 2005/06/06 15:27:28 joerg Exp $
37 * 3Com 3c90x Etherlink XL PCI NIC driver
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
79 * The 3c90x series chips use a bus-master DMA interface for transfering
80 * packets to and from the controller chip. Some of the "vortex" cards
81 * (3c59x) also supported a bus master mode, however for those chips
82 * you could only DMA packets to/from a contiguous memory buffer. For
83 * transmission this would mean copying the contents of the queued mbuf
84 * chain into an mbuf cluster and then DMAing the cluster. This extra
85 * copy would sort of defeat the purpose of the bus master support for
86 * any packet that doesn't fit into a single mbuf.
88 * By contrast, the 3c90x cards support a fragment-based bus master
89 * mode where mbuf chains can be encapsulated using TX descriptors.
90 * This is similar to other PCI chips such as the Texas Instruments
91 * ThunderLAN and the Intel 82557/82558.
93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
94 * bus master chips because they maintain the old PIO interface for
95 * backwards compatibility, but starting with the 3c905B and the
96 * "cyclone" chips, the compatibility interface has been dropped.
97 * Since using bus master DMA is a big win, we use this driver to
98 * support the PCI "boomerang" chips even though they work with the
99 * "vortex" driver in order to obtain better performance.
102 #include <sys/param.h>
103 #include <sys/systm.h>
104 #include <sys/sockio.h>
105 #include <sys/endian.h>
106 #include <sys/mbuf.h>
107 #include <sys/kernel.h>
108 #include <sys/socket.h>
111 #include <net/ifq_var.h>
112 #include <net/if_arp.h>
113 #include <net/ethernet.h>
114 #include <net/if_dl.h>
115 #include <net/if_media.h>
116 #include <net/vlan/if_vlan_var.h>
120 #include <machine/bus_memio.h>
121 #include <machine/bus_pio.h>
122 #include <machine/bus.h>
123 #include <machine/clock.h> /* for DELAY */
124 #include <machine/resource.h>
126 #include <sys/rman.h>
128 #include "../mii_layer/mii.h"
129 #include "../mii_layer/miivar.h"
131 #include <bus/pci/pcireg.h>
132 #include <bus/pci/pcivar.h>
134 /* "controller miibus0" required. See GENERIC if you get errors here. */
135 #include "miibus_if.h"
137 #include "if_xlreg.h"
139 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
142 * Various supported device vendors/types and their names.
144 static struct xl_type xl_devs[] = {
145 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
146 "3Com 3c900-TPO Etherlink XL" },
147 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
148 "3Com 3c900-COMBO Etherlink XL" },
149 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
150 "3Com 3c905-TX Fast Etherlink XL" },
151 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
152 "3Com 3c905-T4 Fast Etherlink XL" },
153 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
154 "3Com 3c900B-TPO Etherlink XL" },
155 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
156 "3Com 3c900B-COMBO Etherlink XL" },
157 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
158 "3Com 3c900B-TPC Etherlink XL" },
159 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
160 "3Com 3c900B-FL Etherlink XL" },
161 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
162 "3Com 3c905B-TX Fast Etherlink XL" },
163 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
164 "3Com 3c905B-T4 Fast Etherlink XL" },
165 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
166 "3Com 3c905B-FX/SC Fast Etherlink XL" },
167 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
168 "3Com 3c905B-COMBO Fast Etherlink XL" },
169 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
170 "3Com 3c905C-TX Fast Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
172 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
174 "3Com 3c980 Fast Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
176 "3Com 3c980C Fast Etherlink XL" },
177 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
178 "3Com 3cSOHO100-TX OfficeConnect" },
179 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
180 "3Com 3c450-TX HomeConnect" },
181 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
182 "3Com 3c555 Fast Etherlink XL" },
183 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
184 "3Com 3c556 Fast Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
186 "3Com 3c556B Fast Etherlink XL" },
187 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
188 "3Com 3c575TX Fast Etherlink XL" },
189 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
190 "3Com 3c575B Fast Etherlink XL" },
191 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
192 "3Com 3c575C Fast Etherlink XL" },
193 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
194 "3Com 3c656 Fast Etherlink XL" },
195 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
196 "3Com 3c656B Fast Etherlink XL" },
197 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
198 "3Com 3c656C Fast Etherlink XL" },
202 static int xl_probe (device_t);
203 static int xl_attach (device_t);
204 static int xl_detach (device_t);
206 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *);
207 static void xl_stats_update (void *);
208 static int xl_encap (struct xl_softc *, struct xl_chain *,
210 static void xl_rxeof (struct xl_softc *);
211 static int xl_rx_resync (struct xl_softc *);
212 static void xl_txeof (struct xl_softc *);
213 static void xl_txeof_90xB (struct xl_softc *);
214 static void xl_txeoc (struct xl_softc *);
215 static void xl_intr (void *);
216 static void xl_start (struct ifnet *);
217 static void xl_start_90xB (struct ifnet *);
218 static int xl_ioctl (struct ifnet *, u_long, caddr_t,
220 static void xl_init (void *);
221 static void xl_stop (struct xl_softc *);
222 static void xl_watchdog (struct ifnet *);
223 static void xl_shutdown (device_t);
224 static int xl_suspend (device_t);
225 static int xl_resume (device_t);
227 static int xl_ifmedia_upd (struct ifnet *);
228 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
230 static int xl_eeprom_wait (struct xl_softc *);
231 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int);
232 static void xl_mii_sync (struct xl_softc *);
233 static void xl_mii_send (struct xl_softc *, u_int32_t, int);
234 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *);
235 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *);
237 static void xl_setcfg (struct xl_softc *);
238 static void xl_setmode (struct xl_softc *, int);
239 static u_int8_t xl_calchash (caddr_t);
240 static void xl_setmulti (struct xl_softc *);
241 static void xl_setmulti_hash (struct xl_softc *);
242 static void xl_reset (struct xl_softc *);
243 static int xl_list_rx_init (struct xl_softc *);
244 static int xl_list_tx_init (struct xl_softc *);
245 static int xl_list_tx_init_90xB (struct xl_softc *);
246 static void xl_wait (struct xl_softc *);
247 static void xl_mediacheck (struct xl_softc *);
248 static void xl_choose_xcvr (struct xl_softc *, int);
249 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int);
250 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t,
252 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t,
255 static void xl_testpacket (struct xl_softc *);
258 static int xl_miibus_readreg (device_t, int, int);
259 static int xl_miibus_writereg (device_t, int, int, int);
260 static void xl_miibus_statchg (device_t);
261 static void xl_miibus_mediainit (device_t);
263 static device_method_t xl_methods[] = {
264 /* Device interface */
265 DEVMETHOD(device_probe, xl_probe),
266 DEVMETHOD(device_attach, xl_attach),
267 DEVMETHOD(device_detach, xl_detach),
268 DEVMETHOD(device_shutdown, xl_shutdown),
269 DEVMETHOD(device_suspend, xl_suspend),
270 DEVMETHOD(device_resume, xl_resume),
273 DEVMETHOD(bus_print_child, bus_generic_print_child),
274 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
277 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
278 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
279 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
280 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
285 static driver_t xl_driver = {
288 sizeof(struct xl_softc)
291 static devclass_t xl_devclass;
293 DECLARE_DUMMY_MODULE(if_xl);
294 MODULE_DEPEND(if_xl, miibus, 1, 1, 1);
295 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0);
296 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
299 xl_dma_map_addr(arg, segs, nseg, error)
301 bus_dma_segment_t *segs;
307 *paddr = segs->ds_addr;
311 xl_dma_map_rxbuf(arg, segs, nseg, mapsize, error)
313 bus_dma_segment_t *segs;
322 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments"));
324 *paddr = segs->ds_addr;
328 xl_dma_map_txbuf(arg, segs, nseg, mapsize, error)
330 bus_dma_segment_t *segs;
341 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments"));
345 for (i = 0; i < nseg; i++) {
346 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
347 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr);
348 l->xl_frag[i].xl_len = htole32(segs[i].ds_len);
349 total_len += segs[i].ds_len;
351 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len |
353 l->xl_status = htole32(total_len);
358 * Murphy's law says that it's possible the chip can wedge and
359 * the 'command in progress' bit may never clear. Hence, we wait
360 * only a finite amount of time to avoid getting caught in an
361 * infinite loop. Normally this delay routine would be a macro,
362 * but it isn't called during normal operation so we can afford
363 * to make it a function.
371 for (i = 0; i < XL_TIMEOUT; i++) {
372 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
377 if_printf(&sc->arpcom.ac_if, "command never completed!");
383 * MII access routines are provided for adapters with external
384 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
385 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
386 * Note: if you don't perform the MDIO operations just right,
387 * it's possible to end up with code that works correctly with
388 * some chips/CPUs/processor speeds/bus speeds/etc but not
392 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
393 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
396 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
397 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
400 * Sync the PHYs by setting data bit and strobing the clock 32 times.
409 MII_SET(XL_MII_DIR|XL_MII_DATA);
411 for (i = 0; i < 32; i++) {
413 MII_SET(XL_MII_DATA);
414 MII_SET(XL_MII_DATA);
416 MII_SET(XL_MII_DATA);
417 MII_SET(XL_MII_DATA);
424 * Clock a series of bits through the MII.
427 xl_mii_send(sc, bits, cnt)
437 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
439 MII_SET(XL_MII_DATA);
441 MII_CLR(XL_MII_DATA);
449 * Read an PHY register through the MII.
452 xl_mii_readreg(sc, frame)
454 struct xl_mii_frame *frame;
462 * Set up frame for RX.
464 frame->mii_stdelim = XL_MII_STARTDELIM;
465 frame->mii_opcode = XL_MII_READOP;
466 frame->mii_turnaround = 0;
470 * Select register window 4.
475 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
484 * Send command/address info.
486 xl_mii_send(sc, frame->mii_stdelim, 2);
487 xl_mii_send(sc, frame->mii_opcode, 2);
488 xl_mii_send(sc, frame->mii_phyaddr, 5);
489 xl_mii_send(sc, frame->mii_regaddr, 5);
492 MII_CLR((XL_MII_CLK|XL_MII_DATA));
500 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
504 * Now try reading data bits. If the ack failed, we still
505 * need to clock through 16 cycles to keep the PHY(s) in sync.
508 for(i = 0; i < 16; i++) {
515 for (i = 0x8000; i; i >>= 1) {
518 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
519 frame->mii_data |= i;
537 * Write to a PHY register through the MII.
540 xl_mii_writereg(sc, frame)
542 struct xl_mii_frame *frame;
550 * Set up frame for TX.
553 frame->mii_stdelim = XL_MII_STARTDELIM;
554 frame->mii_opcode = XL_MII_WRITEOP;
555 frame->mii_turnaround = XL_MII_TURNAROUND;
558 * Select the window 4.
563 * Turn on data output.
569 xl_mii_send(sc, frame->mii_stdelim, 2);
570 xl_mii_send(sc, frame->mii_opcode, 2);
571 xl_mii_send(sc, frame->mii_phyaddr, 5);
572 xl_mii_send(sc, frame->mii_regaddr, 5);
573 xl_mii_send(sc, frame->mii_turnaround, 2);
574 xl_mii_send(sc, frame->mii_data, 16);
591 xl_miibus_readreg(dev, phy, reg)
596 struct xl_mii_frame frame;
598 sc = device_get_softc(dev);
601 * Pretend that PHYs are only available at MII address 24.
602 * This is to guard against problems with certain 3Com ASIC
603 * revisions that incorrectly map the internal transceiver
604 * control registers at all MII addresses. This can cause
605 * the miibus code to attach the same PHY several times over.
607 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
610 bzero((char *)&frame, sizeof(frame));
612 frame.mii_phyaddr = phy;
613 frame.mii_regaddr = reg;
614 xl_mii_readreg(sc, &frame);
616 return(frame.mii_data);
620 xl_miibus_writereg(dev, phy, reg, data)
625 struct xl_mii_frame frame;
627 sc = device_get_softc(dev);
629 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
632 bzero((char *)&frame, sizeof(frame));
634 frame.mii_phyaddr = phy;
635 frame.mii_regaddr = reg;
636 frame.mii_data = data;
638 xl_mii_writereg(sc, &frame);
644 xl_miibus_statchg(dev)
648 struct mii_data *mii;
651 sc = device_get_softc(dev);
652 mii = device_get_softc(sc->xl_miibus);
656 /* Set ASIC's duplex mode to match the PHY. */
658 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
659 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
661 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
662 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
668 * Special support for the 3c905B-COMBO. This card has 10/100 support
669 * plus BNC and AUI ports. This means we will have both an miibus attached
670 * plus some non-MII media settings. In order to allow this, we have to
671 * add the extra media to the miibus's ifmedia struct, but we can't do
672 * that during xl_attach() because the miibus hasn't been attached yet.
673 * So instead, we wait until the miibus probe/attach is done, at which
674 * point we will get a callback telling is that it's safe to add our
678 xl_miibus_mediainit(dev)
682 struct mii_data *mii;
685 sc = device_get_softc(dev);
686 mii = device_get_softc(sc->xl_miibus);
687 ifm = &mii->mii_media;
689 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
691 * Check for a 10baseFL board in disguise.
693 if (sc->xl_type == XL_TYPE_905B &&
694 sc->xl_media == XL_MEDIAOPT_10FL) {
696 device_printf(dev, "found 10baseFL\n");
697 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL);
698 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL);
699 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
701 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
704 device_printf(dev, "found AUI\n");
705 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL);
709 if (sc->xl_media & XL_MEDIAOPT_BNC) {
711 device_printf(dev, "found BNC\n");
712 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL);
719 * The EEPROM is slow: give it time to come ready after issuing
728 for (i = 0; i < 100; i++) {
729 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
736 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n");
744 * Read a sequence of words from the EEPROM. Note that ethernet address
745 * data is stored in the EEPROM in network byte order.
748 xl_read_eeprom(sc, dest, off, cnt, swap)
756 u_int16_t word = 0, *ptr;
757 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
758 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
760 * It's easy to accidentally overwrite the rom content!
761 * Note: the 3c575 uses 8bit EEPROM offsets.
765 if (xl_eeprom_wait(sc))
768 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
771 for (i = 0; i < cnt; i++) {
772 if (sc->xl_flags & XL_FLAG_8BITROM)
773 CSR_WRITE_2(sc, XL_W0_EE_CMD,
774 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
776 CSR_WRITE_2(sc, XL_W0_EE_CMD,
777 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
778 err = xl_eeprom_wait(sc);
781 word = CSR_READ_2(sc, XL_W0_EE_DATA);
782 ptr = (u_int16_t *)(dest + (i * 2));
793 * This routine is taken from the 3Com Etherlink XL manual,
794 * page 10-7. It calculates a CRC of the supplied multicast
795 * group address and returns the lower 8 bits, which are used
796 * as the multicast filter position.
797 * Note: the 3c905B currently only supports a 64-bit hash table,
798 * which means we really only need 6 bits, but the manual indicates
799 * that future chip revisions will have a 256-bit hash table,
800 * hence the routine is set up to calculate 8 bits of position
801 * info in case we need it some day.
802 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have a
803 * 256 bit hash table. This means we have to use all 8 bits regardless.
804 * On older cards, the upper 2 bits will be ignored. Grrrr....
806 static u_int8_t xl_calchash(addr)
809 u_int32_t crc, carry;
813 /* Compute CRC for the address value. */
814 crc = 0xFFFFFFFF; /* initial value */
816 for (i = 0; i < 6; i++) {
818 for (j = 0; j < 8; j++) {
819 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
823 crc = (crc ^ 0x04c11db6) | carry;
827 /* return the filter bit position */
828 return(crc & 0x000000FF);
832 * NICs older than the 3c905B have only one multicast option, which
833 * is to enable reception of all multicast frames.
840 struct ifmultiaddr *ifma;
844 ifp = &sc->arpcom.ac_if;
847 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
849 if (ifp->if_flags & IFF_ALLMULTI) {
850 rxfilt |= XL_RXFILTER_ALLMULTI;
851 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
855 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
856 ifma = ifma->ifma_link.le_next)
860 rxfilt |= XL_RXFILTER_ALLMULTI;
862 rxfilt &= ~XL_RXFILTER_ALLMULTI;
864 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
870 * 3c905B adapters have a hash filter that we can program.
878 struct ifmultiaddr *ifma;
882 ifp = &sc->arpcom.ac_if;
885 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
887 if (ifp->if_flags & IFF_ALLMULTI) {
888 rxfilt |= XL_RXFILTER_ALLMULTI;
889 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
892 rxfilt &= ~XL_RXFILTER_ALLMULTI;
895 /* first, zot all the existing hash bits */
896 for (i = 0; i < XL_HASHFILT_SIZE; i++)
897 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
899 /* now program new ones */
900 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
901 ifma = ifma->ifma_link.le_next) {
902 if (ifma->ifma_addr->sa_family != AF_LINK)
904 h = xl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
905 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
910 rxfilt |= XL_RXFILTER_MULTIHASH;
912 rxfilt &= ~XL_RXFILTER_MULTIHASH;
914 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
927 ifp = &sc->arpcom.ac_if;
929 MGETHDR(m, MB_DONTWAIT, MT_DATA);
934 bcopy(&sc->arpcom.ac_enaddr,
935 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
936 bcopy(&sc->arpcom.ac_enaddr,
937 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
938 mtod(m, struct ether_header *)->ether_type = htons(3);
939 mtod(m, unsigned char *)[14] = 0;
940 mtod(m, unsigned char *)[15] = 0;
941 mtod(m, unsigned char *)[16] = 0xE3;
942 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
943 IF_ENQUEUE(&ifp->if_snd, m);
957 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
958 icfg &= ~XL_ICFG_CONNECTOR_MASK;
959 if (sc->xl_media & XL_MEDIAOPT_MII ||
960 sc->xl_media & XL_MEDIAOPT_BT4)
961 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
962 if (sc->xl_media & XL_MEDIAOPT_BTX)
963 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
965 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
966 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
972 xl_setmode(sc, media)
976 struct ifnet *ifp = &sc->arpcom.ac_if;
980 if_printf(ifp, "selecting ");
983 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
985 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
987 if (sc->xl_media & XL_MEDIAOPT_BT) {
988 if (IFM_SUBTYPE(media) == IFM_10_T) {
989 printf("10baseT transceiver, ");
990 sc->xl_xcvr = XL_XCVR_10BT;
991 icfg &= ~XL_ICFG_CONNECTOR_MASK;
992 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
993 mediastat |= XL_MEDIASTAT_LINKBEAT|
994 XL_MEDIASTAT_JABGUARD;
995 mediastat &= ~XL_MEDIASTAT_SQEENB;
999 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1000 if (IFM_SUBTYPE(media) == IFM_100_FX) {
1001 printf("100baseFX port, ");
1002 sc->xl_xcvr = XL_XCVR_100BFX;
1003 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1004 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
1005 mediastat |= XL_MEDIASTAT_LINKBEAT;
1006 mediastat &= ~XL_MEDIASTAT_SQEENB;
1010 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1011 if (IFM_SUBTYPE(media) == IFM_10_5) {
1012 printf("AUI port, ");
1013 sc->xl_xcvr = XL_XCVR_AUI;
1014 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1015 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
1016 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
1017 XL_MEDIASTAT_JABGUARD);
1018 mediastat |= ~XL_MEDIASTAT_SQEENB;
1020 if (IFM_SUBTYPE(media) == IFM_10_FL) {
1021 printf("10baseFL transceiver, ");
1022 sc->xl_xcvr = XL_XCVR_AUI;
1023 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1024 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
1025 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
1026 XL_MEDIASTAT_JABGUARD);
1027 mediastat |= ~XL_MEDIASTAT_SQEENB;
1031 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1032 if (IFM_SUBTYPE(media) == IFM_10_2) {
1033 printf("BNC port, ");
1034 sc->xl_xcvr = XL_XCVR_COAX;
1035 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1036 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
1037 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
1038 XL_MEDIASTAT_JABGUARD|
1039 XL_MEDIASTAT_SQEENB);
1043 if ((media & IFM_GMASK) == IFM_FDX ||
1044 IFM_SUBTYPE(media) == IFM_100_FX) {
1045 printf("full duplex\n");
1047 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
1049 printf("half duplex\n");
1051 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
1052 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
1055 if (IFM_SUBTYPE(media) == IFM_10_2)
1056 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
1058 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
1059 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
1061 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
1068 struct xl_softc *sc;
1073 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
1074 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
1075 XL_RESETOPT_DISADVFD:0));
1078 * If we're using memory mapped register mode, pause briefly
1079 * after issuing the reset command before trying to access any
1080 * other registers. With my 3c575C cardbus card, failing to do
1081 * this results in the system locking up while trying to poll
1082 * the command busy bit in the status register.
1084 if (sc->xl_flags & XL_FLAG_USE_MMIO)
1087 for (i = 0; i < XL_TIMEOUT; i++) {
1089 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
1093 if (i == XL_TIMEOUT)
1094 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n");
1096 /* Reset TX and RX. */
1097 /* Note: the RX reset takes an absurd amount of time
1098 * on newer versions of the Tornado chips such as those
1099 * on the 3c905CX and newer 3c908C cards. We wait an
1100 * extra amount of time so that xl_wait() doesn't complain
1101 * and annoy the users.
1103 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1106 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1109 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
1110 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
1112 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,
1113 XL_W2_RESET_OPTIONS)
1114 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0)
1115 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0)
1119 /* Wait a little while for the chip to get its brains in order. */
1125 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1126 * IDs against our list and return a device name if we find a match.
1136 while(t->xl_name != NULL) {
1137 if ((pci_get_vendor(dev) == t->xl_vid) &&
1138 (pci_get_device(dev) == t->xl_did)) {
1139 device_set_desc(dev, t->xl_name);
1149 * This routine is a kludge to work around possible hardware faults
1150 * or manufacturing defects that can cause the media options register
1151 * (or reset options register, as it's called for the first generation
1152 * 3c90x adapters) to return an incorrect result. I have encountered
1153 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1154 * which doesn't have any of the 'mediaopt' bits set. This screws up
1155 * the attach routine pretty badly because it doesn't know what media
1156 * to look for. If we find ourselves in this predicament, this routine
1157 * will try to guess the media options values and warn the user of a
1158 * possible manufacturing defect with his adapter/system/whatever.
1162 struct xl_softc *sc;
1164 struct ifnet *ifp = &sc->arpcom.ac_if;
1167 * If some of the media options bits are set, assume they are
1168 * correct. If not, try to figure it out down below.
1169 * XXX I should check for 10baseFL, but I don't have an adapter
1172 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1174 * Check the XCVR value. If it's not in the normal range
1175 * of values, we need to fake it up here.
1177 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1180 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n",
1183 "choosing new default based on card type\n");
1186 if (sc->xl_type == XL_TYPE_905B &&
1187 sc->xl_media & XL_MEDIAOPT_10FL)
1189 if_printf(ifp, "WARNING: no media options bits set in "
1190 "the media options register!!\n");
1191 if_printf(ifp, "this could be a manufacturing defect in "
1192 "your adapter or system\n");
1193 if_printf(ifp, "attempting to guess media type; you "
1194 "should probably consult your vendor\n");
1197 xl_choose_xcvr(sc, 1);
1201 xl_choose_xcvr(sc, verbose)
1202 struct xl_softc *sc;
1205 struct ifnet *ifp = &sc->arpcom.ac_if;
1209 * Read the device ID from the EEPROM.
1210 * This is what's loaded into the PCI device ID register, so it has
1211 * to be correct otherwise we wouldn't have gotten this far.
1213 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1216 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1217 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1218 sc->xl_media = XL_MEDIAOPT_BT;
1219 sc->xl_xcvr = XL_XCVR_10BT;
1221 if_printf(ifp, "guessing 10BaseT transceiver\n");
1223 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1224 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1225 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1226 sc->xl_xcvr = XL_XCVR_10BT;
1228 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n");
1230 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1231 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1232 sc->xl_xcvr = XL_XCVR_10BT;
1234 if_printf(ifp, "guessing TPC (BNC/TP)\n");
1236 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1237 sc->xl_media = XL_MEDIAOPT_10FL;
1238 sc->xl_xcvr = XL_XCVR_AUI;
1240 if_printf(ifp, "guessing 10baseFL\n");
1242 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1243 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1244 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1245 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1246 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1247 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1248 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1249 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1250 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1251 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1252 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1253 sc->xl_media = XL_MEDIAOPT_MII;
1254 sc->xl_xcvr = XL_XCVR_MII;
1256 if_printf(ifp, "guessing MII\n");
1258 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1259 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1260 sc->xl_media = XL_MEDIAOPT_BT4;
1261 sc->xl_xcvr = XL_XCVR_MII;
1263 if_printf(ifp, "guessing 100BaseT4/MII\n");
1265 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1266 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1267 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1268 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1269 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1270 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1271 sc->xl_media = XL_MEDIAOPT_BTX;
1272 sc->xl_xcvr = XL_XCVR_AUTO;
1274 if_printf(ifp, "guessing 10/100 internal\n");
1276 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1277 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1278 sc->xl_xcvr = XL_XCVR_AUTO;
1280 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n");
1284 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1285 sc->xl_media = XL_MEDIAOPT_BT;
1293 * Attach the interface. Allocate softc structures, do ifmedia
1294 * setup and ethernet/BPF attach.
1300 u_char eaddr[ETHER_ADDR_LEN];
1303 struct xl_softc *sc;
1305 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1306 int unit, error = 0, rid, res;
1308 sc = device_get_softc(dev);
1309 unit = device_get_unit(dev);
1311 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1314 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555)
1315 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1316 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 ||
1317 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1318 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1319 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1320 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1321 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555 ||
1322 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556)
1323 sc->xl_flags |= XL_FLAG_8BITROM;
1324 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1325 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1327 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A ||
1328 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B ||
1329 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C ||
1330 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B ||
1331 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1332 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1333 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM;
1334 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656)
1335 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1336 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B)
1337 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1338 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C)
1339 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1340 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1341 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1342 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 ||
1343 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B)
1344 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1345 XL_FLAG_INVERT_LED_PWR;
1346 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_10_100BT_920B)
1347 sc->xl_flags |= XL_FLAG_PHYOK;
1348 #ifndef BURN_BRIDGES
1350 * If this is a 3c905B, we have to check one extra thing.
1351 * The 905B supports power management and may be placed in
1352 * a low-power mode (D3 mode), typically by certain operating
1353 * systems which shall not be named. The PCI BIOS is supposed
1354 * to reset the NIC and bring it out of low-power mode, but
1355 * some do not. Consequently, we have to see if this chip
1356 * supports power management, and if so, make sure it's not
1357 * in low-power mode. If power management is available, the
1358 * capid byte will be 0x01.
1360 * I _think_ that what actually happens is that the chip
1361 * loses its PCI configuration during the transition from
1362 * D3 back to D0; this means that it should be possible for
1363 * us to save the PCI iobase, membase and IRQ, put the chip
1364 * back in the D0 state, then restore the PCI config ourselves.
1367 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1368 u_int32_t iobase, membase, irq;
1370 /* Save important PCI config data. */
1371 iobase = pci_read_config(dev, XL_PCI_LOIO, 4);
1372 membase = pci_read_config(dev, XL_PCI_LOMEM, 4);
1373 irq = pci_read_config(dev, XL_PCI_INTLINE, 4);
1375 /* Reset the power state. */
1376 device_printf(dev, "chip is in D%d power mode "
1377 "-- setting to D0\n", pci_get_powerstate(dev));
1379 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1381 /* Restore PCI config data. */
1382 pci_write_config(dev, XL_PCI_LOIO, iobase, 4);
1383 pci_write_config(dev, XL_PCI_LOMEM, membase, 4);
1384 pci_write_config(dev, XL_PCI_INTLINE, irq, 4);
1388 * Map control/status registers.
1390 pci_enable_busmaster(dev);
1391 pci_enable_io(dev, SYS_RES_IOPORT);
1392 pci_enable_io(dev, SYS_RES_MEMORY);
1393 command = pci_read_config(dev, PCIR_COMMAND, 4);
1395 if (!(command & PCIM_CMD_PORTEN) && !(command & PCIM_CMD_MEMEN)) {
1397 "failed to enable I/O ports and memory mappings!\n");
1403 res = SYS_RES_MEMORY;
1406 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1409 if (sc->xl_res != NULL) {
1410 sc->xl_flags |= XL_FLAG_USE_MMIO;
1412 device_printf(dev, "using memory mapped I/O\n");
1415 res = SYS_RES_IOPORT;
1416 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1417 if (sc->xl_res == NULL) {
1418 device_printf(dev, "couldn't map ports/memory\n");
1423 device_printf(dev, "using port I/O\n");
1426 sc->xl_btag = rman_get_bustag(sc->xl_res);
1427 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1429 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1430 rid = XL_PCI_FUNCMEM;
1431 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1434 if (sc->xl_fres == NULL) {
1435 device_printf(dev, "couldn't map ports/memory\n");
1440 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1441 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1444 /* Allocate interrupt */
1446 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1447 RF_SHAREABLE | RF_ACTIVE);
1448 if (sc->xl_irq == NULL) {
1449 device_printf(dev, "couldn't map interrupt\n");
1454 sc->xl_flags |= XL_FLAG_ATTACH_MAPPED;
1456 ifp = &sc->arpcom.ac_if;
1457 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1459 /* Reset the adapter. */
1463 * Get station address from the EEPROM.
1465 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1466 device_printf(dev, "failed to read station address\n");
1471 callout_init(&sc->xl_stat_timer);
1474 * Now allocate a tag for the DMA descriptor lists and a chunk
1475 * of DMA-able memory based on the tag. Also obtain the DMA
1476 * addresses of the RX and TX ring, which we'll need later.
1477 * All of our lists are allocated as a contiguous block
1480 error = bus_dma_tag_create(NULL, 8, 0,
1481 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1482 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0,
1483 &sc->xl_ldata.xl_rx_tag);
1485 device_printf(dev, "failed to allocate rx dma tag\n");
1489 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1490 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT,
1491 &sc->xl_ldata.xl_rx_dmamap);
1493 device_printf(dev, "no memory for rx list buffers!\n");
1494 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1495 sc->xl_ldata.xl_rx_tag = NULL;
1499 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1500 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1501 XL_RX_LIST_SZ, xl_dma_map_addr,
1502 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1504 device_printf(dev, "cannot get dma address of the rx ring!\n");
1505 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1506 sc->xl_ldata.xl_rx_dmamap);
1507 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1508 sc->xl_ldata.xl_rx_tag = NULL;
1512 error = bus_dma_tag_create(NULL, 8, 0,
1513 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1514 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0,
1515 &sc->xl_ldata.xl_tx_tag);
1517 device_printf(dev, "failed to allocate tx dma tag\n");
1521 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1522 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT,
1523 &sc->xl_ldata.xl_tx_dmamap);
1525 device_printf(dev, "no memory for list buffers!\n");
1526 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1527 sc->xl_ldata.xl_tx_tag = NULL;
1531 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1532 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1533 XL_TX_LIST_SZ, xl_dma_map_addr,
1534 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1536 device_printf(dev, "cannot get dma address of the tx ring!\n");
1537 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1538 sc->xl_ldata.xl_tx_dmamap);
1539 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1540 sc->xl_ldata.xl_tx_tag = NULL;
1545 * Allocate a DMA tag for the mapping of mbufs.
1547 error = bus_dma_tag_create(NULL, 1, 0,
1548 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1549 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0,
1552 device_printf(dev, "failed to allocate mbuf dma tag\n");
1556 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
1557 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
1559 /* We need a spare DMA map for the RX ring. */
1560 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1565 * Figure out the card type. 3c905B adapters have the
1566 * 'supportsNoTxLength' bit set in the capabilities
1567 * word in the EEPROM.
1568 * Note: my 3c575C cardbus card lies. It returns a value
1569 * of 0x1578 for its capabilities word, which is somewhat
1570 * nonsensical. Another way to distinguish a 3c90x chip
1571 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1572 * bit. This will only be set for 3c90x boomerage chips.
1574 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1575 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1576 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1577 sc->xl_type = XL_TYPE_905B;
1579 sc->xl_type = XL_TYPE_90X;
1582 ifp->if_mtu = ETHERMTU;
1583 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1584 ifp->if_ioctl = xl_ioctl;
1585 ifp->if_capabilities = 0;
1586 if (sc->xl_type == XL_TYPE_905B) {
1587 ifp->if_start = xl_start_90xB;
1588 ifp->if_capabilities |= IFCAP_HWCSUM;
1590 ifp->if_start = xl_start;
1592 ifp->if_watchdog = xl_watchdog;
1593 ifp->if_init = xl_init;
1594 ifp->if_baudrate = 10000000;
1595 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1596 ifq_set_ready(&ifp->if_snd);
1598 * NOTE: features disabled by default. This seems to corrupt
1599 * tx packet data one out of a million packets or so and then
1600 * generates a good checksum so the receiver doesn't
1601 * know the packet is bad
1603 ifp->if_capenable = 0; /*ifp->if_capabilities;*/
1604 if (ifp->if_capenable & IFCAP_TXCSUM)
1605 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1608 * Now we have to see what sort of media we have.
1609 * This includes probing for an MII interace and a
1613 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1615 if_printf(ifp, "media options word: %x\n", sc->xl_media);
1617 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1618 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1619 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1620 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1624 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
1625 || sc->xl_media & XL_MEDIAOPT_BT4) {
1627 if_printf(ifp, "found MII/AUTO\n");
1629 if (mii_phy_probe(dev, &sc->xl_miibus,
1630 xl_ifmedia_upd, xl_ifmedia_sts)) {
1631 if_printf(ifp, "no PHY found!\n");
1640 * Sanity check. If the user has selected "auto" and this isn't
1641 * a 10/100 card of some kind, we need to force the transceiver
1642 * type to something sane.
1644 if (sc->xl_xcvr == XL_XCVR_AUTO)
1645 xl_choose_xcvr(sc, bootverbose);
1650 if (sc->xl_media & XL_MEDIAOPT_BT) {
1652 if_printf(ifp, "found 10baseT\n");
1653 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1654 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1655 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1656 ifmedia_add(&sc->ifmedia,
1657 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1660 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1662 * Check for a 10baseFL board in disguise.
1664 if (sc->xl_type == XL_TYPE_905B &&
1665 sc->xl_media == XL_MEDIAOPT_10FL) {
1667 if_printf(ifp, "found 10baseFL\n");
1668 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1669 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1671 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1672 ifmedia_add(&sc->ifmedia,
1673 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1676 if_printf(ifp, "found AUI\n");
1677 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1681 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1683 if_printf(ifp, "found BNC\n");
1684 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1687 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1689 if_printf(ifp, "found 100baseFX\n");
1690 ifp->if_baudrate = 100000000;
1691 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1694 /* Choose a default media. */
1695 switch(sc->xl_xcvr) {
1697 media = IFM_ETHER|IFM_10_T;
1698 xl_setmode(sc, media);
1701 if (sc->xl_type == XL_TYPE_905B &&
1702 sc->xl_media == XL_MEDIAOPT_10FL) {
1703 media = IFM_ETHER|IFM_10_FL;
1704 xl_setmode(sc, media);
1706 media = IFM_ETHER|IFM_10_5;
1707 xl_setmode(sc, media);
1711 media = IFM_ETHER|IFM_10_2;
1712 xl_setmode(sc, media);
1715 case XL_XCVR_100BTX:
1717 /* Chosen by miibus */
1719 case XL_XCVR_100BFX:
1720 media = IFM_ETHER|IFM_100_FX;
1723 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr);
1725 * This will probably be wrong, but it prevents
1726 * the ifmedia code from panicking.
1728 media = IFM_ETHER|IFM_10_T;
1732 if (sc->xl_miibus == NULL)
1733 ifmedia_set(&sc->ifmedia, media);
1737 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1739 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1743 * Call MI attach routine.
1745 ether_ifattach(ifp, eaddr);
1748 * Tell the upper layer(s) we support long frames.
1750 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1752 /* Hook interrupt last to avoid having to lock softc */
1753 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET,
1754 xl_intr, sc, &sc->xl_intrhand, NULL);
1756 if_printf(ifp, "couldn't set up irq\n");
1757 ether_ifdetach(ifp);
1769 * Shutdown hardware and free up resources. This can be called any
1770 * time after the mutex has been initialized. It is called in both
1771 * the error case in attach and the normal detach case so it needs
1772 * to be careful about only freeing resources that have actually been
1779 struct xl_softc *sc;
1786 sc = device_get_softc(dev);
1787 ifp = &sc->arpcom.ac_if;
1789 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1791 res = SYS_RES_MEMORY;
1794 res = SYS_RES_IOPORT;
1798 * Only try to communicate with the device if we were able to map
1799 * the ports. This flag is set before ether_ifattach() so it also
1800 * governs our call to ether_ifdetach().
1802 if (sc->xl_flags & XL_FLAG_ATTACH_MAPPED) {
1805 ether_ifdetach(ifp);
1809 device_delete_child(dev, sc->xl_miibus);
1810 bus_generic_detach(dev);
1811 ifmedia_removeall(&sc->ifmedia);
1813 if (sc->xl_intrhand)
1814 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1816 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1817 if (sc->xl_fres != NULL)
1818 bus_release_resource(dev, SYS_RES_MEMORY,
1819 XL_PCI_FUNCMEM, sc->xl_fres);
1821 bus_release_resource(dev, res, rid, sc->xl_res);
1824 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1825 bus_dma_tag_destroy(sc->xl_mtag);
1827 if (sc->xl_ldata.xl_rx_tag) {
1828 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1829 sc->xl_ldata.xl_rx_dmamap);
1830 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1831 sc->xl_ldata.xl_rx_dmamap);
1832 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1834 if (sc->xl_ldata.xl_tx_tag) {
1835 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1836 sc->xl_ldata.xl_tx_dmamap);
1837 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1838 sc->xl_ldata.xl_tx_dmamap);
1839 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1848 * Initialize the transmit descriptors.
1852 struct xl_softc *sc;
1854 struct xl_chain_data *cd;
1855 struct xl_list_data *ld;
1860 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1861 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1862 error = bus_dmamap_create(sc->xl_mtag, 0,
1863 &cd->xl_tx_chain[i].xl_map);
1866 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1867 i * sizeof(struct xl_list);
1868 if (i == (XL_TX_LIST_CNT - 1))
1869 cd->xl_tx_chain[i].xl_next = NULL;
1871 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1874 cd->xl_tx_free = &cd->xl_tx_chain[0];
1875 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1877 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1882 * Initialize the transmit descriptors.
1885 xl_list_tx_init_90xB(sc)
1886 struct xl_softc *sc;
1888 struct xl_chain_data *cd;
1889 struct xl_list_data *ld;
1894 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1895 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1896 error = bus_dmamap_create(sc->xl_mtag, 0,
1897 &cd->xl_tx_chain[i].xl_map);
1900 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1901 i * sizeof(struct xl_list);
1902 if (i == (XL_TX_LIST_CNT - 1))
1903 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1905 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1907 cd->xl_tx_chain[i].xl_prev =
1908 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1910 cd->xl_tx_chain[i].xl_prev =
1911 &cd->xl_tx_chain[i - 1];
1914 bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1915 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1921 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1926 * Initialize the RX descriptors and allocate mbufs for them. Note that
1927 * we arrange the descriptors in a closed ring, so that the last descriptor
1928 * points back to the first.
1932 struct xl_softc *sc;
1934 struct xl_chain_data *cd;
1935 struct xl_list_data *ld;
1942 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1943 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1944 error = bus_dmamap_create(sc->xl_mtag, 0,
1945 &cd->xl_rx_chain[i].xl_map);
1948 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1951 if (i == (XL_RX_LIST_CNT - 1))
1955 nextptr = ld->xl_rx_dmaaddr +
1956 next * sizeof(struct xl_list_onefrag);
1957 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1958 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1961 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1962 cd->xl_rx_head = &cd->xl_rx_chain[0];
1968 * Initialize an RX descriptor and attach an MBUF cluster.
1969 * If we fail to do so, we need to leave the old mbuf and
1970 * the old DMA map untouched so that it can be reused.
1974 struct xl_softc *sc;
1975 struct xl_chain_onefrag *c;
1977 struct mbuf *m_new = NULL;
1982 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1986 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1988 /* Force longword alignment for packet payload. */
1989 m_adj(m_new, ETHER_ALIGN);
1991 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new,
1992 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT);
1995 if_printf(&sc->arpcom.ac_if, "can't map mbuf (error %d)\n",
2000 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
2002 c->xl_map = sc->xl_tmpmap;
2003 sc->xl_tmpmap = map;
2005 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
2006 c->xl_ptr->xl_status = 0;
2007 c->xl_ptr->xl_frag.xl_addr = htole32(baddr);
2008 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
2014 struct xl_softc *sc;
2016 struct xl_chain_onefrag *pos;
2019 pos = sc->xl_cdata.xl_rx_head;
2021 for (i = 0; i < XL_RX_LIST_CNT; i++) {
2022 if (pos->xl_ptr->xl_status)
2027 if (i == XL_RX_LIST_CNT)
2030 sc->xl_cdata.xl_rx_head = pos;
2036 * A frame has been uploaded: pass the resulting mbuf chain up to
2037 * the higher level protocols.
2041 struct xl_softc *sc;
2045 struct xl_chain_onefrag *cur_rx;
2049 ifp = &sc->arpcom.ac_if;
2053 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
2054 BUS_DMASYNC_POSTREAD);
2055 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
2056 cur_rx = sc->xl_cdata.xl_rx_head;
2057 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
2058 total_len = rxstat & XL_RXSTAT_LENMASK;
2061 * Since we have told the chip to allow large frames,
2062 * we need to trap giant frame errors in software. We allow
2063 * a little more than the normal frame size to account for
2064 * frames with VLAN tags.
2066 if (total_len > XL_MAX_FRAMELEN)
2067 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
2070 * If an error occurs, update stats, clear the
2071 * status word and leave the mbuf cluster in place:
2072 * it should simply get re-used next time this descriptor
2073 * comes up in the ring.
2075 if (rxstat & XL_RXSTAT_UP_ERROR) {
2077 cur_rx->xl_ptr->xl_status = 0;
2078 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2079 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2084 * If the error bit was not set, the upload complete
2085 * bit should be set which means we have a valid packet.
2086 * If not, something truly strange has happened.
2088 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
2090 "bad receive status -- packet dropped\n");
2092 cur_rx->xl_ptr->xl_status = 0;
2093 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2094 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2098 /* No errors; receive the packet. */
2099 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
2100 BUS_DMASYNC_POSTREAD);
2101 m = cur_rx->xl_mbuf;
2104 * Try to conjure up a new mbuf cluster. If that
2105 * fails, it means we have an out of memory condition and
2106 * should leave the buffer in place and continue. This will
2107 * result in a lost packet, but there's little else we
2108 * can do in this situation.
2110 if (xl_newbuf(sc, cur_rx)) {
2112 cur_rx->xl_ptr->xl_status = 0;
2113 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2114 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2117 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2118 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2121 m->m_pkthdr.rcvif = ifp;
2122 m->m_pkthdr.len = m->m_len = total_len;
2124 if (ifp->if_capenable & IFCAP_RXCSUM) {
2125 /* Do IP checksum checking. */
2126 if (rxstat & XL_RXSTAT_IPCKOK)
2127 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2128 if (!(rxstat & XL_RXSTAT_IPCKERR))
2129 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2130 if ((rxstat & XL_RXSTAT_TCPCOK &&
2131 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
2132 (rxstat & XL_RXSTAT_UDPCKOK &&
2133 !(rxstat & XL_RXSTAT_UDPCKERR))) {
2134 m->m_pkthdr.csum_flags |=
2135 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2136 m->m_pkthdr.csum_data = 0xffff;
2140 (*ifp->if_input)(ifp, m);
2144 * Handle the 'end of channel' condition. When the upload
2145 * engine hits the end of the RX ring, it will stall. This
2146 * is our cue to flush the RX ring, reload the uplist pointer
2147 * register and unstall the engine.
2148 * XXX This is actually a little goofy. With the ThunderLAN
2149 * chip, you get an interrupt when the receiver hits the end
2150 * of the receive ring, which tells you exactly when you
2151 * you need to reload the ring pointer. Here we have to
2152 * fake it. I'm mad at myself for not being clever enough
2153 * to avoid the use of a goto here.
2155 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2156 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2157 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2159 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2160 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2161 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2169 * A frame was downloaded to the chip. It's safe for us to clean up
2174 struct xl_softc *sc;
2176 struct xl_chain *cur_tx;
2179 ifp = &sc->arpcom.ac_if;
2181 /* Clear the timeout timer. */
2185 * Go through our tx list and free mbufs for those
2186 * frames that have been uploaded. Note: the 3c905B
2187 * sets a special bit in the status word to let us
2188 * know that a frame has been downloaded, but the
2189 * original 3c900/3c905 adapters don't do that.
2190 * Consequently, we have to use a different test if
2191 * xl_type != XL_TYPE_905B.
2193 while(sc->xl_cdata.xl_tx_head != NULL) {
2194 cur_tx = sc->xl_cdata.xl_tx_head;
2196 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2199 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2200 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2201 BUS_DMASYNC_POSTWRITE);
2202 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2203 m_freem(cur_tx->xl_mbuf);
2204 cur_tx->xl_mbuf = NULL;
2207 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2208 sc->xl_cdata.xl_tx_free = cur_tx;
2211 if (sc->xl_cdata.xl_tx_head == NULL) {
2212 ifp->if_flags &= ~IFF_OACTIVE;
2213 sc->xl_cdata.xl_tx_tail = NULL;
2215 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2216 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2217 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2218 sc->xl_cdata.xl_tx_head->xl_phys);
2219 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2228 struct xl_softc *sc;
2230 struct xl_chain *cur_tx = NULL;
2234 ifp = &sc->arpcom.ac_if;
2236 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2237 BUS_DMASYNC_POSTREAD);
2238 idx = sc->xl_cdata.xl_tx_cons;
2239 while(idx != sc->xl_cdata.xl_tx_prod) {
2241 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2243 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2244 XL_TXSTAT_DL_COMPLETE))
2247 if (cur_tx->xl_mbuf != NULL) {
2248 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2249 BUS_DMASYNC_POSTWRITE);
2250 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2251 m_freem(cur_tx->xl_mbuf);
2252 cur_tx->xl_mbuf = NULL;
2257 sc->xl_cdata.xl_tx_cnt--;
2258 XL_INC(idx, XL_TX_LIST_CNT);
2262 sc->xl_cdata.xl_tx_cons = idx;
2265 ifp->if_flags &= ~IFF_OACTIVE;
2271 * TX 'end of channel' interrupt handler. Actually, we should
2272 * only get a 'TX complete' interrupt if there's a transmit error,
2273 * so this is really TX error handler.
2277 struct xl_softc *sc;
2279 struct ifnet *ifp = &sc->arpcom.ac_if;
2282 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2283 if (txstat & XL_TXSTATUS_UNDERRUN ||
2284 txstat & XL_TXSTATUS_JABBER ||
2285 txstat & XL_TXSTATUS_RECLAIM) {
2286 if_printf(ifp, "transmission error: %x\n", txstat);
2287 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2289 if (sc->xl_type == XL_TYPE_905B) {
2290 if (sc->xl_cdata.xl_tx_cnt) {
2293 i = sc->xl_cdata.xl_tx_cons;
2294 c = &sc->xl_cdata.xl_tx_chain[i];
2295 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2297 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2300 if (sc->xl_cdata.xl_tx_head != NULL)
2301 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2302 sc->xl_cdata.xl_tx_head->xl_phys);
2305 * Remember to set this for the
2306 * first generation 3c90X chips.
2308 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2309 if (txstat & XL_TXSTATUS_UNDERRUN &&
2310 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2311 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2312 if_printf(ifp, "tx underrun, increasing tx start"
2313 " threshold to %d bytes\n",
2316 CSR_WRITE_2(sc, XL_COMMAND,
2317 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2318 if (sc->xl_type == XL_TYPE_905B) {
2319 CSR_WRITE_2(sc, XL_COMMAND,
2320 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2322 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2323 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2325 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2326 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2329 * Write an arbitrary byte to the TX_STATUS register
2330 * to clear this interrupt/error and advance to the next.
2332 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2342 struct xl_softc *sc;
2347 ifp = &sc->arpcom.ac_if;
2349 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) {
2351 CSR_WRITE_2(sc, XL_COMMAND,
2352 XL_CMD_INTR_ACK|(status & XL_INTRS));
2354 if (status & XL_STAT_UP_COMPLETE) {
2357 curpkts = ifp->if_ipackets;
2359 if (curpkts == ifp->if_ipackets) {
2360 while (xl_rx_resync(sc))
2365 if (status & XL_STAT_DOWN_COMPLETE) {
2366 if (sc->xl_type == XL_TYPE_905B)
2372 if (status & XL_STAT_TX_COMPLETE) {
2377 if (status & XL_STAT_ADFAIL) {
2382 if (status & XL_STAT_STATSOFLOW) {
2383 sc->xl_stats_no_timeout = 1;
2384 xl_stats_update(sc);
2385 sc->xl_stats_no_timeout = 0;
2389 if (!ifq_is_empty(&ifp->if_snd))
2390 (*ifp->if_start)(ifp);
2396 xl_stats_update(xsc)
2399 struct xl_softc *sc;
2401 struct xl_stats xl_stats;
2404 struct mii_data *mii = NULL;
2406 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2409 ifp = &sc->arpcom.ac_if;
2410 if (sc->xl_miibus != NULL)
2411 mii = device_get_softc(sc->xl_miibus);
2413 p = (u_int8_t *)&xl_stats;
2415 /* Read all the stats registers. */
2418 for (i = 0; i < 16; i++)
2419 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2421 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2423 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2424 xl_stats.xl_tx_single_collision +
2425 xl_stats.xl_tx_late_collision;
2428 * Boomerang and cyclone chips have an extra stats counter
2429 * in window 4 (BadSSD). We have to read this too in order
2430 * to clear out all the stats registers and avoid a statsoflow
2434 CSR_READ_1(sc, XL_W4_BADSSD);
2436 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2441 if (!sc->xl_stats_no_timeout)
2442 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
2448 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2449 * pointers to the fragment pointers.
2452 xl_encap(sc, c, m_head)
2453 struct xl_softc *sc;
2455 struct mbuf *m_head;
2461 ifp = &sc->arpcom.ac_if;
2464 * Start packing the mbufs in this chain into
2465 * the fragment pointers. Stop when we run out
2466 * of fragments or hit the end of the mbuf chain.
2468 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head,
2469 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2471 if (error && error != EFBIG) {
2473 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2478 * Handle special case: we used up all 63 fragments,
2479 * but we have more mbufs left in the chain. Copy the
2480 * data into an mbuf cluster. Note that we don't
2481 * bother clearing the values in the other fragment
2482 * pointers/counters; it wouldn't gain us anything,
2483 * and would waste cycles.
2488 m_new = m_defrag(m_head, MB_DONTWAIT);
2489 if (m_new == NULL) {
2496 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map,
2497 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2500 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2505 if (sc->xl_type == XL_TYPE_905B) {
2506 status = XL_TXSTAT_RND_DEFEAT;
2508 if (m_head->m_pkthdr.csum_flags) {
2509 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2510 status |= XL_TXSTAT_IPCKSUM;
2511 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2512 status |= XL_TXSTAT_TCPCKSUM;
2513 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2514 status |= XL_TXSTAT_UDPCKSUM;
2516 c->xl_ptr->xl_status = htole32(status);
2519 c->xl_mbuf = m_head;
2520 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2525 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2526 * to the mbuf data regions directly in the transmit lists. We also save a
2527 * copy of the pointers since the transmit list fragment pointers are
2528 * physical addresses.
2534 struct xl_softc *sc;
2535 struct mbuf *m_head = NULL;
2536 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2537 struct xl_chain *prev_tx;
2543 * Check for an available queue slot. If there are none,
2546 if (sc->xl_cdata.xl_tx_free == NULL) {
2549 if (sc->xl_cdata.xl_tx_free == NULL) {
2550 ifp->if_flags |= IFF_OACTIVE;
2555 start_tx = sc->xl_cdata.xl_tx_free;
2557 while(sc->xl_cdata.xl_tx_free != NULL) {
2558 m_head = ifq_dequeue(&ifp->if_snd);
2562 /* Pick a descriptor off the free list. */
2564 cur_tx = sc->xl_cdata.xl_tx_free;
2566 /* Pack the data into the descriptor. */
2567 error = xl_encap(sc, cur_tx, m_head);
2573 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2574 cur_tx->xl_next = NULL;
2576 /* Chain it together. */
2578 prev->xl_next = cur_tx;
2579 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2583 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2587 * If there are no packets queued, bail.
2589 if (cur_tx == NULL) {
2594 * Place the request for the upload interrupt
2595 * in the last descriptor in the chain. This way, if
2596 * we're chaining several packets at once, we'll only
2597 * get an interupt once for the whole chain rather than
2598 * once for each packet.
2600 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2602 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2603 BUS_DMASYNC_PREWRITE);
2606 * Queue the packets. If the TX channel is clear, update
2607 * the downlist pointer register.
2609 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2612 if (sc->xl_cdata.xl_tx_head != NULL) {
2613 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2614 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2615 htole32(start_tx->xl_phys);
2616 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2617 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2618 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2619 sc->xl_cdata.xl_tx_tail = cur_tx;
2621 sc->xl_cdata.xl_tx_head = start_tx;
2622 sc->xl_cdata.xl_tx_tail = cur_tx;
2624 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2625 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2627 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2632 * Set a timeout in case the chip goes out to lunch.
2637 * XXX Under certain conditions, usually on slower machines
2638 * where interrupts may be dropped, it's possible for the
2639 * adapter to chew up all the buffers in the receive ring
2640 * and stall, without us being able to do anything about it.
2641 * To guard against this, we need to make a pass over the
2642 * RX queue to make sure there aren't any packets pending.
2643 * Doing it here means we can flush the receive ring at the
2644 * same time the chip is DMAing the transmit descriptors we
2647 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2648 * nature of their chips in all their marketing literature;
2649 * we may as well take advantage of it. :)
2660 struct xl_softc *sc;
2661 struct mbuf *m_head = NULL;
2662 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2663 struct xl_chain *prev_tx;
2668 if (ifp->if_flags & IFF_OACTIVE) {
2672 idx = sc->xl_cdata.xl_tx_prod;
2673 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2675 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2677 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2678 ifp->if_flags |= IFF_OACTIVE;
2682 m_head = ifq_dequeue(&ifp->if_snd);
2687 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2689 /* Pack the data into the descriptor. */
2690 error = xl_encap(sc, cur_tx, m_head);
2696 /* Chain it together. */
2698 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2701 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2703 XL_INC(idx, XL_TX_LIST_CNT);
2704 sc->xl_cdata.xl_tx_cnt++;
2708 * If there are no packets queued, bail.
2710 if (cur_tx == NULL) {
2715 * Place the request for the upload interrupt
2716 * in the last descriptor in the chain. This way, if
2717 * we're chaining several packets at once, we'll only
2718 * get an interupt once for the whole chain rather than
2719 * once for each packet.
2721 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2723 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2724 BUS_DMASYNC_PREWRITE);
2726 /* Start transmission */
2727 sc->xl_cdata.xl_tx_prod = idx;
2728 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2731 * Set a timeout in case the chip goes out to lunch.
2742 struct xl_softc *sc = xsc;
2743 struct ifnet *ifp = &sc->arpcom.ac_if;
2745 u_int16_t rxfilt = 0;
2746 struct mii_data *mii = NULL;
2752 * Cancel pending I/O and free all RX/TX buffers.
2756 if (sc->xl_miibus == NULL) {
2757 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2760 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2764 if (sc->xl_miibus != NULL)
2765 mii = device_get_softc(sc->xl_miibus);
2767 /* Init our MAC address */
2769 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2770 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2771 sc->arpcom.ac_enaddr[i]);
2774 /* Clear the station mask. */
2775 for (i = 0; i < 3; i++)
2776 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2778 /* Reset TX and RX. */
2779 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2781 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2784 /* Init circular RX list. */
2785 error = xl_list_rx_init(sc);
2787 if_printf(ifp, "initialization of the rx ring failed (%d)\n",
2794 /* Init TX descriptors. */
2795 if (sc->xl_type == XL_TYPE_905B)
2796 error = xl_list_tx_init_90xB(sc);
2798 error = xl_list_tx_init(sc);
2800 if_printf(ifp, "initialization of the tx ring failed (%d)\n",
2807 * Set the TX freethresh value.
2808 * Note that this has no effect on 3c905B "cyclone"
2809 * cards but is required for 3c900/3c905 "boomerang"
2810 * cards in order to enable the download engine.
2812 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2814 /* Set the TX start threshold for best performance. */
2815 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2816 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2819 * If this is a 3c905B, also set the tx reclaim threshold.
2820 * This helps cut down on the number of tx reclaim errors
2821 * that could happen on a busy network. The chip multiplies
2822 * the register value by 16 to obtain the actual threshold
2823 * in bytes, so we divide by 16 when setting the value here.
2824 * The existing threshold value can be examined by reading
2825 * the register at offset 9 in window 5.
2827 if (sc->xl_type == XL_TYPE_905B) {
2828 CSR_WRITE_2(sc, XL_COMMAND,
2829 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2832 /* Set RX filter bits. */
2834 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2836 /* Set the individual bit to receive frames for this host only. */
2837 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2839 /* If we want promiscuous mode, set the allframes bit. */
2840 if (ifp->if_flags & IFF_PROMISC) {
2841 rxfilt |= XL_RXFILTER_ALLFRAMES;
2842 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2844 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2845 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2849 * Set capture broadcast bit to capture broadcast frames.
2851 if (ifp->if_flags & IFF_BROADCAST) {
2852 rxfilt |= XL_RXFILTER_BROADCAST;
2853 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2855 rxfilt &= ~XL_RXFILTER_BROADCAST;
2856 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2860 * Program the multicast filter, if necessary.
2862 if (sc->xl_type == XL_TYPE_905B)
2863 xl_setmulti_hash(sc);
2868 * Load the address of the RX list. We have to
2869 * stall the upload engine before we can manipulate
2870 * the uplist pointer register, then unstall it when
2871 * we're finished. We also have to wait for the
2872 * stall command to complete before proceeding.
2873 * Note that we have to do this after any RX resets
2874 * have completed since the uplist register is cleared
2877 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2879 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2880 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2884 if (sc->xl_type == XL_TYPE_905B) {
2885 /* Set polling interval */
2886 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2887 /* Load the address of the TX list */
2888 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2890 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2891 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2892 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2897 * If the coax transceiver is on, make sure to enable
2898 * the DC-DC converter.
2901 if (sc->xl_xcvr == XL_XCVR_COAX)
2902 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2904 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2907 * increase packet size to allow reception of 802.1q or ISL packets.
2908 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2909 * control register. For 3c90xB/C chips, use the RX packet size
2913 if (sc->xl_type == XL_TYPE_905B)
2914 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2917 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2918 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2919 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2922 /* Clear out the stats counters. */
2923 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2924 sc->xl_stats_no_timeout = 1;
2925 xl_stats_update(sc);
2926 sc->xl_stats_no_timeout = 0;
2928 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2929 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2932 * Enable interrupts.
2934 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2935 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2936 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2937 if (sc->xl_flags & XL_FLAG_FUNCREG)
2938 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2940 /* Set the RX early threshold */
2941 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2942 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2944 /* Enable receiver and transmitter. */
2945 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2947 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2953 /* Select window 7 for normal operations. */
2956 ifp->if_flags |= IFF_RUNNING;
2957 ifp->if_flags &= ~IFF_OACTIVE;
2959 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
2967 * Set media options.
2973 struct xl_softc *sc;
2974 struct ifmedia *ifm = NULL;
2975 struct mii_data *mii = NULL;
2978 if (sc->xl_miibus != NULL)
2979 mii = device_get_softc(sc->xl_miibus);
2983 ifm = &mii->mii_media;
2985 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2990 xl_setmode(sc, ifm->ifm_media);
2997 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
2998 || sc->xl_media & XL_MEDIAOPT_BT4) {
3001 xl_setmode(sc, ifm->ifm_media);
3008 * Report current media status.
3011 xl_ifmedia_sts(ifp, ifmr)
3013 struct ifmediareq *ifmr;
3015 struct xl_softc *sc;
3017 struct mii_data *mii = NULL;
3020 if (sc->xl_miibus != NULL)
3021 mii = device_get_softc(sc->xl_miibus);
3024 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
3025 icfg >>= XL_ICFG_CONNECTOR_BITS;
3027 ifmr->ifm_active = IFM_ETHER;
3031 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
3032 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3033 ifmr->ifm_active |= IFM_FDX;
3035 ifmr->ifm_active |= IFM_HDX;
3038 if (sc->xl_type == XL_TYPE_905B &&
3039 sc->xl_media == XL_MEDIAOPT_10FL) {
3040 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3041 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3042 ifmr->ifm_active |= IFM_FDX;
3044 ifmr->ifm_active |= IFM_HDX;
3046 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3049 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3052 * XXX MII and BTX/AUTO should be separate cases.
3055 case XL_XCVR_100BTX:
3060 ifmr->ifm_active = mii->mii_media_active;
3061 ifmr->ifm_status = mii->mii_media_status;
3064 case XL_XCVR_100BFX:
3065 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3068 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
3076 xl_ioctl(ifp, command, data, cr)
3082 struct xl_softc *sc = ifp->if_softc;
3083 struct ifreq *ifr = (struct ifreq *) data;
3085 struct mii_data *mii = NULL;
3094 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3095 if (ifp->if_flags & IFF_UP) {
3096 if (ifp->if_flags & IFF_RUNNING &&
3097 ifp->if_flags & IFF_PROMISC &&
3098 !(sc->xl_if_flags & IFF_PROMISC)) {
3099 rxfilt |= XL_RXFILTER_ALLFRAMES;
3100 CSR_WRITE_2(sc, XL_COMMAND,
3101 XL_CMD_RX_SET_FILT|rxfilt);
3103 } else if (ifp->if_flags & IFF_RUNNING &&
3104 !(ifp->if_flags & IFF_PROMISC) &&
3105 sc->xl_if_flags & IFF_PROMISC) {
3106 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3107 CSR_WRITE_2(sc, XL_COMMAND,
3108 XL_CMD_RX_SET_FILT|rxfilt);
3113 if (ifp->if_flags & IFF_RUNNING)
3116 sc->xl_if_flags = ifp->if_flags;
3121 if (sc->xl_type == XL_TYPE_905B)
3122 xl_setmulti_hash(sc);
3129 if (sc->xl_miibus != NULL)
3130 mii = device_get_softc(sc->xl_miibus);
3132 error = ifmedia_ioctl(ifp, ifr,
3133 &sc->ifmedia, command);
3135 error = ifmedia_ioctl(ifp, ifr,
3136 &mii->mii_media, command);
3139 ifp->if_capenable = ifr->ifr_reqcap;
3140 if (ifp->if_capenable & IFCAP_TXCSUM)
3141 ifp->if_hwassist = XL905B_CSUM_FEATURES;
3143 ifp->if_hwassist = 0;
3146 error = ether_ioctl(ifp, command, data);
3158 struct xl_softc *sc;
3159 u_int16_t status = 0;
3165 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3166 if_printf(ifp, "watchdog timeout\n");
3168 if (status & XL_MEDIASTAT_CARRIER)
3169 if_printf(ifp, "no carrier - transceiver cable problem?\n");
3176 if (!ifq_is_empty(&ifp->if_snd))
3177 (*ifp->if_start)(ifp);
3181 * Stop the adapter and free any mbufs allocated to the
3186 struct xl_softc *sc;
3191 ifp = &sc->arpcom.ac_if;
3194 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3195 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3196 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3197 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3199 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3200 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3204 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3206 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3210 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3211 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3212 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3213 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3215 /* Stop the stats updater. */
3216 callout_stop(&sc->xl_stat_timer);
3219 * Free data in the RX lists.
3221 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3222 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3223 bus_dmamap_unload(sc->xl_mtag,
3224 sc->xl_cdata.xl_rx_chain[i].xl_map);
3225 bus_dmamap_destroy(sc->xl_mtag,
3226 sc->xl_cdata.xl_rx_chain[i].xl_map);
3227 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3228 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3231 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3233 * Free the TX list buffers.
3235 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3236 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3237 bus_dmamap_unload(sc->xl_mtag,
3238 sc->xl_cdata.xl_tx_chain[i].xl_map);
3239 bus_dmamap_destroy(sc->xl_mtag,
3240 sc->xl_cdata.xl_tx_chain[i].xl_map);
3241 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3242 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3245 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3247 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3253 * Stop all chip I/O so that the kernel's probe routines don't
3254 * get confused by errant DMAs when rebooting.
3260 struct xl_softc *sc;
3262 sc = device_get_softc(dev);
3274 struct xl_softc *sc;
3279 sc = device_get_softc(dev);
3292 struct xl_softc *sc;
3298 sc = device_get_softc(dev);
3299 ifp = &sc->arpcom.ac_if;
3302 if (ifp->if_flags & IFF_UP)