2 * Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/dev/sound/pci/emu10k1.c,v 1.6.2.9 2002/04/22 15:49:32 cg Exp $
27 * $DragonFly: src/sys/dev/sound/pci/emu10k1.c,v 1.4 2004/01/06 16:07:40 asmodai Exp $
30 #include <dev/sound/pcm/sound.h>
31 #include <dev/sound/pcm/ac97.h>
32 #include "gnu/emu10k1.h"
34 #include <bus/pci/pcireg.h>
35 #include <bus/pci/pcivar.h>
36 #include <sys/queue.h>
38 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/emu10k1.c,v 1.4 2004/01/06 16:07:40 asmodai Exp $");
40 /* -------------------------------------------------------------------- */
42 #define EMU10K1_PCI_ID 0x00021102
43 #define EMU10K2_PCI_ID 0x00041102
44 #define EMU_DEFAULT_BUFSZ 4096
45 #define EMU_MAX_CHANS 8
49 SLIST_ENTRY(emu_memblk) link;
51 u_int32_t pte_start, pte_size;
55 u_int8_t bmap[MAXPAGES / 8];
58 SLIST_HEAD(, emu_memblk) blocks;
63 int b16:1, stereo:1, busy:1, running:1, ismaster:1;
66 int fxrt1; /* FX routing */
67 int fxrt2; /* FX routing (only for audigy) */
69 struct emu_voice *slave;
70 struct pcm_channel *channel;
75 /* channel registers */
77 int spd, fmt, blksz, run;
78 struct emu_voice *master, *slave;
79 struct snd_dbuf *buffer;
80 struct pcm_channel *channel;
81 struct sc_info *parent;
85 int spd, fmt, run, blksz, num;
86 u_int32_t idxreg, basereg, sizereg, setupreg, irqmask;
87 struct snd_dbuf *buffer;
88 struct pcm_channel *channel;
89 struct sc_info *parent;
92 /* device private data */
96 u_int32_t tos_link:1, APS:1, audigy:1, audigy2:1;
97 u_int32_t addrmask; /* wider if audigy */
100 bus_space_handle_t sh;
101 bus_dma_tag_t parent_dmat;
103 struct resource *reg, *irq;
108 int timer, timerinterval;
112 struct emu_voice voice[64];
113 struct sc_pchinfo pch[EMU_MAX_CHANS];
114 struct sc_rchinfo rch[3];
117 /* -------------------------------------------------------------------- */
124 static int emu_init(struct sc_info *);
125 static void emu_intr(void *);
126 static void *emu_malloc(struct sc_info *sc, u_int32_t sz);
127 static void *emu_memalloc(struct sc_info *sc, u_int32_t sz);
128 static int emu_memfree(struct sc_info *sc, void *buf);
129 static int emu_memstart(struct sc_info *sc, void *buf);
131 static void emu_vdump(struct sc_info *sc, struct emu_voice *v);
134 /* talk to the card */
135 static u_int32_t emu_rd(struct sc_info *, int, int);
136 static void emu_wr(struct sc_info *, int, u_int32_t, int);
138 /* -------------------------------------------------------------------- */
140 static u_int32_t emu_rfmt_ac97[] = {
142 AFMT_STEREO | AFMT_S16_LE,
146 static u_int32_t emu_rfmt_mic[] = {
151 static u_int32_t emu_rfmt_efx[] = {
152 AFMT_STEREO | AFMT_S16_LE,
156 static struct pcmchan_caps emu_reccaps[3] = {
157 {8000, 48000, emu_rfmt_ac97, 0},
158 {8000, 8000, emu_rfmt_mic, 0},
159 {48000, 48000, emu_rfmt_efx, 0},
162 static u_int32_t emu_pfmt[] = {
164 AFMT_STEREO | AFMT_U8,
166 AFMT_STEREO | AFMT_S16_LE,
170 static struct pcmchan_caps emu_playcaps = {4000, 48000, emu_pfmt, 0};
172 static int adcspeed[8] = {48000, 44100, 32000, 24000, 22050, 16000, 11025, 8000};
173 /* audigy supports 12kHz. */
174 static int audigy_adcspeed[9] = {48000, 44100, 32000, 24000, 22050, 16000, 12000, 11025, 8000};
176 /* -------------------------------------------------------------------- */
179 emu_rd(struct sc_info *sc, int regno, int size)
183 return bus_space_read_1(sc->st, sc->sh, regno);
185 return bus_space_read_2(sc->st, sc->sh, regno);
187 return bus_space_read_4(sc->st, sc->sh, regno);
194 emu_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
198 bus_space_write_1(sc->st, sc->sh, regno, data);
201 bus_space_write_2(sc->st, sc->sh, regno, data);
204 bus_space_write_4(sc->st, sc->sh, regno, data);
210 emu_rdptr(struct sc_info *sc, int chn, int reg)
212 u_int32_t ptr, val, mask, size, offset;
214 ptr = ((reg << 16) & sc->addrmask) | (chn & PTR_CHANNELNUM_MASK);
215 emu_wr(sc, PTR, ptr, 4);
216 val = emu_rd(sc, DATA, 4);
217 if (reg & 0xff000000) {
218 size = (reg >> 24) & 0x3f;
219 offset = (reg >> 16) & 0x1f;
220 mask = ((1 << size) - 1) << offset;
228 emu_wrptr(struct sc_info *sc, int chn, int reg, u_int32_t data)
230 u_int32_t ptr, mask, size, offset;
232 ptr = ((reg << 16) & sc->addrmask) | (chn & PTR_CHANNELNUM_MASK);
233 emu_wr(sc, PTR, ptr, 4);
234 if (reg & 0xff000000) {
235 size = (reg >> 24) & 0x3f;
236 offset = (reg >> 16) & 0x1f;
237 mask = ((1 << size) - 1) << offset;
240 data |= emu_rd(sc, DATA, 4) & ~mask;
242 emu_wr(sc, DATA, data, 4);
246 emu_wrefx(struct sc_info *sc, unsigned int pc, unsigned int data)
248 pc += sc->audigy ? AUDIGY_CODEBASE : MICROCODEBASE;
249 emu_wrptr(sc, 0, pc, data);
252 /* -------------------------------------------------------------------- */
254 /* no locking needed */
257 emu_rdcd(kobj_t obj, void *devinfo, int regno)
259 struct sc_info *sc = (struct sc_info *)devinfo;
261 emu_wr(sc, AC97ADDRESS, regno, 1);
262 return emu_rd(sc, AC97DATA, 2);
266 emu_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
268 struct sc_info *sc = (struct sc_info *)devinfo;
270 emu_wr(sc, AC97ADDRESS, regno, 1);
271 emu_wr(sc, AC97DATA, data, 2);
275 static kobj_method_t emu_ac97_methods[] = {
276 KOBJMETHOD(ac97_read, emu_rdcd),
277 KOBJMETHOD(ac97_write, emu_wrcd),
280 AC97_DECLARE(emu_ac97);
282 /* -------------------------------------------------------------------- */
285 emu_settimer(struct sc_info *sc)
287 struct sc_pchinfo *pch;
288 struct sc_rchinfo *rch;
292 for (i = 0; i < sc->nchans; i++) {
295 tmp = (pch->spd * sndbuf_getbps(pch->buffer)) / pch->blksz;
301 for (i = 0; i < 3; i++) {
304 tmp = (rch->spd * sndbuf_getbps(rch->buffer)) / rch->blksz;
309 RANGE(rate, 48, 9600);
310 sc->timerinterval = 48000 / rate;
311 emu_wr(sc, TIMER, sc->timerinterval & 0x03ff, 2);
313 return sc->timerinterval;
317 emu_enatimer(struct sc_info *sc, int go)
321 if (sc->timer++ == 0) {
322 x = emu_rd(sc, INTE, 4);
323 x |= INTE_INTERVALTIMERENB;
324 emu_wr(sc, INTE, x, 4);
328 x = emu_rd(sc, INTE, 4);
329 x &= ~INTE_INTERVALTIMERENB;
330 emu_wr(sc, INTE, x, 4);
336 emu_enastop(struct sc_info *sc, char channel, int enable)
338 int reg = (channel & 0x20)? SOLEH : SOLEL;
341 reg |= channel << 16;
342 emu_wrptr(sc, 0, reg, enable);
346 emu_recval(int speed) {
350 while (val < 7 && speed < adcspeed[val])
356 audigy_recval(int speed) {
360 while (val < 8 && speed < audigy_adcspeed[val])
366 emu_rate_to_pitch(u_int32_t rate)
368 static u_int32_t logMagTable[128] = {
369 0x00000, 0x02dfc, 0x05b9e, 0x088e6, 0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2,
370 0x1663f, 0x1918a, 0x1bc84, 0x1e72e, 0x2118b, 0x23b9a, 0x2655d, 0x28ed5,
371 0x2b803, 0x2e0e8, 0x30985, 0x331db, 0x359eb, 0x381b6, 0x3a93d, 0x3d081,
372 0x3f782, 0x41e42, 0x444c1, 0x46b01, 0x49101, 0x4b6c4, 0x4dc49, 0x50191,
373 0x5269e, 0x54b6f, 0x57006, 0x59463, 0x5b888, 0x5dc74, 0x60029, 0x623a7,
374 0x646ee, 0x66a00, 0x68cdd, 0x6af86, 0x6d1fa, 0x6f43c, 0x7164b, 0x73829,
375 0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5, 0x7dea1, 0x7ff5e, 0x81fed, 0x8404e,
376 0x86082, 0x88089, 0x8a064, 0x8c014, 0x8df98, 0x8fef1, 0x91e20, 0x93d26,
377 0x95c01, 0x97ab4, 0x9993e, 0x9b79f, 0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d,
378 0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537, 0xac241, 0xadf26, 0xafbe7, 0xb1885,
379 0xb3500, 0xb5157, 0xb6d8c, 0xb899f, 0xba58f, 0xbc15e, 0xbdd0c, 0xbf899,
380 0xc1404, 0xc2f50, 0xc4a7b, 0xc6587, 0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c,
381 0xceaec, 0xd053f, 0xd1f73, 0xd398a, 0xd5384, 0xd6d60, 0xd8720, 0xda0c3,
382 0xdba4a, 0xdd3b4, 0xded03, 0xe0636, 0xe1f4e, 0xe384a, 0xe512c, 0xe69f3,
383 0xe829f, 0xe9b31, 0xeb3a9, 0xecc08, 0xee44c, 0xefc78, 0xf148a, 0xf2c83,
384 0xf4463, 0xf5c2a, 0xf73da, 0xf8b71, 0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df
386 static char logSlopeTable[128] = {
387 0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58,
388 0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53,
389 0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f,
390 0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b,
391 0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47,
392 0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44,
393 0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41,
394 0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e,
395 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c,
396 0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39,
397 0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37,
398 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35,
399 0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34,
400 0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32,
401 0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30,
402 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f
407 return 0; /* Bail out if no leading "1" */
408 rate *= 11185; /* Scale 48000 to 0x20002380 */
409 for (i = 31; i > 0; i--) {
410 if (rate & 0x80000000) { /* Detect leading "1" */
411 return (((u_int32_t) (i - 15) << 20) +
412 logMagTable[0x7f & (rate >> 24)] +
413 (0x7f & (rate >> 17)) *
414 logSlopeTable[0x7f & (rate >> 24)]);
419 return 0; /* Should never reach this point */
423 emu_rate_to_linearpitch(u_int32_t rate)
425 rate = (rate << 8) / 375;
426 return (rate >> 1) + (rate & 1);
429 static struct emu_voice *
430 emu_valloc(struct sc_info *sc)
436 for (i = 0; i < 64 && sc->voice[i].busy; i++);
445 emu_vinit(struct sc_info *sc, struct emu_voice *m, struct emu_voice *s,
446 u_int32_t sz, struct snd_dbuf *b)
450 buf = emu_memalloc(sc, sz);
454 sndbuf_setup(b, buf, sz);
455 m->start = emu_memstart(sc, buf) * EMUPAGESIZE;
456 m->end = m->start + sz;
464 m->buf = vtophys(buf);
467 m->fxrt1 = A_FXBUS_PCM_LEFT | A_FXBUS_PCM_RIGHT << 8 |
468 A_FXBUS_PCM_LEFT_REAR << 16 |
469 A_FXBUS_PCM_RIGHT_REAR << 24;
470 m->fxrt2 = A_FXBUS_PCM_CENTER | A_FXBUS_PCM_LFE << 8 |
471 A_FXBUS_MIDI_CHORUS << 16 |
472 A_FXBUS_MIDI_REVERB << 24;
474 m->fxrt1 = FXBUS_PCM_LEFT | FXBUS_PCM_RIGHT << 4 |
475 FXBUS_MIDI_CHORUS << 8 |
476 FXBUS_MIDI_REVERB << 12;
499 emu_vsetup(struct sc_pchinfo *ch)
501 struct emu_voice *v = ch->master;
504 v->b16 = (ch->fmt & AFMT_16BIT)? 1 : 0;
505 v->stereo = (ch->fmt & AFMT_STEREO)? 1 : 0;
506 if (v->slave != NULL) {
507 v->slave->b16 = v->b16;
508 v->slave->stereo = v->stereo;
513 if (v->slave != NULL)
514 v->slave->speed = v->speed;
519 emu_vwrite(struct sc_info *sc, struct emu_voice *v)
523 u_int32_t sa, ea, start, val, silent_page;
525 s = (v->stereo? 1 : 0) + (v->b16? 1 : 0);
530 l = r = x = y = v->vol;
532 l = v->ismaster? l : 0;
533 r = v->ismaster? 0 : r;
536 emu_wrptr(sc, v->vnum, CPF, v->stereo? CPF_STEREO_MASK : 0);
537 val = v->stereo? 28 : 30;
538 val *= v->b16? 1 : 2;
542 emu_wrptr(sc, v->vnum, A_FXRT1, v->fxrt1);
543 emu_wrptr(sc, v->vnum, A_FXRT2, v->fxrt2);
544 emu_wrptr(sc, v->vnum, A_SENDAMOUNTS, 0);
547 emu_wrptr(sc, v->vnum, FXRT, v->fxrt1 << 16);
549 emu_wrptr(sc, v->vnum, PTRX, (x << 8) | r);
550 emu_wrptr(sc, v->vnum, DSL, ea | (y << 24));
551 emu_wrptr(sc, v->vnum, PSST, sa | (l << 24));
552 emu_wrptr(sc, v->vnum, CCCA, start | (v->b16? 0 : CCCA_8BITSELECT));
554 emu_wrptr(sc, v->vnum, Z1, 0);
555 emu_wrptr(sc, v->vnum, Z2, 0);
557 silent_page = ((u_int32_t)vtophys(sc->mem.silent_page) << 1) | MAP_PTI_MASK;
558 emu_wrptr(sc, v->vnum, MAPA, silent_page);
559 emu_wrptr(sc, v->vnum, MAPB, silent_page);
561 emu_wrptr(sc, v->vnum, CVCF, CVCF_CURRENTFILTER_MASK);
562 emu_wrptr(sc, v->vnum, VTFT, VTFT_FILTERTARGET_MASK);
563 emu_wrptr(sc, v->vnum, ATKHLDM, 0);
564 emu_wrptr(sc, v->vnum, DCYSUSM, DCYSUSM_DECAYTIME_MASK);
565 emu_wrptr(sc, v->vnum, LFOVAL1, 0x8000);
566 emu_wrptr(sc, v->vnum, LFOVAL2, 0x8000);
567 emu_wrptr(sc, v->vnum, FMMOD, 0);
568 emu_wrptr(sc, v->vnum, TREMFRQ, 0);
569 emu_wrptr(sc, v->vnum, FM2FRQ2, 0);
570 emu_wrptr(sc, v->vnum, ENVVAL, 0x8000);
572 emu_wrptr(sc, v->vnum, ATKHLDV, ATKHLDV_HOLDTIME_MASK | ATKHLDV_ATTACKTIME_MASK);
573 emu_wrptr(sc, v->vnum, ENVVOL, 0x8000);
575 emu_wrptr(sc, v->vnum, PEFE_FILTERAMOUNT, 0x7f);
576 emu_wrptr(sc, v->vnum, PEFE_PITCHAMOUNT, 0);
578 if (v->slave != NULL)
579 emu_vwrite(sc, v->slave);
583 emu_vtrigger(struct sc_info *sc, struct emu_voice *v, int go)
585 u_int32_t pitch_target, initial_pitch;
586 u_int32_t cra, cs, ccis;
591 cs = v->stereo? 4 : 2;
592 ccis = v->stereo? 28 : 30;
593 ccis *= v->b16? 1 : 2;
594 sample = v->b16? 0x00000000 : 0x80808080;
596 for (i = 0; i < cs; i++)
597 emu_wrptr(sc, v->vnum, CD0 + i, sample);
598 emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, 0);
599 emu_wrptr(sc, v->vnum, CCR_READADDRESS, cra);
600 emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, ccis);
602 emu_wrptr(sc, v->vnum, IFATN, 0xff00);
603 emu_wrptr(sc, v->vnum, VTFT, 0xffffffff);
604 emu_wrptr(sc, v->vnum, CVCF, 0xffffffff);
605 emu_wrptr(sc, v->vnum, DCYSUSV, 0x00007f7f);
606 emu_enastop(sc, v->vnum, 0);
608 pitch_target = emu_rate_to_linearpitch(v->speed);
609 initial_pitch = emu_rate_to_pitch(v->speed) >> 8;
610 emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, pitch_target);
611 emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, pitch_target);
612 emu_wrptr(sc, v->vnum, IP, initial_pitch);
614 emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, 0);
615 emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, 0);
616 emu_wrptr(sc, v->vnum, IFATN, 0xffff);
617 emu_wrptr(sc, v->vnum, VTFT, 0x0000ffff);
618 emu_wrptr(sc, v->vnum, CVCF, 0x0000ffff);
619 emu_wrptr(sc, v->vnum, IP, 0);
620 emu_enastop(sc, v->vnum, 1);
622 if (v->slave != NULL)
623 emu_vtrigger(sc, v->slave, go);
627 emu_vpos(struct sc_info *sc, struct emu_voice *v)
631 s = (v->b16? 1 : 0) + (v->stereo? 1 : 0);
632 ptr = (emu_rdptr(sc, v->vnum, CCCA_CURRADDR) - (v->start >> s)) << s;
633 return ptr & ~0x0000001f;
638 emu_vdump(struct sc_info *sc, struct emu_voice *v)
640 char *regname[] = { "cpf", "ptrx", "cvcf", "vtft", "z2", "z1", "psst", "dsl",
641 "ccca", "ccr", "clp", "fxrt", "mapa", "mapb", NULL, NULL,
642 "envvol", "atkhldv", "dcysusv", "lfoval1",
643 "envval", "atkhldm", "dcysusm", "lfoval2",
644 "ip", "ifatn", "pefe", "fmmod", "tremfrq", "fmfrq2",
646 char *regname2[] = { "mudata1", "mustat1", "mudata2", "mustat2",
647 "fxwc1", "fxwc2", "spdrate", NULL, NULL,
648 NULL, NULL, NULL, "fxrt2", "sndamnt", "fxrt1",
652 printf("voice number %d\n", v->vnum);
653 for (i = 0, x = 0; i <= 0x1e; i++) {
654 if (regname[i] == NULL)
656 printf("%s\t[%08x]", regname[i], emu_rdptr(sc, v->vnum, i));
657 printf("%s", (x == 2)? "\n" : "\t");
663 /* Print out audigy extra registers */
665 for (i = 0; i <= 0xe; i++) {
666 if (regname2[i] == NULL)
668 printf("%s\t[%08x]", regname2[i], emu_rdptr(sc, v->vnum, i + 0x70));
669 printf("%s", (x == 2)? "\n" : "\t");
680 /* channel interface */
682 emupchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
684 struct sc_info *sc = devinfo;
685 struct sc_pchinfo *ch;
688 KASSERT(dir == PCMDIR_PLAY, ("emupchan_init: bad direction"));
689 ch = &sc->pch[sc->pnum++];
693 ch->blksz = sc->bufsz / 2;
696 snd_mtxlock(sc->lock);
697 ch->master = emu_valloc(sc);
698 ch->slave = emu_valloc(sc);
699 r = (emu_vinit(sc, ch->master, ch->slave, sc->bufsz, ch->buffer))? NULL : ch;
700 snd_mtxunlock(sc->lock);
706 emupchan_free(kobj_t obj, void *data)
708 struct sc_pchinfo *ch = data;
709 struct sc_info *sc = ch->parent;
712 snd_mtxlock(sc->lock);
713 r = emu_memfree(sc, sndbuf_getbuf(ch->buffer));
714 snd_mtxunlock(sc->lock);
720 emupchan_setformat(kobj_t obj, void *data, u_int32_t format)
722 struct sc_pchinfo *ch = data;
729 emupchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
731 struct sc_pchinfo *ch = data;
738 emupchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
740 struct sc_pchinfo *ch = data;
741 struct sc_info *sc = ch->parent;
744 ch->blksz = blocksize;
745 snd_mtxlock(sc->lock);
747 irqrate = 48000 / sc->timerinterval;
748 snd_mtxunlock(sc->lock);
749 blksz = (ch->spd * sndbuf_getbps(ch->buffer)) / irqrate;
754 emupchan_trigger(kobj_t obj, void *data, int go)
756 struct sc_pchinfo *ch = data;
757 struct sc_info *sc = ch->parent;
759 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD)
762 snd_mtxlock(sc->lock);
763 if (go == PCMTRIG_START) {
765 emu_vwrite(sc, ch->master);
769 printf("start [%d bit, %s, %d hz]\n",
770 ch->master->b16? 16 : 8,
771 ch->master->stereo? "stereo" : "mono",
773 emu_vdump(sc, ch->master);
774 emu_vdump(sc, ch->slave);
777 ch->run = (go == PCMTRIG_START)? 1 : 0;
778 emu_vtrigger(sc, ch->master, ch->run);
779 snd_mtxunlock(sc->lock);
784 emupchan_getptr(kobj_t obj, void *data)
786 struct sc_pchinfo *ch = data;
787 struct sc_info *sc = ch->parent;
790 snd_mtxlock(sc->lock);
791 r = emu_vpos(sc, ch->master);
792 snd_mtxunlock(sc->lock);
797 static struct pcmchan_caps *
798 emupchan_getcaps(kobj_t obj, void *data)
800 return &emu_playcaps;
803 static kobj_method_t emupchan_methods[] = {
804 KOBJMETHOD(channel_init, emupchan_init),
805 KOBJMETHOD(channel_free, emupchan_free),
806 KOBJMETHOD(channel_setformat, emupchan_setformat),
807 KOBJMETHOD(channel_setspeed, emupchan_setspeed),
808 KOBJMETHOD(channel_setblocksize, emupchan_setblocksize),
809 KOBJMETHOD(channel_trigger, emupchan_trigger),
810 KOBJMETHOD(channel_getptr, emupchan_getptr),
811 KOBJMETHOD(channel_getcaps, emupchan_getcaps),
814 CHANNEL_DECLARE(emupchan);
816 /* channel interface */
818 emurchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
820 struct sc_info *sc = devinfo;
821 struct sc_rchinfo *ch;
823 KASSERT(dir == PCMDIR_REC, ("emurchan_init: bad direction"));
824 ch = &sc->rch[sc->rnum];
828 ch->blksz = sc->bufsz / 2;
834 ch->idxreg = sc->audigy ? A_ADCIDX : ADCIDX;
837 ch->setupreg = ADCCR;
838 ch->irqmask = INTE_ADCBUFENABLE;
846 ch->irqmask = INTE_EFXBUFENABLE;
854 ch->irqmask = INTE_MICBUFENABLE;
858 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) == -1)
861 snd_mtxlock(sc->lock);
862 emu_wrptr(sc, 0, ch->basereg, vtophys(sndbuf_getbuf(ch->buffer)));
863 emu_wrptr(sc, 0, ch->sizereg, 0); /* off */
864 snd_mtxunlock(sc->lock);
870 emurchan_setformat(kobj_t obj, void *data, u_int32_t format)
872 struct sc_rchinfo *ch = data;
879 emurchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
881 struct sc_rchinfo *ch = data;
884 if (ch->parent->audigy)
885 speed = audigy_adcspeed[audigy_recval(speed)];
887 speed = adcspeed[emu_recval(speed)];
898 emurchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
900 struct sc_rchinfo *ch = data;
901 struct sc_info *sc = ch->parent;
904 ch->blksz = blocksize;
905 snd_mtxlock(sc->lock);
907 irqrate = 48000 / sc->timerinterval;
908 snd_mtxunlock(sc->lock);
909 blksz = (ch->spd * sndbuf_getbps(ch->buffer)) / irqrate;
913 /* semantic note: must start at beginning of buffer */
915 emurchan_trigger(kobj_t obj, void *data, int go)
917 struct sc_rchinfo *ch = data;
918 struct sc_info *sc = ch->parent;
923 sz = ADCBS_BUFSIZE_4096;
927 sz = ADCBS_BUFSIZE_8192;
931 sz = ADCBS_BUFSIZE_16384;
935 sz = ADCBS_BUFSIZE_32768;
939 sz = ADCBS_BUFSIZE_65536;
943 sz = ADCBS_BUFSIZE_4096;
946 snd_mtxlock(sc->lock);
950 emu_wrptr(sc, 0, ch->sizereg, sz);
953 val = A_ADCCR_LCHANENABLE;
954 if (ch->fmt & AFMT_STEREO)
955 val |= A_ADCCR_RCHANENABLE;
956 val |= audigy_recval(ch->spd);
958 val = ADCCR_LCHANENABLE;
959 if (ch->fmt & AFMT_STEREO)
960 val |= ADCCR_RCHANENABLE;
961 val |= emu_recval(ch->spd);
964 emu_wrptr(sc, 0, ch->setupreg, 0);
965 emu_wrptr(sc, 0, ch->setupreg, val);
967 val = emu_rd(sc, INTE, 4);
969 emu_wr(sc, INTE, val, 4);
975 emu_wrptr(sc, 0, ch->sizereg, 0);
977 emu_wrptr(sc, 0, ch->setupreg, 0);
978 val = emu_rd(sc, INTE, 4);
980 emu_wr(sc, INTE, val, 4);
983 case PCMTRIG_EMLDMAWR:
984 case PCMTRIG_EMLDMARD:
988 snd_mtxunlock(sc->lock);
994 emurchan_getptr(kobj_t obj, void *data)
996 struct sc_rchinfo *ch = data;
997 struct sc_info *sc = ch->parent;
1000 snd_mtxlock(sc->lock);
1001 r = emu_rdptr(sc, 0, ch->idxreg) & 0x0000ffff;
1002 snd_mtxunlock(sc->lock);
1007 static struct pcmchan_caps *
1008 emurchan_getcaps(kobj_t obj, void *data)
1010 struct sc_rchinfo *ch = data;
1012 return &emu_reccaps[ch->num];
1015 static kobj_method_t emurchan_methods[] = {
1016 KOBJMETHOD(channel_init, emurchan_init),
1017 KOBJMETHOD(channel_setformat, emurchan_setformat),
1018 KOBJMETHOD(channel_setspeed, emurchan_setspeed),
1019 KOBJMETHOD(channel_setblocksize, emurchan_setblocksize),
1020 KOBJMETHOD(channel_trigger, emurchan_trigger),
1021 KOBJMETHOD(channel_getptr, emurchan_getptr),
1022 KOBJMETHOD(channel_getcaps, emurchan_getcaps),
1025 CHANNEL_DECLARE(emurchan);
1027 /* -------------------------------------------------------------------- */
1028 /* The interrupt handler */
1032 struct sc_info *sc = (struct sc_info *)p;
1033 u_int32_t stat, ack, i, x;
1036 stat = emu_rd(sc, IPR, 4);
1042 if (stat & IPR_INTERVALTIMER) {
1043 ack |= IPR_INTERVALTIMER;
1045 for (i = 0; i < sc->nchans; i++) {
1046 if (sc->pch[i].run) {
1048 chn_intr(sc->pch[i].channel);
1052 emu_enatimer(sc, 0);
1056 if (stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL)) {
1057 ack |= stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL);
1058 if (sc->rch[0].channel)
1059 chn_intr(sc->rch[0].channel);
1061 if (stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL)) {
1062 ack |= stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL);
1063 if (sc->rch[1].channel)
1064 chn_intr(sc->rch[1].channel);
1066 if (stat & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL)) {
1067 ack |= stat & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL);
1068 if (sc->rch[2].channel)
1069 chn_intr(sc->rch[2].channel);
1071 if (stat & IPR_PCIERROR) {
1072 ack |= IPR_PCIERROR;
1073 device_printf(sc->dev, "pci error\n");
1074 /* we still get an nmi with ecc ram even if we ack this */
1076 if (stat & IPR_SAMPLERATETRACKER) {
1077 ack |= IPR_SAMPLERATETRACKER;
1078 /* device_printf(sc->dev, "sample rate tracker lock status change\n"); */
1082 device_printf(sc->dev, "dodgy irq: %x (harmless)\n", stat & ~ack);
1084 emu_wr(sc, IPR, stat, 4);
1088 /* -------------------------------------------------------------------- */
1091 emu_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1095 *phys = error? 0 : (void *)segs->ds_addr;
1098 printf("emu: setmap (%lx, %lx), nseg=%d, error=%d\n",
1099 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len,
1105 emu_malloc(struct sc_info *sc, u_int32_t sz)
1107 void *buf, *phys = 0;
1110 if (bus_dmamem_alloc(sc->parent_dmat, &buf, BUS_DMA_NOWAIT, &map))
1112 if (bus_dmamap_load(sc->parent_dmat, map, buf, sz, emu_setmap, &phys, 0)
1119 emu_free(struct sc_info *sc, void *buf)
1121 bus_dmamem_free(sc->parent_dmat, buf, NULL);
1125 emu_memalloc(struct sc_info *sc, u_int32_t sz)
1127 u_int32_t blksz, start, idx, ofs, tmp, found;
1128 struct emu_mem *mem = &sc->mem;
1129 struct emu_memblk *blk;
1132 blksz = sz / EMUPAGESIZE;
1133 if (sz > (blksz * EMUPAGESIZE))
1135 /* find a free block in the bitmap */
1138 while (!found && start + blksz < MAXPAGES) {
1140 for (idx = start; idx < start + blksz; idx++)
1141 if (mem->bmap[idx >> 3] & (1 << (idx & 7)))
1148 blk = malloc(sizeof(*blk), M_DEVBUF, M_NOWAIT);
1151 buf = emu_malloc(sc, sz);
1153 free(blk, M_DEVBUF);
1157 blk->pte_start = start;
1158 blk->pte_size = blksz;
1159 /* printf("buf %p, pte_start %d, pte_size %d\n", blk->buf, blk->pte_start, blk->pte_size); */
1161 for (idx = start; idx < start + blksz; idx++) {
1162 mem->bmap[idx >> 3] |= 1 << (idx & 7);
1163 tmp = (u_int32_t)vtophys((u_int8_t *)buf + ofs);
1164 /* printf("pte[%d] -> %x phys, %x virt\n", idx, tmp, ((u_int32_t)buf) + ofs); */
1165 mem->ptb_pages[idx] = (tmp << 1) | idx;
1168 SLIST_INSERT_HEAD(&mem->blocks, blk, link);
1173 emu_memfree(struct sc_info *sc, void *buf)
1176 struct emu_mem *mem = &sc->mem;
1177 struct emu_memblk *blk, *i;
1180 SLIST_FOREACH(i, &mem->blocks, link) {
1186 SLIST_REMOVE(&mem->blocks, blk, emu_memblk, link);
1188 tmp = (u_int32_t)vtophys(sc->mem.silent_page) << 1;
1189 for (idx = blk->pte_start; idx < blk->pte_start + blk->pte_size; idx++) {
1190 mem->bmap[idx >> 3] &= ~(1 << (idx & 7));
1191 mem->ptb_pages[idx] = tmp | idx;
1193 free(blk, M_DEVBUF);
1198 emu_memstart(struct sc_info *sc, void *buf)
1200 struct emu_mem *mem = &sc->mem;
1201 struct emu_memblk *blk, *i;
1204 SLIST_FOREACH(i, &mem->blocks, link) {
1210 return blk->pte_start;
1214 emu_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y, u_int32_t *pc)
1216 emu_wrefx(sc, (*pc) * 2, (x << 10) | y);
1217 emu_wrefx(sc, (*pc) * 2 + 1, (op << 20) | (z << 10) | w);
1222 audigy_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y, u_int32_t *pc)
1224 emu_wrefx(sc, (*pc) * 2, (x << 12) | y);
1225 emu_wrefx(sc, (*pc) * 2 + 1, (op << 24) | (z << 12) | w);
1230 audigy_initefx(struct sc_info *sc)
1235 /* skip 0, 0, -1, 0 - NOPs */
1236 for (i = 0; i < 512; i++)
1237 audigy_addefxop(sc, 0x0f, 0x0c0, 0x0c0, 0x0cf, 0x0c0, &pc);
1239 for (i = 0; i < 512; i++)
1240 emu_wrptr(sc, 0, A_FXGPREGBASE + i, 0x0);
1244 /* stop fx processor */
1245 emu_wrptr(sc, 0, A_DBG, A_DBG_SINGLE_STEP);
1247 /* Audigy 2 (EMU10K2) DSP Registers:
1249 0x000-0x00f : 16 registers (???)
1251 0x040/0x041 : AC97 Codec (l/r)
1252 0x042/0x043 : ADC, S/PDIF (l/r)
1253 0x044/0x045 : Optical S/PDIF in (l/r)
1255 0x048/0x049 : Line/Mic 2 (l/r)
1256 0x04a/0x04b : RCA S/PDIF (l/r)
1257 0x04c/0x04d : Aux 2 (l/r)
1259 0x060/0x061 : Digital Front (l/r)
1260 0x062/0x063 : Digital Center/LFE
1261 0x064/0x065 : AudigyDrive Heaphone (l/r)
1262 0x066/0x067 : Digital Rear (l/r)
1263 0x068/0x069 : Analog Front (l/r)
1264 0x06a/0x06b : Analog Center/LFE
1266 0x06e/0x06f : Analog Rear (l/r)
1267 0x070/0x071 : AC97 Output (l/r)
1270 0x076/0x077 : ADC Recording Buffer (l/r)
1272 0x0c0 - 0x0c4 = 0 - 4
1273 0x0c5 = 0x8, 0x0c6 = 0x10, 0x0c7 = 0x20
1274 0x0c8 = 0x100, 0x0c9 = 0x10000, 0x0ca = 0x80000
1275 0x0cb = 0x10000000, 0x0cc = 0x20000000, 0x0cd = 0x40000000
1276 0x0ce = 0x80000000, 0x0cf = 0x7fffffff, 0x0d0 = 0xffffffff
1277 0x0d1 = 0xfffffffe, 0x0d2 = 0xc0000000, 0x0d3 = 0x41fbbcdc
1278 0x0d4 = 0x5a7ef9db, 0x0d5 = 0x00100000, 0x0dc = 0x00000001 (???)
1280 0x0d6 : Accumulator (???)
1281 0x0d7 : Condition Register
1282 0x0d8 : Noise source
1283 0x0d9 : Noise source
1284 Tank Memory Data Registers
1286 Tank Memory Address Registers
1288 General Purpose Registers
1292 /* AC97Output[l/r] = FXBus PCM[l/r] */
1293 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_L), A_C_00000000,
1294 A_C_00000000, A_FXBUS(A_FXBUS_PCM_LEFT), &pc);
1295 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_R), A_C_00000000,
1296 A_C_00000000, A_FXBUS(A_FXBUS_PCM_RIGHT), &pc);
1298 /* GPR[0/1] = RCA S/PDIF[l/r] -- Master volume */
1299 audigy_addefxop(sc, iACC3, A_GPR(0), A_C_00000000,
1300 A_C_00000000, A_EXTIN(A_EXTIN_RCA_SPDIF_L), &pc);
1301 audigy_addefxop(sc, iACC3, A_GPR(1), A_C_00000000,
1302 A_C_00000000, A_EXTIN(A_EXTIN_RCA_SPDIF_R), &pc);
1304 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */
1305 audigy_addefxop(sc, iINTERP, A_GPR(2), A_GPR(1),
1306 A_C_40000000, A_GPR(0), &pc);
1308 /* Headphones[l/r] = GPR[0/1] */
1309 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_L),
1310 A_C_00000000, A_C_00000000, A_GPR(0), &pc);
1311 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_R),
1312 A_C_00000000, A_C_00000000, A_GPR(1), &pc);
1314 /* Analog Front[l/r] = GPR[0/1] */
1315 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_L), A_C_00000000,
1316 A_C_00000000, A_GPR(0), &pc);
1317 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_R), A_C_00000000,
1318 A_C_00000000, A_GPR(1), &pc);
1320 /* Digital Front[l/r] = GPR[0/1] */
1321 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L), A_C_00000000,
1322 A_C_00000000, A_GPR(0), &pc);
1323 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_R), A_C_00000000,
1324 A_C_00000000, A_GPR(1), &pc);
1326 /* Center and Subwoofer configuration */
1327 /* Analog Center = GPR[0] + GPR[2] */
1328 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ACENTER), A_C_00000000,
1329 A_GPR(0), A_GPR(2), &pc);
1330 /* Analog Sub = GPR[1] + GPR[2] */
1331 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ALFE), A_C_00000000,
1332 A_GPR(1), A_GPR(2), &pc);
1334 /* Digital Center = GPR[0] + GPR[2] */
1335 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_CENTER), A_C_00000000,
1336 A_GPR(0), A_GPR(2), &pc);
1337 /* Digital Sub = GPR[1] + GPR[2] */
1338 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_LFE), A_C_00000000,
1339 A_GPR(1), A_GPR(2), &pc);
1342 /* Analog Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */
1343 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */
1344 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000,
1345 A_GPR(16), A_GPR(0), &pc);
1346 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000,
1347 A_GPR(17), A_GPR(1), &pc);
1349 /* Digital Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */
1350 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */
1351 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000,
1352 A_GPR(16), A_GPR(0), &pc);
1353 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000,
1354 A_GPR(17), A_GPR(1), &pc);
1356 /* XXX This is just a copy to the channel, since we do not have
1357 * a patch manager, it is useful for have another output enabled.
1360 /* Analog Rear[l/r] = GPR[0/1] */
1361 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000,
1362 A_C_00000000, A_GPR(0), &pc);
1363 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000,
1364 A_C_00000000, A_GPR(1), &pc);
1366 /* Digital Rear[l/r] = GPR[0/1] */
1367 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000,
1368 A_C_00000000, A_GPR(0), &pc);
1369 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000,
1370 A_C_00000000, A_GPR(1), &pc);
1373 /* ADC Recording buffer[l/r] = AC97Input[l/r] */
1374 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_L), A_C_00000000,
1375 A_C_00000000, A_EXTIN(A_EXTIN_AC97_L), &pc);
1376 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_R), A_C_00000000,
1377 A_C_00000000, A_EXTIN(A_EXTIN_AC97_R), &pc);
1379 /* resume normal operations */
1380 emu_wrptr(sc, 0, A_DBG, 0);
1384 emu_initefx(struct sc_info *sc)
1389 /* acc3 0,0,0,0 - NOPs */
1390 for (i = 0; i < 512; i++) {
1391 emu_wrefx(sc, i * 2, 0x10040);
1392 emu_wrefx(sc, i * 2 + 1, 0x610040);
1395 for (i = 0; i < 256; i++)
1396 emu_wrptr(sc, 0, FXGPREGBASE + i, 0);
1398 /* FX-8010 DSP Registers:
1400 0x000-0x00f : 16 registers
1402 0x010/0x011 : AC97 Codec (l/r)
1403 0x012/0x013 : ADC, S/PDIF (l/r)
1404 0x014/0x015 : Mic(left), Zoom (l/r)
1405 0x016/0x017 : TOS link in (l/r)
1406 0x018/0x019 : Line/Mic 1 (l/r)
1407 0x01a/0x01b : COAX S/PDIF (l/r)
1408 0x01c/0x01d : Line/Mic 2 (l/r)
1410 0x020/0x021 : AC97 Output (l/r)
1411 0x022/0x023 : TOS link out (l/r)
1412 0x024/0x025 : Center/LFE
1413 0x026/0x027 : LiveDrive Headphone (l/r)
1414 0x028/0x029 : Rear Channel (l/r)
1415 0x02a/0x02b : ADC Recording Buffer (l/r)
1416 0x02c : Mic Recording Buffer
1417 0x031/0x032 : Analog Center/LFE
1419 0x040 - 0x044 = 0 - 4
1420 0x045 = 0x8, 0x046 = 0x10, 0x047 = 0x20
1421 0x048 = 0x100, 0x049 = 0x10000, 0x04a = 0x80000
1422 0x04b = 0x10000000, 0x04c = 0x20000000, 0x04d = 0x40000000
1423 0x04e = 0x80000000, 0x04f = 0x7fffffff, 0x050 = 0xffffffff
1424 0x051 = 0xfffffffe, 0x052 = 0xc0000000, 0x053 = 0x41fbbcdc
1425 0x054 = 0x5a7ef9db, 0x055 = 0x00100000
1428 0x057 : Condition Register
1429 0x058 : Noise source
1430 0x059 : Noise source
1431 0x05a : IRQ Register
1432 0x05b : TRAM Delay Base Address Count
1433 General Purpose Registers
1435 Tank Memory Data Registers
1437 Tank Memory Address Registers
1441 /* Routing - this will be configurable in later version */
1443 /* GPR[0/1] = FX * 4 + SPDIF-in */
1444 emu_addefxop(sc, iMACINT0, GPR(0), EXTIN(EXTIN_SPDIF_CD_L),
1445 FXBUS(FXBUS_PCM_LEFT), C_00000004, &pc);
1446 emu_addefxop(sc, iMACINT0, GPR(1), EXTIN(EXTIN_SPDIF_CD_R),
1447 FXBUS(FXBUS_PCM_RIGHT), C_00000004, &pc);
1449 /* GPR[0/1] += APS-input */
1450 emu_addefxop(sc, iACC3, GPR(0), GPR(0), C_00000000,
1451 sc->APS ? EXTIN(EXTIN_TOSLINK_L) : C_00000000, &pc);
1452 emu_addefxop(sc, iACC3, GPR(1), GPR(1), C_00000000,
1453 sc->APS ? EXTIN(EXTIN_TOSLINK_R) : C_00000000, &pc);
1455 /* FrontOut (AC97) = GPR[0/1] */
1456 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_L), C_00000000,
1457 C_00000000, GPR(0), &pc);
1458 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_R), C_00000000,
1459 C_00000001, GPR(1), &pc);
1461 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */
1462 emu_addefxop(sc, iINTERP, GPR(2), GPR(1), C_40000000, GPR(0), &pc);
1465 /* RearOut = (GPR[0/1] * RearVolume) >> 31 */
1466 /* RearVolume = GPR[0x10/0x11] */
1467 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_L), C_00000000,
1468 GPR(16), GPR(0), &pc);
1469 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_R), C_00000000,
1470 GPR(17), GPR(1), &pc);
1472 /* XXX This is just a copy to the channel, since we do not have
1473 * a patch manager, it is useful for have another output enabled.
1476 /* Rear[l/r] = GPR[0/1] */
1477 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_L), C_00000000,
1478 C_00000000, GPR(0), &pc);
1479 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_R), C_00000000,
1480 C_00000000, GPR(1), &pc);
1483 /* TOS out[l/r] = GPR[0/1] */
1484 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_L), C_00000000,
1485 C_00000000, GPR(0), &pc);
1486 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_R), C_00000000,
1487 C_00000000, GPR(1), &pc);
1489 /* Center and Subwoofer configuration */
1490 /* Analog Center = GPR[0] + GPR[2] */
1491 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ACENTER), C_00000000,
1492 GPR(0), GPR(2), &pc);
1493 /* Analog Sub = GPR[1] + GPR[2] */
1494 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ALFE), C_00000000,
1495 GPR(1), GPR(2), &pc);
1496 /* Digital Center = GPR[0] + GPR[2] */
1497 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_CENTER), C_00000000,
1498 GPR(0), GPR(2), &pc);
1499 /* Digital Sub = GPR[1] + GPR[2] */
1500 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_LFE), C_00000000,
1501 GPR(1), GPR(2), &pc);
1503 /* Headphones[l/r] = GPR[0/1] */
1504 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_L), C_00000000,
1505 C_00000000, GPR(0), &pc);
1506 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_R), C_00000000,
1507 C_00000000, GPR(1), &pc);
1509 /* ADC Recording buffer[l/r] = AC97Input[l/r] */
1510 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_L), C_00000000,
1511 C_00000000, EXTIN(EXTIN_AC97_L), &pc);
1512 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_R), C_00000000,
1513 C_00000000, EXTIN(EXTIN_AC97_R), &pc);
1515 /* resume normal operations */
1516 emu_wrptr(sc, 0, DBG, 0);
1519 /* Probe and attach the card */
1521 emu_init(struct sc_info *sc)
1523 u_int32_t spcs, ch, tmp, i;
1525 /* enable additional AC97 slots */
1526 emu_wrptr(sc, 0, AC97SLOT, AC97SLOT_CNTR | AC97SLOT_LFE);
1528 /* disable audio and lock cache */
1529 emu_wr(sc, HCFG, HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE | HCFG_MUTEBUTTONENABLE, 4);
1531 /* reset recording buffers */
1532 emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE);
1533 emu_wrptr(sc, 0, MICBA, 0);
1534 emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE);
1535 emu_wrptr(sc, 0, FXBA, 0);
1536 emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE);
1537 emu_wrptr(sc, 0, ADCBA, 0);
1539 /* disable channel interrupt */
1540 emu_wr(sc, INTE, INTE_INTERVALTIMERENB | INTE_SAMPLERATETRACKER | INTE_PCIERRORENABLE, 4);
1541 emu_wrptr(sc, 0, CLIEL, 0);
1542 emu_wrptr(sc, 0, CLIEH, 0);
1543 emu_wrptr(sc, 0, SOLEL, 0);
1544 emu_wrptr(sc, 0, SOLEH, 0);
1546 /* wonder what these do... */
1548 emu_wrptr(sc, 0, SPBYPASS, 0xf00);
1549 emu_wrptr(sc, 0, AC97SLOT, 0x3);
1552 /* init envelope engine */
1553 for (ch = 0; ch < NUM_G; ch++) {
1554 emu_wrptr(sc, ch, DCYSUSV, ENV_OFF);
1555 emu_wrptr(sc, ch, IP, 0);
1556 emu_wrptr(sc, ch, VTFT, 0xffff);
1557 emu_wrptr(sc, ch, CVCF, 0xffff);
1558 emu_wrptr(sc, ch, PTRX, 0);
1559 emu_wrptr(sc, ch, CPF, 0);
1560 emu_wrptr(sc, ch, CCR, 0);
1562 emu_wrptr(sc, ch, PSST, 0);
1563 emu_wrptr(sc, ch, DSL, 0x10);
1564 emu_wrptr(sc, ch, CCCA, 0);
1565 emu_wrptr(sc, ch, Z1, 0);
1566 emu_wrptr(sc, ch, Z2, 0);
1567 emu_wrptr(sc, ch, FXRT, 0xd01c0000);
1569 emu_wrptr(sc, ch, ATKHLDM, 0);
1570 emu_wrptr(sc, ch, DCYSUSM, 0);
1571 emu_wrptr(sc, ch, IFATN, 0xffff);
1572 emu_wrptr(sc, ch, PEFE, 0);
1573 emu_wrptr(sc, ch, FMMOD, 0);
1574 emu_wrptr(sc, ch, TREMFRQ, 24); /* 1 Hz */
1575 emu_wrptr(sc, ch, FM2FRQ2, 24); /* 1 Hz */
1576 emu_wrptr(sc, ch, TEMPENV, 0);
1578 /*** these are last so OFF prevents writing ***/
1579 emu_wrptr(sc, ch, LFOVAL2, 0);
1580 emu_wrptr(sc, ch, LFOVAL1, 0);
1581 emu_wrptr(sc, ch, ATKHLDV, 0);
1582 emu_wrptr(sc, ch, ENVVOL, 0);
1583 emu_wrptr(sc, ch, ENVVAL, 0);
1586 /* audigy cards need this to initialize correctly */
1587 emu_wrptr(sc, ch, 0x4c, 0);
1588 emu_wrptr(sc, ch, 0x4d, 0);
1589 emu_wrptr(sc, ch, 0x4e, 0);
1590 emu_wrptr(sc, ch, 0x4f, 0);
1591 /* set default routing */
1592 emu_wrptr(sc, ch, A_FXRT1, 0x03020100);
1593 emu_wrptr(sc, ch, A_FXRT2, 0x3f3f3f3f);
1594 emu_wrptr(sc, ch, A_SENDAMOUNTS, 0);
1597 sc->voice[ch].vnum = ch;
1598 sc->voice[ch].slave = NULL;
1599 sc->voice[ch].busy = 0;
1600 sc->voice[ch].ismaster = 0;
1601 sc->voice[ch].running = 0;
1602 sc->voice[ch].b16 = 0;
1603 sc->voice[ch].stereo = 0;
1604 sc->voice[ch].speed = 0;
1605 sc->voice[ch].start = 0;
1606 sc->voice[ch].end = 0;
1607 sc->voice[ch].channel = NULL;
1609 sc->pnum = sc->rnum = 0;
1612 * Init to 0x02109204 :
1613 * Clock accuracy = 0 (1000ppm)
1614 * Sample Rate = 2 (48kHz)
1615 * Audio Channel = 1 (Left of 2)
1616 * Source Number = 0 (Unspecified)
1617 * Generation Status = 1 (Original for Cat Code 12)
1618 * Cat Code = 12 (Digital Signal Mixer)
1620 * Emphasis = 0 (None)
1621 * CP = 1 (Copyright unasserted)
1622 * AN = 0 (Audio data)
1625 spcs = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
1626 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
1627 SPCS_GENERATIONSTATUS | 0x00001200 | 0x00000000 |
1628 SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT;
1629 emu_wrptr(sc, 0, SPCS0, spcs);
1630 emu_wrptr(sc, 0, SPCS1, spcs);
1631 emu_wrptr(sc, 0, SPCS2, spcs);
1635 else if (sc->audigy2) { /* Audigy 2 */
1636 /* from ALSA initialization code: */
1638 /* Hack for Alice3 to work independent of haP16V driver */
1641 /* Setup SRCMulti_I2S SamplingRate */
1642 tmp = emu_rdptr(sc, 0, A_SPDIF_SAMPLERATE) & 0xfffff1ff;
1643 emu_wrptr(sc, 0, A_SPDIF_SAMPLERATE, tmp | 0x400);
1645 /* Setup SRCSel (Enable SPDIF, I2S SRCMulti) */
1646 emu_wr(sc, 0x20, 0x00600000, 4);
1647 emu_wr(sc, 0x24, 0x00000014, 4);
1649 /* Setup SRCMulti Input Audio Enable */
1650 emu_wr(sc, 0x20, 0x006e0000, 4);
1651 emu_wr(sc, 0x24, 0xff00ff00, 4);
1654 SLIST_INIT(&sc->mem.blocks);
1655 sc->mem.ptb_pages = emu_malloc(sc, MAXPAGES * sizeof(u_int32_t));
1656 if (sc->mem.ptb_pages == NULL)
1659 sc->mem.silent_page = emu_malloc(sc, EMUPAGESIZE);
1660 if (sc->mem.silent_page == NULL) {
1661 emu_free(sc, sc->mem.ptb_pages);
1664 /* Clear page with silence & setup all pointers to this page */
1665 bzero(sc->mem.silent_page, EMUPAGESIZE);
1666 tmp = (u_int32_t)vtophys(sc->mem.silent_page) << 1;
1667 for (i = 0; i < MAXPAGES; i++)
1668 sc->mem.ptb_pages[i] = tmp | i;
1670 emu_wrptr(sc, 0, PTB, vtophys(sc->mem.ptb_pages));
1671 emu_wrptr(sc, 0, TCB, 0); /* taken from original driver */
1672 emu_wrptr(sc, 0, TCBS, 0); /* taken from original driver */
1674 for (ch = 0; ch < NUM_G; ch++) {
1675 emu_wrptr(sc, ch, MAPA, tmp | MAP_PTI_MASK);
1676 emu_wrptr(sc, ch, MAPB, tmp | MAP_PTI_MASK);
1679 /* emu_memalloc(sc, EMUPAGESIZE); */
1681 * Hokay, now enable the AUD bit
1684 * Enable Audio = 0 (enabled after fx processor initialization)
1685 * Mute Disable Audio = 0
1690 * Mute Disable Audio = 0
1692 * GP S/PDIF AC3 Enable = 1
1693 * CD S/PDIF AC3 Enable = 1
1697 * Mute Disable Audio = 0
1698 * Lock Tank Memory = 1
1699 * Lock Sound Memory = 0
1703 tmp = HCFG_AUTOMUTE | HCFG_JOYENABLE;
1704 if (sc->audigy2) /* Audigy 2 */
1705 tmp = HCFG_AUDIOENABLE | HCFG_AC3ENABLE_CDSPDIF |
1706 HCFG_AC3ENABLE_GPSPDIF;
1707 emu_wr(sc, HCFG, tmp, 4);
1711 /* from ALSA initialization code: */
1713 /* enable audio and disable both audio/digital outputs */
1714 emu_wr(sc, HCFG, emu_rd(sc, HCFG, 4) | HCFG_AUDIOENABLE, 4);
1715 emu_wr(sc, A_IOCFG, emu_rd(sc, A_IOCFG, 4) & ~A_IOCFG_GPOUT_AD, 4);
1716 if (sc->audigy2) { /* Audigy 2 */
1717 /* Unmute Analog. Set GPO6 to 1 for Apollo.
1718 * This has to be done after init Alice3 I2SOut beyond 48kHz.
1719 * So, sequence is important.
1721 emu_wr(sc, A_IOCFG, emu_rd(sc, A_IOCFG, 4) | A_IOCFG_GPOUT_A, 4);
1724 /* EMU10K1 initialization code */
1725 tmp = HCFG_AUDIOENABLE | HCFG_AUTOMUTE | HCFG_LOCKTANKCACHE;
1727 tmp |= HCFG_JOYENABLE;
1729 emu_wr(sc, HCFG, tmp, 4);
1731 /* TOSLink detection */
1733 tmp = emu_rd(sc, HCFG, 4);
1734 if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) {
1735 emu_wr(sc, HCFG, tmp | HCFG_GPOUT1, 4);
1737 if (tmp != (emu_rd(sc, HCFG, 4) & ~HCFG_GPOUT1)) {
1739 emu_wr(sc, HCFG, tmp, 4);
1748 emu_uninit(struct sc_info *sc)
1752 emu_wr(sc, INTE, 0, 4);
1753 for (ch = 0; ch < NUM_G; ch++)
1754 emu_wrptr(sc, ch, DCYSUSV, ENV_OFF);
1755 for (ch = 0; ch < NUM_G; ch++) {
1756 emu_wrptr(sc, ch, VTFT, 0);
1757 emu_wrptr(sc, ch, CVCF, 0);
1758 emu_wrptr(sc, ch, PTRX, 0);
1759 emu_wrptr(sc, ch, CPF, 0);
1763 /* stop fx processor */
1764 emu_wrptr(sc, 0, A_DBG, A_DBG_SINGLE_STEP);
1767 /* disable audio and lock cache */
1768 emu_wr(sc, HCFG, HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE | HCFG_MUTEBUTTONENABLE, 4);
1770 emu_wrptr(sc, 0, PTB, 0);
1771 /* reset recording buffers */
1772 emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE);
1773 emu_wrptr(sc, 0, MICBA, 0);
1774 emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE);
1775 emu_wrptr(sc, 0, FXBA, 0);
1776 emu_wrptr(sc, 0, FXWC, 0);
1777 emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE);
1778 emu_wrptr(sc, 0, ADCBA, 0);
1779 emu_wrptr(sc, 0, TCB, 0);
1780 emu_wrptr(sc, 0, TCBS, 0);
1782 /* disable channel interrupt */
1783 emu_wrptr(sc, 0, CLIEL, 0);
1784 emu_wrptr(sc, 0, CLIEH, 0);
1785 emu_wrptr(sc, 0, SOLEL, 0);
1786 emu_wrptr(sc, 0, SOLEH, 0);
1789 /* init envelope engine */
1790 if (!SLIST_EMPTY(&sc->mem.blocks))
1791 device_printf(sc->dev, "warning: memblock list not empty\n");
1792 emu_free(sc, sc->mem.ptb_pages);
1793 emu_free(sc, sc->mem.silent_page);
1799 emu_pci_probe(device_t dev)
1803 switch (pci_get_devid(dev)) {
1804 case EMU10K1_PCI_ID:
1805 s = "Creative EMU10K1";
1808 case EMU10K2_PCI_ID:
1809 if (pci_get_revid(dev) == 0x04)
1810 s = "Creative Audigy 2 (EMU10K2)";
1812 s = "Creative Audigy (EMU10K2)";
1819 device_set_desc(dev, s);
1824 emu_pci_attach(device_t dev)
1826 struct ac97_info *codec = NULL;
1830 char status[SND_STATUSLEN];
1832 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO)) == NULL) {
1833 device_printf(dev, "cannot allocate softc\n");
1837 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc");
1839 sc->type = pci_get_devid(dev);
1840 sc->rev = pci_get_revid(dev);
1841 sc->audigy = (sc->type == EMU10K2_PCI_ID);
1842 sc->audigy2 = (sc->audigy && sc->rev == 0x04);
1843 sc->nchans = sc->audigy ? 8 : 4;
1844 sc->addrmask = sc->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK;
1846 data = pci_read_config(dev, PCIR_COMMAND, 2);
1847 data |= (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN);
1848 pci_write_config(dev, PCIR_COMMAND, data, 2);
1849 data = pci_read_config(dev, PCIR_COMMAND, 2);
1852 sc->reg = bus_alloc_resource(dev, SYS_RES_IOPORT, &i, 0, ~0, 1, RF_ACTIVE);
1853 if (sc->reg == NULL) {
1854 device_printf(dev, "unable to map register space\n");
1857 sc->st = rman_get_bustag(sc->reg);
1858 sc->sh = rman_get_bushandle(sc->reg);
1860 sc->bufsz = pcm_getbuffersize(dev, 4096, EMU_DEFAULT_BUFSZ, 65536);
1862 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
1863 /*lowaddr*/1 << 31, /* can only access 0-2gb */
1864 /*highaddr*/BUS_SPACE_MAXADDR,
1865 /*filter*/NULL, /*filterarg*/NULL,
1866 /*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff,
1867 /*flags*/0, &sc->parent_dmat) != 0) {
1868 device_printf(dev, "unable to create dma tag\n");
1872 if (emu_init(sc) == -1) {
1873 device_printf(dev, "unable to initialize the card\n");
1877 codec = AC97_CREATE(dev, sc, emu_ac97);
1878 if (codec == NULL) goto bad;
1879 gotmic = (ac97_getcaps(codec) & AC97_CAP_MICCHANNEL)? 1 : 0;
1880 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad;
1883 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &i, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
1884 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, emu_intr, sc, &sc->ih)) {
1885 device_printf(dev, "unable to map interrupt\n");
1889 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld", rman_get_start(sc->reg), rman_get_start(sc->irq));
1891 if (pcm_register(dev, sc, sc->nchans, gotmic? 3 : 2)) goto bad;
1892 for (i = 0; i < sc->nchans; i++)
1893 pcm_addchan(dev, PCMDIR_PLAY, &emupchan_class, sc);
1894 for (i = 0; i < (gotmic? 3 : 2); i++)
1895 pcm_addchan(dev, PCMDIR_REC, &emurchan_class, sc);
1897 pcm_setstatus(dev, status);
1902 if (codec) ac97_destroy(codec);
1903 if (sc->reg) bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS, sc->reg);
1904 if (sc->ih) bus_teardown_intr(dev, sc->irq, sc->ih);
1905 if (sc->irq) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
1906 if (sc->parent_dmat) bus_dma_tag_destroy(sc->parent_dmat);
1907 if (sc->lock) snd_mtxfree(sc->lock);
1913 emu_pci_detach(device_t dev)
1918 r = pcm_unregister(dev);
1922 sc = pcm_getdevinfo(dev);
1926 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS, sc->reg);
1927 bus_teardown_intr(dev, sc->irq, sc->ih);
1928 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
1929 bus_dma_tag_destroy(sc->parent_dmat);
1930 snd_mtxfree(sc->lock);
1936 /* add suspend, resume */
1937 static device_method_t emu_methods[] = {
1938 /* Device interface */
1939 DEVMETHOD(device_probe, emu_pci_probe),
1940 DEVMETHOD(device_attach, emu_pci_attach),
1941 DEVMETHOD(device_detach, emu_pci_detach),
1946 static driver_t emu_driver = {
1952 DRIVER_MODULE(snd_emu10k1, pci, emu_driver, pcm_devclass, 0, 0);
1953 MODULE_DEPEND(snd_emu10k1, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
1954 MODULE_VERSION(snd_emu10k1, 1);
1956 /* dummy driver to silence the joystick device */
1958 emujoy_pci_probe(device_t dev)
1962 switch (pci_get_devid(dev)) {
1964 s = "Creative EMU10K1 Joystick";
1968 s = "Creative EMU10K2 Joystick";
1973 if (s) device_set_desc(dev, s);
1974 return s? -1000 : ENXIO;
1978 emujoy_pci_attach(device_t dev)
1984 emujoy_pci_detach(device_t dev)
1989 static device_method_t emujoy_methods[] = {
1990 DEVMETHOD(device_probe, emujoy_pci_probe),
1991 DEVMETHOD(device_attach, emujoy_pci_attach),
1992 DEVMETHOD(device_detach, emujoy_pci_detach),
1997 static driver_t emujoy_driver = {
2003 static devclass_t emujoy_devclass;
2005 DRIVER_MODULE(emujoy, pci, emujoy_driver, emujoy_devclass, 0, 0);