2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/export.h>
31 #include <linux/slab.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 static const struct dp_link_dpll gen4_dpll[] = {
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53 static const struct dp_link_dpll pch_dpll[] = {
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60 static const struct dp_link_dpll vlv_dpll[] = {
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
68 * CHV supports eDP 1.4 that have more link rates.
69 * Below only provides the fixed rate but exclude variable rate.
71 static const struct dp_link_dpll chv_dpll[] = {
73 * CHV requires to program fractional division for m2.
74 * m2 is stored in fixed point format using formula below
75 * (m2_int << 22) | m2_fraction
77 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
78 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
79 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
80 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
81 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
86 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
87 * @intel_dp: DP struct
89 * If a CPU or PCH DP output is attached to an eDP panel, this function
90 * will return true, and false otherwise.
92 static bool is_edp(struct intel_dp *intel_dp)
94 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
96 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
99 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
101 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
103 return intel_dig_port->base.base.dev;
106 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
108 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
111 static void intel_dp_link_down(struct intel_dp *intel_dp);
112 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
115 intel_dp_max_link_bw(struct intel_dp *intel_dp)
117 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
118 struct drm_device *dev = intel_dp->attached_connector->base.dev;
120 switch (max_link_bw) {
121 case DP_LINK_BW_1_62:
124 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
125 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
126 INTEL_INFO(dev)->gen >= 8) &&
127 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
128 max_link_bw = DP_LINK_BW_5_4;
130 max_link_bw = DP_LINK_BW_2_7;
133 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
135 max_link_bw = DP_LINK_BW_1_62;
141 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
143 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
144 struct drm_device *dev = intel_dig_port->base.base.dev;
145 u8 source_max, sink_max;
148 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
149 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
152 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
154 return min(source_max, sink_max);
158 * The units on the numbers in the next two are... bizarre. Examples will
159 * make it clearer; this one parallels an example in the eDP spec.
161 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
163 * 270000 * 1 * 8 / 10 == 216000
165 * The actual data capacity of that configuration is 2.16Gbit/s, so the
166 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
167 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
168 * 119000. At 18bpp that's 2142000 kilobits per second.
170 * Thus the strange-looking division by 10 in intel_dp_link_required, to
171 * get the result in decakilobits instead of kilobits.
175 intel_dp_link_required(int pixel_clock, int bpp)
177 return (pixel_clock * bpp + 9) / 10;
181 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
183 return (max_link_clock * max_lanes * 8) / 10;
186 static enum drm_mode_status
187 intel_dp_mode_valid(struct drm_connector *connector,
188 struct drm_display_mode *mode)
190 struct intel_dp *intel_dp = intel_attached_dp(connector);
191 struct intel_connector *intel_connector = to_intel_connector(connector);
192 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
193 int target_clock = mode->clock;
194 int max_rate, mode_rate, max_lanes, max_link_clock;
196 if (is_edp(intel_dp) && fixed_mode) {
197 if (mode->hdisplay > fixed_mode->hdisplay)
200 if (mode->vdisplay > fixed_mode->vdisplay)
203 target_clock = fixed_mode->clock;
206 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
207 max_lanes = intel_dp_max_lane_count(intel_dp);
209 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
210 mode_rate = intel_dp_link_required(target_clock, 18);
212 if (mode_rate > max_rate)
213 return MODE_CLOCK_HIGH;
215 if (mode->clock < 10000)
216 return MODE_CLOCK_LOW;
218 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
219 return MODE_H_ILLEGAL;
225 pack_aux(uint8_t *src, int src_bytes)
232 for (i = 0; i < src_bytes; i++)
233 v |= ((uint32_t) src[i]) << ((3-i) * 8);
238 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
243 for (i = 0; i < dst_bytes; i++)
244 dst[i] = src >> ((3-i) * 8);
247 /* hrawclock is 1/4 the FSB frequency */
249 intel_hrawclk(struct drm_device *dev)
251 struct drm_i915_private *dev_priv = dev->dev_private;
254 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
255 if (IS_VALLEYVIEW(dev))
258 clkcfg = I915_READ(CLKCFG);
259 switch (clkcfg & CLKCFG_FSB_MASK) {
268 case CLKCFG_FSB_1067:
270 case CLKCFG_FSB_1333:
272 /* these two are just a guess; one of them might be right */
273 case CLKCFG_FSB_1600:
274 case CLKCFG_FSB_1600_ALT:
282 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
283 struct intel_dp *intel_dp,
284 struct edp_power_seq *out);
286 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
287 struct intel_dp *intel_dp,
288 struct edp_power_seq *out);
290 static enum i915_pipe
291 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
293 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
294 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
295 struct drm_device *dev = intel_dig_port->base.base.dev;
296 struct drm_i915_private *dev_priv = dev->dev_private;
297 enum port port = intel_dig_port->port;
300 /* modeset should have pipe */
302 return to_intel_crtc(crtc)->pipe;
304 /* init time, try to find a pipe with this port selected */
305 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
306 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
307 PANEL_PORT_SELECT_MASK;
308 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
310 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
318 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
320 struct drm_device *dev = intel_dp_to_dev(intel_dp);
322 if (HAS_PCH_SPLIT(dev))
323 return PCH_PP_CONTROL;
325 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
328 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
330 struct drm_device *dev = intel_dp_to_dev(intel_dp);
332 if (HAS_PCH_SPLIT(dev))
333 return PCH_PP_STATUS;
335 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
338 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
339 This function only applicable when panel PM state is not to be tracked */
341 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
344 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
346 struct drm_device *dev = intel_dp_to_dev(intel_dp);
347 struct drm_i915_private *dev_priv = dev->dev_private;
349 u32 pp_ctrl_reg, pp_div_reg;
350 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);
352 if (!is_edp(intel_dp) || code != SYS_RESTART)
355 if (IS_VALLEYVIEW(dev)) {
356 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
357 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
358 pp_div = I915_READ(pp_div_reg);
359 pp_div &= PP_REFERENCE_DIVIDER_MASK;
361 /* 0x1F write to PP_DIV_REG sets max cycle delay */
362 I915_WRITE(pp_div_reg, pp_div | 0x1F);
363 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
364 msleep(intel_dp->panel_power_cycle_delay);
371 static bool edp_have_panel_power(struct intel_dp *intel_dp)
373 struct drm_device *dev = intel_dp_to_dev(intel_dp);
374 struct drm_i915_private *dev_priv = dev->dev_private;
376 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
379 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
381 struct drm_device *dev = intel_dp_to_dev(intel_dp);
382 struct drm_i915_private *dev_priv = dev->dev_private;
383 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
384 struct intel_encoder *intel_encoder = &intel_dig_port->base;
385 enum intel_display_power_domain power_domain;
387 power_domain = intel_display_port_power_domain(intel_encoder);
388 return intel_display_power_enabled(dev_priv, power_domain) &&
389 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
393 intel_dp_check_edp(struct intel_dp *intel_dp)
395 struct drm_device *dev = intel_dp_to_dev(intel_dp);
396 struct drm_i915_private *dev_priv = dev->dev_private;
398 if (!is_edp(intel_dp))
401 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
402 WARN(1, "eDP powered off while attempting aux channel communication.\n");
403 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
404 I915_READ(_pp_stat_reg(intel_dp)),
405 I915_READ(_pp_ctrl_reg(intel_dp)));
410 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
412 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
413 struct drm_device *dev = intel_dig_port->base.base.dev;
414 struct drm_i915_private *dev_priv = dev->dev_private;
415 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
419 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
421 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
422 msecs_to_jiffies_timeout(10));
424 done = wait_for_atomic(C, 10) == 0;
426 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
433 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
435 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
436 struct drm_device *dev = intel_dig_port->base.base.dev;
439 * The clock divider is based off the hrawclk, and would like to run at
440 * 2MHz. So, take the hrawclk value and divide by 2 and use that
442 return index ? 0 : intel_hrawclk(dev) / 2;
445 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
447 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
448 struct drm_device *dev = intel_dig_port->base.base.dev;
453 if (intel_dig_port->port == PORT_A) {
454 if (IS_GEN6(dev) || IS_GEN7(dev))
455 return 200; /* SNB & IVB eDP input clock at 400Mhz */
457 return 225; /* eDP input clock at 450Mhz */
459 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
463 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
465 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
466 struct drm_device *dev = intel_dig_port->base.base.dev;
467 struct drm_i915_private *dev_priv = dev->dev_private;
469 if (intel_dig_port->port == PORT_A) {
472 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
473 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
474 /* Workaround for non-ULT HSW */
481 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
485 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
487 return index ? 0 : 100;
490 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
493 uint32_t aux_clock_divider)
495 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
496 struct drm_device *dev = intel_dig_port->base.base.dev;
497 uint32_t precharge, timeout;
504 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
505 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
507 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
509 return DP_AUX_CH_CTL_SEND_BUSY |
511 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
512 DP_AUX_CH_CTL_TIME_OUT_ERROR |
514 DP_AUX_CH_CTL_RECEIVE_ERROR |
515 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
516 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
517 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
521 intel_dp_aux_ch(struct intel_dp *intel_dp,
522 uint8_t *send, int send_bytes,
523 uint8_t *recv, int recv_size)
525 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
526 struct drm_device *dev = intel_dig_port->base.base.dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
529 uint32_t ch_data = ch_ctl + 4;
530 uint32_t aux_clock_divider;
531 int i, ret, recv_bytes;
534 bool has_aux_irq = HAS_AUX_IRQ(dev);
536 /* dp aux is extremely sensitive to irq latency, hence request the
537 * lowest possible wakeup latency and so prevent the cpu from going into
540 pm_qos_update_request(&dev_priv->pm_qos, 0);
542 intel_dp_check_edp(intel_dp);
544 intel_aux_display_runtime_get(dev_priv);
546 /* Try to wait for any previous AUX channel activity */
547 for (try = 0; try < 3; try++) {
548 status = I915_READ_NOTRACE(ch_ctl);
549 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
555 WARN(1, "dp_aux_ch not started status 0x%08x\n",
561 /* Only 5 data registers! */
562 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
567 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
568 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
573 /* Must try at least 3 times according to DP spec */
574 for (try = 0; try < 5; try++) {
575 /* Load the send data into the aux channel data registers */
576 for (i = 0; i < send_bytes; i += 4)
577 I915_WRITE(ch_data + i,
578 pack_aux(send + i, send_bytes - i));
580 /* Send the command and wait for it to complete */
581 I915_WRITE(ch_ctl, send_ctl);
583 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
585 /* Clear done status and any errors */
589 DP_AUX_CH_CTL_TIME_OUT_ERROR |
590 DP_AUX_CH_CTL_RECEIVE_ERROR);
592 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
593 DP_AUX_CH_CTL_RECEIVE_ERROR))
595 if (status & DP_AUX_CH_CTL_DONE)
598 if (status & DP_AUX_CH_CTL_DONE)
602 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
603 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
608 /* Check for timeout or receive error.
609 * Timeouts occur when the sink is not connected
611 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
612 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
617 /* Timeouts occur when the device isn't connected, so they're
618 * "normal" -- don't fill the kernel log with these */
619 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
620 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
625 /* Unload any bytes sent back from the other side */
626 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
627 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
628 if (recv_bytes > recv_size)
629 recv_bytes = recv_size;
631 for (i = 0; i < recv_bytes; i += 4)
632 unpack_aux(I915_READ(ch_data + i),
633 recv + i, recv_bytes - i);
637 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
638 intel_aux_display_runtime_put(dev_priv);
643 #define BARE_ADDRESS_SIZE 3
644 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
646 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
648 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
649 uint8_t txbuf[20], rxbuf[20];
650 size_t txsize, rxsize;
653 txbuf[0] = msg->request << 4;
654 txbuf[1] = msg->address >> 8;
655 txbuf[2] = msg->address & 0xff;
656 txbuf[3] = msg->size - 1;
658 switch (msg->request & ~DP_AUX_I2C_MOT) {
659 case DP_AUX_NATIVE_WRITE:
660 case DP_AUX_I2C_WRITE:
661 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
664 if (WARN_ON(txsize > 20))
667 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
669 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
671 msg->reply = rxbuf[0] >> 4;
673 /* Return payload size. */
678 case DP_AUX_NATIVE_READ:
679 case DP_AUX_I2C_READ:
680 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
681 rxsize = msg->size + 1;
683 if (WARN_ON(rxsize > 20))
686 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
688 msg->reply = rxbuf[0] >> 4;
690 * Assume happy day, and copy the data. The caller is
691 * expected to check msg->reply before touching it.
693 * Return payload size.
696 memcpy(msg->buffer, rxbuf + 1, ret);
709 intel_dp_i2c_aux_ch(struct device *adapter, int mode,
710 uint8_t write_byte, uint8_t *read_byte)
712 struct i2c_algo_dp_aux_data *data = device_get_softc(adapter);
713 struct intel_dp *intel_dp = data->priv;
714 uint16_t address = data->address;
722 intel_edp_panel_vdd_on(intel_dp);
723 intel_dp_check_edp(intel_dp);
724 /* Set up the command byte */
725 if (mode & MODE_I2C_READ)
726 msg[0] = DP_AUX_I2C_READ << 4;
728 msg[0] = DP_AUX_I2C_WRITE << 4;
730 if (!(mode & MODE_I2C_STOP))
731 msg[0] |= DP_AUX_I2C_MOT << 4;
733 msg[1] = address >> 8;
755 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
756 * required to retry at least seven times upon receiving AUX_DEFER
757 * before giving up the AUX transaction.
759 for (retry = 0; retry < 7; retry++) {
760 ret = intel_dp_aux_ch(intel_dp,
764 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
768 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
769 case DP_AUX_NATIVE_REPLY_ACK:
770 /* I2C-over-AUX Reply field is only valid
771 * when paired with AUX ACK.
774 case DP_AUX_NATIVE_REPLY_NACK:
775 DRM_DEBUG_KMS("aux_ch native nack\n");
778 case DP_AUX_NATIVE_REPLY_DEFER:
780 * For now, just give more slack to branch devices. We
781 * could check the DPCD for I2C bit rate capabilities,
782 * and if available, adjust the interval. We could also
783 * be more careful with DP-to-Legacy adapters where a
784 * long legacy cable may force very low I2C bit rates.
786 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
787 DP_DWN_STRM_PORT_PRESENT)
788 usleep_range(500, 600);
790 usleep_range(300, 400);
793 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
799 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
800 case DP_AUX_I2C_REPLY_ACK:
801 if (mode == MODE_I2C_READ) {
802 *read_byte = reply[1];
804 ret = 0; /* reply_bytes - 1 */
806 case DP_AUX_I2C_REPLY_NACK:
807 DRM_DEBUG_KMS("aux_i2c nack\n");
810 case DP_AUX_I2C_REPLY_DEFER:
811 DRM_DEBUG_KMS("aux_i2c defer\n");
815 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
821 DRM_ERROR("too many retries, giving up\n");
829 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
831 struct drm_device *dev = intel_dp_to_dev(intel_dp);
832 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
833 enum port port = intel_dig_port->port;
834 const char *name = NULL;
839 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
843 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
847 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
851 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
859 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
861 intel_dp->aux.name = name;
862 intel_dp->aux.dev = dev->dev;
863 intel_dp->aux.transfer = intel_dp_aux_transfer;
865 DRM_DEBUG_KMS("i2c_init %s\n", name);
866 ret = iic_dp_aux_add_bus(connector->base.dev->dev, name,
867 intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,
869 WARN(ret, "intel_dp_i2c_init failed with error %d for port %c\n",
870 ret, port_name(port));
875 intel_dp_connector_unregister(struct intel_connector *intel_connector)
877 intel_connector_unregister(intel_connector);
882 intel_dp_i2c_init(struct intel_dp *intel_dp,
883 struct intel_connector *intel_connector, const char *name)
887 DRM_DEBUG_KMS("i2c_init %s\n", name);
889 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
890 intel_dp->adapter.owner = THIS_MODULE;
891 intel_dp->adapter.class = I2C_CLASS_DDC;
892 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
893 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
894 intel_dp->adapter.algo_data = &intel_dp->algo;
895 intel_dp->adapter.dev.parent = intel_connector->base.dev->dev;
897 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
901 ret = sysfs_create_link(&intel_connector->base.kdev->kobj,
902 &intel_dp->adapter.dev.kobj,
903 intel_dp->adapter.dev.kobj.name);
905 ret = iic_dp_aux_add_bus(intel_connector->base.dev->dev, name,
906 intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,
914 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
917 case DP_LINK_BW_1_62:
918 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
921 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
924 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
930 intel_dp_set_clock(struct intel_encoder *encoder,
931 struct intel_crtc_config *pipe_config, int link_bw)
933 struct drm_device *dev = encoder->base.dev;
934 const struct dp_link_dpll *divisor = NULL;
939 count = ARRAY_SIZE(gen4_dpll);
940 } else if (HAS_PCH_SPLIT(dev)) {
942 count = ARRAY_SIZE(pch_dpll);
943 } else if (IS_CHERRYVIEW(dev)) {
945 count = ARRAY_SIZE(chv_dpll);
946 } else if (IS_VALLEYVIEW(dev)) {
948 count = ARRAY_SIZE(vlv_dpll);
951 if (divisor && count) {
952 for (i = 0; i < count; i++) {
953 if (link_bw == divisor[i].link_bw) {
954 pipe_config->dpll = divisor[i].dpll;
955 pipe_config->clock_set = true;
963 intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
965 struct drm_device *dev = crtc->base.dev;
966 struct drm_i915_private *dev_priv = dev->dev_private;
967 enum transcoder transcoder = crtc->config.cpu_transcoder;
969 I915_WRITE(PIPE_DATA_M2(transcoder),
970 TU_SIZE(m_n->tu) | m_n->gmch_m);
971 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
972 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
973 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
977 intel_dp_compute_config(struct intel_encoder *encoder,
978 struct intel_crtc_config *pipe_config)
980 struct drm_device *dev = encoder->base.dev;
981 struct drm_i915_private *dev_priv = dev->dev_private;
982 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
983 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
984 enum port port = dp_to_dig_port(intel_dp)->port;
985 struct intel_crtc *intel_crtc = encoder->new_crtc;
986 struct intel_connector *intel_connector = intel_dp->attached_connector;
987 int lane_count, clock;
988 int min_lane_count = 1;
989 int max_lane_count = intel_dp_max_lane_count(intel_dp);
990 /* Conveniently, the link BW constants become indices with a shift...*/
992 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
994 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
995 int link_avail, link_clock;
997 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
998 pipe_config->has_pch_encoder = true;
1000 pipe_config->has_dp_encoder = true;
1001 pipe_config->has_audio = intel_dp->has_audio;
1003 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1004 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1006 if (!HAS_PCH_SPLIT(dev))
1007 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1008 intel_connector->panel.fitting_mode);
1010 intel_pch_panel_fitting(intel_crtc, pipe_config,
1011 intel_connector->panel.fitting_mode);
1014 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1017 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1018 "max bw %02x pixel clock %iKHz\n",
1019 max_lane_count, bws[max_clock],
1020 adjusted_mode->crtc_clock);
1022 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1023 * bpc in between. */
1024 bpp = pipe_config->pipe_bpp;
1025 if (is_edp(intel_dp)) {
1026 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1027 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1028 dev_priv->vbt.edp_bpp);
1029 bpp = dev_priv->vbt.edp_bpp;
1032 if (IS_BROADWELL(dev)) {
1033 /* Yes, it's an ugly hack. */
1034 min_lane_count = max_lane_count;
1035 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
1037 } else if (dev_priv->vbt.edp_lanes) {
1038 min_lane_count = min(dev_priv->vbt.edp_lanes,
1040 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
1044 if (dev_priv->vbt.edp_rate) {
1045 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
1046 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
1051 for (; bpp >= 6*3; bpp -= 2*3) {
1052 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1055 for (clock = min_clock; clock <= max_clock; clock++) {
1056 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
1057 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1058 link_avail = intel_dp_max_data_rate(link_clock,
1061 if (mode_rate <= link_avail) {
1071 if (intel_dp->color_range_auto) {
1074 * CEA-861-E - 5.1 Default Encoding Parameters
1075 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1077 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
1078 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1080 intel_dp->color_range = 0;
1083 if (intel_dp->color_range)
1084 pipe_config->limited_color_range = true;
1086 intel_dp->link_bw = bws[clock];
1087 intel_dp->lane_count = lane_count;
1088 pipe_config->pipe_bpp = bpp;
1089 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
1091 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1092 intel_dp->link_bw, intel_dp->lane_count,
1093 pipe_config->port_clock, bpp);
1094 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1095 mode_rate, link_avail);
1097 intel_link_compute_m_n(bpp, lane_count,
1098 adjusted_mode->crtc_clock,
1099 pipe_config->port_clock,
1100 &pipe_config->dp_m_n);
1102 if (intel_connector->panel.downclock_mode != NULL &&
1103 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
1104 intel_link_compute_m_n(bpp, lane_count,
1105 intel_connector->panel.downclock_mode->clock,
1106 pipe_config->port_clock,
1107 &pipe_config->dp_m2_n2);
1111 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1113 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
1118 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1120 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1121 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1122 struct drm_device *dev = crtc->base.dev;
1123 struct drm_i915_private *dev_priv = dev->dev_private;
1126 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
1127 dpa_ctl = I915_READ(DP_A);
1128 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1130 if (crtc->config.port_clock == 162000) {
1131 /* For a long time we've carried around a ILK-DevA w/a for the
1132 * 160MHz clock. If we're really unlucky, it's still required.
1134 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1135 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1136 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1138 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1139 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1142 I915_WRITE(DP_A, dpa_ctl);
1148 static void intel_dp_prepare(struct intel_encoder *encoder)
1150 struct drm_device *dev = encoder->base.dev;
1151 struct drm_i915_private *dev_priv = dev->dev_private;
1152 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1153 enum port port = dp_to_dig_port(intel_dp)->port;
1154 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1155 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1158 * There are four kinds of DP registers:
1165 * IBX PCH and CPU are the same for almost everything,
1166 * except that the CPU DP PLL is configured in this
1169 * CPT PCH is quite different, having many bits moved
1170 * to the TRANS_DP_CTL register instead. That
1171 * configuration happens (oddly) in ironlake_pch_enable
1174 /* Preserve the BIOS-computed detected bit. This is
1175 * supposed to be read-only.
1177 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1179 /* Handle DP bits in common between all three register formats */
1180 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1181 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1183 if (crtc->config.has_audio) {
1184 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1185 pipe_name(crtc->pipe));
1186 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1187 intel_write_eld(&encoder->base, adjusted_mode);
1190 /* Split out the IBX/CPU vs CPT settings */
1192 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1193 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1194 intel_dp->DP |= DP_SYNC_HS_HIGH;
1195 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1196 intel_dp->DP |= DP_SYNC_VS_HIGH;
1197 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1199 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1200 intel_dp->DP |= DP_ENHANCED_FRAMING;
1202 intel_dp->DP |= crtc->pipe << 29;
1203 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1204 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1205 intel_dp->DP |= intel_dp->color_range;
1207 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1208 intel_dp->DP |= DP_SYNC_HS_HIGH;
1209 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1210 intel_dp->DP |= DP_SYNC_VS_HIGH;
1211 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1213 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1214 intel_dp->DP |= DP_ENHANCED_FRAMING;
1216 if (!IS_CHERRYVIEW(dev)) {
1217 if (crtc->pipe == 1)
1218 intel_dp->DP |= DP_PIPEB_SELECT;
1220 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1223 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1227 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1228 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1230 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1231 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1233 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1234 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1236 static void wait_panel_status(struct intel_dp *intel_dp,
1240 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1241 struct drm_i915_private *dev_priv = dev->dev_private;
1242 u32 pp_stat_reg, pp_ctrl_reg;
1244 pp_stat_reg = _pp_stat_reg(intel_dp);
1245 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1247 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1249 I915_READ(pp_stat_reg),
1250 I915_READ(pp_ctrl_reg));
1252 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1253 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1254 I915_READ(pp_stat_reg),
1255 I915_READ(pp_ctrl_reg));
1258 DRM_DEBUG_KMS("Wait complete\n");
1261 static void wait_panel_on(struct intel_dp *intel_dp)
1263 DRM_DEBUG_KMS("Wait for panel power on\n");
1264 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1267 static void wait_panel_off(struct intel_dp *intel_dp)
1269 DRM_DEBUG_KMS("Wait for panel power off time\n");
1270 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1273 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1275 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1277 /* When we disable the VDD override bit last we have to do the manual
1279 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1280 intel_dp->panel_power_cycle_delay);
1282 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1285 static void wait_backlight_on(struct intel_dp *intel_dp)
1287 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1288 intel_dp->backlight_on_delay);
1291 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1293 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1294 intel_dp->backlight_off_delay);
1297 /* Read the current pp_control value, unlocking the register if it
1301 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1303 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1307 control = I915_READ(_pp_ctrl_reg(intel_dp));
1308 control &= ~PANEL_UNLOCK_MASK;
1309 control |= PANEL_UNLOCK_REGS;
1313 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1315 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1316 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1317 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1318 struct drm_i915_private *dev_priv = dev->dev_private;
1319 enum intel_display_power_domain power_domain;
1321 u32 pp_stat_reg, pp_ctrl_reg;
1323 if (!is_edp(intel_dp))
1326 WARN(intel_dp->want_panel_vdd,
1327 "eDP VDD already requested on\n");
1329 intel_dp->want_panel_vdd = true;
1331 if (edp_have_panel_vdd(intel_dp))
1334 power_domain = intel_display_port_power_domain(intel_encoder);
1335 intel_display_power_get(dev_priv, power_domain);
1337 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1339 if (!edp_have_panel_power(intel_dp))
1340 wait_panel_power_cycle(intel_dp);
1342 pp = ironlake_get_pp_control(intel_dp);
1343 pp |= EDP_FORCE_VDD;
1345 pp_stat_reg = _pp_stat_reg(intel_dp);
1346 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1348 I915_WRITE(pp_ctrl_reg, pp);
1349 POSTING_READ(pp_ctrl_reg);
1350 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1351 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1353 * If the panel wasn't on, delay before accessing aux channel
1355 if (!edp_have_panel_power(intel_dp)) {
1356 DRM_DEBUG_KMS("eDP was not running\n");
1357 msleep(intel_dp->panel_power_up_delay);
1361 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1363 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1364 struct drm_i915_private *dev_priv = dev->dev_private;
1366 u32 pp_stat_reg, pp_ctrl_reg;
1368 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1370 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1371 struct intel_digital_port *intel_dig_port =
1372 dp_to_dig_port(intel_dp);
1373 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1374 enum intel_display_power_domain power_domain;
1376 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1378 pp = ironlake_get_pp_control(intel_dp);
1379 pp &= ~EDP_FORCE_VDD;
1381 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1382 pp_stat_reg = _pp_stat_reg(intel_dp);
1384 I915_WRITE(pp_ctrl_reg, pp);
1385 POSTING_READ(pp_ctrl_reg);
1387 /* Make sure sequencer is idle before allowing subsequent activity */
1388 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1389 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1391 if ((pp & POWER_TARGET_ON) == 0)
1392 intel_dp->last_power_cycle = jiffies;
1394 power_domain = intel_display_port_power_domain(intel_encoder);
1395 intel_display_power_put(dev_priv, power_domain);
1399 static void edp_panel_vdd_work(struct work_struct *__work)
1401 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1402 struct intel_dp, panel_vdd_work);
1403 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1405 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1406 edp_panel_vdd_off_sync(intel_dp);
1407 drm_modeset_unlock(&dev->mode_config.connection_mutex);
1410 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1412 unsigned long delay;
1415 * Queue the timer to fire a long time from now (relative to the power
1416 * down delay) to keep the panel power up across a sequence of
1419 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1420 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1423 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1425 if (!is_edp(intel_dp))
1428 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1430 intel_dp->want_panel_vdd = false;
1433 edp_panel_vdd_off_sync(intel_dp);
1435 edp_panel_vdd_schedule_off(intel_dp);
1438 void intel_edp_panel_on(struct intel_dp *intel_dp)
1440 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1441 struct drm_i915_private *dev_priv = dev->dev_private;
1445 if (!is_edp(intel_dp))
1448 DRM_DEBUG_KMS("Turn eDP power on\n");
1450 if (edp_have_panel_power(intel_dp)) {
1451 DRM_DEBUG_KMS("eDP power already on\n");
1455 wait_panel_power_cycle(intel_dp);
1457 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1458 pp = ironlake_get_pp_control(intel_dp);
1460 /* ILK workaround: disable reset around power sequence */
1461 pp &= ~PANEL_POWER_RESET;
1462 I915_WRITE(pp_ctrl_reg, pp);
1463 POSTING_READ(pp_ctrl_reg);
1466 pp |= POWER_TARGET_ON;
1468 pp |= PANEL_POWER_RESET;
1470 I915_WRITE(pp_ctrl_reg, pp);
1471 POSTING_READ(pp_ctrl_reg);
1473 wait_panel_on(intel_dp);
1474 intel_dp->last_power_on = jiffies;
1477 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1478 I915_WRITE(pp_ctrl_reg, pp);
1479 POSTING_READ(pp_ctrl_reg);
1483 void intel_edp_panel_off(struct intel_dp *intel_dp)
1485 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1486 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1487 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1488 struct drm_i915_private *dev_priv = dev->dev_private;
1489 enum intel_display_power_domain power_domain;
1493 if (!is_edp(intel_dp))
1496 DRM_DEBUG_KMS("Turn eDP power off\n");
1498 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1500 pp = ironlake_get_pp_control(intel_dp);
1501 /* We need to switch off panel power _and_ force vdd, for otherwise some
1502 * panels get very unhappy and cease to work. */
1503 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1506 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1508 intel_dp->want_panel_vdd = false;
1510 I915_WRITE(pp_ctrl_reg, pp);
1511 POSTING_READ(pp_ctrl_reg);
1513 intel_dp->last_power_cycle = jiffies;
1514 wait_panel_off(intel_dp);
1516 /* We got a reference when we enabled the VDD. */
1517 power_domain = intel_display_port_power_domain(intel_encoder);
1518 intel_display_power_put(dev_priv, power_domain);
1521 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1523 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1524 struct drm_device *dev = intel_dig_port->base.base.dev;
1525 struct drm_i915_private *dev_priv = dev->dev_private;
1529 if (!is_edp(intel_dp))
1532 DRM_DEBUG_KMS("\n");
1534 intel_panel_enable_backlight(intel_dp->attached_connector);
1537 * If we enable the backlight right away following a panel power
1538 * on, we may see slight flicker as the panel syncs with the eDP
1539 * link. So delay a bit to make sure the image is solid before
1540 * allowing it to appear.
1542 wait_backlight_on(intel_dp);
1543 pp = ironlake_get_pp_control(intel_dp);
1544 pp |= EDP_BLC_ENABLE;
1546 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1548 I915_WRITE(pp_ctrl_reg, pp);
1549 POSTING_READ(pp_ctrl_reg);
1552 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1554 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1555 struct drm_i915_private *dev_priv = dev->dev_private;
1559 if (!is_edp(intel_dp))
1562 DRM_DEBUG_KMS("\n");
1563 pp = ironlake_get_pp_control(intel_dp);
1564 pp &= ~EDP_BLC_ENABLE;
1566 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1568 I915_WRITE(pp_ctrl_reg, pp);
1569 POSTING_READ(pp_ctrl_reg);
1570 intel_dp->last_backlight_off = jiffies;
1572 edp_wait_backlight_off(intel_dp);
1574 intel_panel_disable_backlight(intel_dp->attached_connector);
1577 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1579 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1580 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1581 struct drm_device *dev = crtc->dev;
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1585 assert_pipe_disabled(dev_priv,
1586 to_intel_crtc(crtc)->pipe);
1588 DRM_DEBUG_KMS("\n");
1589 dpa_ctl = I915_READ(DP_A);
1590 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1591 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1593 /* We don't adjust intel_dp->DP while tearing down the link, to
1594 * facilitate link retraining (e.g. after hotplug). Hence clear all
1595 * enable bits here to ensure that we don't enable too much. */
1596 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1597 intel_dp->DP |= DP_PLL_ENABLE;
1598 I915_WRITE(DP_A, intel_dp->DP);
1603 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1605 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1606 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1607 struct drm_device *dev = crtc->dev;
1608 struct drm_i915_private *dev_priv = dev->dev_private;
1611 assert_pipe_disabled(dev_priv,
1612 to_intel_crtc(crtc)->pipe);
1614 dpa_ctl = I915_READ(DP_A);
1615 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1616 "dp pll off, should be on\n");
1617 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1619 /* We can't rely on the value tracked for the DP register in
1620 * intel_dp->DP because link_down must not change that (otherwise link
1621 * re-training will fail. */
1622 dpa_ctl &= ~DP_PLL_ENABLE;
1623 I915_WRITE(DP_A, dpa_ctl);
1628 /* If the sink supports it, try to set the power state appropriately */
1629 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1633 /* Should have a valid DPCD by this point */
1634 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1637 if (mode != DRM_MODE_DPMS_ON) {
1638 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1641 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1644 * When turning on, we need to retry for 1ms to give the sink
1647 for (i = 0; i < 3; i++) {
1648 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1657 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1658 enum i915_pipe *pipe)
1660 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1661 enum port port = dp_to_dig_port(intel_dp)->port;
1662 struct drm_device *dev = encoder->base.dev;
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664 enum intel_display_power_domain power_domain;
1667 power_domain = intel_display_port_power_domain(encoder);
1668 if (!intel_display_power_enabled(dev_priv, power_domain))
1671 tmp = I915_READ(intel_dp->output_reg);
1673 if (!(tmp & DP_PORT_EN))
1676 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1677 *pipe = PORT_TO_PIPE_CPT(tmp);
1678 } else if (IS_CHERRYVIEW(dev)) {
1679 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1680 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1681 *pipe = PORT_TO_PIPE(tmp);
1687 switch (intel_dp->output_reg) {
1689 trans_sel = TRANS_DP_PORT_SEL_B;
1692 trans_sel = TRANS_DP_PORT_SEL_C;
1695 trans_sel = TRANS_DP_PORT_SEL_D;
1702 trans_dp = I915_READ(TRANS_DP_CTL(i));
1703 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1709 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1710 intel_dp->output_reg);
1716 static void intel_dp_get_config(struct intel_encoder *encoder,
1717 struct intel_crtc_config *pipe_config)
1719 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1721 struct drm_device *dev = encoder->base.dev;
1722 struct drm_i915_private *dev_priv = dev->dev_private;
1723 enum port port = dp_to_dig_port(intel_dp)->port;
1724 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1727 tmp = I915_READ(intel_dp->output_reg);
1728 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1729 pipe_config->has_audio = true;
1731 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1732 if (tmp & DP_SYNC_HS_HIGH)
1733 flags |= DRM_MODE_FLAG_PHSYNC;
1735 flags |= DRM_MODE_FLAG_NHSYNC;
1737 if (tmp & DP_SYNC_VS_HIGH)
1738 flags |= DRM_MODE_FLAG_PVSYNC;
1740 flags |= DRM_MODE_FLAG_NVSYNC;
1742 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1743 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1744 flags |= DRM_MODE_FLAG_PHSYNC;
1746 flags |= DRM_MODE_FLAG_NHSYNC;
1748 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1749 flags |= DRM_MODE_FLAG_PVSYNC;
1751 flags |= DRM_MODE_FLAG_NVSYNC;
1754 pipe_config->adjusted_mode.flags |= flags;
1756 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1757 tmp & DP_COLOR_RANGE_16_235)
1758 pipe_config->limited_color_range = true;
1760 pipe_config->has_dp_encoder = true;
1762 intel_dp_get_m_n(crtc, pipe_config);
1764 if (port == PORT_A) {
1765 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1766 pipe_config->port_clock = 162000;
1768 pipe_config->port_clock = 270000;
1771 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1772 &pipe_config->dp_m_n);
1774 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1775 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1777 pipe_config->adjusted_mode.crtc_clock = dotclock;
1779 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1780 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1782 * This is a big fat ugly hack.
1784 * Some machines in UEFI boot mode provide us a VBT that has 18
1785 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1786 * unknown we fail to light up. Yet the same BIOS boots up with
1787 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1788 * max, not what it tells us to use.
1790 * Note: This will still be broken if the eDP panel is not lit
1791 * up by the BIOS, and thus we can't get the mode at module
1794 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1795 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1796 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1800 static bool is_edp_psr(struct intel_dp *intel_dp)
1802 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1805 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1807 struct drm_i915_private *dev_priv = dev->dev_private;
1812 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1815 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1816 struct edp_vsc_psr *vsc_psr)
1818 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1819 struct drm_device *dev = dig_port->base.base.dev;
1820 struct drm_i915_private *dev_priv = dev->dev_private;
1821 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1822 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1823 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1824 uint32_t *data = (uint32_t *) vsc_psr;
1827 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1828 the video DIP being updated before program video DIP data buffer
1829 registers for DIP being updated. */
1830 I915_WRITE(ctl_reg, 0);
1831 POSTING_READ(ctl_reg);
1833 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1834 if (i < sizeof(struct edp_vsc_psr))
1835 I915_WRITE(data_reg + i, *data++);
1837 I915_WRITE(data_reg + i, 0);
1840 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1841 POSTING_READ(ctl_reg);
1844 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1846 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1847 struct drm_i915_private *dev_priv = dev->dev_private;
1848 struct edp_vsc_psr psr_vsc;
1850 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1851 memset(&psr_vsc, 0, sizeof(psr_vsc));
1852 psr_vsc.sdp_header.HB0 = 0;
1853 psr_vsc.sdp_header.HB1 = 0x7;
1854 psr_vsc.sdp_header.HB2 = 0x2;
1855 psr_vsc.sdp_header.HB3 = 0x8;
1856 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1858 /* Avoid continuous PSR exit by masking memup and hpd */
1859 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1860 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1863 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1865 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1866 struct drm_device *dev = dig_port->base.base.dev;
1867 struct drm_i915_private *dev_priv = dev->dev_private;
1868 uint32_t aux_clock_divider;
1869 int precharge = 0x3;
1870 int msg_size = 5; /* Header(4) + Message(1) */
1871 bool only_standby = false;
1873 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1875 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1876 only_standby = true;
1878 /* Enable PSR in sink */
1879 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
1880 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1881 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1883 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1884 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1886 /* Setup AUX registers */
1887 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1888 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1889 I915_WRITE(EDP_PSR_AUX_CTL(dev),
1890 DP_AUX_CH_CTL_TIME_OUT_400us |
1891 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1892 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1893 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1896 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1898 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1899 struct drm_device *dev = dig_port->base.base.dev;
1900 struct drm_i915_private *dev_priv = dev->dev_private;
1901 uint32_t max_sleep_time = 0x1f;
1902 uint32_t idle_frames = 1;
1904 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1905 bool only_standby = false;
1907 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1908 only_standby = true;
1910 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
1911 val |= EDP_PSR_LINK_STANDBY;
1912 val |= EDP_PSR_TP2_TP3_TIME_0us;
1913 val |= EDP_PSR_TP1_TIME_0us;
1914 val |= EDP_PSR_SKIP_AUX_EXIT;
1915 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
1917 val |= EDP_PSR_LINK_DISABLE;
1919 I915_WRITE(EDP_PSR_CTL(dev), val |
1920 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1921 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1922 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1926 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1928 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1929 struct drm_device *dev = dig_port->base.base.dev;
1930 struct drm_i915_private *dev_priv = dev->dev_private;
1931 struct drm_crtc *crtc = dig_port->base.base.crtc;
1932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1935 lockdep_assert_held(&dev_priv->psr.lock);
1937 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1938 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1940 dev_priv->psr.source_ok = false;
1942 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
1943 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1947 if (!i915.enable_psr) {
1948 DRM_DEBUG_KMS("PSR disable by flag\n");
1952 /* Below limitations aren't valid for Broadwell */
1953 if (IS_BROADWELL(dev))
1956 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1958 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1962 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1963 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1968 dev_priv->psr.source_ok = true;
1972 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1974 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1975 struct drm_device *dev = intel_dig_port->base.base.dev;
1976 struct drm_i915_private *dev_priv = dev->dev_private;
1978 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1979 WARN_ON(dev_priv->psr.active);
1981 lockdep_assert_held(&dev_priv->psr.lock);
1984 /* Enable PSR on the panel */
1985 intel_edp_psr_enable_sink(intel_dp);
1987 /* Enable PSR on the host */
1988 intel_edp_psr_enable_source(intel_dp);
1990 dev_priv->psr.active = true;
1993 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1995 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1996 struct drm_i915_private *dev_priv = dev->dev_private;
1998 if (!HAS_PSR(dev)) {
1999 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2003 if (!is_edp_psr(intel_dp)) {
2004 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2008 mutex_lock(&dev_priv->psr.lock);
2009 if (dev_priv->psr.enabled) {
2010 DRM_DEBUG_KMS("PSR already in use\n");
2011 mutex_unlock(&dev_priv->psr.lock);
2015 dev_priv->psr.busy_frontbuffer_bits = 0;
2017 /* Setup PSR once */
2018 intel_edp_psr_setup(intel_dp);
2020 if (intel_edp_psr_match_conditions(intel_dp))
2021 dev_priv->psr.enabled = intel_dp;
2022 mutex_unlock(&dev_priv->psr.lock);
2025 void intel_edp_psr_disable(struct intel_dp *intel_dp)
2027 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2028 struct drm_i915_private *dev_priv = dev->dev_private;
2030 mutex_lock(&dev_priv->psr.lock);
2031 if (!dev_priv->psr.enabled) {
2032 mutex_unlock(&dev_priv->psr.lock);
2036 if (dev_priv->psr.active) {
2037 I915_WRITE(EDP_PSR_CTL(dev),
2038 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2040 /* Wait till PSR is idle */
2041 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2042 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2043 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2045 dev_priv->psr.active = false;
2047 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2050 dev_priv->psr.enabled = NULL;
2051 mutex_unlock(&dev_priv->psr.lock);
2053 cancel_delayed_work_sync(&dev_priv->psr.work);
2056 static void intel_edp_psr_work(struct work_struct *work)
2058 struct drm_i915_private *dev_priv =
2059 container_of(work, typeof(*dev_priv), psr.work.work);
2060 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2062 mutex_lock(&dev_priv->psr.lock);
2063 intel_dp = dev_priv->psr.enabled;
2069 * The delayed work can race with an invalidate hence we need to
2070 * recheck. Since psr_flush first clears this and then reschedules we
2071 * won't ever miss a flush when bailing out here.
2073 if (dev_priv->psr.busy_frontbuffer_bits)
2076 intel_edp_psr_do_enable(intel_dp);
2078 mutex_unlock(&dev_priv->psr.lock);
2081 static void intel_edp_psr_do_exit(struct drm_device *dev)
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2085 if (dev_priv->psr.active) {
2086 u32 val = I915_READ(EDP_PSR_CTL(dev));
2088 WARN_ON(!(val & EDP_PSR_ENABLE));
2090 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2092 dev_priv->psr.active = false;
2097 void intel_edp_psr_invalidate(struct drm_device *dev,
2098 unsigned frontbuffer_bits)
2100 struct drm_i915_private *dev_priv = dev->dev_private;
2101 struct drm_crtc *crtc;
2102 enum i915_pipe pipe;
2104 mutex_lock(&dev_priv->psr.lock);
2105 if (!dev_priv->psr.enabled) {
2106 mutex_unlock(&dev_priv->psr.lock);
2110 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2111 pipe = to_intel_crtc(crtc)->pipe;
2113 intel_edp_psr_do_exit(dev);
2115 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2117 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2118 mutex_unlock(&dev_priv->psr.lock);
2121 void intel_edp_psr_flush(struct drm_device *dev,
2122 unsigned frontbuffer_bits)
2124 struct drm_i915_private *dev_priv = dev->dev_private;
2125 struct drm_crtc *crtc;
2126 enum i915_pipe pipe;
2128 mutex_lock(&dev_priv->psr.lock);
2129 if (!dev_priv->psr.enabled) {
2130 mutex_unlock(&dev_priv->psr.lock);
2134 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2135 pipe = to_intel_crtc(crtc)->pipe;
2136 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2139 * On Haswell sprite plane updates don't result in a psr invalidating
2140 * signal in the hardware. Which means we need to manually fake this in
2141 * software for all flushes, not just when we've seen a preceding
2142 * invalidation through frontbuffer rendering.
2144 if (IS_HASWELL(dev) &&
2145 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2146 intel_edp_psr_do_exit(dev);
2148 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2149 schedule_delayed_work(&dev_priv->psr.work,
2150 msecs_to_jiffies(100));
2151 mutex_unlock(&dev_priv->psr.lock);
2154 void intel_edp_psr_init(struct drm_device *dev)
2156 struct drm_i915_private *dev_priv = dev->dev_private;
2158 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
2159 lockinit(&dev_priv->psr.lock, "i915dpl", 0, LK_CANRECURSE);
2162 static void intel_disable_dp(struct intel_encoder *encoder)
2164 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2165 enum port port = dp_to_dig_port(intel_dp)->port;
2166 struct drm_device *dev = encoder->base.dev;
2168 /* Make sure the panel is off before trying to change the mode. But also
2169 * ensure that we have vdd while we switch off the panel. */
2170 intel_edp_panel_vdd_on(intel_dp);
2171 intel_edp_backlight_off(intel_dp);
2172 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2173 intel_edp_panel_off(intel_dp);
2175 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
2176 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
2177 intel_dp_link_down(intel_dp);
2180 static void g4x_post_disable_dp(struct intel_encoder *encoder)
2182 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2183 enum port port = dp_to_dig_port(intel_dp)->port;
2188 intel_dp_link_down(intel_dp);
2189 ironlake_edp_pll_off(intel_dp);
2192 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2194 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2196 intel_dp_link_down(intel_dp);
2199 static void chv_post_disable_dp(struct intel_encoder *encoder)
2201 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2202 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2203 struct drm_device *dev = encoder->base.dev;
2204 struct drm_i915_private *dev_priv = dev->dev_private;
2205 struct intel_crtc *intel_crtc =
2206 to_intel_crtc(encoder->base.crtc);
2207 enum dpio_channel ch = vlv_dport_to_channel(dport);
2208 enum i915_pipe pipe = intel_crtc->pipe;
2211 intel_dp_link_down(intel_dp);
2213 mutex_lock(&dev_priv->dpio_lock);
2215 /* Propagate soft reset to data lane reset */
2216 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2217 val |= CHV_PCS_REQ_SOFTRESET_EN;
2218 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2220 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2221 val |= CHV_PCS_REQ_SOFTRESET_EN;
2222 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2224 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2225 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2226 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2228 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2229 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2230 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2232 mutex_unlock(&dev_priv->dpio_lock);
2235 static void intel_enable_dp(struct intel_encoder *encoder)
2237 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2238 struct drm_device *dev = encoder->base.dev;
2239 struct drm_i915_private *dev_priv = dev->dev_private;
2240 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2242 if (WARN_ON(dp_reg & DP_PORT_EN))
2245 intel_edp_panel_vdd_on(intel_dp);
2246 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2247 intel_dp_start_link_train(intel_dp);
2248 intel_edp_panel_on(intel_dp);
2249 edp_panel_vdd_off(intel_dp, true);
2250 intel_dp_complete_link_train(intel_dp);
2251 intel_dp_stop_link_train(intel_dp);
2254 static void g4x_enable_dp(struct intel_encoder *encoder)
2256 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2258 intel_enable_dp(encoder);
2259 intel_edp_backlight_on(intel_dp);
2262 static void vlv_enable_dp(struct intel_encoder *encoder)
2264 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2266 intel_edp_backlight_on(intel_dp);
2269 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2271 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2272 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2274 intel_dp_prepare(encoder);
2276 /* Only ilk+ has port A */
2277 if (dport->port == PORT_A) {
2278 ironlake_set_pll_cpu_edp(intel_dp);
2279 ironlake_edp_pll_on(intel_dp);
2283 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2285 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2286 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2287 struct drm_device *dev = encoder->base.dev;
2288 struct drm_i915_private *dev_priv = dev->dev_private;
2289 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2290 enum dpio_channel port = vlv_dport_to_channel(dport);
2291 int pipe = intel_crtc->pipe;
2292 struct edp_power_seq power_seq;
2295 mutex_lock(&dev_priv->dpio_lock);
2297 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2304 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2305 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2306 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2308 mutex_unlock(&dev_priv->dpio_lock);
2310 if (is_edp(intel_dp)) {
2311 /* init power sequencer on this pipe and port */
2312 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2313 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2317 intel_enable_dp(encoder);
2319 vlv_wait_port_ready(dev_priv, dport);
2322 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2324 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2325 struct drm_device *dev = encoder->base.dev;
2326 struct drm_i915_private *dev_priv = dev->dev_private;
2327 struct intel_crtc *intel_crtc =
2328 to_intel_crtc(encoder->base.crtc);
2329 enum dpio_channel port = vlv_dport_to_channel(dport);
2330 int pipe = intel_crtc->pipe;
2332 intel_dp_prepare(encoder);
2334 /* Program Tx lane resets to default */
2335 mutex_lock(&dev_priv->dpio_lock);
2336 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2337 DPIO_PCS_TX_LANE2_RESET |
2338 DPIO_PCS_TX_LANE1_RESET);
2339 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2340 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2341 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2342 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2343 DPIO_PCS_CLK_SOFT_RESET);
2345 /* Fix up inter-pair skew failure */
2346 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2347 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2348 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2349 mutex_unlock(&dev_priv->dpio_lock);
2352 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2354 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2355 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2356 struct drm_device *dev = encoder->base.dev;
2357 struct drm_i915_private *dev_priv = dev->dev_private;
2358 struct edp_power_seq power_seq;
2359 struct intel_crtc *intel_crtc =
2360 to_intel_crtc(encoder->base.crtc);
2361 enum dpio_channel ch = vlv_dport_to_channel(dport);
2362 int pipe = intel_crtc->pipe;
2366 mutex_lock(&dev_priv->dpio_lock);
2368 /* Deassert soft data lane reset*/
2369 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2370 val |= CHV_PCS_REQ_SOFTRESET_EN;
2371 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2373 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2374 val |= CHV_PCS_REQ_SOFTRESET_EN;
2375 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2377 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2378 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2379 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2381 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2382 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2383 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2385 /* Program Tx lane latency optimal setting*/
2386 for (i = 0; i < 4; i++) {
2387 /* Set the latency optimal bit */
2388 data = (i == 1) ? 0x0 : 0x6;
2389 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2390 data << DPIO_FRC_LATENCY_SHFIT);
2392 /* Set the upar bit */
2393 data = (i == 1) ? 0x0 : 0x1;
2394 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2395 data << DPIO_UPAR_SHIFT);
2398 /* Data lane stagger programming */
2399 /* FIXME: Fix up value only after power analysis */
2401 mutex_unlock(&dev_priv->dpio_lock);
2403 if (is_edp(intel_dp)) {
2404 /* init power sequencer on this pipe and port */
2405 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2406 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2410 intel_enable_dp(encoder);
2412 vlv_wait_port_ready(dev_priv, dport);
2415 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2417 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2418 struct drm_device *dev = encoder->base.dev;
2419 struct drm_i915_private *dev_priv = dev->dev_private;
2420 struct intel_crtc *intel_crtc =
2421 to_intel_crtc(encoder->base.crtc);
2422 enum dpio_channel ch = vlv_dport_to_channel(dport);
2423 enum i915_pipe pipe = intel_crtc->pipe;
2426 mutex_lock(&dev_priv->dpio_lock);
2428 /* program left/right clock distribution */
2429 if (pipe != PIPE_B) {
2430 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2431 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2433 val |= CHV_BUFLEFTENA1_FORCE;
2435 val |= CHV_BUFRIGHTENA1_FORCE;
2436 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2438 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2439 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2441 val |= CHV_BUFLEFTENA2_FORCE;
2443 val |= CHV_BUFRIGHTENA2_FORCE;
2444 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2447 /* program clock channel usage */
2448 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2449 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2451 val &= ~CHV_PCS_USEDCLKCHANNEL;
2453 val |= CHV_PCS_USEDCLKCHANNEL;
2454 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2456 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2457 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2459 val &= ~CHV_PCS_USEDCLKCHANNEL;
2461 val |= CHV_PCS_USEDCLKCHANNEL;
2462 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2465 * This a a bit weird since generally CL
2466 * matches the pipe, but here we need to
2467 * pick the CL based on the port.
2469 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2471 val &= ~CHV_CMN_USEDCLKCHANNEL;
2473 val |= CHV_CMN_USEDCLKCHANNEL;
2474 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2476 mutex_unlock(&dev_priv->dpio_lock);
2480 * Native read with retry for link status and receiver capability reads for
2481 * cases where the sink may still be asleep.
2483 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2484 * supposed to retry 3 times per the spec.
2487 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2488 void *buffer, size_t size)
2493 for (i = 0; i < 3; i++) {
2494 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2504 * Fetch AUX CH registers 0x202 - 0x207 which contain
2505 * link status information
2508 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2510 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2513 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2516 /* These are source-specific values. */
2518 intel_dp_voltage_max(struct intel_dp *intel_dp)
2520 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2521 enum port port = dp_to_dig_port(intel_dp)->port;
2523 if (IS_VALLEYVIEW(dev))
2524 return DP_TRAIN_VOLTAGE_SWING_1200;
2525 else if (IS_GEN7(dev) && port == PORT_A)
2526 return DP_TRAIN_VOLTAGE_SWING_800;
2527 else if (HAS_PCH_CPT(dev) && port != PORT_A)
2528 return DP_TRAIN_VOLTAGE_SWING_1200;
2530 return DP_TRAIN_VOLTAGE_SWING_800;
2534 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2536 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2537 enum port port = dp_to_dig_port(intel_dp)->port;
2539 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2540 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2541 case DP_TRAIN_VOLTAGE_SWING_400:
2542 return DP_TRAIN_PRE_EMPHASIS_9_5;
2543 case DP_TRAIN_VOLTAGE_SWING_600:
2544 return DP_TRAIN_PRE_EMPHASIS_6;
2545 case DP_TRAIN_VOLTAGE_SWING_800:
2546 return DP_TRAIN_PRE_EMPHASIS_3_5;
2547 case DP_TRAIN_VOLTAGE_SWING_1200:
2549 return DP_TRAIN_PRE_EMPHASIS_0;
2551 } else if (IS_VALLEYVIEW(dev)) {
2552 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2553 case DP_TRAIN_VOLTAGE_SWING_400:
2554 return DP_TRAIN_PRE_EMPHASIS_9_5;
2555 case DP_TRAIN_VOLTAGE_SWING_600:
2556 return DP_TRAIN_PRE_EMPHASIS_6;
2557 case DP_TRAIN_VOLTAGE_SWING_800:
2558 return DP_TRAIN_PRE_EMPHASIS_3_5;
2559 case DP_TRAIN_VOLTAGE_SWING_1200:
2561 return DP_TRAIN_PRE_EMPHASIS_0;
2563 } else if (IS_GEN7(dev) && port == PORT_A) {
2564 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2565 case DP_TRAIN_VOLTAGE_SWING_400:
2566 return DP_TRAIN_PRE_EMPHASIS_6;
2567 case DP_TRAIN_VOLTAGE_SWING_600:
2568 case DP_TRAIN_VOLTAGE_SWING_800:
2569 return DP_TRAIN_PRE_EMPHASIS_3_5;
2571 return DP_TRAIN_PRE_EMPHASIS_0;
2574 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2575 case DP_TRAIN_VOLTAGE_SWING_400:
2576 return DP_TRAIN_PRE_EMPHASIS_6;
2577 case DP_TRAIN_VOLTAGE_SWING_600:
2578 return DP_TRAIN_PRE_EMPHASIS_6;
2579 case DP_TRAIN_VOLTAGE_SWING_800:
2580 return DP_TRAIN_PRE_EMPHASIS_3_5;
2581 case DP_TRAIN_VOLTAGE_SWING_1200:
2583 return DP_TRAIN_PRE_EMPHASIS_0;
2588 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2590 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2591 struct drm_i915_private *dev_priv = dev->dev_private;
2592 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2593 struct intel_crtc *intel_crtc =
2594 to_intel_crtc(dport->base.base.crtc);
2595 unsigned long demph_reg_value, preemph_reg_value,
2596 uniqtranscale_reg_value;
2597 uint8_t train_set = intel_dp->train_set[0];
2598 enum dpio_channel port = vlv_dport_to_channel(dport);
2599 int pipe = intel_crtc->pipe;
2601 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2602 case DP_TRAIN_PRE_EMPHASIS_0:
2603 preemph_reg_value = 0x0004000;
2604 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2605 case DP_TRAIN_VOLTAGE_SWING_400:
2606 demph_reg_value = 0x2B405555;
2607 uniqtranscale_reg_value = 0x552AB83A;
2609 case DP_TRAIN_VOLTAGE_SWING_600:
2610 demph_reg_value = 0x2B404040;
2611 uniqtranscale_reg_value = 0x5548B83A;
2613 case DP_TRAIN_VOLTAGE_SWING_800:
2614 demph_reg_value = 0x2B245555;
2615 uniqtranscale_reg_value = 0x5560B83A;
2617 case DP_TRAIN_VOLTAGE_SWING_1200:
2618 demph_reg_value = 0x2B405555;
2619 uniqtranscale_reg_value = 0x5598DA3A;
2625 case DP_TRAIN_PRE_EMPHASIS_3_5:
2626 preemph_reg_value = 0x0002000;
2627 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2628 case DP_TRAIN_VOLTAGE_SWING_400:
2629 demph_reg_value = 0x2B404040;
2630 uniqtranscale_reg_value = 0x5552B83A;
2632 case DP_TRAIN_VOLTAGE_SWING_600:
2633 demph_reg_value = 0x2B404848;
2634 uniqtranscale_reg_value = 0x5580B83A;
2636 case DP_TRAIN_VOLTAGE_SWING_800:
2637 demph_reg_value = 0x2B404040;
2638 uniqtranscale_reg_value = 0x55ADDA3A;
2644 case DP_TRAIN_PRE_EMPHASIS_6:
2645 preemph_reg_value = 0x0000000;
2646 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2647 case DP_TRAIN_VOLTAGE_SWING_400:
2648 demph_reg_value = 0x2B305555;
2649 uniqtranscale_reg_value = 0x5570B83A;
2651 case DP_TRAIN_VOLTAGE_SWING_600:
2652 demph_reg_value = 0x2B2B4040;
2653 uniqtranscale_reg_value = 0x55ADDA3A;
2659 case DP_TRAIN_PRE_EMPHASIS_9_5:
2660 preemph_reg_value = 0x0006000;
2661 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2662 case DP_TRAIN_VOLTAGE_SWING_400:
2663 demph_reg_value = 0x1B405555;
2664 uniqtranscale_reg_value = 0x55ADDA3A;
2674 mutex_lock(&dev_priv->dpio_lock);
2675 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2676 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2677 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2678 uniqtranscale_reg_value);
2679 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2680 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2681 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2682 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2683 mutex_unlock(&dev_priv->dpio_lock);
2688 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2690 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2691 struct drm_i915_private *dev_priv = dev->dev_private;
2692 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2693 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2694 u32 deemph_reg_value, margin_reg_value, val;
2695 uint8_t train_set = intel_dp->train_set[0];
2696 enum dpio_channel ch = vlv_dport_to_channel(dport);
2697 enum i915_pipe pipe = intel_crtc->pipe;
2700 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2701 case DP_TRAIN_PRE_EMPHASIS_0:
2702 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2703 case DP_TRAIN_VOLTAGE_SWING_400:
2704 deemph_reg_value = 128;
2705 margin_reg_value = 52;
2707 case DP_TRAIN_VOLTAGE_SWING_600:
2708 deemph_reg_value = 128;
2709 margin_reg_value = 77;
2711 case DP_TRAIN_VOLTAGE_SWING_800:
2712 deemph_reg_value = 128;
2713 margin_reg_value = 102;
2715 case DP_TRAIN_VOLTAGE_SWING_1200:
2716 deemph_reg_value = 128;
2717 margin_reg_value = 154;
2718 /* FIXME extra to set for 1200 */
2724 case DP_TRAIN_PRE_EMPHASIS_3_5:
2725 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2726 case DP_TRAIN_VOLTAGE_SWING_400:
2727 deemph_reg_value = 85;
2728 margin_reg_value = 78;
2730 case DP_TRAIN_VOLTAGE_SWING_600:
2731 deemph_reg_value = 85;
2732 margin_reg_value = 116;
2734 case DP_TRAIN_VOLTAGE_SWING_800:
2735 deemph_reg_value = 85;
2736 margin_reg_value = 154;
2742 case DP_TRAIN_PRE_EMPHASIS_6:
2743 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2744 case DP_TRAIN_VOLTAGE_SWING_400:
2745 deemph_reg_value = 64;
2746 margin_reg_value = 104;
2748 case DP_TRAIN_VOLTAGE_SWING_600:
2749 deemph_reg_value = 64;
2750 margin_reg_value = 154;
2756 case DP_TRAIN_PRE_EMPHASIS_9_5:
2757 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2758 case DP_TRAIN_VOLTAGE_SWING_400:
2759 deemph_reg_value = 43;
2760 margin_reg_value = 154;
2770 mutex_lock(&dev_priv->dpio_lock);
2772 /* Clear calc init */
2773 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2774 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2775 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2777 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2778 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2779 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2781 /* Program swing deemph */
2782 for (i = 0; i < 4; i++) {
2783 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2784 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2785 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2786 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2789 /* Program swing margin */
2790 for (i = 0; i < 4; i++) {
2791 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2792 val &= ~DPIO_SWING_MARGIN_MASK;
2793 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2794 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2797 /* Disable unique transition scale */
2798 for (i = 0; i < 4; i++) {
2799 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2800 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2801 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2804 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2805 == DP_TRAIN_PRE_EMPHASIS_0) &&
2806 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2807 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2810 * The document said it needs to set bit 27 for ch0 and bit 26
2811 * for ch1. Might be a typo in the doc.
2812 * For now, for this unique transition scale selection, set bit
2813 * 27 for ch0 and ch1.
2815 for (i = 0; i < 4; i++) {
2816 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2817 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2818 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2821 for (i = 0; i < 4; i++) {
2822 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2823 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2824 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2825 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2829 /* Start swing calculation */
2830 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2831 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2832 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2834 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2835 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2836 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2839 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2840 val |= DPIO_LRC_BYPASS;
2841 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2843 mutex_unlock(&dev_priv->dpio_lock);
2849 intel_get_adjust_train(struct intel_dp *intel_dp,
2850 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2855 uint8_t voltage_max;
2856 uint8_t preemph_max;
2858 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2859 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2860 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2868 voltage_max = intel_dp_voltage_max(intel_dp);
2869 if (v >= voltage_max)
2870 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2872 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2873 if (p >= preemph_max)
2874 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2876 for (lane = 0; lane < 4; lane++)
2877 intel_dp->train_set[lane] = v | p;
2881 intel_gen4_signal_levels(uint8_t train_set)
2883 uint32_t signal_levels = 0;
2885 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2886 case DP_TRAIN_VOLTAGE_SWING_400:
2888 signal_levels |= DP_VOLTAGE_0_4;
2890 case DP_TRAIN_VOLTAGE_SWING_600:
2891 signal_levels |= DP_VOLTAGE_0_6;
2893 case DP_TRAIN_VOLTAGE_SWING_800:
2894 signal_levels |= DP_VOLTAGE_0_8;
2896 case DP_TRAIN_VOLTAGE_SWING_1200:
2897 signal_levels |= DP_VOLTAGE_1_2;
2900 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2901 case DP_TRAIN_PRE_EMPHASIS_0:
2903 signal_levels |= DP_PRE_EMPHASIS_0;
2905 case DP_TRAIN_PRE_EMPHASIS_3_5:
2906 signal_levels |= DP_PRE_EMPHASIS_3_5;
2908 case DP_TRAIN_PRE_EMPHASIS_6:
2909 signal_levels |= DP_PRE_EMPHASIS_6;
2911 case DP_TRAIN_PRE_EMPHASIS_9_5:
2912 signal_levels |= DP_PRE_EMPHASIS_9_5;
2915 return signal_levels;
2918 /* Gen6's DP voltage swing and pre-emphasis control */
2920 intel_gen6_edp_signal_levels(uint8_t train_set)
2922 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2923 DP_TRAIN_PRE_EMPHASIS_MASK);
2924 switch (signal_levels) {
2925 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2926 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2927 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2928 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2929 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2930 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2931 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2932 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2933 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2934 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2935 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2936 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2937 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2938 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2940 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2941 "0x%x\n", signal_levels);
2942 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2946 /* Gen7's DP voltage swing and pre-emphasis control */
2948 intel_gen7_edp_signal_levels(uint8_t train_set)
2950 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2951 DP_TRAIN_PRE_EMPHASIS_MASK);
2952 switch (signal_levels) {
2953 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2954 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2955 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2956 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2957 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2958 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2960 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2961 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2962 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2963 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2965 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2966 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2967 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2968 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2971 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2972 "0x%x\n", signal_levels);
2973 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2977 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2979 intel_hsw_signal_levels(uint8_t train_set)
2981 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2982 DP_TRAIN_PRE_EMPHASIS_MASK);
2983 switch (signal_levels) {
2984 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2985 return DDI_BUF_EMP_400MV_0DB_HSW;
2986 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2987 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2988 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2989 return DDI_BUF_EMP_400MV_6DB_HSW;
2990 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2991 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2993 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2994 return DDI_BUF_EMP_600MV_0DB_HSW;
2995 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2996 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2997 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2998 return DDI_BUF_EMP_600MV_6DB_HSW;
3000 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3001 return DDI_BUF_EMP_800MV_0DB_HSW;
3002 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
3003 return DDI_BUF_EMP_800MV_3_5DB_HSW;
3005 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3006 "0x%x\n", signal_levels);
3007 return DDI_BUF_EMP_400MV_0DB_HSW;
3011 /* Properly updates "DP" with the correct signal levels. */
3013 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3015 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3016 enum port port = intel_dig_port->port;
3017 struct drm_device *dev = intel_dig_port->base.base.dev;
3018 uint32_t signal_levels, mask;
3019 uint8_t train_set = intel_dp->train_set[0];
3021 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3022 signal_levels = intel_hsw_signal_levels(train_set);
3023 mask = DDI_BUF_EMP_MASK;
3024 } else if (IS_CHERRYVIEW(dev)) {
3025 signal_levels = intel_chv_signal_levels(intel_dp);
3027 } else if (IS_VALLEYVIEW(dev)) {
3028 signal_levels = intel_vlv_signal_levels(intel_dp);
3030 } else if (IS_GEN7(dev) && port == PORT_A) {
3031 signal_levels = intel_gen7_edp_signal_levels(train_set);
3032 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3033 } else if (IS_GEN6(dev) && port == PORT_A) {
3034 signal_levels = intel_gen6_edp_signal_levels(train_set);
3035 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3037 signal_levels = intel_gen4_signal_levels(train_set);
3038 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3041 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3043 *DP = (*DP & ~mask) | signal_levels;
3047 intel_dp_set_link_train(struct intel_dp *intel_dp,
3049 uint8_t dp_train_pat)
3051 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3052 struct drm_device *dev = intel_dig_port->base.base.dev;
3053 struct drm_i915_private *dev_priv = dev->dev_private;
3054 enum port port = intel_dig_port->port;
3055 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3059 uint32_t temp = I915_READ(DP_TP_CTL(port));
3061 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3062 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3064 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3066 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3067 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3068 case DP_TRAINING_PATTERN_DISABLE:
3069 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3072 case DP_TRAINING_PATTERN_1:
3073 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3075 case DP_TRAINING_PATTERN_2:
3076 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3078 case DP_TRAINING_PATTERN_3:
3079 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3082 I915_WRITE(DP_TP_CTL(port), temp);
3084 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3085 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3087 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3088 case DP_TRAINING_PATTERN_DISABLE:
3089 *DP |= DP_LINK_TRAIN_OFF_CPT;
3091 case DP_TRAINING_PATTERN_1:
3092 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3094 case DP_TRAINING_PATTERN_2:
3095 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3097 case DP_TRAINING_PATTERN_3:
3098 DRM_ERROR("DP training pattern 3 not supported\n");
3099 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3104 *DP &= ~DP_LINK_TRAIN_MASK;
3106 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3107 case DP_TRAINING_PATTERN_DISABLE:
3108 *DP |= DP_LINK_TRAIN_OFF;
3110 case DP_TRAINING_PATTERN_1:
3111 *DP |= DP_LINK_TRAIN_PAT_1;
3113 case DP_TRAINING_PATTERN_2:
3114 *DP |= DP_LINK_TRAIN_PAT_2;
3116 case DP_TRAINING_PATTERN_3:
3117 DRM_ERROR("DP training pattern 3 not supported\n");
3118 *DP |= DP_LINK_TRAIN_PAT_2;
3123 I915_WRITE(intel_dp->output_reg, *DP);
3124 POSTING_READ(intel_dp->output_reg);
3126 buf[0] = dp_train_pat;
3127 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3128 DP_TRAINING_PATTERN_DISABLE) {
3129 /* don't write DP_TRAINING_LANEx_SET on disable */
3132 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3133 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3134 len = intel_dp->lane_count + 1;
3137 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3144 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3145 uint8_t dp_train_pat)
3147 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3148 intel_dp_set_signal_levels(intel_dp, DP);
3149 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3153 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3154 const uint8_t link_status[DP_LINK_STATUS_SIZE])
3156 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3157 struct drm_device *dev = intel_dig_port->base.base.dev;
3158 struct drm_i915_private *dev_priv = dev->dev_private;
3161 intel_get_adjust_train(intel_dp, link_status);
3162 intel_dp_set_signal_levels(intel_dp, DP);
3164 I915_WRITE(intel_dp->output_reg, *DP);
3165 POSTING_READ(intel_dp->output_reg);
3167 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3168 intel_dp->train_set, intel_dp->lane_count);
3170 return ret == intel_dp->lane_count;
3173 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3175 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3176 struct drm_device *dev = intel_dig_port->base.base.dev;
3177 struct drm_i915_private *dev_priv = dev->dev_private;
3178 enum port port = intel_dig_port->port;
3184 val = I915_READ(DP_TP_CTL(port));
3185 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3186 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3187 I915_WRITE(DP_TP_CTL(port), val);
3190 * On PORT_A we can have only eDP in SST mode. There the only reason
3191 * we need to set idle transmission mode is to work around a HW issue
3192 * where we enable the pipe while not in idle link-training mode.
3193 * In this case there is requirement to wait for a minimum number of
3194 * idle patterns to be sent.
3199 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3201 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3204 /* Enable corresponding port and start training pattern 1 */
3206 intel_dp_start_link_train(struct intel_dp *intel_dp)
3208 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3209 struct drm_device *dev = encoder->dev;
3212 int voltage_tries, loop_tries;
3213 uint32_t DP = intel_dp->DP;
3214 uint8_t link_config[2];
3217 intel_ddi_prepare_link_retrain(encoder);
3219 /* Write the link configuration data */
3220 link_config[0] = intel_dp->link_bw;
3221 link_config[1] = intel_dp->lane_count;
3222 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3223 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3224 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3227 link_config[1] = DP_SET_ANSI_8B10B;
3228 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3232 /* clock recovery */
3233 if (!intel_dp_reset_link_train(intel_dp, &DP,
3234 DP_TRAINING_PATTERN_1 |
3235 DP_LINK_SCRAMBLING_DISABLE)) {
3236 DRM_ERROR("failed to enable link training\n");
3244 uint8_t link_status[DP_LINK_STATUS_SIZE];
3246 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3247 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3248 DRM_ERROR("failed to get link status\n");
3252 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3253 DRM_DEBUG_KMS("clock recovery OK\n");
3257 /* Check to see if we've tried the max voltage */
3258 for (i = 0; i < intel_dp->lane_count; i++)
3259 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3261 if (i == intel_dp->lane_count) {
3263 if (loop_tries == 5) {
3264 DRM_ERROR("too many full retries, give up\n");
3267 intel_dp_reset_link_train(intel_dp, &DP,
3268 DP_TRAINING_PATTERN_1 |
3269 DP_LINK_SCRAMBLING_DISABLE);
3274 /* Check to see if we've tried the same voltage 5 times */
3275 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3277 if (voltage_tries == 5) {
3278 DRM_ERROR("too many voltage retries, give up\n");
3283 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3285 /* Update training set as requested by target */
3286 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3287 DRM_ERROR("failed to update link training\n");
3296 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3298 bool channel_eq = false;
3299 int tries, cr_tries;
3300 uint32_t DP = intel_dp->DP;
3301 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3303 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3304 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3305 training_pattern = DP_TRAINING_PATTERN_3;
3307 /* channel equalization */
3308 if (!intel_dp_set_link_train(intel_dp, &DP,
3310 DP_LINK_SCRAMBLING_DISABLE)) {
3311 DRM_ERROR("failed to start channel equalization\n");
3319 uint8_t link_status[DP_LINK_STATUS_SIZE];
3322 DRM_ERROR("failed to train DP, aborting\n");
3326 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3327 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3328 DRM_ERROR("failed to get link status\n");
3332 /* Make sure clock is still ok */
3333 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3334 intel_dp_start_link_train(intel_dp);
3335 intel_dp_set_link_train(intel_dp, &DP,
3337 DP_LINK_SCRAMBLING_DISABLE);
3342 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3347 /* Try 5 times, then try clock recovery if that fails */
3349 intel_dp_link_down(intel_dp);
3350 intel_dp_start_link_train(intel_dp);
3351 intel_dp_set_link_train(intel_dp, &DP,
3353 DP_LINK_SCRAMBLING_DISABLE);
3359 /* Update training set as requested by target */
3360 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3361 DRM_ERROR("failed to update link training\n");
3367 intel_dp_set_idle_link_train(intel_dp);
3372 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3376 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3378 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3379 DP_TRAINING_PATTERN_DISABLE);
3383 intel_dp_link_down(struct intel_dp *intel_dp)
3385 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3386 enum port port = intel_dig_port->port;
3387 struct drm_device *dev = intel_dig_port->base.base.dev;
3388 struct drm_i915_private *dev_priv = dev->dev_private;
3389 struct intel_crtc *intel_crtc =
3390 to_intel_crtc(intel_dig_port->base.base.crtc);
3391 uint32_t DP = intel_dp->DP;
3393 if (WARN_ON(HAS_DDI(dev)))
3396 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3399 DRM_DEBUG_KMS("\n");
3401 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3402 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3403 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3405 DP &= ~DP_LINK_TRAIN_MASK;
3406 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3408 POSTING_READ(intel_dp->output_reg);
3410 if (HAS_PCH_IBX(dev) &&
3411 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3412 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3414 /* Hardware workaround: leaving our transcoder select
3415 * set to transcoder B while it's off will prevent the
3416 * corresponding HDMI output on transcoder A.
3418 * Combine this with another hardware workaround:
3419 * transcoder select bit can only be cleared while the
3422 DP &= ~DP_PIPEB_SELECT;
3423 I915_WRITE(intel_dp->output_reg, DP);
3425 /* Changes to enable or select take place the vblank
3426 * after being written.
3428 if (WARN_ON(crtc == NULL)) {
3429 /* We should never try to disable a port without a crtc
3430 * attached. For paranoia keep the code around for a
3432 POSTING_READ(intel_dp->output_reg);
3435 intel_wait_for_vblank(dev, intel_crtc->pipe);
3438 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3439 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3440 POSTING_READ(intel_dp->output_reg);
3441 msleep(intel_dp->panel_power_down_delay);
3445 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3447 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3448 struct drm_device *dev = dig_port->base.base.dev;
3449 struct drm_i915_private *dev_priv = dev->dev_private;
3451 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3453 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3454 sizeof(intel_dp->dpcd)) < 0)
3455 return false; /* aux transfer failed */
3457 ksnprintf(dpcd_hex_dump,
3458 sizeof(dpcd_hex_dump),
3459 "%02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
3460 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
3461 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
3462 intel_dp->dpcd[6], intel_dp->dpcd[7]);
3463 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3465 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3466 return false; /* DPCD not present */
3468 /* Check if the panel supports PSR */
3469 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3470 if (is_edp(intel_dp)) {
3471 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3473 sizeof(intel_dp->psr_dpcd));
3474 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3475 dev_priv->psr.sink_support = true;
3476 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3480 /* Training Pattern 3 support */
3481 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3482 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3483 intel_dp->use_tps3 = true;
3484 DRM_DEBUG_KMS("Displayport TPS3 supported");
3486 intel_dp->use_tps3 = false;
3488 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3489 DP_DWN_STRM_PORT_PRESENT))
3490 return true; /* native DP sink */
3492 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3493 return true; /* no per-port downstream info */
3495 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3496 intel_dp->downstream_ports,
3497 DP_MAX_DOWNSTREAM_PORTS) < 0)
3498 return false; /* downstream port status fetch failed */
3504 intel_dp_probe_oui(struct intel_dp *intel_dp)
3508 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3511 intel_edp_panel_vdd_on(intel_dp);
3513 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3514 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3515 buf[0], buf[1], buf[2]);
3517 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3518 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3519 buf[0], buf[1], buf[2]);
3521 edp_panel_vdd_off(intel_dp, false);
3524 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3526 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3527 struct drm_device *dev = intel_dig_port->base.base.dev;
3528 struct intel_crtc *intel_crtc =
3529 to_intel_crtc(intel_dig_port->base.base.crtc);
3532 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
3535 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3538 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3539 DP_TEST_SINK_START) < 0)
3542 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3543 intel_wait_for_vblank(dev, intel_crtc->pipe);
3544 intel_wait_for_vblank(dev, intel_crtc->pipe);
3546 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3549 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
3554 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3556 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3557 DP_DEVICE_SERVICE_IRQ_VECTOR,
3558 sink_irq_vector, 1) == 1;
3562 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3564 /* NAK by default */
3565 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3569 * According to DP spec
3572 * 2. Configure link according to Receiver Capabilities
3573 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3574 * 4. Check link status on receipt of hot-plug interrupt
3577 intel_dp_check_link_status(struct intel_dp *intel_dp)
3579 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3580 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3582 u8 link_status[DP_LINK_STATUS_SIZE];
3584 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3586 if (!intel_encoder->connectors_active)
3589 if (WARN_ON(!intel_encoder->base.crtc))
3592 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3595 /* Try to read receiver status if the link appears to be up */
3596 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3600 /* Now read the DPCD to see if it's actually running */
3601 if (!intel_dp_get_dpcd(intel_dp)) {
3605 /* Try to read the source of the interrupt */
3606 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3607 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3608 /* Clear interrupt source */
3609 drm_dp_dpcd_writeb(&intel_dp->aux,
3610 DP_DEVICE_SERVICE_IRQ_VECTOR,
3613 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3614 intel_dp_handle_test_request(intel_dp);
3615 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3616 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3619 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3620 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3621 intel_encoder->base.name);
3622 intel_dp_start_link_train(intel_dp);
3623 intel_dp_complete_link_train(intel_dp);
3624 intel_dp_stop_link_train(intel_dp);
3628 /* XXX this is probably wrong for multiple downstream ports */
3629 static enum drm_connector_status
3630 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3632 uint8_t *dpcd = intel_dp->dpcd;
3635 if (!intel_dp_get_dpcd(intel_dp))
3636 return connector_status_disconnected;
3638 /* if there's no downstream port, we're done */
3639 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3640 return connector_status_connected;
3642 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3643 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3644 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3647 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3649 return connector_status_unknown;
3651 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3652 : connector_status_disconnected;
3655 /* If no HPD, poke DDC gently */
3656 if (drm_probe_ddc(intel_dp->aux.ddc))
3657 return connector_status_connected;
3659 /* Well we tried, say unknown for unreliable port types */
3660 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3661 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3662 if (type == DP_DS_PORT_TYPE_VGA ||
3663 type == DP_DS_PORT_TYPE_NON_EDID)
3664 return connector_status_unknown;
3666 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3667 DP_DWN_STRM_PORT_TYPE_MASK;
3668 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3669 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3670 return connector_status_unknown;
3673 /* Anything else is out of spec, warn and ignore */
3674 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3675 return connector_status_disconnected;
3678 static enum drm_connector_status
3679 ironlake_dp_detect(struct intel_dp *intel_dp)
3681 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3682 struct drm_i915_private *dev_priv = dev->dev_private;
3683 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3684 enum drm_connector_status status;
3686 /* Can't disconnect eDP, but you can close the lid... */
3687 if (is_edp(intel_dp)) {
3688 status = intel_panel_detect(dev);
3689 if (status == connector_status_unknown)
3690 status = connector_status_connected;
3694 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3695 return connector_status_disconnected;
3697 return intel_dp_detect_dpcd(intel_dp);
3700 static int g4x_digital_port_connected(struct drm_device *dev,
3701 struct intel_digital_port *intel_dig_port)
3703 struct drm_i915_private *dev_priv = dev->dev_private;
3706 if (IS_VALLEYVIEW(dev)) {
3707 switch (intel_dig_port->port) {
3709 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3712 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3715 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3721 switch (intel_dig_port->port) {
3723 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3726 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3729 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3736 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3741 static enum drm_connector_status
3742 g4x_dp_detect(struct intel_dp *intel_dp)
3744 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3745 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3748 /* Can't disconnect eDP, but you can close the lid... */
3749 if (is_edp(intel_dp)) {
3750 enum drm_connector_status status;
3752 status = intel_panel_detect(dev);
3753 if (status == connector_status_unknown)
3754 status = connector_status_connected;
3758 ret = g4x_digital_port_connected(dev, intel_dig_port);
3760 return connector_status_unknown;
3762 return connector_status_disconnected;
3764 return intel_dp_detect_dpcd(intel_dp);
3767 static struct edid *
3768 intel_dp_get_edid(struct drm_connector *connector, struct device *adapter)
3770 struct intel_connector *intel_connector = to_intel_connector(connector);
3772 /* use cached edid if we have one */
3773 if (intel_connector->edid) {
3775 if (IS_ERR(intel_connector->edid))
3778 return drm_edid_duplicate(intel_connector->edid);
3781 return drm_get_edid(connector, adapter);
3785 intel_dp_get_edid_modes(struct drm_connector *connector, struct device *adapter)
3787 struct intel_connector *intel_connector = to_intel_connector(connector);
3789 /* use cached edid if we have one */
3790 if (intel_connector->edid) {
3792 if (IS_ERR(intel_connector->edid))
3795 return intel_connector_update_modes(connector,
3796 intel_connector->edid);
3799 return intel_ddc_get_modes(connector, adapter);
3802 static enum drm_connector_status
3803 intel_dp_detect(struct drm_connector *connector, bool force)
3805 struct intel_dp *intel_dp = intel_attached_dp(connector);
3806 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3807 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3808 struct drm_device *dev = connector->dev;
3809 struct drm_i915_private *dev_priv = dev->dev_private;
3810 enum drm_connector_status status;
3811 enum intel_display_power_domain power_domain;
3812 struct edid *edid = NULL;
3814 power_domain = intel_display_port_power_domain(intel_encoder);
3815 intel_display_power_get(dev_priv, power_domain);
3817 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3818 connector->base.id, connector->name);
3820 intel_dp->has_audio = false;
3822 if (HAS_PCH_SPLIT(dev))
3823 status = ironlake_dp_detect(intel_dp);
3825 status = g4x_dp_detect(intel_dp);
3827 if (status != connector_status_connected)
3830 intel_dp_probe_oui(intel_dp);
3832 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3833 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3835 edid = intel_dp_get_edid(connector, intel_dp->aux.ddc);
3837 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3842 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3843 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3844 status = connector_status_connected;
3847 intel_display_power_put(dev_priv, power_domain);
3851 static int intel_dp_get_modes(struct drm_connector *connector)
3853 struct intel_dp *intel_dp = intel_attached_dp(connector);
3854 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3855 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3856 struct intel_connector *intel_connector = to_intel_connector(connector);
3857 struct drm_device *dev = connector->dev;
3858 struct drm_i915_private *dev_priv = dev->dev_private;
3859 enum intel_display_power_domain power_domain;
3862 /* We should parse the EDID data and find out if it has an audio sink
3865 power_domain = intel_display_port_power_domain(intel_encoder);
3866 intel_display_power_get(dev_priv, power_domain);
3868 ret = intel_dp_get_edid_modes(connector, intel_dp->aux.ddc);
3869 intel_display_power_put(dev_priv, power_domain);
3873 /* if eDP has no EDID, fall back to fixed mode */
3874 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3875 struct drm_display_mode *mode;
3876 mode = drm_mode_duplicate(dev,
3877 intel_connector->panel.fixed_mode);
3879 drm_mode_probed_add(connector, mode);
3887 intel_dp_detect_audio(struct drm_connector *connector)
3889 struct intel_dp *intel_dp = intel_attached_dp(connector);
3890 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3891 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3892 struct drm_device *dev = connector->dev;
3893 struct drm_i915_private *dev_priv = dev->dev_private;
3894 enum intel_display_power_domain power_domain;
3896 bool has_audio = false;
3898 power_domain = intel_display_port_power_domain(intel_encoder);
3899 intel_display_power_get(dev_priv, power_domain);
3901 edid = intel_dp_get_edid(connector, intel_dp->aux.ddc);
3903 has_audio = drm_detect_monitor_audio(edid);
3907 intel_display_power_put(dev_priv, power_domain);
3913 intel_dp_set_property(struct drm_connector *connector,
3914 struct drm_property *property,
3917 struct drm_i915_private *dev_priv = connector->dev->dev_private;
3918 struct intel_connector *intel_connector = to_intel_connector(connector);
3919 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3920 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3923 ret = drm_object_property_set_value(&connector->base, property, val);
3927 if (property == dev_priv->force_audio_property) {
3931 if (i == intel_dp->force_audio)
3934 intel_dp->force_audio = i;
3936 if (i == HDMI_AUDIO_AUTO)
3937 has_audio = intel_dp_detect_audio(connector);
3939 has_audio = (i == HDMI_AUDIO_ON);
3941 if (has_audio == intel_dp->has_audio)
3944 intel_dp->has_audio = has_audio;
3948 if (property == dev_priv->broadcast_rgb_property) {
3949 bool old_auto = intel_dp->color_range_auto;
3950 uint32_t old_range = intel_dp->color_range;
3953 case INTEL_BROADCAST_RGB_AUTO:
3954 intel_dp->color_range_auto = true;
3956 case INTEL_BROADCAST_RGB_FULL:
3957 intel_dp->color_range_auto = false;
3958 intel_dp->color_range = 0;
3960 case INTEL_BROADCAST_RGB_LIMITED:
3961 intel_dp->color_range_auto = false;
3962 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3968 if (old_auto == intel_dp->color_range_auto &&
3969 old_range == intel_dp->color_range)
3975 if (is_edp(intel_dp) &&
3976 property == connector->dev->mode_config.scaling_mode_property) {
3977 if (val == DRM_MODE_SCALE_NONE) {
3978 DRM_DEBUG_KMS("no scaling not supported\n");
3982 if (intel_connector->panel.fitting_mode == val) {
3983 /* the eDP scaling property is not changed */
3986 intel_connector->panel.fitting_mode = val;
3994 if (intel_encoder->base.crtc)
3995 intel_crtc_restore_mode(intel_encoder->base.crtc);
4001 intel_dp_connector_destroy(struct drm_connector *connector)
4003 struct intel_connector *intel_connector = to_intel_connector(connector);
4005 if (!IS_ERR_OR_NULL(intel_connector->edid))
4006 kfree(intel_connector->edid);
4008 /* Can't call is_edp() since the encoder may have been destroyed
4010 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4011 intel_panel_fini(&intel_connector->panel);
4013 drm_connector_cleanup(connector);
4017 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4019 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4020 struct intel_dp *intel_dp = &intel_dig_port->dp;
4021 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4023 if (intel_dp->dp_iic_bus != NULL) {
4024 if (intel_dp->aux.ddc != NULL) {
4025 device_delete_child(intel_dp->dp_iic_bus,
4028 device_delete_child(dev->dev, intel_dp->dp_iic_bus);
4031 drm_encoder_cleanup(encoder);
4032 if (is_edp(intel_dp)) {
4033 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4034 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4035 edp_panel_vdd_off_sync(intel_dp);
4036 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4038 if (intel_dp->edp_notifier.notifier_call) {
4039 unregister_reboot_notifier(&intel_dp->edp_notifier);
4040 intel_dp->edp_notifier.notifier_call = NULL;
4044 kfree(intel_dig_port);
4047 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4049 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4051 if (!is_edp(intel_dp))
4054 edp_panel_vdd_off_sync(intel_dp);
4057 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4059 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4062 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4063 .dpms = intel_connector_dpms,
4064 .detect = intel_dp_detect,
4065 .fill_modes = drm_helper_probe_single_connector_modes,
4066 .set_property = intel_dp_set_property,
4067 .destroy = intel_dp_connector_destroy,
4070 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4071 .get_modes = intel_dp_get_modes,
4072 .mode_valid = intel_dp_mode_valid,
4073 .best_encoder = intel_best_encoder,
4076 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4077 .reset = intel_dp_encoder_reset,
4078 .destroy = intel_dp_encoder_destroy,
4082 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4084 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4086 intel_dp_check_link_status(intel_dp);
4090 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4092 struct intel_dp *intel_dp = &intel_dig_port->dp;
4093 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4094 struct drm_device *dev = intel_dig_port->base.base.dev;
4095 struct drm_i915_private *dev_priv = dev->dev_private;
4096 enum intel_display_power_domain power_domain;
4099 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4100 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4102 DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port,
4103 long_hpd ? "long" : "short");
4105 power_domain = intel_display_port_power_domain(intel_encoder);
4106 intel_display_power_get(dev_priv, power_domain);
4114 * we'll check the link status via the normal hot plug path later -
4115 * but for short hpds we should check it now
4117 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4118 intel_dp_check_link_status(intel_dp);
4119 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4123 intel_display_power_put(dev_priv, power_domain);
4128 /* Return which DP Port should be selected for Transcoder DP control */
4130 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4132 struct drm_device *dev = crtc->dev;
4133 struct intel_encoder *intel_encoder;
4134 struct intel_dp *intel_dp;
4136 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4137 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4139 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4140 intel_encoder->type == INTEL_OUTPUT_EDP)
4141 return intel_dp->output_reg;
4147 /* check the VBT to see whether the eDP is on DP-D port */
4148 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4150 struct drm_i915_private *dev_priv = dev->dev_private;
4151 union child_device_config *p_child;
4153 static const short port_mapping[] = {
4154 [PORT_B] = PORT_IDPB,
4155 [PORT_C] = PORT_IDPC,
4156 [PORT_D] = PORT_IDPD,
4162 if (!dev_priv->vbt.child_dev_num)
4165 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4166 p_child = dev_priv->vbt.child_dev + i;
4168 if (p_child->common.dvo_port == port_mapping[port] &&
4169 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4170 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4177 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4179 struct intel_connector *intel_connector = to_intel_connector(connector);
4181 intel_attach_force_audio_property(connector);
4182 intel_attach_broadcast_rgb_property(connector);
4183 intel_dp->color_range_auto = true;
4185 if (is_edp(intel_dp)) {
4186 drm_mode_create_scaling_mode_property(connector->dev);
4187 drm_object_attach_property(
4189 connector->dev->mode_config.scaling_mode_property,
4190 DRM_MODE_SCALE_ASPECT);
4191 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4195 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4197 intel_dp->last_power_cycle = jiffies;
4198 intel_dp->last_power_on = jiffies;
4199 intel_dp->last_backlight_off = jiffies;
4203 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4204 struct intel_dp *intel_dp,
4205 struct edp_power_seq *out)
4207 struct drm_i915_private *dev_priv = dev->dev_private;
4208 struct edp_power_seq cur, vbt, spec, final;
4209 u32 pp_on, pp_off, pp_div, pp;
4210 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4212 if (HAS_PCH_SPLIT(dev)) {
4213 pp_ctrl_reg = PCH_PP_CONTROL;
4214 pp_on_reg = PCH_PP_ON_DELAYS;
4215 pp_off_reg = PCH_PP_OFF_DELAYS;
4216 pp_div_reg = PCH_PP_DIVISOR;
4218 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4220 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4221 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4222 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4223 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4226 /* Workaround: Need to write PP_CONTROL with the unlock key as
4227 * the very first thing. */
4228 pp = ironlake_get_pp_control(intel_dp);
4229 I915_WRITE(pp_ctrl_reg, pp);
4231 pp_on = I915_READ(pp_on_reg);
4232 pp_off = I915_READ(pp_off_reg);
4233 pp_div = I915_READ(pp_div_reg);
4235 /* Pull timing values out of registers */
4236 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4237 PANEL_POWER_UP_DELAY_SHIFT;
4239 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4240 PANEL_LIGHT_ON_DELAY_SHIFT;
4242 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4243 PANEL_LIGHT_OFF_DELAY_SHIFT;
4245 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4246 PANEL_POWER_DOWN_DELAY_SHIFT;
4248 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4249 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4251 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4252 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4254 vbt = dev_priv->vbt.edp_pps;
4256 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4257 * our hw here, which are all in 100usec. */
4258 spec.t1_t3 = 210 * 10;
4259 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4260 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4261 spec.t10 = 500 * 10;
4262 /* This one is special and actually in units of 100ms, but zero
4263 * based in the hw (so we need to add 100 ms). But the sw vbt
4264 * table multiplies it with 1000 to make it in units of 100usec,
4266 spec.t11_t12 = (510 + 100) * 10;
4268 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4269 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4271 /* Use the max of the register settings and vbt. If both are
4272 * unset, fall back to the spec limits. */
4273 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4275 max(cur.field, vbt.field))
4276 assign_final(t1_t3);
4280 assign_final(t11_t12);
4283 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4284 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4285 intel_dp->backlight_on_delay = get_delay(t8);
4286 intel_dp->backlight_off_delay = get_delay(t9);
4287 intel_dp->panel_power_down_delay = get_delay(t10);
4288 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4291 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4292 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4293 intel_dp->panel_power_cycle_delay);
4295 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4296 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4303 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4304 struct intel_dp *intel_dp,
4305 struct edp_power_seq *seq)
4307 struct drm_i915_private *dev_priv = dev->dev_private;
4308 u32 pp_on, pp_off, pp_div, port_sel = 0;
4309 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4310 int pp_on_reg, pp_off_reg, pp_div_reg;
4312 if (HAS_PCH_SPLIT(dev)) {
4313 pp_on_reg = PCH_PP_ON_DELAYS;
4314 pp_off_reg = PCH_PP_OFF_DELAYS;
4315 pp_div_reg = PCH_PP_DIVISOR;
4317 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4319 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4320 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4321 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4325 * And finally store the new values in the power sequencer. The
4326 * backlight delays are set to 1 because we do manual waits on them. For
4327 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4328 * we'll end up waiting for the backlight off delay twice: once when we
4329 * do the manual sleep, and once when we disable the panel and wait for
4330 * the PP_STATUS bit to become zero.
4332 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4333 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4334 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4335 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4336 /* Compute the divisor for the pp clock, simply match the Bspec
4338 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4339 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4340 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4342 /* Haswell doesn't have any port selection bits for the panel
4343 * power sequencer any more. */
4344 if (IS_VALLEYVIEW(dev)) {
4345 if (dp_to_dig_port(intel_dp)->port == PORT_B)
4346 port_sel = PANEL_PORT_SELECT_DPB_VLV;
4348 port_sel = PANEL_PORT_SELECT_DPC_VLV;
4349 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4350 if (dp_to_dig_port(intel_dp)->port == PORT_A)
4351 port_sel = PANEL_PORT_SELECT_DPA;
4353 port_sel = PANEL_PORT_SELECT_DPD;
4358 I915_WRITE(pp_on_reg, pp_on);
4359 I915_WRITE(pp_off_reg, pp_off);
4360 I915_WRITE(pp_div_reg, pp_div);
4362 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4363 I915_READ(pp_on_reg),
4364 I915_READ(pp_off_reg),
4365 I915_READ(pp_div_reg));
4368 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4370 struct drm_i915_private *dev_priv = dev->dev_private;
4371 struct intel_encoder *encoder;
4372 struct intel_dp *intel_dp = NULL;
4373 struct intel_crtc_config *config = NULL;
4374 struct intel_crtc *intel_crtc = NULL;
4375 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4377 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4379 if (refresh_rate <= 0) {
4380 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4384 if (intel_connector == NULL) {
4385 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4390 * FIXME: This needs proper synchronization with psr state. But really
4391 * hard to tell without seeing the user of this function of this code.
4392 * Check locking and ordering once that lands.
4394 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4395 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4399 encoder = intel_attached_encoder(&intel_connector->base);
4400 intel_dp = enc_to_intel_dp(&encoder->base);
4401 intel_crtc = encoder->new_crtc;
4404 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4408 config = &intel_crtc->config;
4410 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4411 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4415 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4416 index = DRRS_LOW_RR;
4418 if (index == intel_dp->drrs_state.refresh_rate_type) {
4420 "DRRS requested for previously set RR...ignoring\n");
4424 if (!intel_crtc->active) {
4425 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4429 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4430 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4431 val = I915_READ(reg);
4432 if (index > DRRS_HIGH_RR) {
4433 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4434 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
4436 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4438 I915_WRITE(reg, val);
4442 * mutex taken to ensure that there is no race between differnt
4443 * drrs calls trying to update refresh rate. This scenario may occur
4444 * in future when idleness detection based DRRS in kernel and
4445 * possible calls from user space to set differnt RR are made.
4448 mutex_lock(&intel_dp->drrs_state.mutex);
4450 intel_dp->drrs_state.refresh_rate_type = index;
4452 mutex_unlock(&intel_dp->drrs_state.mutex);
4454 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4457 static struct drm_display_mode *
4458 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4459 struct intel_connector *intel_connector,
4460 struct drm_display_mode *fixed_mode)
4462 struct drm_connector *connector = &intel_connector->base;
4463 struct intel_dp *intel_dp = &intel_dig_port->dp;
4464 struct drm_device *dev = intel_dig_port->base.base.dev;
4465 struct drm_i915_private *dev_priv = dev->dev_private;
4466 struct drm_display_mode *downclock_mode = NULL;
4468 if (INTEL_INFO(dev)->gen <= 6) {
4469 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4473 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4474 DRM_INFO("VBT doesn't support DRRS\n");
4478 downclock_mode = intel_find_panel_downclock
4479 (dev, fixed_mode, connector);
4481 if (!downclock_mode) {
4482 DRM_INFO("DRRS not supported\n");
4486 dev_priv->drrs.connector = intel_connector;
4488 lockinit(&intel_dp->drrs_state.mutex, "i915dsm", 0, LK_CANRECURSE);
4490 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4492 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4493 DRM_INFO("seamless DRRS supported for eDP panel.\n");
4494 return downclock_mode;
4497 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4499 struct drm_device *dev = intel_encoder->base.dev;
4500 struct drm_i915_private *dev_priv = dev->dev_private;
4501 struct intel_dp *intel_dp;
4502 enum intel_display_power_domain power_domain;
4504 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4507 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4508 if (!edp_have_panel_vdd(intel_dp))
4511 * The VDD bit needs a power domain reference, so if the bit is
4512 * already enabled when we boot or resume, grab this reference and
4513 * schedule a vdd off, so we don't hold on to the reference
4516 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4517 power_domain = intel_display_port_power_domain(intel_encoder);
4518 intel_display_power_get(dev_priv, power_domain);
4520 edp_panel_vdd_schedule_off(intel_dp);
4523 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4524 struct intel_connector *intel_connector,
4525 struct edp_power_seq *power_seq)
4527 struct drm_connector *connector = &intel_connector->base;
4528 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4529 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4530 struct drm_device *dev = intel_encoder->base.dev;
4531 struct drm_i915_private *dev_priv = dev->dev_private;
4532 struct drm_display_mode *fixed_mode = NULL;
4533 struct drm_display_mode *downclock_mode = NULL;
4535 struct drm_display_mode *scan;
4538 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4540 if (!is_edp(intel_dp))
4543 intel_edp_panel_vdd_sanitize(intel_encoder);
4545 /* Cache DPCD and EDID for edp. */
4546 intel_edp_panel_vdd_on(intel_dp);
4547 has_dpcd = intel_dp_get_dpcd(intel_dp);
4548 edp_panel_vdd_off(intel_dp, false);
4551 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4552 dev_priv->no_aux_handshake =
4553 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4554 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4556 /* if this fails, presume the device is a ghost */
4557 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4561 /* We now know it's not a ghost, init power sequence regs. */
4562 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
4564 mutex_lock(&dev->mode_config.mutex);
4565 edid = drm_get_edid(connector, intel_dp->aux.ddc);
4567 if (drm_add_edid_modes(connector, edid)) {
4568 drm_mode_connector_update_edid_property(connector,
4570 drm_edid_to_eld(connector, edid);
4573 edid = ERR_PTR(-EINVAL);
4576 edid = ERR_PTR(-ENOENT);
4578 intel_connector->edid = edid;
4580 /* prefer fixed mode from EDID if available */
4581 list_for_each_entry(scan, &connector->probed_modes, head) {
4582 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4583 fixed_mode = drm_mode_duplicate(dev, scan);
4584 downclock_mode = intel_dp_drrs_init(
4586 intel_connector, fixed_mode);
4591 /* fallback to VBT if available for eDP */
4592 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4593 fixed_mode = drm_mode_duplicate(dev,
4594 dev_priv->vbt.lfp_lvds_vbt_mode);
4596 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4598 mutex_unlock(&dev->mode_config.mutex);
4601 if (IS_VALLEYVIEW(dev)) {
4602 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4603 register_reboot_notifier(&intel_dp->edp_notifier);
4607 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4608 intel_panel_setup_backlight(connector);
4614 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4615 struct intel_connector *intel_connector)
4617 struct drm_connector *connector = &intel_connector->base;
4618 struct intel_dp *intel_dp = &intel_dig_port->dp;
4619 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4620 struct drm_device *dev = intel_encoder->base.dev;
4621 struct drm_i915_private *dev_priv = dev->dev_private;
4622 enum port port = intel_dig_port->port;
4623 struct edp_power_seq power_seq = { 0 };
4626 /* intel_dp vfuncs */
4627 if (IS_VALLEYVIEW(dev))
4628 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4629 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4630 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4631 else if (HAS_PCH_SPLIT(dev))
4632 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4634 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4636 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4638 /* Preserve the current hw state. */
4639 intel_dp->DP = I915_READ(intel_dp->output_reg);
4640 intel_dp->attached_connector = intel_connector;
4642 if (intel_dp_is_edp(dev, port))
4643 type = DRM_MODE_CONNECTOR_eDP;
4645 type = DRM_MODE_CONNECTOR_DisplayPort;
4648 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4649 * for DP the encoder type can be set by the caller to
4650 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4652 if (type == DRM_MODE_CONNECTOR_eDP)
4653 intel_encoder->type = INTEL_OUTPUT_EDP;
4655 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4656 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4659 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
4660 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4662 connector->interlace_allowed = true;
4663 connector->doublescan_allowed = 0;
4665 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4666 edp_panel_vdd_work);
4668 intel_connector_attach_encoder(intel_connector, intel_encoder);
4669 drm_connector_register(connector);
4672 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4674 intel_connector->get_hw_state = intel_connector_get_hw_state;
4675 intel_connector->unregister = intel_dp_connector_unregister;
4677 /* Set up the hotplug pin. */
4680 intel_encoder->hpd_pin = HPD_PORT_A;
4683 intel_encoder->hpd_pin = HPD_PORT_B;
4686 intel_encoder->hpd_pin = HPD_PORT_C;
4689 intel_encoder->hpd_pin = HPD_PORT_D;
4695 if (is_edp(intel_dp)) {
4696 intel_dp_init_panel_power_timestamps(intel_dp);
4697 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
4700 intel_dp_aux_init(intel_dp, intel_connector);
4702 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4704 drm_dp_aux_unregister(&intel_dp->aux);
4705 i2c_del_adapter(&intel_dp->adapter);
4707 if (is_edp(intel_dp)) {
4708 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4709 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4710 edp_panel_vdd_off_sync(intel_dp);
4711 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4713 drm_connector_unregister(connector);
4714 drm_connector_cleanup(connector);
4718 intel_dp_add_properties(intel_dp, connector);
4720 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4721 * 0xd. Failure to do so will result in spurious interrupts being
4722 * generated on the port when a cable is not attached.
4724 if (IS_G4X(dev) && !IS_GM45(dev)) {
4725 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4726 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4733 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4735 struct drm_i915_private *dev_priv = dev->dev_private;
4736 struct intel_digital_port *intel_dig_port;
4737 struct intel_encoder *intel_encoder;
4738 struct drm_encoder *encoder;
4739 struct intel_connector *intel_connector;
4741 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4742 if (!intel_dig_port)
4745 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
4746 if (!intel_connector) {
4747 kfree(intel_dig_port);
4751 intel_encoder = &intel_dig_port->base;
4752 encoder = &intel_encoder->base;
4754 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4755 DRM_MODE_ENCODER_TMDS);
4757 intel_encoder->compute_config = intel_dp_compute_config;
4758 intel_encoder->disable = intel_disable_dp;
4759 intel_encoder->get_hw_state = intel_dp_get_hw_state;
4760 intel_encoder->get_config = intel_dp_get_config;
4761 intel_encoder->suspend = intel_dp_encoder_suspend;
4762 if (IS_CHERRYVIEW(dev)) {
4763 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
4764 intel_encoder->pre_enable = chv_pre_enable_dp;
4765 intel_encoder->enable = vlv_enable_dp;
4766 intel_encoder->post_disable = chv_post_disable_dp;
4767 } else if (IS_VALLEYVIEW(dev)) {
4768 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
4769 intel_encoder->pre_enable = vlv_pre_enable_dp;
4770 intel_encoder->enable = vlv_enable_dp;
4771 intel_encoder->post_disable = vlv_post_disable_dp;
4773 intel_encoder->pre_enable = g4x_pre_enable_dp;
4774 intel_encoder->enable = g4x_enable_dp;
4775 intel_encoder->post_disable = g4x_post_disable_dp;
4778 intel_dig_port->port = port;
4779 intel_dig_port->dp.output_reg = output_reg;
4781 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4782 if (IS_CHERRYVIEW(dev)) {
4784 intel_encoder->crtc_mask = 1 << 2;
4786 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4788 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4790 intel_encoder->cloneable = 0;
4791 intel_encoder->hot_plug = intel_dp_hot_plug;
4793 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4794 dev_priv->hpd_irq_port[port] = intel_dig_port;
4796 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4797 drm_encoder_cleanup(encoder);
4798 kfree(intel_dig_port);
4799 kfree(intel_connector);