2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.28 2005/10/30 04:41:10 dillon Exp $
34 #include "opt_simos.h"
35 #include "opt_compat_oldpci.h"
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/fcntl.h>
43 #include <sys/kernel.h>
44 #include <sys/queue.h>
45 #include <sys/types.h>
50 #include <vm/vm_extern.h>
53 #include <machine/bus.h>
55 #include <machine/resource.h>
56 #include <machine/md_var.h> /* For the Alpha */
58 #include <bus/pci/i386/pci_cfgreg.h>
61 #include <sys/pciio.h>
64 #include "pci_private.h"
69 #include <machine/smp.h>
72 devclass_t pci_devclass;
73 const char *pcib_owner;
75 static void pci_read_extcap(device_t dev, pcicfgregs *cfg);
78 u_int32_t devid; /* Vendor/device of the card */
80 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
85 struct pci_quirk pci_quirks[] = {
87 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
89 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
90 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
91 /* As does the Serverworks OSB4 (the SMBus mapping register) */
92 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
97 /* map register information */
98 #define PCI_MAPMEM 0x01 /* memory map */
99 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
100 #define PCI_MAPPORT 0x04 /* port map */
102 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
103 u_int32_t pci_numdevs = 0;
104 static u_int32_t pci_generation = 0;
107 pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func)
109 struct pci_devinfo *dinfo;
111 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
112 if ((dinfo->cfg.bus == bus) &&
113 (dinfo->cfg.slot == slot) &&
114 (dinfo->cfg.func == func)) {
115 return (dinfo->cfg.dev);
123 pci_find_device (u_int16_t vendor, u_int16_t device)
125 struct pci_devinfo *dinfo;
127 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
128 if ((dinfo->cfg.vendor == vendor) &&
129 (dinfo->cfg.device == device)) {
130 return (dinfo->cfg.dev);
137 /* return base address of memory or port map */
140 pci_mapbase(unsigned mapreg)
143 if ((mapreg & 0x01) == 0)
145 return (mapreg & ~mask);
148 /* return map type of memory or port map */
151 pci_maptype(unsigned mapreg)
153 static u_int8_t maptype[0x10] = {
154 PCI_MAPMEM, PCI_MAPPORT,
156 PCI_MAPMEM, PCI_MAPPORT,
158 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
159 PCI_MAPMEM|PCI_MAPMEMP, 0,
160 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
164 return maptype[mapreg & 0x0f];
167 /* return log2 of map size decoded for memory or port map */
170 pci_mapsize(unsigned testval)
174 testval = pci_mapbase(testval);
177 while ((testval & 1) == 0)
186 /* return log2 of address range supported by map register */
189 pci_maprange(unsigned mapreg)
192 switch (mapreg & 0x07) {
208 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
211 pci_fixancient(pcicfgregs *cfg)
213 if (cfg->hdrtype != 0)
216 /* PCI to PCI bridges use header type 1 */
217 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
221 /* read config data specific to header type 1 device (PCI to PCI bridge) */
224 pci_readppb(device_t pcib, int b, int s, int f)
228 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
232 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
233 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
235 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
237 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
239 PCIB_READ_CONFIG(pcib, b, s, f,
241 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
243 PCIB_READ_CONFIG(pcib, b, s, f,
244 PCIR_IOLIMITL_1, 1));
246 p->membase = PCI_PPBMEMBASE (0,
247 PCIB_READ_CONFIG(pcib, b, s, f,
249 p->memlimit = PCI_PPBMEMLIMIT (0,
250 PCIB_READ_CONFIG(pcib, b, s, f,
251 PCIR_MEMLIMIT_1, 2));
253 p->pmembase = PCI_PPBMEMBASE (
254 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
255 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
257 p->pmemlimit = PCI_PPBMEMLIMIT (
258 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
260 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
265 /* read config data specific to header type 2 device (PCI to CardBus bridge) */
268 pci_readpcb(device_t pcib, int b, int s, int f)
272 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
276 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
277 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
279 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
281 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
282 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
283 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
284 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
286 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
287 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
288 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
289 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
291 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
295 /* extract header type specific config data */
298 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
300 #define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
301 switch (cfg->hdrtype) {
303 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
304 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
305 cfg->nummaps = PCI_MAXMAPS_0;
308 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
309 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
310 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
311 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
312 cfg->nummaps = PCI_MAXMAPS_1;
313 cfg->hdrspec = pci_readppb(pcib, b, s, f);
316 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
317 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
318 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
319 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
320 cfg->nummaps = PCI_MAXMAPS_2;
321 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
327 /* read configuration header into pcicfgrect structure */
330 pci_read_device(device_t pcib, int b, int s, int f, size_t size)
332 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
334 pcicfgregs *cfg = NULL;
335 struct pci_devinfo *devlist_entry;
336 struct devlist *devlist_head;
338 devlist_head = &pci_devq;
340 devlist_entry = NULL;
342 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
344 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
345 if (devlist_entry == NULL)
348 cfg = &devlist_entry->cfg;
353 cfg->vendor = REG(PCIR_VENDOR, 2);
354 cfg->device = REG(PCIR_DEVICE, 2);
355 cfg->cmdreg = REG(PCIR_COMMAND, 2);
356 cfg->statreg = REG(PCIR_STATUS, 2);
357 cfg->baseclass = REG(PCIR_CLASS, 1);
358 cfg->subclass = REG(PCIR_SUBCLASS, 1);
359 cfg->progif = REG(PCIR_PROGIF, 1);
360 cfg->revid = REG(PCIR_REVID, 1);
361 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
362 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
363 cfg->lattimer = REG(PCIR_LATTIMER, 1);
364 cfg->intpin = REG(PCIR_INTPIN, 1);
365 cfg->intline = REG(PCIR_INTLINE, 1);
368 if (cfg->intpin != 0) {
371 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
373 /* PCI specific entry found in MP table */
374 if (airq != cfg->intline) {
375 undirect_pci_irq(cfg->intline);
380 * PCI interrupts might be redirected to the
381 * ISA bus according to some MP tables. Use the
382 * same methods as used by the ISA devices
383 * devices to find the proper IOAPIC int pin.
385 airq = isa_apic_irq(cfg->intline);
386 if ((airq >= 0) && (airq != cfg->intline)) {
387 /* XXX: undirect_pci_irq() ? */
388 undirect_isa_irq(cfg->intline);
395 cfg->mingnt = REG(PCIR_MINGNT, 1);
396 cfg->maxlat = REG(PCIR_MAXLAT, 1);
398 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
399 cfg->hdrtype &= ~PCIM_MFDEV;
402 pci_hdrtypedata(pcib, b, s, f, cfg);
404 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
405 pci_read_extcap(pcib, cfg);
407 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
409 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
410 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
411 devlist_entry->conf.pc_sel.pc_func = cfg->func;
412 devlist_entry->conf.pc_hdr = cfg->hdrtype;
414 devlist_entry->conf.pc_subvendor = cfg->subvendor;
415 devlist_entry->conf.pc_subdevice = cfg->subdevice;
416 devlist_entry->conf.pc_vendor = cfg->vendor;
417 devlist_entry->conf.pc_device = cfg->device;
419 devlist_entry->conf.pc_class = cfg->baseclass;
420 devlist_entry->conf.pc_subclass = cfg->subclass;
421 devlist_entry->conf.pc_progif = cfg->progif;
422 devlist_entry->conf.pc_revid = cfg->revid;
427 return (devlist_entry);
432 pci_read_extcap(device_t pcib, pcicfgregs *cfg)
434 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
435 int ptr, nextptr, ptrptr;
437 switch (cfg->hdrtype) {
445 return; /* no extended capabilities support */
447 nextptr = REG(ptrptr, 1); /* sanity check? */
450 * Read capability entries.
452 while (nextptr != 0) {
455 printf("illegal PCI extended capability offset %d\n",
459 /* Find the next entry */
461 nextptr = REG(ptr + 1, 1);
463 /* Process this entry */
464 switch (REG(ptr, 1)) {
465 case 0x01: /* PCI power management */
466 if (cfg->pp_cap == 0) {
467 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
468 cfg->pp_status = ptr + PCIR_POWER_STATUS;
469 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
470 if ((nextptr - ptr) > PCIR_POWER_DATA)
471 cfg->pp_data = ptr + PCIR_POWER_DATA;
481 /* free pcicfgregs structure and all depending data structures */
484 pci_freecfg(struct pci_devinfo *dinfo)
486 struct devlist *devlist_head;
488 devlist_head = &pci_devq;
490 if (dinfo->cfg.hdrspec != NULL)
491 free(dinfo->cfg.hdrspec, M_DEVBUF);
492 /* XXX this hasn't been tested */
493 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
494 free(dinfo, M_DEVBUF);
496 /* increment the generation count */
499 /* we're losing one device */
506 * PCI power manangement
509 pci_set_powerstate_method(device_t dev, device_t child, int state)
511 struct pci_devinfo *dinfo = device_get_ivars(child);
512 pcicfgregs *cfg = &dinfo->cfg;
516 if (cfg->pp_cap != 0) {
517 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK;
520 case PCI_POWERSTATE_D0:
521 status |= PCIM_PSTAT_D0;
523 case PCI_POWERSTATE_D1:
524 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) {
525 status |= PCIM_PSTAT_D1;
530 case PCI_POWERSTATE_D2:
531 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) {
532 status |= PCIM_PSTAT_D2;
537 case PCI_POWERSTATE_D3:
538 status |= PCIM_PSTAT_D3;
544 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2);
552 pci_get_powerstate_method(device_t dev, device_t child)
554 struct pci_devinfo *dinfo = device_get_ivars(child);
555 pcicfgregs *cfg = &dinfo->cfg;
559 if (cfg->pp_cap != 0) {
560 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2);
561 switch (status & PCIM_PSTAT_DMASK) {
563 result = PCI_POWERSTATE_D0;
566 result = PCI_POWERSTATE_D1;
569 result = PCI_POWERSTATE_D2;
572 result = PCI_POWERSTATE_D3;
575 result = PCI_POWERSTATE_UNKNOWN;
579 /* No support, device is always at D0 */
580 result = PCI_POWERSTATE_D0;
586 * Some convenience functions for PCI device drivers.
590 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
594 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
596 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
600 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
604 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
606 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
610 pci_enable_busmaster_method(device_t dev, device_t child)
612 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
617 pci_disable_busmaster_method(device_t dev, device_t child)
619 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
624 pci_enable_io_method(device_t dev, device_t child, int space)
635 bit = PCIM_CMD_PORTEN;
639 bit = PCIM_CMD_MEMEN;
645 pci_set_command_bit(dev, child, bit);
646 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
649 device_printf(child, "failed to enable %s mapping!\n", error);
654 pci_disable_io_method(device_t dev, device_t child, int space)
665 bit = PCIM_CMD_PORTEN;
669 bit = PCIM_CMD_MEMEN;
675 pci_clear_command_bit(dev, child, bit);
676 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
678 device_printf(child, "failed to disable %s mapping!\n", error);
685 * This is the user interface to PCI configuration space.
689 pci_open(dev_t dev, int oflags, int devtype, struct thread *td)
691 if ((oflags & FWRITE) && securelevel > 0) {
698 pci_close(dev_t dev, int flag, int devtype, struct thread *td)
704 * Match a single pci_conf structure against an array of pci_match_conf
705 * structures. The first argument, 'matches', is an array of num_matches
706 * pci_match_conf structures. match_buf is a pointer to the pci_conf
707 * structure that will be compared to every entry in the matches array.
708 * This function returns 1 on failure, 0 on success.
711 pci_conf_match(struct pci_match_conf *matches, int num_matches,
712 struct pci_conf *match_buf)
716 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
719 for (i = 0; i < num_matches; i++) {
721 * I'm not sure why someone would do this...but...
723 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
727 * Look at each of the match flags. If it's set, do the
728 * comparison. If the comparison fails, we don't have a
729 * match, go on to the next item if there is one.
731 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
732 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
735 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
736 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
739 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
740 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
743 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
744 && (match_buf->pc_vendor != matches[i].pc_vendor))
747 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
748 && (match_buf->pc_device != matches[i].pc_device))
751 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
752 && (match_buf->pc_class != matches[i].pc_class))
755 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
756 && (match_buf->pd_unit != matches[i].pd_unit))
759 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
760 && (strncmp(matches[i].pd_name, match_buf->pd_name,
761 sizeof(match_buf->pd_name)) != 0))
771 * Locate the parent of a PCI device by scanning the PCI devlist
772 * and return the entry for the parent.
773 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
774 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
778 pci_devlist_get_parent(pcicfgregs *cfg)
780 struct devlist *devlist_head;
781 struct pci_devinfo *dinfo;
782 pcicfgregs *bridge_cfg;
785 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
787 /* If the device is on PCI bus 0, look for the host */
789 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
790 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
791 bridge_cfg = &dinfo->cfg;
792 if (bridge_cfg->baseclass == PCIC_BRIDGE
793 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
794 && bridge_cfg->bus == cfg->bus) {
800 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
802 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
803 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
804 bridge_cfg = &dinfo->cfg;
805 if (bridge_cfg->baseclass == PCIC_BRIDGE
806 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
807 && bridge_cfg->secondarybus == cfg->bus) {
817 pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td)
824 if (!(flag & FWRITE))
831 struct pci_devinfo *dinfo;
832 struct pci_conf_io *cio;
833 struct devlist *devlist_head;
834 struct pci_match_conf *pattern_buf;
839 cio = (struct pci_conf_io *)data;
845 * Hopefully the user won't pass in a null pointer, but it
846 * can't hurt to check.
854 * If the user specified an offset into the device list,
855 * but the list has changed since they last called this
856 * ioctl, tell them that the list has changed. They will
857 * have to get the list from the beginning.
859 if ((cio->offset != 0)
860 && (cio->generation != pci_generation)){
861 cio->num_matches = 0;
862 cio->status = PCI_GETCONF_LIST_CHANGED;
868 * Check to see whether the user has asked for an offset
869 * past the end of our list.
871 if (cio->offset >= pci_numdevs) {
872 cio->num_matches = 0;
873 cio->status = PCI_GETCONF_LAST_DEVICE;
878 /* get the head of the device queue */
879 devlist_head = &pci_devq;
882 * Determine how much room we have for pci_conf structures.
883 * Round the user's buffer size down to the nearest
884 * multiple of sizeof(struct pci_conf) in case the user
885 * didn't specify a multiple of that size.
887 iolen = min(cio->match_buf_len -
888 (cio->match_buf_len % sizeof(struct pci_conf)),
889 pci_numdevs * sizeof(struct pci_conf));
892 * Since we know that iolen is a multiple of the size of
893 * the pciconf union, it's okay to do this.
895 ionum = iolen / sizeof(struct pci_conf);
898 * If this test is true, the user wants the pci_conf
899 * structures returned to match the supplied entries.
901 if ((cio->num_patterns > 0)
902 && (cio->pat_buf_len > 0)) {
904 * pat_buf_len needs to be:
905 * num_patterns * sizeof(struct pci_match_conf)
906 * While it is certainly possible the user just
907 * allocated a large buffer, but set the number of
908 * matches correctly, it is far more likely that
909 * their kernel doesn't match the userland utility
910 * they're using. It's also possible that the user
911 * forgot to initialize some variables. Yes, this
912 * may be overly picky, but I hazard to guess that
913 * it's far more likely to just catch folks that
914 * updated their kernel but not their userland.
916 if ((cio->num_patterns *
917 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
918 /* The user made a mistake, return an error*/
919 cio->status = PCI_GETCONF_ERROR;
920 printf("pci_ioctl: pat_buf_len %d != "
921 "num_patterns (%d) * sizeof(struct "
922 "pci_match_conf) (%d)\npci_ioctl: "
923 "pat_buf_len should be = %d\n",
924 cio->pat_buf_len, cio->num_patterns,
925 (int)sizeof(struct pci_match_conf),
926 (int)sizeof(struct pci_match_conf) *
928 printf("pci_ioctl: do your headers match your "
930 cio->num_matches = 0;
936 * Check the user's buffer to make sure it's readable.
938 if (!useracc((caddr_t)cio->patterns,
939 cio->pat_buf_len, VM_PROT_READ)) {
940 printf("pci_ioctl: pattern buffer %p, "
941 "length %u isn't user accessible for"
942 " READ\n", cio->patterns,
948 * Allocate a buffer to hold the patterns.
950 pattern_buf = malloc(cio->pat_buf_len, M_TEMP,
952 error = copyin(cio->patterns, pattern_buf,
956 num_patterns = cio->num_patterns;
958 } else if ((cio->num_patterns > 0)
959 || (cio->pat_buf_len > 0)) {
961 * The user made a mistake, spit out an error.
963 cio->status = PCI_GETCONF_ERROR;
964 cio->num_matches = 0;
965 printf("pci_ioctl: invalid GETCONF arguments\n");
972 * Make sure we can write to the match buffer.
974 if (!useracc((caddr_t)cio->matches,
975 cio->match_buf_len, VM_PROT_WRITE)) {
976 printf("pci_ioctl: match buffer %p, length %u "
977 "isn't user accessible for WRITE\n",
978 cio->matches, cio->match_buf_len);
984 * Go through the list of devices and copy out the devices
985 * that match the user's criteria.
987 for (cio->num_matches = 0, error = 0, i = 0,
988 dinfo = STAILQ_FIRST(devlist_head);
989 (dinfo != NULL) && (cio->num_matches < ionum)
990 && (error == 0) && (i < pci_numdevs);
991 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
996 /* Populate pd_name and pd_unit */
998 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
999 name = device_get_name(dinfo->cfg.dev);
1001 strncpy(dinfo->conf.pd_name, name,
1002 sizeof(dinfo->conf.pd_name));
1003 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1004 dinfo->conf.pd_unit =
1005 device_get_unit(dinfo->cfg.dev);
1008 if ((pattern_buf == NULL) ||
1009 (pci_conf_match(pattern_buf, num_patterns,
1010 &dinfo->conf) == 0)) {
1013 * If we've filled up the user's buffer,
1014 * break out at this point. Since we've
1015 * got a match here, we'll pick right back
1016 * up at the matching entry. We can also
1017 * tell the user that there are more matches
1020 if (cio->num_matches >= ionum)
1023 error = copyout(&dinfo->conf,
1024 &cio->matches[cio->num_matches],
1025 sizeof(struct pci_conf));
1031 * Set the pointer into the list, so if the user is getting
1032 * n records at a time, where n < pci_numdevs,
1037 * Set the generation, the user will need this if they make
1038 * another ioctl call with offset != 0.
1040 cio->generation = pci_generation;
1043 * If this is the last device, inform the user so he won't
1044 * bother asking for more devices. If dinfo isn't NULL, we
1045 * know that there are more matches in the list because of
1046 * the way the traversal is done.
1049 cio->status = PCI_GETCONF_LAST_DEVICE;
1051 cio->status = PCI_GETCONF_MORE_DEVS;
1053 if (pattern_buf != NULL)
1054 free(pattern_buf, M_TEMP);
1059 io = (struct pci_io *)data;
1060 switch(io->pi_width) {
1065 * Assume that the user-level bus number is
1066 * actually the pciN instance number. We map
1067 * from that to the real pcib+bus combination.
1069 pci = devclass_get_device(pci_devclass,
1073 * pci is the pci device and may contain
1074 * several children (for each function code).
1075 * The governing pci bus is the parent to
1080 pcib = device_get_parent(pci);
1081 b = pcib_get_bus(pcib);
1083 PCIB_READ_CONFIG(pcib,
1101 io = (struct pci_io *)data;
1102 switch(io->pi_width) {
1107 * Assume that the user-level bus number is
1108 * actually the pciN instance number. We map
1109 * from that to the real pcib+bus combination.
1111 pci = devclass_get_device(pci_devclass,
1115 * pci is the pci device and may contain
1116 * several children (for each function code).
1117 * The governing pci bus is the parent to
1122 pcib = device_get_parent(pci);
1123 b = pcib_get_bus(pcib);
1124 PCIB_WRITE_CONFIG(pcib,
1152 static struct cdevsw pcicdev = {
1159 /* open */ pci_open,
1160 /* close */ pci_close,
1162 /* write */ nowrite,
1163 /* ioctl */ pci_ioctl,
1166 /* strategy */ nostrategy,
1174 * New style pci driver. Parent device is either a pci-host-bridge or a
1175 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1178 pci_class_to_string(int baseclass)
1195 case PCIC_MULTIMEDIA:
1196 name = "MULTIMEDIA";
1204 case PCIC_SIMPLECOMM:
1205 name = "SIMPLECOMM";
1207 case PCIC_BASEPERIPH:
1208 name = "BASEPERIPH";
1216 case PCIC_PROCESSOR:
1219 case PCIC_SERIALBUS:
1228 case PCIC_SATELLITE:
1248 pci_print_verbose(struct pci_devinfo *dinfo)
1251 pcicfgregs *cfg = &dinfo->cfg;
1253 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
1254 cfg->vendor, cfg->device, cfg->revid);
1255 printf("\tbus=%d, slot=%d, func=%d\n",
1256 cfg->bus, cfg->slot, cfg->func);
1257 printf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
1258 pci_class_to_string(cfg->baseclass),
1259 cfg->baseclass, cfg->subclass, cfg->progif,
1260 cfg->hdrtype, cfg->mfdev);
1261 printf("\tsubordinatebus=%x \tsecondarybus=%x\n",
1262 cfg->subordinatebus, cfg->secondarybus);
1264 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
1265 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
1266 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
1267 cfg->lattimer, cfg->lattimer * 30,
1268 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1269 #endif /* PCI_DEBUG */
1270 if (cfg->intpin > 0)
1271 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
1276 pci_porten(device_t pcib, int b, int s, int f)
1278 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1279 & PCIM_CMD_PORTEN) != 0;
1283 pci_memen(device_t pcib, int b, int s, int f)
1285 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1286 & PCIM_CMD_MEMEN) != 0;
1290 * Add a resource based on a pci map register. Return 1 if the map
1291 * register is a 32bit map register or 2 if it is a 64bit register.
1294 pci_add_map(device_t pcib, int b, int s, int f, int reg,
1295 struct resource_list *rl)
1304 #ifdef PCI_ENABLE_IO_MODES
1309 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1311 if (map == 0 || map == 0xffffffff)
1312 return 1; /* skip invalid entry */
1314 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1315 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1316 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
1318 base = pci_mapbase(map);
1319 if (pci_maptype(map) & PCI_MAPMEM)
1320 type = SYS_RES_MEMORY;
1322 type = SYS_RES_IOPORT;
1323 ln2size = pci_mapsize(testval);
1324 ln2range = pci_maprange(testval);
1325 if (ln2range == 64) {
1326 /* Read the other half of a 64bit map register */
1327 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
1331 * This code theoretically does the right thing, but has
1332 * undesirable side effects in some cases where
1333 * peripherals respond oddly to having these bits
1334 * enabled. Leave them alone by default.
1336 #ifdef PCI_ENABLE_IO_MODES
1337 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1338 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1339 cmd |= PCIM_CMD_PORTEN;
1340 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1342 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1343 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1344 cmd |= PCIM_CMD_MEMEN;
1345 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1348 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
1350 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
1354 resource_list_add(rl, type, reg,
1355 base, base + (1 << ln2size) - 1,
1359 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
1360 reg, pci_maptype(base), ln2range,
1361 (unsigned int) base, ln2size);
1364 return (ln2range == 64) ? 2 : 1;
1368 pci_add_resources(device_t pcib, device_t bus, device_t dev)
1370 struct pci_devinfo *dinfo = device_get_ivars(dev);
1371 pcicfgregs *cfg = &dinfo->cfg;
1372 struct resource_list *rl = &dinfo->resources;
1373 struct pci_quirk *q;
1375 #if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1382 for (i = 0; i < cfg->nummaps;) {
1383 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
1386 for (q = &pci_quirks[0]; q->devid; q++) {
1387 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1388 && q->type == PCI_QUIRK_MAP_REG)
1389 pci_add_map(pcib, b, s, f, q->arg1, rl);
1392 if (cfg->intpin > 0 && cfg->intline != 255)
1393 resource_list_add(rl, SYS_RES_IRQ, 0,
1394 cfg->intline, cfg->intline, 1);
1398 pci_add_children(device_t dev, int busno, size_t dinfo_size)
1400 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
1401 device_t pcib = device_get_parent(dev);
1402 struct pci_devinfo *dinfo;
1404 int s, f, pcifunchigh;
1407 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
1409 maxslots = PCIB_MAXSLOTS(pcib);
1411 for (s = 0; s <= maxslots; s++) {
1414 hdrtype = REG(PCIR_HDRTYPE, 1);
1415 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1417 if (hdrtype & PCIM_MFDEV)
1418 pcifunchigh = PCI_FUNCMAX;
1419 for (f = 0; f <= pcifunchigh; f++) {
1420 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
1421 if (dinfo != NULL) {
1422 pci_add_child(dev, dinfo);
1430 * The actual PCI child that we add has a NULL driver whos parent
1431 * device will be "pci". The child contains the ivars, not the parent.
1434 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1438 pcib = device_get_parent(bus);
1439 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1440 device_set_ivars(dinfo->cfg.dev, dinfo);
1441 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1442 pci_print_verbose(dinfo);
1446 * Probe the PCI bus. Note: probe code is not supposed to add children
1450 pci_probe(device_t dev)
1452 device_set_desc(dev, "PCI bus");
1454 /* Allow other subclasses to override this driver */
1459 pci_attach(device_t dev)
1462 int lunit = device_get_unit(dev);
1464 cdevsw_add(&pcicdev, -1, lunit);
1465 make_dev(&pcicdev, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
1468 * Since there can be multiple independantly numbered PCI
1469 * busses on some large alpha systems, we can't use the unit
1470 * number to decide what bus we are probing. We ask the parent
1471 * pcib what our bus number is.
1473 * pcib_get_bus() must act on the pci bus device, not on the pci
1474 * device, because it uses badly hacked nexus-based ivars to
1475 * store and retrieve the physical bus number. XXX
1477 busno = pcib_get_bus(device_get_parent(dev));
1479 device_printf(dev, "pci_attach() physical bus=%d\n", busno);
1481 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1483 return (bus_generic_attach(dev));
1487 pci_print_resources(struct resource_list *rl, const char *name, int type,
1490 struct resource_list_entry *rle;
1491 int printed, retval;
1495 /* Yes, this is kinda cheating */
1496 SLIST_FOREACH(rle, rl, link) {
1497 if (rle->type == type) {
1499 retval += printf(" %s ", name);
1500 else if (printed > 0)
1501 retval += printf(",");
1503 retval += printf(format, rle->start);
1504 if (rle->count > 1) {
1505 retval += printf("-");
1506 retval += printf(format, rle->start +
1515 pci_print_child(device_t dev, device_t child)
1517 struct pci_devinfo *dinfo;
1518 struct resource_list *rl;
1522 dinfo = device_get_ivars(child);
1524 rl = &dinfo->resources;
1526 retval += bus_print_child_header(dev, child);
1528 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1529 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1530 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1531 if (device_get_flags(dev))
1532 retval += printf(" flags %#x", device_get_flags(dev));
1534 retval += printf(" at device %d.%d", pci_get_slot(child),
1535 pci_get_function(child));
1537 retval += bus_print_child_footer(dev, child);
1543 pci_probe_nomatch(device_t dev, device_t child)
1545 struct pci_devinfo *dinfo;
1551 dinfo = device_get_ivars(child);
1553 desc = pci_ata_match(child);
1554 if (!desc) desc = pci_usb_match(child);
1555 if (!desc) desc = pci_vga_match(child);
1556 if (!desc) desc = pci_chip_match(child);
1558 desc = "unknown card";
1561 device_printf(dev, "<%s>", desc);
1562 if (bootverbose || unknown) {
1563 printf(" (vendor=0x%04x, dev=0x%04x)",
1568 pci_get_slot(child),
1569 pci_get_function(child));
1570 if (cfg->intpin > 0 && cfg->intline != 255) {
1571 printf(" irq %d", cfg->intline);
1579 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1581 struct pci_devinfo *dinfo;
1584 dinfo = device_get_ivars(child);
1588 case PCI_IVAR_SUBVENDOR:
1589 *result = cfg->subvendor;
1591 case PCI_IVAR_SUBDEVICE:
1592 *result = cfg->subdevice;
1594 case PCI_IVAR_VENDOR:
1595 *result = cfg->vendor;
1597 case PCI_IVAR_DEVICE:
1598 *result = cfg->device;
1600 case PCI_IVAR_DEVID:
1601 *result = (cfg->device << 16) | cfg->vendor;
1603 case PCI_IVAR_CLASS:
1604 *result = cfg->baseclass;
1606 case PCI_IVAR_SUBCLASS:
1607 *result = cfg->subclass;
1609 case PCI_IVAR_PROGIF:
1610 *result = cfg->progif;
1612 case PCI_IVAR_REVID:
1613 *result = cfg->revid;
1615 case PCI_IVAR_INTPIN:
1616 *result = cfg->intpin;
1619 *result = cfg->intline;
1625 *result = cfg->slot;
1627 case PCI_IVAR_FUNCTION:
1628 *result = cfg->func;
1630 case PCI_IVAR_SECONDARYBUS:
1631 *result = cfg->secondarybus;
1633 case PCI_IVAR_SUBORDINATEBUS:
1634 *result = cfg->subordinatebus;
1636 case PCI_IVAR_ETHADDR:
1638 * The generic accessor doesn't deal with failure, so
1639 * we set the return value, then return an error.
1650 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1652 struct pci_devinfo *dinfo;
1655 dinfo = device_get_ivars(child);
1659 case PCI_IVAR_SUBVENDOR:
1660 case PCI_IVAR_SUBDEVICE:
1661 case PCI_IVAR_VENDOR:
1662 case PCI_IVAR_DEVICE:
1663 case PCI_IVAR_DEVID:
1664 case PCI_IVAR_CLASS:
1665 case PCI_IVAR_SUBCLASS:
1666 case PCI_IVAR_PROGIF:
1667 case PCI_IVAR_REVID:
1668 case PCI_IVAR_INTPIN:
1672 case PCI_IVAR_FUNCTION:
1673 case PCI_IVAR_ETHADDR:
1674 return EINVAL; /* disallow for now */
1676 case PCI_IVAR_SECONDARYBUS:
1677 cfg->secondarybus = value;
1679 case PCI_IVAR_SUBORDINATEBUS:
1680 cfg->subordinatebus = value;
1689 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1690 u_long start, u_long end, u_long count, u_int flags)
1692 struct pci_devinfo *dinfo = device_get_ivars(child);
1693 struct resource_list *rl = &dinfo->resources;
1694 pcicfgregs *cfg = &dinfo->cfg;
1697 * Perform lazy resource allocation
1699 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY
1701 if (device_get_parent(child) == dev) {
1706 * If device doesn't have an interrupt routed, and is
1707 * deserving of an interrupt, try to assign it one.
1709 if ((cfg->intline == 255 || cfg->intline == 0) &&
1710 (cfg->intpin != 0) &&
1711 (start == 0) && (end == ~0UL)) {
1712 cfg->intline = PCIB_ROUTE_INTERRUPT(
1713 device_get_parent(dev), child,
1715 if (cfg->intline != 255) {
1716 pci_write_config(child, PCIR_INTLINE,
1718 resource_list_add(rl, SYS_RES_IRQ, 0,
1719 cfg->intline, cfg->intline, 1);
1724 case SYS_RES_IOPORT:
1725 case SYS_RES_MEMORY:
1726 if (*rid < PCIR_BAR(cfg->nummaps)) {
1728 * Enable the I/O mode. We should
1729 * also be assigning resources too
1730 * when none are present. The
1731 * resource_list_alloc kind of sorta does
1734 if (PCI_ENABLE_IO(dev, child, type))
1740 return resource_list_alloc(rl, dev, child, type, rid,
1741 start, end, count, flags);
1745 pci_release_resource(device_t dev, device_t child, int type, int rid,
1748 struct pci_devinfo *dinfo = device_get_ivars(child);
1749 struct resource_list *rl = &dinfo->resources;
1751 return resource_list_release(rl, dev, child, type, rid, r);
1755 pci_set_resource(device_t dev, device_t child, int type, int rid,
1756 u_long start, u_long count)
1758 struct pci_devinfo *dinfo = device_get_ivars(child);
1759 struct resource_list *rl = &dinfo->resources;
1761 resource_list_add(rl, type, rid, start, start + count - 1, count);
1766 pci_get_resource(device_t dev, device_t child, int type, int rid,
1767 u_long *startp, u_long *countp)
1769 struct pci_devinfo *dinfo = device_get_ivars(child);
1770 struct resource_list *rl = &dinfo->resources;
1771 struct resource_list_entry *rle;
1773 rle = resource_list_find(rl, type, rid);
1778 *startp = rle->start;
1780 *countp = rle->count;
1786 pci_delete_resource(device_t dev, device_t child, int type, int rid)
1788 printf("pci_delete_resource: PCI resources can not be deleted\n");
1791 struct resource_list *
1792 pci_get_resource_list (device_t dev, device_t child)
1794 struct pci_devinfo * dinfo = device_get_ivars(child);
1795 struct resource_list * rl = &dinfo->resources;
1804 pci_read_config_method(device_t dev, device_t child, int reg, int width)
1806 struct pci_devinfo *dinfo = device_get_ivars(child);
1807 pcicfgregs *cfg = &dinfo->cfg;
1809 return PCIB_READ_CONFIG(device_get_parent(dev),
1810 cfg->bus, cfg->slot, cfg->func,
1815 pci_write_config_method(device_t dev, device_t child, int reg,
1816 u_int32_t val, int width)
1818 struct pci_devinfo *dinfo = device_get_ivars(child);
1819 pcicfgregs *cfg = &dinfo->cfg;
1821 PCIB_WRITE_CONFIG(device_get_parent(dev),
1822 cfg->bus, cfg->slot, cfg->func,
1827 pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
1830 struct pci_devinfo *dinfo;
1832 dinfo = device_get_ivars(child);
1833 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
1834 pci_get_function(child));
1839 pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
1842 struct pci_devinfo *dinfo;
1845 dinfo = device_get_ivars(child);
1847 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
1848 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
1849 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
1855 pci_assign_interrupt_method(device_t dev, device_t child)
1857 struct pci_devinfo *dinfo = device_get_ivars(child);
1858 pcicfgregs *cfg = &dinfo->cfg;
1860 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
1865 pci_modevent(module_t mod, int what, void *arg)
1869 STAILQ_INIT(&pci_devq);
1879 pci_resume(device_t dev)
1885 struct pci_devinfo *dinfo;
1888 device_get_children(dev, &children, &numdevs);
1890 for (i = 0; i < numdevs; i++) {
1891 child = children[i];
1893 dinfo = device_get_ivars(child);
1895 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
1896 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
1897 if (PCI_INTERRUPT_VALID(cfg->intline)) {
1898 pci_write_config(child, PCIR_INTLINE,
1904 free(children, M_TEMP);
1906 return (bus_generic_resume(dev));
1909 static device_method_t pci_methods[] = {
1910 /* Device interface */
1911 DEVMETHOD(device_probe, pci_probe),
1912 DEVMETHOD(device_attach, pci_attach),
1913 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1914 DEVMETHOD(device_suspend, bus_generic_suspend),
1915 DEVMETHOD(device_resume, pci_resume),
1918 DEVMETHOD(bus_print_child, pci_print_child),
1919 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
1920 DEVMETHOD(bus_read_ivar, pci_read_ivar),
1921 DEVMETHOD(bus_write_ivar, pci_write_ivar),
1922 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1923 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1924 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1926 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
1927 DEVMETHOD(bus_set_resource, pci_set_resource),
1928 DEVMETHOD(bus_get_resource, pci_get_resource),
1929 DEVMETHOD(bus_delete_resource, pci_delete_resource),
1930 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
1931 DEVMETHOD(bus_release_resource, pci_release_resource),
1932 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1933 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1934 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
1935 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
1938 DEVMETHOD(pci_read_config, pci_read_config_method),
1939 DEVMETHOD(pci_write_config, pci_write_config_method),
1940 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
1941 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
1942 DEVMETHOD(pci_enable_io, pci_enable_io_method),
1943 DEVMETHOD(pci_disable_io, pci_disable_io_method),
1944 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
1945 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
1946 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
1951 static driver_t pci_driver = {
1957 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
1958 MODULE_VERSION(pci, 1);