2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/alc/if_alc.c,v 1.6 2009/09/29 23:03:16 yongari Exp $
31 /* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
39 #include <sys/malloc.h>
41 #include <sys/module.h>
42 #include <sys/spinlock.h>
44 #include <sys/queue.h>
45 #include <sys/socket.h>
46 #include <sys/sockio.h>
47 #include <sys/sysctl.h>
48 #include <sys/taskqueue.h>
52 #include <net/if_arp.h>
53 #include <net/ethernet.h>
54 #include <net/if_dl.h>
55 #include <net/if_llc.h>
56 #include <net/if_media.h>
57 #include <net/if_types.h>
58 #include <net/ifq_var.h>
59 #include <net/vlan/if_vlan_var.h>
60 #include <net/vlan/if_vlan_ether.h>
62 #include <netinet/in.h>
63 #include <netinet/in_systm.h>
64 #include <netinet/ip.h>
65 #include <netinet/tcp.h>
67 #include <dev/netif/mii_layer/mii.h>
68 #include <dev/netif/mii_layer/miivar.h>
70 #include <bus/pci/pcireg.h>
71 #include <bus/pci/pcivar.h>
73 #include <machine/atomic.h>
76 #include <machine/bus.h>
77 #include <machine/in_cksum.h>
80 #include "if_alcreg.h"
81 #include "if_alcvar.h"
83 /* "device miibus" required. See GENERIC if you get errors here. */
84 #include "miibus_if.h"
85 #undef ALC_USE_CUSTOM_CSUM
87 #ifdef ALC_USE_CUSTOM_CSUM
88 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
90 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
92 #ifndef IFCAP_VLAN_HWTSO
93 #define IFCAP_VLAN_HWTSO 0
96 MODULE_DEPEND(alc, pci, 1, 1, 1);
97 MODULE_DEPEND(alc, ether, 1, 1, 1);
98 MODULE_DEPEND(alc, miibus, 1, 1, 1);
101 static int msi_disable = 0;
102 static int msix_disable = 0;
103 TUNABLE_INT("hw.alc.msi_disable", &msi_disable);
104 TUNABLE_INT("hw.alc.msix_disable", &msix_disable);
107 * Devices supported by this driver.
110 static struct alc_ident alc_ident_table[] = {
111 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024,
112 "Atheros AR8131 PCIe Gigabit Ethernet" },
113 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024,
114 "Atheros AR8132 PCIe Fast Ethernet" },
115 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024,
116 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" },
117 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024,
118 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" },
119 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024,
120 "Atheros AR8152 v1.1 PCIe Fast Ethernet" },
121 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024,
122 "Atheros AR8152 v2.0 PCIe Fast Ethernet" },
126 static void alc_aspm(struct alc_softc *, int);
127 static int alc_attach(device_t);
128 static int alc_check_boundary(struct alc_softc *);
129 static int alc_detach(device_t);
130 static void alc_disable_l0s_l1(struct alc_softc *);
131 static int alc_dma_alloc(struct alc_softc *);
132 static void alc_dma_free(struct alc_softc *);
133 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int);
134 static int alc_encap(struct alc_softc *, struct mbuf **);
135 static struct alc_ident *alc_find_ident(device_t);
136 #ifndef __NO_STRICT_ALIGNMENT
138 alc_fixup_rx(struct ifnet *, struct mbuf *);
140 static void alc_get_macaddr(struct alc_softc *);
141 static void alc_init(void *);
142 static void alc_init_cmb(struct alc_softc *);
143 static void alc_init_locked(struct alc_softc *);
144 static void alc_init_rr_ring(struct alc_softc *);
145 static int alc_init_rx_ring(struct alc_softc *);
146 static void alc_init_smb(struct alc_softc *);
147 static void alc_init_tx_ring(struct alc_softc *);
148 static void alc_int_task(void *, int);
149 static void alc_intr(void *);
150 static int alc_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
151 static void alc_mac_config(struct alc_softc *);
152 static int alc_miibus_readreg(device_t, int, int);
153 static void alc_miibus_statchg(device_t);
154 static int alc_miibus_writereg(device_t, int, int, int);
155 static int alc_mediachange(struct ifnet *);
156 static void alc_mediastatus(struct ifnet *, struct ifmediareq *);
157 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *);
158 static void alc_phy_down(struct alc_softc *);
159 static void alc_phy_reset(struct alc_softc *);
160 static int alc_probe(device_t);
161 static void alc_reset(struct alc_softc *);
162 static int alc_resume(device_t);
163 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *);
164 static int alc_rxintr(struct alc_softc *, int);
165 static void alc_rxfilter(struct alc_softc *);
166 static void alc_rxvlan(struct alc_softc *);
168 static void alc_setlinkspeed(struct alc_softc *);
170 static void alc_setwol(struct alc_softc *);
172 static int alc_shutdown(device_t);
173 static void alc_start(struct ifnet *);
174 static void alc_start_queue(struct alc_softc *);
175 static void alc_stats_clear(struct alc_softc *);
176 static void alc_stats_update(struct alc_softc *);
177 static void alc_stop(struct alc_softc *);
178 static void alc_stop_mac(struct alc_softc *);
179 static void alc_stop_queue(struct alc_softc *);
180 static int alc_suspend(device_t);
181 static void alc_sysctl_node(struct alc_softc *);
182 static void alc_tick(void *);
183 static void alc_tx_task(void *, int);
184 static void alc_txeof(struct alc_softc *);
185 static void alc_watchdog(struct alc_softc *);
186 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS);
187 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS);
189 static device_method_t alc_methods[] = {
190 /* Device interface. */
191 DEVMETHOD(device_probe, alc_probe),
192 DEVMETHOD(device_attach, alc_attach),
193 DEVMETHOD(device_detach, alc_detach),
194 DEVMETHOD(device_shutdown, alc_shutdown),
195 DEVMETHOD(device_suspend, alc_suspend),
196 DEVMETHOD(device_resume, alc_resume),
199 DEVMETHOD(miibus_readreg, alc_miibus_readreg),
200 DEVMETHOD(miibus_writereg, alc_miibus_writereg),
201 DEVMETHOD(miibus_statchg, alc_miibus_statchg),
206 static driver_t alc_driver = {
209 sizeof(struct alc_softc)
212 static devclass_t alc_devclass;
214 DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0);
215 DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0);
217 static struct resource_spec alc_res_spec_mem[] = {
218 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
222 static struct resource_spec alc_irq_spec_legacy[] = {
223 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
227 static struct resource_spec alc_irq_spec_msi[] = {
228 { SYS_RES_IRQ, 1, RF_ACTIVE },
232 static struct resource_spec alc_irq_spec_msix[] = {
233 { SYS_RES_IRQ, 1, RF_ACTIVE },
237 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 };
240 alc_miibus_readreg(device_t dev, int phy, int reg)
242 struct alc_softc *sc;
246 sc = device_get_softc(dev);
248 if (phy != sc->alc_phyaddr)
252 * For AR8132 fast ethernet controller, do not report 1000baseT
253 * capability to mii(4). Even though AR8132 uses the same
254 * model/revision number of F1 gigabit PHY, the PHY has no
255 * ability to establish 1000baseT link.
257 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 &&
261 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
262 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
263 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
265 v = CSR_READ_4(sc, ALC_MDIO);
266 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
271 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg);
275 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
279 alc_miibus_writereg(device_t dev, int phy, int reg, int val)
281 struct alc_softc *sc;
285 sc = device_get_softc(dev);
287 if (phy != sc->alc_phyaddr)
290 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
291 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
292 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
293 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
295 v = CSR_READ_4(sc, ALC_MDIO);
296 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
301 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg);
307 alc_miibus_statchg(device_t dev)
309 struct alc_softc *sc;
310 struct mii_data *mii;
314 sc = device_get_softc(dev);
316 mii = device_get_softc(sc->alc_miibus);
318 if (mii == NULL || ifp == NULL ||
319 (ifp->if_flags & IFF_RUNNING) == 0)
322 sc->alc_flags &= ~ALC_FLAG_LINK;
323 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
324 (IFM_ACTIVE | IFM_AVALID)) {
325 switch (IFM_SUBTYPE(mii->mii_media_active)) {
328 sc->alc_flags |= ALC_FLAG_LINK;
331 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
332 sc->alc_flags |= ALC_FLAG_LINK;
339 /* Stop Rx/Tx MACs. */
342 /* Program MACs with resolved speed/duplex/flow-control. */
343 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
346 /* Re-enable Tx/Rx MACs. */
347 reg = CSR_READ_4(sc, ALC_MAC_CFG);
348 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
349 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
351 alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active));
355 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
357 struct alc_softc *sc;
358 struct mii_data *mii;
362 if ((ifp->if_flags & IFF_UP) == 0) {
366 mii = device_get_softc(sc->alc_miibus);
370 ifmr->ifm_status = mii->mii_media_status;
371 ifmr->ifm_active = mii->mii_media_active;
375 alc_mediachange(struct ifnet *ifp)
377 struct alc_softc *sc;
378 struct mii_data *mii;
379 struct mii_softc *miisc;
384 mii = device_get_softc(sc->alc_miibus);
385 if (mii->mii_instance != 0) {
386 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
387 mii_phy_reset(miisc);
389 error = mii_mediachg(mii);
395 static struct alc_ident *
396 alc_find_ident(device_t dev)
398 struct alc_ident *ident;
399 uint16_t vendor, devid;
401 vendor = pci_get_vendor(dev);
402 devid = pci_get_device(dev);
403 for (ident = alc_ident_table; ident->name != NULL; ident++) {
404 if (vendor == ident->vendorid && devid == ident->deviceid)
411 alc_probe(device_t dev)
413 struct alc_ident *ident;
415 ident = alc_find_ident(dev);
417 device_set_desc(dev, ident->name);
418 return (BUS_PROBE_DEFAULT);
424 alc_get_macaddr(struct alc_softc *sc)
431 opt = CSR_READ_4(sc, ALC_OPT_CFG);
432 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&
433 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
435 * EEPROM found, let TWSI reload EEPROM configuration.
436 * This will set ethernet address of controller.
439 switch (sc->alc_ident->deviceid) {
440 case DEVICEID_ATHEROS_AR8131:
441 case DEVICEID_ATHEROS_AR8132:
442 if ((opt & OPT_CFG_CLK_ENB) == 0) {
443 opt |= OPT_CFG_CLK_ENB;
444 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
445 CSR_READ_4(sc, ALC_OPT_CFG);
449 case DEVICEID_ATHEROS_AR8151:
450 case DEVICEID_ATHEROS_AR8151_V2:
451 case DEVICEID_ATHEROS_AR8152_B:
452 case DEVICEID_ATHEROS_AR8152_B2:
453 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
454 ALC_MII_DBG_ADDR, 0x00);
455 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
457 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
458 ALC_MII_DBG_DATA, val & 0xFF7F);
459 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
460 ALC_MII_DBG_ADDR, 0x3B);
461 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
463 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
464 ALC_MII_DBG_DATA, val | 0x0008);
469 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
470 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
471 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
472 CSR_READ_4(sc, ALC_WOL_CFG);
474 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |
475 TWSI_CFG_SW_LD_START);
477 for (i = 100; i > 0; i--) {
479 if ((CSR_READ_4(sc, ALC_TWSI_CFG) &
480 TWSI_CFG_SW_LD_START) == 0)
484 device_printf(sc->alc_dev,
485 "reloading EEPROM timeout!\n");
488 device_printf(sc->alc_dev, "EEPROM not found!\n");
492 switch (sc->alc_ident->deviceid) {
493 case DEVICEID_ATHEROS_AR8131:
494 case DEVICEID_ATHEROS_AR8132:
495 if ((opt & OPT_CFG_CLK_ENB) != 0) {
496 opt &= ~OPT_CFG_CLK_ENB;
497 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
498 CSR_READ_4(sc, ALC_OPT_CFG);
502 case DEVICEID_ATHEROS_AR8151:
503 case DEVICEID_ATHEROS_AR8151_V2:
504 case DEVICEID_ATHEROS_AR8152_B:
505 case DEVICEID_ATHEROS_AR8152_B2:
506 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
507 ALC_MII_DBG_ADDR, 0x00);
508 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
510 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
511 ALC_MII_DBG_DATA, val | 0x0080);
512 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
513 ALC_MII_DBG_ADDR, 0x3B);
514 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
516 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
517 ALC_MII_DBG_DATA, val & 0xFFF7);
523 ea[0] = CSR_READ_4(sc, ALC_PAR0);
524 ea[1] = CSR_READ_4(sc, ALC_PAR1);
525 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF;
526 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF;
527 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF;
528 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF;
529 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF;
530 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF;
534 alc_disable_l0s_l1(struct alc_softc *sc)
538 /* Another magic from vendor. */
539 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
540 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 |
541 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK |
542 PM_CFG_SERDES_PD_EX_L1);
543 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB |
544 PM_CFG_SERDES_L1_ENB;
545 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
549 alc_phy_reset(struct alc_softc *sc)
553 /* Reset magic from Linux. */
554 CSR_WRITE_2(sc, ALC_GPHY_CFG,
555 GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET);
556 CSR_READ_2(sc, ALC_GPHY_CFG);
559 CSR_WRITE_2(sc, ALC_GPHY_CFG,
560 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
561 GPHY_CFG_SEL_ANA_RESET);
562 CSR_READ_2(sc, ALC_GPHY_CFG);
565 /* DSP fixup, Vendor magic. */
566 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) {
567 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
568 ALC_MII_DBG_ADDR, 0x000A);
569 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
571 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
572 ALC_MII_DBG_DATA, data & 0xDFFF);
574 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
575 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
576 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
577 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) {
578 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
579 ALC_MII_DBG_ADDR, 0x003B);
580 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
582 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
583 ALC_MII_DBG_DATA, data & 0xFFF7);
586 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) {
587 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
588 ALC_MII_DBG_ADDR, 0x0029);
589 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
590 ALC_MII_DBG_DATA, 0x929D);
592 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 ||
593 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 ||
594 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
595 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) {
596 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
597 ALC_MII_DBG_ADDR, 0x0029);
598 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
599 ALC_MII_DBG_DATA, 0xB6DD);
602 /* Load DSP codes, vendor magic. */
603 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
604 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK);
605 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
606 ALC_MII_DBG_ADDR, MII_ANA_CFG18);
607 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
608 ALC_MII_DBG_DATA, data);
610 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) |
611 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL |
613 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
614 ALC_MII_DBG_ADDR, MII_ANA_CFG5);
615 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
616 ALC_MII_DBG_DATA, data);
618 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) &
619 ANA_LONG_CABLE_TH_100_MASK) |
620 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) &
621 ANA_SHORT_CABLE_TH_100_SHIFT) |
622 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW;
623 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
624 ALC_MII_DBG_ADDR, MII_ANA_CFG54);
625 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
626 ALC_MII_DBG_DATA, data);
628 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) |
629 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) |
630 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) |
631 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK);
632 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
633 ALC_MII_DBG_ADDR, MII_ANA_CFG4);
634 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
635 ALC_MII_DBG_DATA, data);
637 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) |
638 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB |
640 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
641 ALC_MII_DBG_ADDR, MII_ANA_CFG0);
642 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
643 ALC_MII_DBG_DATA, data);
648 alc_phy_down(struct alc_softc *sc)
650 switch (sc->alc_ident->deviceid) {
651 case DEVICEID_ATHEROS_AR8151:
652 case DEVICEID_ATHEROS_AR8151_V2:
654 * GPHY power down caused more problems on AR8151 v2.0.
655 * When driver is reloaded after GPHY power down,
656 * accesses to PHY/MAC registers hung the system. Only
657 * cold boot recovered from it. I'm not sure whether
658 * AR8151 v1.0 also requires this one though. I don't
659 * have AR8151 v1.0 controller in hand.
660 * The only option left is to isolate the PHY and
661 * initiates power down the PHY which in turn saves
662 * more power when driver is unloaded.
664 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
665 MII_BMCR, BMCR_ISO | BMCR_PDOWN);
668 /* Force PHY down. */
669 CSR_WRITE_2(sc, ALC_GPHY_CFG,
670 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
671 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ |
680 alc_aspm(struct alc_softc *sc, int media)
687 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
688 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) ==
689 (ALC_FLAG_APS | ALC_FLAG_PCIE)) {
690 linkcfg = CSR_READ_2(sc, sc->alc_expcap +
691 PCIR_EXPRESS_LINK_CTL);
696 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1;
697 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK);
698 pmcfg |= PM_CFG_MAC_ASPM_CHK;
699 pmcfg |= PM_CFG_SERDES_ENB | PM_CFG_RBER_ENB;
700 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
702 if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
703 /* Disable extended sync except AR8152 B v1.0 */
705 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B &&
706 sc->alc_rev == ATHEROS_AR8152_B_V10)
708 CSR_WRITE_2(sc, sc->alc_expcap + PCIR_EXPRESS_LINK_CTL,
710 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB |
712 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT <<
713 PM_CFG_L1_ENTRY_TIMER_SHIFT);
714 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK;
715 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT <<
716 PM_CFG_PM_REQ_TIMER_SHIFT);
717 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV;
720 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
721 if ((sc->alc_flags & ALC_FLAG_L0S) != 0)
722 pmcfg |= PM_CFG_ASPM_L0S_ENB;
723 if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
724 pmcfg |= PM_CFG_ASPM_L1_ENB;
725 if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
726 if (sc->alc_ident->deviceid ==
727 DEVICEID_ATHEROS_AR8152_B) {
728 pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
730 pmcfg &= ~(PM_CFG_SERDES_L1_ENB |
731 PM_CFG_SERDES_PLL_L1_ENB |
732 PM_CFG_SERDES_BUDS_RX_L1_ENB);
733 pmcfg |= PM_CFG_CLK_SWH_L1;
734 if (media == IFM_100_TX || media == IFM_1000_T) {
735 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
736 switch (sc->alc_ident->deviceid) {
737 case DEVICEID_ATHEROS_AR8152_B:
739 PM_CFG_L1_ENTRY_TIMER_SHIFT);
741 case DEVICEID_ATHEROS_AR8152_B2:
742 case DEVICEID_ATHEROS_AR8151_V2:
744 PM_CFG_L1_ENTRY_TIMER_SHIFT);
748 PM_CFG_L1_ENTRY_TIMER_SHIFT);
753 pmcfg |= PM_CFG_SERDES_L1_ENB |
754 PM_CFG_SERDES_PLL_L1_ENB |
755 PM_CFG_SERDES_BUDS_RX_L1_ENB;
756 pmcfg &= ~(PM_CFG_CLK_SWH_L1 |
757 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
760 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB |
761 PM_CFG_SERDES_PLL_L1_ENB);
762 pmcfg |= PM_CFG_CLK_SWH_L1;
763 if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
764 pmcfg |= PM_CFG_ASPM_L1_ENB;
766 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
770 alc_attach(device_t dev)
772 struct alc_softc *sc;
774 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" };
776 int base, error, i, msic, msixc, state;
777 uint32_t cap, ctl, val;
780 sc = device_get_softc(dev);
783 lockinit(&sc->alc_lock, "alc_lock", 0, LK_CANRECURSE);
784 callout_init_mp(&sc->alc_tick_ch);
785 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc);
786 sc->alc_ident = alc_find_ident(dev);
788 /* Map the device. */
789 pci_enable_busmaster(dev);
790 sc->alc_res_spec = alc_res_spec_mem;
791 sc->alc_irq_spec = alc_irq_spec_legacy;
792 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res);
794 device_printf(dev, "cannot allocate memory resources.\n");
798 /* Set PHY address. */
799 sc->alc_phyaddr = ALC_PHY_ADDR;
801 /* Initialize DMA parameters. */
802 sc->alc_dma_rd_burst = 0;
803 sc->alc_dma_wr_burst = 0;
804 sc->alc_rcb = DMA_CFG_RCB_64;
805 if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) {
806 sc->alc_flags |= ALC_FLAG_PCIE;
807 sc->alc_expcap = base;
808 burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL);
809 sc->alc_dma_rd_burst =
810 (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12;
811 sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5;
813 device_printf(dev, "Read request size : %u bytes.\n",
814 alc_dma_burst[sc->alc_dma_rd_burst]);
815 device_printf(dev, "TLP payload size : %u bytes.\n",
816 alc_dma_burst[sc->alc_dma_wr_burst]);
818 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024)
819 sc->alc_dma_rd_burst = 3;
820 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024)
821 sc->alc_dma_wr_burst = 3;
822 /* Clear data link and flow-control protocol error. */
823 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
824 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP);
825 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
826 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
827 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
828 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC,
829 CSR_READ_4(sc, ALC_PCIE_PHYMISC) |
830 PCIE_PHYMISC_FORCE_RCV_DET);
831 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B &&
832 sc->alc_rev == ATHEROS_AR8152_B_V10) {
833 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2);
834 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK |
835 PCIE_PHYMISC2_SERDES_TH_MASK);
836 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT;
837 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT;
838 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val);
841 /* Disable ASPM L0S and L1. */
842 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP);
843 if ((cap & PCIM_LINK_CAP_ASPM) != 0) {
844 ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL);
845 if ((ctl & 0x08) != 0)
846 sc->alc_rcb = DMA_CFG_RCB_128;
848 device_printf(dev, "RCB %u bytes\n",
849 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128);
852 sc->alc_flags |= ALC_FLAG_L0S;
854 sc->alc_flags |= ALC_FLAG_L1S;
856 device_printf(sc->alc_dev, "ASPM %s %s\n",
858 state == 0 ? "disabled" : "enabled");
859 alc_disable_l0s_l1(sc);
862 device_printf(sc->alc_dev, "no ASPM support\n");
869 /* Reset the ethernet controller. */
873 * One odd thing is AR8132 uses the same PHY hardware(F1
874 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports
875 * the PHY supports 1000Mbps but that's not true. The PHY
876 * used in AR8132 can't establish gigabit link even if it
877 * shows the same PHY model/revision number of AR8131.
879 switch (sc->alc_ident->deviceid) {
880 case DEVICEID_ATHEROS_AR8152_B:
881 case DEVICEID_ATHEROS_AR8152_B2:
882 sc->alc_flags |= ALC_FLAG_APS;
884 case DEVICEID_ATHEROS_AR8132:
885 sc->alc_flags |= ALC_FLAG_FASTETHER;
887 case DEVICEID_ATHEROS_AR8151:
888 case DEVICEID_ATHEROS_AR8151_V2:
889 sc->alc_flags |= ALC_FLAG_APS;
894 sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO;
897 * It seems that AR813x/AR815x has silicon bug for SMB. In
898 * addition, Atheros said that enabling SMB wouldn't improve
899 * performance. However I think it's bad to access lots of
900 * registers to extract MAC statistics.
902 sc->alc_flags |= ALC_FLAG_SMB_BUG;
905 * Don't use Tx CMB. It is known to have silicon bug.
907 sc->alc_flags |= ALC_FLAG_CMB_BUG;
908 sc->alc_rev = pci_get_revid(dev);
909 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >>
910 MASTER_CHIP_REV_SHIFT;
912 device_printf(dev, "PCI device revision : 0x%04x\n",
914 device_printf(dev, "Chip id/revision : 0x%04x\n",
917 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n",
918 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8,
919 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8);
921 /* Allocate IRQ resources. */
922 msixc = pci_msix_count(dev);
923 msic = pci_msi_count(dev);
925 device_printf(dev, "MSIX count : %d\n", msixc);
926 device_printf(dev, "MSI count : %d\n", msic);
928 /* Prefer MSIX over MSI. */
929 if (msix_disable == 0 || msi_disable == 0) {
930 if (msix_disable == 0 && msixc == ALC_MSIX_MESSAGES &&
931 pci_alloc_msix(dev, &msixc) == 0) {
932 if (msic == ALC_MSIX_MESSAGES) {
934 "Using %d MSIX message(s).\n", msixc);
935 sc->alc_flags |= ALC_FLAG_MSIX;
936 sc->alc_irq_spec = alc_irq_spec_msix;
938 pci_release_msi(dev);
940 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 &&
941 msic == ALC_MSI_MESSAGES &&
942 pci_alloc_msi(dev, &msic) == 0) {
943 if (msic == ALC_MSI_MESSAGES) {
945 "Using %d MSI message(s).\n", msic);
946 sc->alc_flags |= ALC_FLAG_MSI;
947 sc->alc_irq_spec = alc_irq_spec_msi;
949 pci_release_msi(dev);
953 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq);
955 device_printf(dev, "cannot allocate IRQ resources.\n");
959 /* Create device sysctl node. */
962 if ((error = alc_dma_alloc(sc) != 0))
965 /* Load station address. */
968 ifp = sc->alc_ifp = &sc->arpcom.ac_if;
970 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
971 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
972 ifp->if_ioctl = alc_ioctl;
973 ifp->if_start = alc_start;
974 ifp->if_init = alc_init;
975 ifp->if_snd.ifq_maxlen = ALC_TX_RING_CNT - 1;
976 ifq_set_maxlen(&ifp->if_snd, ifp->if_snd.ifq_maxlen);
977 ifq_set_ready(&ifp->if_snd);
978 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4;
979 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO;
982 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
983 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
984 sc->alc_flags |= ALC_FLAG_PM;
985 sc->alc_pmcap = base;
988 ifp->if_capenable = ifp->if_capabilities;
990 /* Set up MII bus. */
991 if ((error = mii_phy_probe(dev, &sc->alc_miibus, alc_mediachange,
992 alc_mediastatus)) != 0) {
993 device_printf(dev, "no PHY found!\n");
997 ether_ifattach(ifp, sc->alc_eaddr, NULL);
999 /* VLAN capability setup. */
1000 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1001 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM;
1002 ifp->if_capenable = ifp->if_capabilities;
1005 * It seems enabling Tx checksum offloading makes more trouble.
1006 * Sometimes the controller does not receive any frames when
1007 * Tx checksum offloading is enabled. I'm not sure whether this
1008 * is a bug in Tx checksum offloading logic or I got broken
1009 * sample boards. To safety, don't enable Tx checksum offloading
1010 * by default but give chance to users to toggle it if they know
1011 * their controllers work without problems.
1013 ifp->if_capenable &= ~IFCAP_TXCSUM;
1014 ifp->if_hwassist &= ~ALC_CSUM_FEATURES;
1016 /* Tell the upper layer(s) we support long frames. */
1017 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1019 /* Create local taskq. */
1020 TASK_INIT(&sc->alc_tx_task, 1, alc_tx_task, ifp);
1021 sc->alc_tq = taskqueue_create("alc_taskq", M_WAITOK,
1022 taskqueue_thread_enqueue, &sc->alc_tq);
1023 if (sc->alc_tq == NULL) {
1024 device_printf(dev, "could not create taskqueue.\n");
1025 ether_ifdetach(ifp);
1029 taskqueue_start_threads(&sc->alc_tq, 1, TDPRI_KERN_DAEMON, -1, "%s taskq",
1030 device_get_nameunit(sc->alc_dev));
1032 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
1033 msic = ALC_MSIX_MESSAGES;
1034 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
1035 msic = ALC_MSI_MESSAGES;
1038 for (i = 0; i < msic; i++) {
1039 error = bus_setup_intr(dev, sc->alc_irq[i], INTR_MPSAFE,
1041 &sc->alc_intrhand[i], NULL);
1046 device_printf(dev, "could not set up interrupt handler.\n");
1047 taskqueue_free(sc->alc_tq);
1049 ether_ifdetach(ifp);
1061 alc_detach(device_t dev)
1063 struct alc_softc *sc;
1067 sc = device_get_softc(dev);
1070 if (device_is_attached(dev)) {
1072 sc->alc_flags |= ALC_FLAG_DETACH;
1077 callout_drain(&sc->alc_tick_ch);
1079 taskqueue_drain(sc->alc_tq, &sc->alc_int_task);
1080 taskqueue_drain(sc->alc_tq, &sc->alc_tx_task);
1081 ether_ifdetach(ifp);
1084 if (sc->alc_tq != NULL) {
1085 taskqueue_drain(sc->alc_tq, &sc->alc_int_task);
1086 taskqueue_free(sc->alc_tq);
1090 if (sc->alc_miibus != NULL) {
1091 device_delete_child(dev, sc->alc_miibus);
1092 sc->alc_miibus = NULL;
1094 bus_generic_detach(dev);
1098 // XXX? if_free(ifp);
1102 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
1103 msic = ALC_MSIX_MESSAGES;
1104 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
1105 msic = ALC_MSI_MESSAGES;
1108 for (i = 0; i < msic; i++) {
1109 if (sc->alc_intrhand[i] != NULL) {
1110 bus_teardown_intr(dev, sc->alc_irq[i],
1111 sc->alc_intrhand[i]);
1112 sc->alc_intrhand[i] = NULL;
1115 if (sc->alc_res[0] != NULL)
1117 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq);
1118 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0)
1119 pci_release_msi(dev);
1120 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res);
1121 lockuninit(&sc->alc_lock);
1126 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \
1127 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
1128 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \
1129 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
1132 alc_sysctl_node(struct alc_softc *sc)
1134 struct sysctl_ctx_list *ctx;
1135 struct sysctl_oid *tree;
1136 struct sysctl_oid_list *child, *parent;
1137 struct alc_hw_stats *stats;
1140 stats = &sc->alc_stats;
1141 ctx = &sc->alc_sysctl_ctx;
1142 sysctl_ctx_init(ctx);
1144 tree = SYSCTL_ADD_NODE(ctx, SYSCTL_STATIC_CHILDREN(_hw),
1146 device_get_nameunit(sc->alc_dev),
1149 device_printf(sc->alc_dev, "can't add sysctl node\n");
1152 child = SYSCTL_CHILDREN(tree);
1154 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
1155 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0,
1156 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation");
1157 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
1158 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0,
1159 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation");
1160 /* Pull in device tunables. */
1161 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT;
1162 error = resource_int_value(device_get_name(sc->alc_dev),
1163 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod);
1165 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN ||
1166 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) {
1167 device_printf(sc->alc_dev, "int_rx_mod value out of "
1168 "range; using default: %d\n",
1169 ALC_IM_RX_TIMER_DEFAULT);
1170 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT;
1173 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT;
1174 error = resource_int_value(device_get_name(sc->alc_dev),
1175 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod);
1177 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN ||
1178 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) {
1179 device_printf(sc->alc_dev, "int_tx_mod value out of "
1180 "range; using default: %d\n",
1181 ALC_IM_TX_TIMER_DEFAULT);
1182 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT;
1185 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
1186 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0,
1187 sysctl_hw_alc_proc_limit, "I",
1188 "max number of Rx events to process");
1189 /* Pull in device tunables. */
1190 sc->alc_process_limit = ALC_PROC_DEFAULT;
1191 error = resource_int_value(device_get_name(sc->alc_dev),
1192 device_get_unit(sc->alc_dev), "process_limit",
1193 &sc->alc_process_limit);
1195 if (sc->alc_process_limit < ALC_PROC_MIN ||
1196 sc->alc_process_limit > ALC_PROC_MAX) {
1197 device_printf(sc->alc_dev,
1198 "process_limit value out of range; "
1199 "using default: %d\n", ALC_PROC_DEFAULT);
1200 sc->alc_process_limit = ALC_PROC_DEFAULT;
1204 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
1205 NULL, "ALC statistics");
1206 parent = SYSCTL_CHILDREN(tree);
1208 /* Rx statistics. */
1209 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
1210 NULL, "Rx MAC statistics");
1211 child = SYSCTL_CHILDREN(tree);
1212 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1213 &stats->rx_frames, "Good frames");
1214 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
1215 &stats->rx_bcast_frames, "Good broadcast frames");
1216 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
1217 &stats->rx_mcast_frames, "Good multicast frames");
1218 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
1219 &stats->rx_pause_frames, "Pause control frames");
1220 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
1221 &stats->rx_control_frames, "Control frames");
1222 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
1223 &stats->rx_crcerrs, "CRC errors");
1224 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
1225 &stats->rx_lenerrs, "Frames with length mismatched");
1226 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
1227 &stats->rx_bytes, "Good octets");
1228 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
1229 &stats->rx_bcast_bytes, "Good broadcast octets");
1230 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
1231 &stats->rx_mcast_bytes, "Good multicast octets");
1232 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts",
1233 &stats->rx_runts, "Too short frames");
1234 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments",
1235 &stats->rx_fragments, "Fragmented frames");
1236 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
1237 &stats->rx_pkts_64, "64 bytes frames");
1238 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
1239 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
1240 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
1241 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
1242 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
1243 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
1244 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
1245 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
1246 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
1247 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
1248 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
1249 &stats->rx_pkts_1519_max, "1519 to max frames");
1250 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
1251 &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
1252 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
1253 &stats->rx_fifo_oflows, "FIFO overflows");
1254 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
1255 &stats->rx_rrs_errs, "Return status write-back errors");
1256 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
1257 &stats->rx_alignerrs, "Alignment errors");
1258 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered",
1259 &stats->rx_pkts_filtered,
1260 "Frames dropped due to address filtering");
1262 /* Tx statistics. */
1263 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
1264 NULL, "Tx MAC statistics");
1265 child = SYSCTL_CHILDREN(tree);
1266 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1267 &stats->tx_frames, "Good frames");
1268 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
1269 &stats->tx_bcast_frames, "Good broadcast frames");
1270 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
1271 &stats->tx_mcast_frames, "Good multicast frames");
1272 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
1273 &stats->tx_pause_frames, "Pause control frames");
1274 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
1275 &stats->tx_control_frames, "Control frames");
1276 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
1277 &stats->tx_excess_defer, "Frames with excessive derferrals");
1278 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers",
1279 &stats->tx_excess_defer, "Frames with derferrals");
1280 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
1281 &stats->tx_bytes, "Good octets");
1282 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
1283 &stats->tx_bcast_bytes, "Good broadcast octets");
1284 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
1285 &stats->tx_mcast_bytes, "Good multicast octets");
1286 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
1287 &stats->tx_pkts_64, "64 bytes frames");
1288 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
1289 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
1290 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
1291 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
1292 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
1293 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
1294 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
1295 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
1296 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
1297 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
1298 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
1299 &stats->tx_pkts_1519_max, "1519 to max frames");
1300 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
1301 &stats->tx_single_colls, "Single collisions");
1302 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
1303 &stats->tx_multi_colls, "Multiple collisions");
1304 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
1305 &stats->tx_late_colls, "Late collisions");
1306 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
1307 &stats->tx_excess_colls, "Excessive collisions");
1308 ALC_SYSCTL_STAT_ADD32(ctx, child, "abort",
1309 &stats->tx_abort, "Aborted frames due to Excessive collisions");
1310 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns",
1311 &stats->tx_underrun, "FIFO underruns");
1312 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
1313 &stats->tx_desc_underrun, "Descriptor write-back errors");
1314 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
1315 &stats->tx_lenerrs, "Frames with length mismatched");
1316 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
1317 &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
1320 #undef ALC_SYSCTL_STAT_ADD32
1321 #undef ALC_SYSCTL_STAT_ADD64
1323 struct alc_dmamap_arg {
1324 bus_addr_t alc_busaddr;
1328 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1330 struct alc_dmamap_arg *ctx;
1335 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1337 ctx = (struct alc_dmamap_arg *)arg;
1338 ctx->alc_busaddr = segs[0].ds_addr;
1342 * Normal and high Tx descriptors shares single Tx high address.
1343 * Four Rx descriptor/return rings and CMB shares the same Rx
1347 alc_check_boundary(struct alc_softc *sc)
1349 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end;
1351 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ;
1352 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ;
1353 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ;
1354 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ;
1356 /* 4GB boundary crossing is not allowed. */
1357 if ((ALC_ADDR_HI(rx_ring_end) !=
1358 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) ||
1359 (ALC_ADDR_HI(rr_ring_end) !=
1360 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) ||
1361 (ALC_ADDR_HI(cmb_end) !=
1362 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) ||
1363 (ALC_ADDR_HI(tx_ring_end) !=
1364 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr)))
1367 * Make sure Rx return descriptor/Rx descriptor/CMB use
1368 * the same high address.
1370 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) ||
1371 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end)))
1378 alc_dma_alloc(struct alc_softc *sc)
1380 struct alc_txdesc *txd;
1381 struct alc_rxdesc *rxd;
1383 struct alc_dmamap_arg ctx;
1386 lowaddr = BUS_SPACE_MAXADDR;
1388 /* Create parent DMA tag. */
1389 error = bus_dma_tag_create(
1390 sc->alc_cdata.alc_parent_tag, /* parent */
1391 1, 0, /* alignment, boundary */
1392 lowaddr, /* lowaddr */
1393 BUS_SPACE_MAXADDR, /* highaddr */
1394 NULL, NULL, /* filter, filterarg */
1395 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1397 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1399 &sc->alc_cdata.alc_parent_tag);
1401 device_printf(sc->alc_dev,
1402 "could not create parent DMA tag.\n");
1406 /* Create DMA tag for Tx descriptor ring. */
1407 error = bus_dma_tag_create(
1408 sc->alc_cdata.alc_parent_tag, /* parent */
1409 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */
1410 BUS_SPACE_MAXADDR, /* lowaddr */
1411 BUS_SPACE_MAXADDR, /* highaddr */
1412 NULL, NULL, /* filter, filterarg */
1413 ALC_TX_RING_SZ, /* maxsize */
1415 ALC_TX_RING_SZ, /* maxsegsize */
1417 &sc->alc_cdata.alc_tx_ring_tag);
1419 device_printf(sc->alc_dev,
1420 "could not create Tx ring DMA tag.\n");
1424 /* Create DMA tag for Rx free descriptor ring. */
1425 error = bus_dma_tag_create(
1426 sc->alc_cdata.alc_parent_tag, /* parent */
1427 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */
1428 BUS_SPACE_MAXADDR, /* lowaddr */
1429 BUS_SPACE_MAXADDR, /* highaddr */
1430 NULL, NULL, /* filter, filterarg */
1431 ALC_RX_RING_SZ, /* maxsize */
1433 ALC_RX_RING_SZ, /* maxsegsize */
1435 &sc->alc_cdata.alc_rx_ring_tag);
1437 device_printf(sc->alc_dev,
1438 "could not create Rx ring DMA tag.\n");
1441 /* Create DMA tag for Rx return descriptor ring. */
1442 error = bus_dma_tag_create(
1443 sc->alc_cdata.alc_parent_tag, /* parent */
1444 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */
1445 BUS_SPACE_MAXADDR, /* lowaddr */
1446 BUS_SPACE_MAXADDR, /* highaddr */
1447 NULL, NULL, /* filter, filterarg */
1448 ALC_RR_RING_SZ, /* maxsize */
1450 ALC_RR_RING_SZ, /* maxsegsize */
1452 &sc->alc_cdata.alc_rr_ring_tag);
1454 device_printf(sc->alc_dev,
1455 "could not create Rx return ring DMA tag.\n");
1459 /* Create DMA tag for coalescing message block. */
1460 error = bus_dma_tag_create(
1461 sc->alc_cdata.alc_parent_tag, /* parent */
1462 ALC_CMB_ALIGN, 0, /* alignment, boundary */
1463 BUS_SPACE_MAXADDR, /* lowaddr */
1464 BUS_SPACE_MAXADDR, /* highaddr */
1465 NULL, NULL, /* filter, filterarg */
1466 ALC_CMB_SZ, /* maxsize */
1468 ALC_CMB_SZ, /* maxsegsize */
1470 &sc->alc_cdata.alc_cmb_tag);
1472 device_printf(sc->alc_dev,
1473 "could not create CMB DMA tag.\n");
1476 /* Create DMA tag for status message block. */
1477 error = bus_dma_tag_create(
1478 sc->alc_cdata.alc_parent_tag, /* parent */
1479 ALC_SMB_ALIGN, 0, /* alignment, boundary */
1480 BUS_SPACE_MAXADDR, /* lowaddr */
1481 BUS_SPACE_MAXADDR, /* highaddr */
1482 NULL, NULL, /* filter, filterarg */
1483 ALC_SMB_SZ, /* maxsize */
1485 ALC_SMB_SZ, /* maxsegsize */
1487 &sc->alc_cdata.alc_smb_tag);
1489 device_printf(sc->alc_dev,
1490 "could not create SMB DMA tag.\n");
1494 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1495 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag,
1496 (void **)&sc->alc_rdata.alc_tx_ring,
1497 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1498 &sc->alc_cdata.alc_tx_ring_map);
1500 device_printf(sc->alc_dev,
1501 "could not allocate DMA'able memory for Tx ring.\n");
1504 ctx.alc_busaddr = 0;
1505 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag,
1506 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring,
1507 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0);
1508 if (error != 0 || ctx.alc_busaddr == 0) {
1509 device_printf(sc->alc_dev,
1510 "could not load DMA'able memory for Tx ring.\n");
1513 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr;
1515 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1516 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag,
1517 (void **)&sc->alc_rdata.alc_rx_ring,
1518 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1519 &sc->alc_cdata.alc_rx_ring_map);
1521 device_printf(sc->alc_dev,
1522 "could not allocate DMA'able memory for Rx ring.\n");
1525 ctx.alc_busaddr = 0;
1526 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag,
1527 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring,
1528 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0);
1529 if (error != 0 || ctx.alc_busaddr == 0) {
1530 device_printf(sc->alc_dev,
1531 "could not load DMA'able memory for Rx ring.\n");
1534 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr;
1536 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */
1537 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag,
1538 (void **)&sc->alc_rdata.alc_rr_ring,
1539 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1540 &sc->alc_cdata.alc_rr_ring_map);
1542 device_printf(sc->alc_dev,
1543 "could not allocate DMA'able memory for Rx return ring.\n");
1546 ctx.alc_busaddr = 0;
1547 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag,
1548 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring,
1549 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0);
1550 if (error != 0 || ctx.alc_busaddr == 0) {
1551 device_printf(sc->alc_dev,
1552 "could not load DMA'able memory for Tx ring.\n");
1555 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr;
1557 /* Allocate DMA'able memory and load the DMA map for CMB. */
1558 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag,
1559 (void **)&sc->alc_rdata.alc_cmb,
1560 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1561 &sc->alc_cdata.alc_cmb_map);
1563 device_printf(sc->alc_dev,
1564 "could not allocate DMA'able memory for CMB.\n");
1567 ctx.alc_busaddr = 0;
1568 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag,
1569 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb,
1570 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0);
1571 if (error != 0 || ctx.alc_busaddr == 0) {
1572 device_printf(sc->alc_dev,
1573 "could not load DMA'able memory for CMB.\n");
1576 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr;
1578 /* Allocate DMA'able memory and load the DMA map for SMB. */
1579 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag,
1580 (void **)&sc->alc_rdata.alc_smb,
1581 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1582 &sc->alc_cdata.alc_smb_map);
1584 device_printf(sc->alc_dev,
1585 "could not allocate DMA'able memory for SMB.\n");
1588 ctx.alc_busaddr = 0;
1589 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag,
1590 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb,
1591 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0);
1592 if (error != 0 || ctx.alc_busaddr == 0) {
1593 device_printf(sc->alc_dev,
1594 "could not load DMA'able memory for CMB.\n");
1597 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr;
1599 /* Make sure we've not crossed 4GB boundary. */
1600 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1601 (error = alc_check_boundary(sc)) != 0) {
1602 device_printf(sc->alc_dev, "4GB boundary crossed, "
1603 "switching to 32bit DMA addressing mode.\n");
1606 * Limit max allowable DMA address space to 32bit
1609 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1614 * Create Tx buffer parent tag.
1615 * AR813x/AR815x allows 64bit DMA addressing of Tx/Rx buffers
1616 * so it needs separate parent DMA tag as parent DMA address
1617 * space could be restricted to be within 32bit address space
1618 * by 4GB boundary crossing.
1620 error = bus_dma_tag_create(
1621 sc->alc_cdata.alc_parent_tag, /* parent */
1622 1, 0, /* alignment, boundary */
1623 BUS_SPACE_MAXADDR, /* lowaddr */
1624 BUS_SPACE_MAXADDR, /* highaddr */
1625 NULL, NULL, /* filter, filterarg */
1626 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1628 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1630 &sc->alc_cdata.alc_buffer_tag);
1632 device_printf(sc->alc_dev,
1633 "could not create parent buffer DMA tag.\n");
1637 /* Create DMA tag for Tx buffers. */
1638 error = bus_dma_tag_create(
1639 sc->alc_cdata.alc_buffer_tag, /* parent */
1640 1, 0, /* alignment, boundary */
1641 BUS_SPACE_MAXADDR, /* lowaddr */
1642 BUS_SPACE_MAXADDR, /* highaddr */
1643 NULL, NULL, /* filter, filterarg */
1644 ALC_TSO_MAXSIZE, /* maxsize */
1645 ALC_MAXTXSEGS, /* nsegments */
1646 ALC_TSO_MAXSEGSIZE, /* maxsegsize */
1648 &sc->alc_cdata.alc_tx_tag);
1650 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n");
1654 /* Create DMA tag for Rx buffers. */
1655 error = bus_dma_tag_create(
1656 sc->alc_cdata.alc_buffer_tag, /* parent */
1657 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */
1658 BUS_SPACE_MAXADDR, /* lowaddr */
1659 BUS_SPACE_MAXADDR, /* highaddr */
1660 NULL, NULL, /* filter, filterarg */
1661 MCLBYTES, /* maxsize */
1663 MCLBYTES, /* maxsegsize */
1665 &sc->alc_cdata.alc_rx_tag);
1667 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n");
1670 /* Create DMA maps for Tx buffers. */
1671 for (i = 0; i < ALC_TX_RING_CNT; i++) {
1672 txd = &sc->alc_cdata.alc_txdesc[i];
1674 txd->tx_dmamap = NULL;
1675 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag,
1676 BUS_DMA_WAITOK, &txd->tx_dmamap);
1678 device_printf(sc->alc_dev,
1679 "could not create Tx dmamap.\n");
1683 /* Create DMA maps for Rx buffers. */
1684 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag,
1686 &sc->alc_cdata.alc_rx_sparemap);
1688 device_printf(sc->alc_dev,
1689 "could not create spare Rx dmamap.\n");
1692 for (i = 0; i < ALC_RX_RING_CNT; i++) {
1693 rxd = &sc->alc_cdata.alc_rxdesc[i];
1695 rxd->rx_dmamap = NULL;
1696 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag,
1700 device_printf(sc->alc_dev,
1701 "could not create Rx dmamap.\n");
1711 alc_dma_free(struct alc_softc *sc)
1713 struct alc_txdesc *txd;
1714 struct alc_rxdesc *rxd;
1718 if (sc->alc_cdata.alc_tx_tag != NULL) {
1719 for (i = 0; i < ALC_TX_RING_CNT; i++) {
1720 txd = &sc->alc_cdata.alc_txdesc[i];
1721 if (txd->tx_dmamap != NULL) {
1722 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag,
1724 txd->tx_dmamap = NULL;
1727 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag);
1728 sc->alc_cdata.alc_tx_tag = NULL;
1731 if (sc->alc_cdata.alc_rx_tag != NULL) {
1732 for (i = 0; i < ALC_RX_RING_CNT; i++) {
1733 rxd = &sc->alc_cdata.alc_rxdesc[i];
1734 if (rxd->rx_dmamap != NULL) {
1735 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag,
1737 rxd->rx_dmamap = NULL;
1740 if (sc->alc_cdata.alc_rx_sparemap != NULL) {
1741 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag,
1742 sc->alc_cdata.alc_rx_sparemap);
1743 sc->alc_cdata.alc_rx_sparemap = NULL;
1745 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag);
1746 sc->alc_cdata.alc_rx_tag = NULL;
1748 /* Tx descriptor ring. */
1749 if (sc->alc_cdata.alc_tx_ring_tag != NULL) {
1750 if (sc->alc_cdata.alc_tx_ring_map != NULL)
1751 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag,
1752 sc->alc_cdata.alc_tx_ring_map);
1753 if (sc->alc_cdata.alc_tx_ring_map != NULL &&
1754 sc->alc_rdata.alc_tx_ring != NULL)
1755 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag,
1756 sc->alc_rdata.alc_tx_ring,
1757 sc->alc_cdata.alc_tx_ring_map);
1758 sc->alc_rdata.alc_tx_ring = NULL;
1759 sc->alc_cdata.alc_tx_ring_map = NULL;
1760 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag);
1761 sc->alc_cdata.alc_tx_ring_tag = NULL;
1764 if (sc->alc_cdata.alc_rx_ring_tag != NULL) {
1765 if (sc->alc_cdata.alc_rx_ring_map != NULL)
1766 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag,
1767 sc->alc_cdata.alc_rx_ring_map);
1768 if (sc->alc_cdata.alc_rx_ring_map != NULL &&
1769 sc->alc_rdata.alc_rx_ring != NULL)
1770 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag,
1771 sc->alc_rdata.alc_rx_ring,
1772 sc->alc_cdata.alc_rx_ring_map);
1773 sc->alc_rdata.alc_rx_ring = NULL;
1774 sc->alc_cdata.alc_rx_ring_map = NULL;
1775 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag);
1776 sc->alc_cdata.alc_rx_ring_tag = NULL;
1778 /* Rx return ring. */
1779 if (sc->alc_cdata.alc_rr_ring_tag != NULL) {
1780 if (sc->alc_cdata.alc_rr_ring_map != NULL)
1781 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag,
1782 sc->alc_cdata.alc_rr_ring_map);
1783 if (sc->alc_cdata.alc_rr_ring_map != NULL &&
1784 sc->alc_rdata.alc_rr_ring != NULL)
1785 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag,
1786 sc->alc_rdata.alc_rr_ring,
1787 sc->alc_cdata.alc_rr_ring_map);
1788 sc->alc_rdata.alc_rr_ring = NULL;
1789 sc->alc_cdata.alc_rr_ring_map = NULL;
1790 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag);
1791 sc->alc_cdata.alc_rr_ring_tag = NULL;
1794 if (sc->alc_cdata.alc_cmb_tag != NULL) {
1795 if (sc->alc_cdata.alc_cmb_map != NULL)
1796 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag,
1797 sc->alc_cdata.alc_cmb_map);
1798 if (sc->alc_cdata.alc_cmb_map != NULL &&
1799 sc->alc_rdata.alc_cmb != NULL)
1800 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag,
1801 sc->alc_rdata.alc_cmb,
1802 sc->alc_cdata.alc_cmb_map);
1803 sc->alc_rdata.alc_cmb = NULL;
1804 sc->alc_cdata.alc_cmb_map = NULL;
1805 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag);
1806 sc->alc_cdata.alc_cmb_tag = NULL;
1809 if (sc->alc_cdata.alc_smb_tag != NULL) {
1810 if (sc->alc_cdata.alc_smb_map != NULL)
1811 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag,
1812 sc->alc_cdata.alc_smb_map);
1813 if (sc->alc_cdata.alc_smb_map != NULL &&
1814 sc->alc_rdata.alc_smb != NULL)
1815 bus_dmamem_free(sc->alc_cdata.alc_smb_tag,
1816 sc->alc_rdata.alc_smb,
1817 sc->alc_cdata.alc_smb_map);
1818 sc->alc_rdata.alc_smb = NULL;
1819 sc->alc_cdata.alc_smb_map = NULL;
1820 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag);
1821 sc->alc_cdata.alc_smb_tag = NULL;
1823 if (sc->alc_cdata.alc_buffer_tag != NULL) {
1824 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag);
1825 sc->alc_cdata.alc_buffer_tag = NULL;
1827 if (sc->alc_cdata.alc_parent_tag != NULL) {
1828 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag);
1829 sc->alc_cdata.alc_parent_tag = NULL;
1834 alc_shutdown(device_t dev)
1837 return (alc_suspend(dev));
1841 /* XXX: LINK SPEED */
1843 * Note, this driver resets the link speed to 10/100Mbps by
1844 * restarting auto-negotiation in suspend/shutdown phase but we
1845 * don't know whether that auto-negotiation would succeed or not
1846 * as driver has no control after powering off/suspend operation.
1847 * If the renegotiation fail WOL may not work. Running at 1Gbps
1848 * will draw more power than 375mA at 3.3V which is specified in
1849 * PCI specification and that would result in complete
1850 * shutdowning power to ethernet controller.
1853 * Save current negotiated media speed/duplex/flow-control to
1854 * softc and restore the same link again after resuming. PHY
1855 * handling such as power down/resetting to 100Mbps may be better
1856 * handled in suspend method in phy driver.
1859 alc_setlinkspeed(struct alc_softc *sc)
1861 struct mii_data *mii;
1864 mii = device_get_softc(sc->alc_miibus);
1867 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1868 (IFM_ACTIVE | IFM_AVALID)) {
1869 switch IFM_SUBTYPE(mii->mii_media_active) {
1880 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0);
1881 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
1882 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1883 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
1884 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1888 * Poll link state until alc(4) get a 10/100Mbps link.
1890 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1892 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
1893 == (IFM_ACTIVE | IFM_AVALID)) {
1894 switch (IFM_SUBTYPE(
1895 mii->mii_media_active)) {
1905 pause("alclnk", hz);
1908 if (i == MII_ANEGTICKS_GIGE)
1909 device_printf(sc->alc_dev,
1910 "establishing a link failed, WOL may not work!");
1913 * No link, force MAC to have 100Mbps, full-duplex link.
1914 * This is the last resort and may/may not work.
1916 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1917 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1925 alc_setwol(struct alc_softc *sc)
1931 ALC_LOCK_ASSERT(sc);
1933 alc_disable_l0s_l1(sc);
1935 if ((sc->alc_flags & ALC_FLAG_PM) == 0) {
1937 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
1938 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);
1939 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1940 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);
1941 /* Force PHY power down. */
1943 CSR_WRITE_4(sc, ALC_MASTER_CFG,
1944 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
1948 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1949 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
1950 alc_setlinkspeed(sc);
1951 CSR_WRITE_4(sc, ALC_MASTER_CFG,
1952 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS);
1956 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1957 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1958 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs);
1959 reg = CSR_READ_4(sc, ALC_MAC_CFG);
1960 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1962 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1963 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1964 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1965 reg |= MAC_CFG_RX_ENB;
1966 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
1968 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);
1969 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1970 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);
1971 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1972 /* WOL disabled, PHY power down. */
1974 CSR_WRITE_4(sc, ALC_MASTER_CFG,
1975 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
1979 pmstat = pci_read_config(sc->alc_dev,
1980 sc->alc_pmcap + PCIR_POWER_STATUS, 2);
1981 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1982 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1983 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1984 pci_write_config(sc->alc_dev,
1985 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2);
1990 alc_suspend(device_t dev)
1992 struct alc_softc *sc;
1994 sc = device_get_softc(dev);
2008 alc_resume(device_t dev)
2010 struct alc_softc *sc;
2014 sc = device_get_softc(dev);
2017 if ((sc->alc_flags & ALC_FLAG_PM) != 0) {
2018 /* Disable PME and clear PME status. */
2019 pmstat = pci_read_config(sc->alc_dev,
2020 sc->alc_pmcap + PCIR_POWER_STATUS, 2);
2021 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
2022 pmstat &= ~PCIM_PSTAT_PMEENABLE;
2023 pci_write_config(sc->alc_dev,
2024 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2);
2030 if ((ifp->if_flags & IFF_UP) != 0) {
2031 ifp->if_flags &= ~IFF_RUNNING;
2032 alc_init_locked(sc);
2040 alc_encap(struct alc_softc *sc, struct mbuf **m_head)
2042 struct alc_txdesc *txd, *txd_last;
2043 struct tx_desc *desc;
2047 bus_dma_segment_t txsegs[ALC_MAXTXSEGS];
2049 uint32_t cflags, hdrlen, ip_off, poff, vtag;
2050 int error, idx, nsegs, prod;
2052 ALC_LOCK_ASSERT(sc);
2054 M_ASSERTPKTHDR((*m_head));
2062 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) {
2064 * AR813x/AR815x requires offset of TCP/UDP header in its
2065 * Tx descriptor to perform Tx checksum offloading. TSO
2066 * also requires TCP header offset and modification of
2067 * IP/TCP header. This kind of operation takes many CPU
2068 * cycles on FreeBSD so fast host CPU is required to get
2069 * smooth TSO performance.
2071 struct ether_header *eh;
2073 if (M_WRITABLE(m) == 0) {
2074 /* Get a writable copy. */
2075 m = m_dup(*m_head, MB_DONTWAIT);
2076 /* Release original mbufs. */
2085 ip_off = sizeof(struct ether_header);
2086 m = m_pullup(m, ip_off + sizeof(struct ip));
2091 eh = mtod(m, struct ether_header *);
2093 * Check if hardware VLAN insertion is off.
2094 * Additional check for LLC/SNAP frame?
2096 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
2097 ip_off = sizeof(struct ether_vlan_header);
2098 m = m_pullup(m, ip_off);
2104 m = m_pullup(m, ip_off + sizeof(struct ip));
2109 ip = (struct ip *)(mtod(m, char *) + ip_off);
2110 poff = ip_off + (ip->ip_hl << 2);
2112 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2113 m = m_pullup(m, poff + sizeof(struct tcphdr));
2118 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
2119 m = m_pullup(m, poff + (tcp->th_off << 2));
2125 * Due to strict adherence of Microsoft NDIS
2126 * Large Send specification, hardware expects
2127 * a pseudo TCP checksum inserted by upper
2128 * stack. Unfortunately the pseudo TCP
2129 * checksum that NDIS refers to does not include
2130 * TCP payload length so driver should recompute
2131 * the pseudo checksum here. Hopefully this
2132 * wouldn't be much burden on modern CPUs.
2134 * Reset IP checksum and recompute TCP pseudo
2135 * checksum as NDIS specification said.
2138 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
2139 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2145 prod = sc->alc_cdata.alc_tx_prod;
2146 txd = &sc->alc_cdata.alc_txdesc[prod];
2148 map = txd->tx_dmamap;
2150 error = bus_dmamap_load_mbuf_defrag(
2151 sc->alc_cdata.alc_tx_tag, map, m_head,
2152 txsegs, ALC_MAXTXSEGS, &nsegs, BUS_DMA_NOWAIT);
2164 /* Check descriptor overrun. */
2165 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) {
2166 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map);
2169 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE);
2172 cflags = TD_ETHERNET;
2176 /* Configure VLAN hardware tag insertion. */
2177 if ((m->m_flags & M_VLANTAG) != 0) {
2178 vtag = htons(m->m_pkthdr.ether_vlantag);
2179 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK;
2180 cflags |= TD_INS_VLAN_TAG;
2182 /* Configure Tx checksum offload. */
2183 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) {
2184 #ifdef ALC_USE_CUSTOM_CSUM
2185 cflags |= TD_CUSTOM_CSUM;
2186 /* Set checksum start offset. */
2187 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) &
2188 TD_PLOAD_OFFSET_MASK;
2189 /* Set checksum insertion position of TCP/UDP. */
2190 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) <<
2191 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK;
2193 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
2194 cflags |= TD_IPCSUM;
2195 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
2196 cflags |= TD_TCPCSUM;
2197 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2198 cflags |= TD_UDPCSUM;
2199 /* Set TCP/UDP header offset. */
2200 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) &
2201 TD_L4HDR_OFFSET_MASK;
2203 } else if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2204 /* Request TSO and set MSS. */
2205 cflags |= TD_TSO | TD_TSO_DESCV1;
2208 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) &
2210 /* Set TCP header offset. */
2212 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) &
2213 TD_TCPHDR_OFFSET_MASK;
2215 * AR813x/AR815x requires the first buffer should
2216 * only hold IP/TCP header data. Payload should
2217 * be handled in other descriptors.
2219 hdrlen = poff + (tcp->th_off << 2);
2220 desc = &sc->alc_rdata.alc_tx_ring[prod];
2221 desc->len = htole32(TX_BYTES(hdrlen | vtag));
2222 desc->flags = htole32(cflags);
2223 desc->addr = htole64(txsegs[0].ds_addr);
2224 sc->alc_cdata.alc_tx_cnt++;
2225 ALC_DESC_INC(prod, ALC_TX_RING_CNT);
2226 if (m->m_len - hdrlen > 0) {
2227 /* Handle remaining payload of the first fragment. */
2228 desc = &sc->alc_rdata.alc_tx_ring[prod];
2229 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) |
2231 desc->flags = htole32(cflags);
2232 desc->addr = htole64(txsegs[0].ds_addr + hdrlen);
2233 sc->alc_cdata.alc_tx_cnt++;
2234 ALC_DESC_INC(prod, ALC_TX_RING_CNT);
2236 /* Handle remaining fragments. */
2239 for (; idx < nsegs; idx++) {
2240 desc = &sc->alc_rdata.alc_tx_ring[prod];
2241 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag);
2242 desc->flags = htole32(cflags);
2243 desc->addr = htole64(txsegs[idx].ds_addr);
2244 sc->alc_cdata.alc_tx_cnt++;
2245 ALC_DESC_INC(prod, ALC_TX_RING_CNT);
2247 /* Update producer index. */
2248 sc->alc_cdata.alc_tx_prod = prod;
2250 /* Finally set EOP on the last descriptor. */
2251 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT;
2252 desc = &sc->alc_rdata.alc_tx_ring[prod];
2253 desc->flags |= htole32(TD_EOP);
2255 /* Swap dmamap of the first and the last. */
2256 txd = &sc->alc_cdata.alc_txdesc[prod];
2257 map = txd_last->tx_dmamap;
2258 txd_last->tx_dmamap = txd->tx_dmamap;
2259 txd->tx_dmamap = map;
2266 alc_tx_task(void *arg, int pending)
2270 ifp = (struct ifnet *)arg;
2275 alc_start(struct ifnet *ifp)
2277 struct alc_softc *sc;
2278 struct mbuf *m_head;
2285 /* Reclaim transmitted frames. */
2286 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT)
2289 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) {
2293 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) {
2294 ifq_purge(&ifp->if_snd);
2299 for (enq = 0; !ifq_is_empty(&ifp->if_snd); ) {
2300 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2304 * Pack the data into the transmit ring. If we
2305 * don't have room, set the OACTIVE flag and wait
2306 * for the NIC to drain the ring.
2308 if (alc_encap(sc, &m_head)) {
2311 ifq_prepend(&ifp->if_snd, m_head);
2312 ifp->if_flags |= IFF_OACTIVE;
2318 * If there's a BPF listener, bounce a copy of this frame
2321 ETHER_BPF_MTAP(ifp, m_head);
2325 /* Sync descriptors. */
2326 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
2327 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE);
2328 /* Kick. Assume we're using normal Tx priority queue. */
2329 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX,
2330 (sc->alc_cdata.alc_tx_prod <<
2331 MBOX_TD_PROD_LO_IDX_SHIFT) &
2332 MBOX_TD_PROD_LO_IDX_MASK);
2333 /* Set a timeout in case the chip goes out to lunch. */
2334 sc->alc_watchdog_timer = ALC_TX_TIMEOUT;
2341 alc_watchdog(struct alc_softc *sc)
2345 ALC_LOCK_ASSERT(sc);
2347 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer)
2351 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) {
2352 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n");
2354 ifp->if_flags &= ~IFF_RUNNING;
2355 alc_init_locked(sc);
2358 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n");
2360 ifp->if_flags &= ~IFF_RUNNING;
2361 alc_init_locked(sc);
2362 if (!ifq_is_empty(&ifp->if_snd))
2363 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task);
2367 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
2369 struct alc_softc *sc;
2371 struct mii_data *mii;
2376 ifr = (struct ifreq *)data;
2380 if (ifr->ifr_mtu < ETHERMIN ||
2381 ifr->ifr_mtu > (sc->alc_ident->max_framelen -
2382 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) ||
2383 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 &&
2384 ifr->ifr_mtu > ETHERMTU)) {
2386 } else if (ifp->if_mtu != ifr->ifr_mtu) {
2388 ifp->if_mtu = ifr->ifr_mtu;
2389 /* AR813x/AR815x has 13 bits MSS field. */
2390 if (ifp->if_mtu > ALC_TSO_MTU &&
2391 (ifp->if_capenable & IFCAP_TSO4) != 0) {
2392 ifp->if_capenable &= ~IFCAP_TSO4;
2393 ifp->if_hwassist &= ~CSUM_TSO;
2400 if ((ifp->if_flags & IFF_UP) != 0) {
2401 if ((ifp->if_flags & IFF_RUNNING) != 0 &&
2402 ((ifp->if_flags ^ sc->alc_if_flags) &
2403 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2405 else if ((sc->alc_flags & ALC_FLAG_DETACH) == 0)
2406 alc_init_locked(sc);
2407 } else if ((ifp->if_flags & IFF_RUNNING) != 0)
2409 sc->alc_if_flags = ifp->if_flags;
2415 if ((ifp->if_flags & IFF_RUNNING) != 0)
2421 mii = device_get_softc(sc->alc_miibus);
2422 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
2426 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2427 if ((mask & IFCAP_TXCSUM) != 0 &&
2428 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
2429 ifp->if_capenable ^= IFCAP_TXCSUM;
2430 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2431 ifp->if_hwassist |= ALC_CSUM_FEATURES;
2433 ifp->if_hwassist &= ~ALC_CSUM_FEATURES;
2435 if ((mask & IFCAP_TSO4) != 0 &&
2436 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
2437 ifp->if_capenable ^= IFCAP_TSO4;
2438 if ((ifp->if_capenable & IFCAP_TSO4) != 0) {
2439 /* AR813x/AR815x has 13 bits MSS field. */
2440 if (ifp->if_mtu > ALC_TSO_MTU) {
2441 ifp->if_capenable &= ~IFCAP_TSO4;
2442 ifp->if_hwassist &= ~CSUM_TSO;
2444 ifp->if_hwassist |= CSUM_TSO;
2446 ifp->if_hwassist &= ~CSUM_TSO;
2450 if ((mask & IFCAP_WOL_MCAST) != 0 &&
2451 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
2452 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2453 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2454 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2455 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2457 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2458 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2459 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2462 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2463 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2464 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2465 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2466 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
2467 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2469 * VLAN hardware tagging is required to do checksum
2470 * offload or TSO on VLAN interface. Checksum offload
2471 * on VLAN interface also requires hardware checksum
2472 * offload of parent interface.
2474 if ((ifp->if_capenable & IFCAP_TXCSUM) == 0)
2475 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM;
2476 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
2477 ifp->if_capenable &=
2478 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
2480 // XXX VLAN_CAPABILITIES(ifp);
2483 error = ether_ioctl(ifp, cmd, data);
2491 alc_mac_config(struct alc_softc *sc)
2493 struct mii_data *mii;
2496 ALC_LOCK_ASSERT(sc);
2498 mii = device_get_softc(sc->alc_miibus);
2499 reg = CSR_READ_4(sc, ALC_MAC_CFG);
2500 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
2501 MAC_CFG_SPEED_MASK);
2502 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
2503 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
2504 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) {
2505 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
2507 /* Reprogram MAC with resolved speed/duplex. */
2508 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2511 reg |= MAC_CFG_SPEED_10_100;
2514 reg |= MAC_CFG_SPEED_1000;
2517 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2518 reg |= MAC_CFG_FULL_DUPLEX;
2520 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2521 reg |= MAC_CFG_TX_FC;
2522 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2523 reg |= MAC_CFG_RX_FC;
2526 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
2530 alc_stats_clear(struct alc_softc *sc)
2532 struct smb sb, *smb;
2536 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
2537 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
2538 sc->alc_cdata.alc_smb_map,
2539 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2540 smb = sc->alc_rdata.alc_smb;
2541 /* Update done, clear. */
2543 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
2544 sc->alc_cdata.alc_smb_map,
2545 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2547 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
2549 CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
2550 i += sizeof(uint32_t);
2552 /* Read Tx statistics. */
2553 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
2555 CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
2556 i += sizeof(uint32_t);
2562 alc_stats_update(struct alc_softc *sc)
2564 struct alc_hw_stats *stat;
2565 struct smb sb, *smb;
2570 ALC_LOCK_ASSERT(sc);
2573 stat = &sc->alc_stats;
2574 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
2575 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
2576 sc->alc_cdata.alc_smb_map,
2577 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2578 smb = sc->alc_rdata.alc_smb;
2579 if (smb->updated == 0)
2583 /* Read Rx statistics. */
2584 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
2586 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
2587 i += sizeof(uint32_t);
2589 /* Read Tx statistics. */
2590 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
2592 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
2593 i += sizeof(uint32_t);
2598 stat->rx_frames += smb->rx_frames;
2599 stat->rx_bcast_frames += smb->rx_bcast_frames;
2600 stat->rx_mcast_frames += smb->rx_mcast_frames;
2601 stat->rx_pause_frames += smb->rx_pause_frames;
2602 stat->rx_control_frames += smb->rx_control_frames;
2603 stat->rx_crcerrs += smb->rx_crcerrs;
2604 stat->rx_lenerrs += smb->rx_lenerrs;
2605 stat->rx_bytes += smb->rx_bytes;
2606 stat->rx_runts += smb->rx_runts;
2607 stat->rx_fragments += smb->rx_fragments;
2608 stat->rx_pkts_64 += smb->rx_pkts_64;
2609 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2610 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2611 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2612 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2613 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2614 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2615 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2616 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2617 stat->rx_rrs_errs += smb->rx_rrs_errs;
2618 stat->rx_alignerrs += smb->rx_alignerrs;
2619 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2620 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2621 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2624 stat->tx_frames += smb->tx_frames;
2625 stat->tx_bcast_frames += smb->tx_bcast_frames;
2626 stat->tx_mcast_frames += smb->tx_mcast_frames;
2627 stat->tx_pause_frames += smb->tx_pause_frames;
2628 stat->tx_excess_defer += smb->tx_excess_defer;
2629 stat->tx_control_frames += smb->tx_control_frames;
2630 stat->tx_deferred += smb->tx_deferred;
2631 stat->tx_bytes += smb->tx_bytes;
2632 stat->tx_pkts_64 += smb->tx_pkts_64;
2633 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2634 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2635 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2636 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2637 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2638 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2639 stat->tx_single_colls += smb->tx_single_colls;
2640 stat->tx_multi_colls += smb->tx_multi_colls;
2641 stat->tx_late_colls += smb->tx_late_colls;
2642 stat->tx_excess_colls += smb->tx_excess_colls;
2643 stat->tx_abort += smb->tx_abort;
2644 stat->tx_underrun += smb->tx_underrun;
2645 stat->tx_desc_underrun += smb->tx_desc_underrun;
2646 stat->tx_lenerrs += smb->tx_lenerrs;
2647 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2648 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2649 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2651 /* Update counters in ifnet. */
2652 ifp->if_opackets += smb->tx_frames;
2654 ifp->if_collisions += smb->tx_single_colls +
2655 smb->tx_multi_colls * 2 + smb->tx_late_colls +
2656 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT;
2660 * tx_pkts_truncated counter looks suspicious. It constantly
2661 * increments with no sign of Tx errors. This may indicate
2662 * the counter name is not correct one so I've removed the
2663 * counter in output errors.
2665 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls +
2668 ifp->if_ipackets += smb->rx_frames;
2670 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
2671 smb->rx_runts + smb->rx_pkts_truncated +
2672 smb->rx_fifo_oflows + smb->rx_rrs_errs +
2675 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
2676 /* Update done, clear. */
2678 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
2679 sc->alc_cdata.alc_smb_map,
2680 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2687 struct alc_softc *sc;
2690 sc = (struct alc_softc *)arg;
2692 status = CSR_READ_4(sc, ALC_INTR_STATUS);
2693 if ((status & ALC_INTRS) == 0) {
2696 /* Disable interrupts. */
2697 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT);
2698 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task);
2704 alc_int_task(void *arg, int pending)
2706 struct alc_softc *sc;
2711 sc = (struct alc_softc *)arg;
2714 status = CSR_READ_4(sc, ALC_INTR_STATUS);
2715 more = atomic_readandclear_32(&sc->alc_morework);
2717 status |= INTR_RX_PKT;
2718 if ((status & ALC_INTRS) == 0)
2721 /* Acknowledge interrupts but still disable interrupts. */
2722 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT);
2725 if ((ifp->if_flags & IFF_RUNNING) != 0) {
2726 if ((status & INTR_RX_PKT) != 0) {
2727 more = alc_rxintr(sc, sc->alc_process_limit);
2729 atomic_set_int(&sc->alc_morework, 1);
2730 else if (more == EIO) {
2732 ifp->if_flags &= ~IFF_RUNNING;
2733 alc_init_locked(sc);
2738 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |
2739 INTR_TXQ_TO_RST)) != 0) {
2740 if ((status & INTR_DMA_RD_TO_RST) != 0)
2741 device_printf(sc->alc_dev,
2742 "DMA read error! -- resetting\n");
2743 if ((status & INTR_DMA_WR_TO_RST) != 0)
2744 device_printf(sc->alc_dev,
2745 "DMA write error! -- resetting\n");
2746 if ((status & INTR_TXQ_TO_RST) != 0)
2747 device_printf(sc->alc_dev,
2748 "TxQ reset! -- resetting\n");
2750 ifp->if_flags &= ~IFF_RUNNING;
2751 alc_init_locked(sc);
2755 if ((ifp->if_flags & IFF_RUNNING) != 0 &&
2756 !ifq_is_empty(&ifp->if_snd))
2757 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task);
2760 if (more == EAGAIN ||
2761 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) {
2762 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task);
2767 if ((ifp->if_flags & IFF_RUNNING) != 0) {
2768 /* Re-enable interrupts if we're running. */
2769 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF);
2774 alc_txeof(struct alc_softc *sc)
2777 struct alc_txdesc *txd;
2778 uint32_t cons, prod;
2781 ALC_LOCK_ASSERT(sc);
2785 if (sc->alc_cdata.alc_tx_cnt == 0)
2787 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
2788 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE);
2789 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
2790 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag,
2791 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD);
2792 prod = sc->alc_rdata.alc_cmb->cons;
2794 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX);
2795 /* Assume we're using normal Tx priority queue. */
2796 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >>
2797 MBOX_TD_CONS_LO_IDX_SHIFT;
2798 cons = sc->alc_cdata.alc_tx_cons;
2800 * Go through our Tx list and free mbufs for those
2801 * frames which have been transmitted.
2803 for (prog = 0; cons != prod; prog++,
2804 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) {
2805 if (sc->alc_cdata.alc_tx_cnt <= 0)
2808 ifp->if_flags &= ~IFF_OACTIVE;
2809 sc->alc_cdata.alc_tx_cnt--;
2810 txd = &sc->alc_cdata.alc_txdesc[cons];
2811 if (txd->tx_m != NULL) {
2812 /* Reclaim transmitted mbufs. */
2813 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag,
2814 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2815 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag,
2822 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
2823 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag,
2824 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD);
2825 sc->alc_cdata.alc_tx_cons = cons;
2827 * Unarm watchdog timer only when there is no pending
2828 * frames in Tx queue.
2830 if (sc->alc_cdata.alc_tx_cnt == 0)
2831 sc->alc_watchdog_timer = 0;
2835 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd)
2838 bus_dma_segment_t segs[1];
2843 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
2846 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX;
2847 #ifndef __NO_STRICT_ALIGNMENT
2848 m_adj(m, sizeof(uint64_t));
2851 error = bus_dmamap_load_mbuf_segment(
2852 sc->alc_cdata.alc_rx_tag,
2853 sc->alc_cdata.alc_rx_sparemap,
2854 m, segs, 1, &nsegs, BUS_DMA_NOWAIT);
2859 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2861 if (rxd->rx_m != NULL) {
2862 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap,
2863 BUS_DMASYNC_POSTREAD);
2864 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap);
2866 map = rxd->rx_dmamap;
2867 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap;
2868 sc->alc_cdata.alc_rx_sparemap = map;
2869 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap,
2870 BUS_DMASYNC_PREREAD);
2872 rxd->rx_desc->addr = htole64(segs[0].ds_addr);
2877 alc_rxintr(struct alc_softc *sc, int count)
2880 struct rx_rdesc *rrd;
2881 uint32_t nsegs, status;
2884 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
2885 sc->alc_cdata.alc_rr_ring_map,
2886 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2887 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
2888 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE);
2889 rr_cons = sc->alc_cdata.alc_rr_cons;
2891 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) {
2894 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons];
2895 status = le32toh(rrd->status);
2896 if ((status & RRD_VALID) == 0)
2898 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo));
2900 /* This should not happen! */
2901 device_printf(sc->alc_dev,
2902 "unexpected segment count -- resetting\n");
2906 /* Clear Rx return status. */
2908 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT);
2909 sc->alc_cdata.alc_rx_cons += nsegs;
2910 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT;
2915 /* Update the consumer index. */
2916 sc->alc_cdata.alc_rr_cons = rr_cons;
2917 /* Sync Rx return descriptors. */
2918 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
2919 sc->alc_cdata.alc_rr_ring_map,
2920 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2922 * Sync updated Rx descriptors such that controller see
2923 * modified buffer addresses.
2925 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
2926 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE);
2928 * Let controller know availability of new Rx buffers.
2929 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors
2930 * it may be possible to update ALC_MBOX_RD0_PROD_IDX
2931 * only when Rx buffer pre-fetching is required. In
2932 * addition we already set ALC_RX_RD_FREE_THRESH to
2933 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However
2934 * it still seems that pre-fetching needs more
2937 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX,
2938 sc->alc_cdata.alc_rx_cons);
2941 return (count > 0 ? 0 : EAGAIN);
2944 #ifndef __NO_STRICT_ALIGNMENT
2945 static struct mbuf *
2946 alc_fixup_rx(struct ifnet *ifp, struct mbuf *m)
2950 uint16_t *src, *dst;
2952 src = mtod(m, uint16_t *);
2955 if (m->m_next == NULL) {
2956 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
2962 * Append a new mbuf to received mbuf chain and copy ethernet
2963 * header from the mbuf chain. This can save lots of CPU
2964 * cycles for jumbo frame.
2966 MGETHDR(n, MB_DONTWAIT, MT_DATA);
2972 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
2973 m->m_data += ETHER_HDR_LEN;
2974 m->m_len -= ETHER_HDR_LEN;
2975 n->m_len = ETHER_HDR_LEN;
2976 M_MOVE_PKTHDR(n, m);
2982 /* Receive a frame. */
2984 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd)
2986 struct alc_rxdesc *rxd;
2988 struct mbuf *mp, *m;
2989 uint32_t rdinfo, status, vtag;
2990 int count, nsegs, rx_cons;
2993 status = le32toh(rrd->status);
2994 rdinfo = le32toh(rrd->rdinfo);
2995 rx_cons = RRD_RD_IDX(rdinfo);
2996 nsegs = RRD_RD_CNT(rdinfo);
2998 sc->alc_cdata.alc_rxlen = RRD_BYTES(status);
2999 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) {
3001 * We want to pass the following frames to upper
3002 * layer regardless of error status of Rx return
3005 * o IP/TCP/UDP checksum is bad.
3006 * o frame length and protocol specific length
3009 * Force network stack compute checksum for
3012 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK;
3013 if ((RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC |
3018 for (count = 0; count < nsegs; count++,
3019 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) {
3020 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons];
3022 /* Add a new receive buffer to the ring. */
3023 if (alc_newbuf(sc, rxd) != 0) {
3025 /* Reuse Rx buffers. */
3026 if (sc->alc_cdata.alc_rxhead != NULL)
3027 m_freem(sc->alc_cdata.alc_rxhead);
3032 * Assume we've received a full sized frame.
3033 * Actual size is fixed when we encounter the end of
3034 * multi-segmented frame.
3036 mp->m_len = sc->alc_buf_size;
3038 /* Chain received mbufs. */
3039 if (sc->alc_cdata.alc_rxhead == NULL) {
3040 sc->alc_cdata.alc_rxhead = mp;
3041 sc->alc_cdata.alc_rxtail = mp;
3043 mp->m_flags &= ~M_PKTHDR;
3044 sc->alc_cdata.alc_rxprev_tail =
3045 sc->alc_cdata.alc_rxtail;
3046 sc->alc_cdata.alc_rxtail->m_next = mp;
3047 sc->alc_cdata.alc_rxtail = mp;
3050 if (count == nsegs - 1) {
3051 /* Last desc. for this frame. */
3052 m = sc->alc_cdata.alc_rxhead;
3053 m->m_flags |= M_PKTHDR;
3055 * It seems that L1C/L2C controller has no way
3056 * to tell hardware to strip CRC bytes.
3059 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN;
3061 /* Set last mbuf size. */
3062 mp->m_len = sc->alc_cdata.alc_rxlen -
3063 (nsegs - 1) * sc->alc_buf_size;
3064 /* Remove the CRC bytes in chained mbufs. */
3065 if (mp->m_len <= ETHER_CRC_LEN) {
3066 sc->alc_cdata.alc_rxtail =
3067 sc->alc_cdata.alc_rxprev_tail;
3068 sc->alc_cdata.alc_rxtail->m_len -=
3069 (ETHER_CRC_LEN - mp->m_len);
3070 sc->alc_cdata.alc_rxtail->m_next = NULL;
3073 mp->m_len -= ETHER_CRC_LEN;
3076 m->m_len = m->m_pkthdr.len;
3077 m->m_pkthdr.rcvif = ifp;
3079 * Due to hardware bugs, Rx checksum offloading
3080 * was intentionally disabled.
3082 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
3083 (status & RRD_VLAN_TAG) != 0) {
3084 vtag = RRD_VLAN(le32toh(rrd->vtag));
3085 m->m_pkthdr.ether_vlantag = ntohs(vtag);
3086 m->m_flags |= M_VLANTAG;
3088 #ifndef __NO_STRICT_ALIGNMENT
3089 m = alc_fixup_rx(ifp, m);
3094 (*ifp->if_input)(ifp, m);
3098 /* Reset mbuf chains. */
3099 ALC_RXCHAIN_RESET(sc);
3105 struct alc_softc *sc;
3106 struct mii_data *mii;
3108 sc = (struct alc_softc *)arg;
3112 mii = device_get_softc(sc->alc_miibus);
3114 alc_stats_update(sc);
3116 * alc(4) does not rely on Tx completion interrupts to reclaim
3117 * transferred buffers. Instead Tx completion interrupts are
3118 * used to hint for scheduling Tx task. So it's necessary to
3119 * release transmitted buffers by kicking Tx completion
3120 * handler. This limits the maximum reclamation delay to a hz.
3124 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc);
3129 alc_reset(struct alc_softc *sc)
3134 reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF;
3135 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET;
3136 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
3138 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
3140 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)
3144 device_printf(sc->alc_dev, "master reset timeout!\n");
3146 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
3147 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0)
3153 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg);
3159 struct alc_softc *sc;
3161 sc = (struct alc_softc *)xsc;
3163 alc_init_locked(sc);
3168 alc_init_locked(struct alc_softc *sc)
3171 struct mii_data *mii;
3172 uint8_t eaddr[ETHER_ADDR_LEN];
3174 uint32_t reg, rxf_hi, rxf_lo;
3176 ALC_LOCK_ASSERT(sc);
3179 mii = device_get_softc(sc->alc_miibus);
3181 if ((ifp->if_flags & IFF_RUNNING) != 0)
3184 * Cancel any pending I/O.
3188 * Reset the chip to a known state.
3192 /* Initialize Rx descriptors. */
3193 if (alc_init_rx_ring(sc) != 0) {
3194 device_printf(sc->alc_dev, "no memory for Rx buffers.\n");
3198 alc_init_rr_ring(sc);
3199 alc_init_tx_ring(sc);
3203 /* Reprogram the station address. */
3204 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
3205 CSR_WRITE_4(sc, ALC_PAR0,
3206 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
3207 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]);
3209 * Clear WOL status and disable all WOL feature as WOL
3210 * would interfere Rx operation under normal environments.
3212 CSR_READ_4(sc, ALC_WOL_CFG);
3213 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
3214 /* Set Tx descriptor base addresses. */
3215 paddr = sc->alc_rdata.alc_tx_ring_paddr;
3216 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
3217 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
3218 /* We don't use high priority ring. */
3219 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0);
3220 /* Set Tx descriptor counter. */
3221 CSR_WRITE_4(sc, ALC_TD_RING_CNT,
3222 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK);
3223 /* Set Rx descriptor base addresses. */
3224 paddr = sc->alc_rdata.alc_rx_ring_paddr;
3225 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
3226 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
3227 /* We use one Rx ring. */
3228 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0);
3229 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0);
3230 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0);
3231 /* Set Rx descriptor counter. */
3232 CSR_WRITE_4(sc, ALC_RD_RING_CNT,
3233 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK);
3236 * Let hardware split jumbo frames into alc_max_buf_sized chunks.
3237 * if it do not fit the buffer size. Rx return descriptor holds
3238 * a counter that indicates how many fragments were made by the
3239 * hardware. The buffer size should be multiple of 8 bytes.
3240 * Since hardware has limit on the size of buffer size, always
3241 * use the maximum value.
3242 * For strict-alignment architectures make sure to reduce buffer
3243 * size by 8 bytes to make room for alignment fixup.
3245 #ifndef __NO_STRICT_ALIGNMENT
3246 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t);
3248 sc->alc_buf_size = RX_BUF_SIZE_MAX;
3250 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size);
3252 paddr = sc->alc_rdata.alc_rr_ring_paddr;
3253 /* Set Rx return descriptor base addresses. */
3254 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
3255 /* We use one Rx return ring. */
3256 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0);
3257 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0);
3258 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0);
3259 /* Set Rx return descriptor counter. */
3260 CSR_WRITE_4(sc, ALC_RRD_RING_CNT,
3261 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK);
3262 paddr = sc->alc_rdata.alc_cmb_paddr;
3263 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
3264 paddr = sc->alc_rdata.alc_smb_paddr;
3265 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
3266 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
3268 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) {
3269 /* Reconfigure SRAM - Vendor magic. */
3270 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0);
3271 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100);
3272 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000);
3273 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0);
3274 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0);
3275 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0);
3276 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000);
3277 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000);
3280 /* Tell hardware that we're ready to load DMA blocks. */
3281 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD);
3283 /* Configure interrupt moderation timer. */
3284 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT;
3285 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;
3286 CSR_WRITE_4(sc, ALC_IM_TIMER, reg);
3288 * We don't want to automatic interrupt clear as task queue
3289 * for the interrupt should know interrupt status.
3291 reg = MASTER_SA_TIMER_ENB;
3292 if (ALC_USECS(sc->alc_int_rx_mod) != 0)
3293 reg |= MASTER_IM_RX_TIMER_ENB;
3294 if (ALC_USECS(sc->alc_int_tx_mod) != 0)
3295 reg |= MASTER_IM_TX_TIMER_ENB;
3296 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
3298 * Disable interrupt re-trigger timer. We don't want automatic
3299 * re-triggering of un-ACKed interrupts.
3301 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0));
3302 /* Configure CMB. */
3303 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
3304 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4);
3305 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000));
3307 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0));
3310 * Hardware can be configured to issue SMB interrupt based
3311 * on programmed interval. Since there is a callout that is
3312 * invoked for every hz in driver we use that instead of
3313 * relying on periodic SMB interrupt.
3315 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0));
3316 /* Clear MAC statistics. */
3317 alc_stats_clear(sc);
3320 * Always use maximum frame size that controller can support.
3321 * Otherwise received frames that has larger frame length
3322 * than alc(4) MTU would be silently dropped in hardware. This
3323 * would make path-MTU discovery hard as sender wouldn't get
3324 * any responses from receiver. alc(4) supports
3325 * multi-fragmented frames on Rx path so it has no issue on
3326 * assembling fragmented frames. Using maximum frame size also
3327 * removes the need to reinitialize hardware when interface
3328 * MTU configuration was changed.
3330 * Be conservative in what you do, be liberal in what you
3331 * accept from others - RFC 793.
3333 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen);
3335 /* Disable header split(?) */
3336 CSR_WRITE_4(sc, ALC_HDS_CFG, 0);
3338 /* Configure IPG/IFG parameters. */
3339 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG,
3340 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
3341 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
3342 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
3343 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
3344 /* Set parameters for half-duplex media. */
3345 CSR_WRITE_4(sc, ALC_HDPX_CFG,
3346 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
3347 HDPX_CFG_LCOL_MASK) |
3348 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
3349 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
3350 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
3351 HDPX_CFG_ABEBT_MASK) |
3352 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
3353 HDPX_CFG_JAMIPG_MASK));
3355 * Set TSO/checksum offload threshold. For frames that is
3356 * larger than this threshold, hardware wouldn't do
3357 * TSO/checksum offloading.
3359 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH,
3360 (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
3361 TSO_OFFLOAD_THRESH_MASK);
3362 /* Configure TxQ. */
3363 reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<
3364 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK;
3365 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
3366 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) {
3369 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) &
3370 TXQ_CFG_TD_BURST_MASK;
3371 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);
3373 /* Configure Rx free descriptor pre-fetching. */
3374 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH,
3375 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) &
3376 RX_RD_FREE_THRESH_HI_MASK) |
3377 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) &
3378 RX_RD_FREE_THRESH_LO_MASK));
3381 * Configure flow control parameters.
3382 * XON : 80% of Rx FIFO
3383 * XOFF : 30% of Rx FIFO
3385 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 ||
3386 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) {
3387 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
3388 rxf_hi = (reg * 8) / 10;
3389 rxf_lo = (reg * 3) / 10;
3390 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
3391 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
3392 RX_FIFO_PAUSE_THRESH_LO_MASK) |
3393 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
3394 RX_FIFO_PAUSE_THRESH_HI_MASK));
3397 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
3398 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) {
3399 CSR_WRITE_4(sc, ALC_SERDES_LOCK,
3400 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN |
3401 SERDES_PHY_CLK_SLOWDOWN);
3404 /* Disable RSS until I understand L1C/L2C's RSS logic. */
3405 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0);
3406 CSR_WRITE_4(sc, ALC_RSS_CPU, 0);
3408 /* Configure RxQ. */
3409 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
3410 RXQ_CFG_RD_BURST_MASK;
3411 reg |= RXQ_CFG_RSS_MODE_DIS;
3412 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0)
3413 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M;
3414 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
3416 /* Configure DMA parameters. */
3417 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI;
3419 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
3420 reg |= DMA_CFG_CMB_ENB;
3421 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0)
3422 reg |= DMA_CFG_SMB_ENB;
3424 reg |= DMA_CFG_SMB_DIS;
3425 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) <<
3426 DMA_CFG_RD_BURST_SHIFT;
3427 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) <<
3428 DMA_CFG_WR_BURST_SHIFT;
3429 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
3430 DMA_CFG_RD_DELAY_CNT_MASK;
3431 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
3432 DMA_CFG_WR_DELAY_CNT_MASK;
3433 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
3436 * Configure Tx/Rx MACs.
3437 * - Auto-padding for short frames.
3438 * - Enable CRC generation.
3439 * Actual reconfiguration of MAC for resolved speed/duplex
3440 * is followed after detection of link establishment.
3441 * AR813x/AR815x always does checksum computation regardless
3442 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to
3443 * have bug in protocol field in Rx return structure so
3444 * these controllers can't handle fragmented frames. Disable
3445 * Rx checksum offloading until there is a newer controller
3446 * that has sane implementation.
3448 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
3449 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
3450 MAC_CFG_PREAMBLE_MASK);
3451 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
3452 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
3453 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) {
3454 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
3456 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0)
3457 reg |= MAC_CFG_SPEED_10_100;
3459 reg |= MAC_CFG_SPEED_1000;
3460 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3462 /* Set up the receive filter. */
3466 /* Acknowledge all pending interrupts and clear it. */
3467 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS);
3468 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3469 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0);
3471 sc->alc_flags &= ~ALC_FLAG_LINK;
3472 /* Switch to the current media. */
3475 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc);
3477 ifp->if_flags |= IFF_RUNNING;
3478 ifp->if_flags &= ~IFF_OACTIVE;
3482 alc_stop(struct alc_softc *sc)
3485 struct alc_txdesc *txd;
3486 struct alc_rxdesc *rxd;
3490 ALC_LOCK_ASSERT(sc);
3492 * Mark the interface down and cancel the watchdog timer.
3495 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3496 sc->alc_flags &= ~ALC_FLAG_LINK;
3497 callout_stop(&sc->alc_tick_ch);
3498 sc->alc_watchdog_timer = 0;
3499 alc_stats_update(sc);
3500 /* Disable interrupts. */
3501 CSR_WRITE_4(sc, ALC_INTR_MASK, 0);
3502 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3505 reg = CSR_READ_4(sc, ALC_DMA_CFG);
3506 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB);
3507 reg |= DMA_CFG_SMB_DIS;
3508 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
3510 /* Stop Rx/Tx MACs. */
3512 /* Disable interrupts which might be touched in taskq handler. */
3513 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3515 /* Reclaim Rx buffers that have been processed. */
3516 if (sc->alc_cdata.alc_rxhead != NULL)
3517 m_freem(sc->alc_cdata.alc_rxhead);
3518 ALC_RXCHAIN_RESET(sc);
3520 * Free Tx/Rx mbufs still in the queues.
3522 for (i = 0; i < ALC_RX_RING_CNT; i++) {
3523 rxd = &sc->alc_cdata.alc_rxdesc[i];
3524 if (rxd->rx_m != NULL) {
3525 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag,
3526 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3527 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag,
3533 for (i = 0; i < ALC_TX_RING_CNT; i++) {
3534 txd = &sc->alc_cdata.alc_txdesc[i];
3535 if (txd->tx_m != NULL) {
3536 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag,
3537 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3538 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag,
3547 alc_stop_mac(struct alc_softc *sc)
3552 ALC_LOCK_ASSERT(sc);
3554 /* Disable Rx/Tx MAC. */
3555 reg = CSR_READ_4(sc, ALC_MAC_CFG);
3556 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
3557 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
3558 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3560 for (i = ALC_TIMEOUT; i > 0; i--) {
3561 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
3567 device_printf(sc->alc_dev,
3568 "could not disable Rx/Tx MAC(0x%08x)!\n", reg);
3572 alc_start_queue(struct alc_softc *sc)
3577 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB,
3578 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB,
3583 ALC_LOCK_ASSERT(sc);
3586 cfg = CSR_READ_4(sc, ALC_RXQ_CFG);
3587 cfg &= ~RXQ_CFG_ENB;
3589 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg);
3591 cfg = CSR_READ_4(sc, ALC_TXQ_CFG);
3593 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg);
3597 alc_stop_queue(struct alc_softc *sc)
3602 ALC_LOCK_ASSERT(sc);
3605 reg = CSR_READ_4(sc, ALC_RXQ_CFG);
3606 if ((reg & RXQ_CFG_ENB) != 0) {
3607 reg &= ~RXQ_CFG_ENB;
3608 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
3611 reg = CSR_READ_4(sc, ALC_TXQ_CFG);
3612 if ((reg & TXQ_CFG_ENB) == 0) {
3613 reg &= ~TXQ_CFG_ENB;
3614 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg);
3616 for (i = ALC_TIMEOUT; i > 0; i--) {
3617 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
3618 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)
3623 device_printf(sc->alc_dev,
3624 "could not disable RxQ/TxQ (0x%08x)!\n", reg);
3628 alc_init_tx_ring(struct alc_softc *sc)
3630 struct alc_ring_data *rd;
3631 struct alc_txdesc *txd;
3634 ALC_LOCK_ASSERT(sc);
3636 sc->alc_cdata.alc_tx_prod = 0;
3637 sc->alc_cdata.alc_tx_cons = 0;
3638 sc->alc_cdata.alc_tx_cnt = 0;
3640 rd = &sc->alc_rdata;
3641 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ);
3642 for (i = 0; i < ALC_TX_RING_CNT; i++) {
3643 txd = &sc->alc_cdata.alc_txdesc[i];
3647 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
3648 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE);
3652 alc_init_rx_ring(struct alc_softc *sc)
3654 struct alc_ring_data *rd;
3655 struct alc_rxdesc *rxd;
3658 ALC_LOCK_ASSERT(sc);
3660 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1;
3661 sc->alc_morework = 0;
3662 rd = &sc->alc_rdata;
3663 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ);
3664 for (i = 0; i < ALC_RX_RING_CNT; i++) {
3665 rxd = &sc->alc_cdata.alc_rxdesc[i];
3667 rxd->rx_desc = &rd->alc_rx_ring[i];
3668 if (alc_newbuf(sc, rxd) != 0)
3673 * Since controller does not update Rx descriptors, driver
3674 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE
3675 * is enough to ensure coherence.
3677 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
3678 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE);
3679 /* Let controller know availability of new Rx buffers. */
3680 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons);
3686 alc_init_rr_ring(struct alc_softc *sc)
3688 struct alc_ring_data *rd;
3690 ALC_LOCK_ASSERT(sc);
3692 sc->alc_cdata.alc_rr_cons = 0;
3693 ALC_RXCHAIN_RESET(sc);
3695 rd = &sc->alc_rdata;
3696 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ);
3697 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
3698 sc->alc_cdata.alc_rr_ring_map,
3699 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3703 alc_init_cmb(struct alc_softc *sc)
3705 struct alc_ring_data *rd;
3707 ALC_LOCK_ASSERT(sc);
3709 rd = &sc->alc_rdata;
3710 bzero(rd->alc_cmb, ALC_CMB_SZ);
3711 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map,
3712 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3716 alc_init_smb(struct alc_softc *sc)
3718 struct alc_ring_data *rd;
3720 ALC_LOCK_ASSERT(sc);
3722 rd = &sc->alc_rdata;
3723 bzero(rd->alc_smb, ALC_SMB_SZ);
3724 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map,
3725 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3729 alc_rxvlan(struct alc_softc *sc)
3734 ALC_LOCK_ASSERT(sc);
3737 reg = CSR_READ_4(sc, ALC_MAC_CFG);
3738 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3739 reg |= MAC_CFG_VLAN_TAG_STRIP;
3741 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3742 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3746 alc_rxfilter(struct alc_softc *sc)
3749 struct ifmultiaddr *ifma;
3754 ALC_LOCK_ASSERT(sc);
3758 bzero(mchash, sizeof(mchash));
3759 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG);
3760 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3761 if ((ifp->if_flags & IFF_BROADCAST) != 0)
3762 rxcfg |= MAC_CFG_BCAST;
3763 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3764 if ((ifp->if_flags & IFF_PROMISC) != 0)
3765 rxcfg |= MAC_CFG_PROMISC;
3766 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3767 rxcfg |= MAC_CFG_ALLMULTI;
3768 mchash[0] = 0xFFFFFFFF;
3769 mchash[1] = 0xFFFFFFFF;
3775 if_maddr_rlock(ifp);
3777 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) {
3778 if (ifma->ifma_addr->sa_family != AF_LINK)
3780 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3781 ifma->ifma_addr), ETHER_ADDR_LEN);
3782 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3786 if_maddr_runlock(ifp);
3790 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]);
3791 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]);
3792 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg);
3796 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS)
3798 return (sysctl_int_range(oidp, arg1, arg2, req,
3799 ALC_PROC_MIN, ALC_PROC_MAX));
3803 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS)
3806 return (sysctl_int_range(oidp, arg1, arg2, req,
3807 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX));