2 * from: vector.s, 386BSD 0.1 unknown origin
3 * $FreeBSD: src/sys/i386/isa/icu_vector.s,v 1.14.2.2 2000/07/18 21:12:42 dfr Exp $
4 * $DragonFly: src/sys/i386/isa/Attic/icu_vector.s,v 1.2 2003/06/17 04:28:37 dillon Exp $
8 * modified for PC98 by Kakefuda
12 #define ICU_IMR_OFFSET 2 /* IO_ICU{1,2} + 2 */
14 #define ICU_IMR_OFFSET 1 /* IO_ICU{1,2} + 1 */
17 #define ICU_EOI 0x20 /* XXX - define elsewhere */
19 #define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
20 #define IRQ_BYTE(irq_num) ((irq_num) >> 3)
23 #define ENABLE_ICU1 /* use auto-EOI to reduce i/o */
27 movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
28 OUTB_ICU1 /* ... to clear in service bit */
35 * The data sheet says no auto-EOI on slave, but it sometimes works.
37 #define ENABLE_ICU1_AND_2 ENABLE_ICU1
39 #define ENABLE_ICU1_AND_2 \
40 movb $ICU_EOI,%al ; /* as above */ \
41 outb %al,$IO_ICU2 ; /* but do second icu first ... */ \
42 OUTB_ICU1 /* ... then first icu (if !AUTO_EOI_1) */
46 * Macros for interrupt interrupt entry, call to handler, and exit.
49 #define FAST_INTR(irq_num, vec_name, enable_icus) \
53 pushl %eax ; /* save only call-used registers */ \
61 FAKE_MCOUNT((4+ACTUALLY_PUSHED)*4(%esp)) ; \
62 pushl _intr_unit + (irq_num) * 4 ; \
63 call *_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
64 enable_icus ; /* (re)enable ASAP (helps edge trigger?) */ \
66 incl _cnt+V_INTR ; /* book-keeping can wait */ \
67 movl _intr_countp + (irq_num) * 4,%eax ; \
69 movl _cpl,%eax ; /* are we unmasking pending HWIs or SWIs? */ \
71 andl _ipending,%eax ; \
72 jne 2f ; /* yes, maybe handle them */ \
84 cmpb $3,_intr_nesting_level ; /* is there enough stack? */ \
85 jae 1b ; /* no, return */ \
87 /* XXX next line is probably unnecessary now. */ \
88 movl $HWI_MASK|SWI_MASK,_cpl ; /* limit nesting ... */ \
89 incb _intr_nesting_level ; /* ... really limit it ... */ \
90 sti ; /* ... to do this as early as possible */ \
91 MAYBE_POPL_ES ; /* discard most of thin frame ... */ \
92 popl %ecx ; /* ... original %ds ... */ \
94 xchgl %eax,4(%esp) ; /* orig %eax; save cpl */ \
95 pushal ; /* build fat frame (grrr) ... */ \
96 pushl %ecx ; /* ... actually %ds ... */ \
102 movl (3+8+0)*4(%esp),%ecx ; /* ... %ecx from thin frame ... */ \
103 movl %ecx,(3+6)*4(%esp) ; /* ... to fat frame ... */ \
104 movl (3+8+1)*4(%esp),%eax ; /* ... cpl from thin frame */ \
106 subl $4,%esp ; /* junk for unit number */ \
110 #define INTR(irq_num, vec_name, icu, enable_icus, reg, maybe_extra_ipending) \
114 pushl $0 ; /* dummy error code */ \
115 pushl $0 ; /* dummy trap type */ \
117 pushl %ds ; /* save our data and extra segments ... */ \
120 mov $KDSEL,%ax ; /* ... and reload with kernel's own ... */ \
121 mov %ax,%ds ; /* ... early for obsolete reasons */ \
124 maybe_extra_ipending ; \
125 movb _imen + IRQ_BYTE(irq_num),%al ; \
126 orb $IRQ_BIT(irq_num),%al ; \
127 movb %al,_imen + IRQ_BYTE(irq_num) ; \
128 outb %al,$icu+ICU_IMR_OFFSET ; \
131 testb $IRQ_BIT(irq_num),%reg ; \
133 incb _intr_nesting_level ; \
134 __CONCAT(Xresume,irq_num): ; \
135 FAKE_MCOUNT(13*4(%esp)) ; /* XXX late to avoid double count */ \
136 incl _cnt+V_INTR ; /* tally interrupts */ \
137 movl _intr_countp + (irq_num) * 4,%eax ; \
141 pushl _intr_unit + (irq_num) * 4 ; \
142 orl _intr_mask + (irq_num) * 4,%eax ; \
145 call *_intr_handler + (irq_num) * 4 ; \
146 cli ; /* must unmask _imen and icu atomically */ \
147 movb _imen + IRQ_BYTE(irq_num),%al ; \
148 andb $~IRQ_BIT(irq_num),%al ; \
149 movb %al,_imen + IRQ_BYTE(irq_num) ; \
150 outb %al,$icu+ICU_IMR_OFFSET ; \
151 sti ; /* XXX _doreti repeats the cli/sti */ \
153 /* We could usually avoid the following jmp by inlining some of */ \
154 /* _doreti, but it's probably better to use less cache. */ \
159 /* XXX skip mcounting here to avoid double count */ \
160 orb $IRQ_BIT(irq_num),_ipending + IRQ_BYTE(irq_num) ; \
169 FAST_INTR(0,fastintr0, ENABLE_ICU1)
170 FAST_INTR(1,fastintr1, ENABLE_ICU1)
171 FAST_INTR(2,fastintr2, ENABLE_ICU1)
172 FAST_INTR(3,fastintr3, ENABLE_ICU1)
173 FAST_INTR(4,fastintr4, ENABLE_ICU1)
174 FAST_INTR(5,fastintr5, ENABLE_ICU1)
175 FAST_INTR(6,fastintr6, ENABLE_ICU1)
176 FAST_INTR(7,fastintr7, ENABLE_ICU1)
177 FAST_INTR(8,fastintr8, ENABLE_ICU1_AND_2)
178 FAST_INTR(9,fastintr9, ENABLE_ICU1_AND_2)
179 FAST_INTR(10,fastintr10, ENABLE_ICU1_AND_2)
180 FAST_INTR(11,fastintr11, ENABLE_ICU1_AND_2)
181 FAST_INTR(12,fastintr12, ENABLE_ICU1_AND_2)
182 FAST_INTR(13,fastintr13, ENABLE_ICU1_AND_2)
183 FAST_INTR(14,fastintr14, ENABLE_ICU1_AND_2)
184 FAST_INTR(15,fastintr15, ENABLE_ICU1_AND_2)
185 #define CLKINTR_PENDING movl $1,CNAME(clkintr_pending)
186 INTR(0,intr0, IO_ICU1, ENABLE_ICU1, al, CLKINTR_PENDING)
187 INTR(1,intr1, IO_ICU1, ENABLE_ICU1, al,)
188 INTR(2,intr2, IO_ICU1, ENABLE_ICU1, al,)
189 INTR(3,intr3, IO_ICU1, ENABLE_ICU1, al,)
190 INTR(4,intr4, IO_ICU1, ENABLE_ICU1, al,)
191 INTR(5,intr5, IO_ICU1, ENABLE_ICU1, al,)
192 INTR(6,intr6, IO_ICU1, ENABLE_ICU1, al,)
193 INTR(7,intr7, IO_ICU1, ENABLE_ICU1, al,)
194 INTR(8,intr8, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
195 INTR(9,intr9, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
196 INTR(10,intr10, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
197 INTR(11,intr11, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
198 INTR(12,intr12, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
199 INTR(13,intr13, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
200 INTR(14,intr14, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
201 INTR(15,intr15, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
206 _ihandlers: /* addresses of interrupt handlers */
207 /* actually resumption addresses for HWI's */
208 .long Xresume0, Xresume1, Xresume2, Xresume3
209 .long Xresume4, Xresume5, Xresume6, Xresume7
210 .long Xresume8, Xresume9, Xresume10, Xresume11
211 .long Xresume12, Xresume13, Xresume14, Xresume15
212 .long _swi_null, swi_net, _swi_null, _swi_null
213 .long _swi_vm, _swi_null, _softclock
215 imasks: /* masks for interrupt handlers */
216 .space NHWI*4 /* padding; HWI masks are elsewhere */
218 .long SWI_TTY_MASK, SWI_NET_MASK, SWI_CAMNET_MASK, SWI_CAMBIO_MASK
219 .long SWI_VM_MASK, SWI_TQ_MASK, SWI_CLOCK_MASK