sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.29 2003/12/01 21:06:59 ambrisko Exp $
  34  * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.60 2007/03/26 12:13:58 sephe Exp $
  35  *
  36  */
  37
  38 /*
  39  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  40  *
  41  * Written by Bill Paul <wpaul@windriver.com>
  42  * Senior Engineer, Wind River Systems
  43  */
  44
  45 /*
  46  * The Broadcom BCM5700 is based on technology originally developed by
  47  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  48  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  49  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  50  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  51  * frames, highly configurable RX filtering, and 16 RX and TX queues
  52  * (which, along with RX filter rules, can be used for QOS applications).
  53  * Other features, such as TCP segmentation, may be available as part
  54  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  55  * firmware images can be stored in hardware and need not be compiled
  56  * into the driver.
  57  *
  58  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  59  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  60  *
  61  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  62  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  63  * does not support external SSRAM.
  64  *
  65  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  66  * brand name, which is functionally similar but lacks PCI-X support.
  67  *
  68  * Without external SSRAM, you can only have at most 4 TX rings,
  69  * and the use of the mini RX ring is disabled. This seems to imply
  70  * that these features are simply not available on the BCM5701. As a
  71  * result, this driver does not implement any support for the mini RX
  72  * ring.
  73  */
  74
  75 #include <sys/param.h>
  76 #include <sys/systm.h>
  77 #include <sys/sockio.h>
  78 #include <sys/mbuf.h>
  79 #include <sys/malloc.h>
  80 #include <sys/kernel.h>
  81 #include <sys/socket.h>
  82 #include <sys/queue.h>
  83 #include <sys/serialize.h>
  84 #include <sys/thread2.h>
  85
  86 #include <net/if.h>
  87 #include <net/ifq_var.h>
  88 #include <net/if_arp.h>
  89 #include <net/ethernet.h>
  90 #include <net/if_dl.h>
  91 #include <net/if_media.h>
  92
  93 #include <net/bpf.h>
  94
  95 #include <net/if_types.h>
  96 #include <net/vlan/if_vlan_var.h>
  97
  98 #include <netinet/in_systm.h>
  99 #include <netinet/in.h>
 100 #include <netinet/ip.h>
 101
 102 #include <vm/vm.h>              /* for vtophys */
 103 #include <vm/pmap.h>            /* for vtophys */
 104 #include <sys/bus.h>
 105 #include <sys/rman.h>
 106
 107 #include <dev/netif/mii_layer/mii.h>
 108 #include <dev/netif/mii_layer/miivar.h>
 109 #include <dev/netif/mii_layer/miidevs.h>
 110 #include <dev/netif/mii_layer/brgphyreg.h>
 111
 112 #include <bus/pci/pcidevs.h>
 113 #include <bus/pci/pcireg.h>
 114 #include <bus/pci/pcivar.h>
 115
 116 #include "if_bgereg.h"
 117
 118 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 119
 120 /* "controller miibus0" required.  See GENERIC if you get errors here. */
 121 #include "miibus_if.h"
 122
 123 /*
 124  * Various supported device vendors/types and their names. Note: the
 125  * spec seems to indicate that the hardware still has Alteon's vendor
 126  * ID burned into it, though it will always be overriden by the vendor
 127  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 128  */
 129 #define BGE_DEVDESC_MAX         64      /* Maximum device description length */
 130
 131 static struct bge_type bge_devs[] = {
 132         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 133                 "Alteon BCM5700 Gigabit Ethernet" },
 134         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 135                 "Alteon BCM5701 Gigabit Ethernet" },
 136         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 137                 "Broadcom BCM5700 Gigabit Ethernet" },
 138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 139                 "Broadcom BCM5701 Gigabit Ethernet" },
 140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 141                 "Broadcom BCM5702X Gigabit Ethernet" },
 142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 143                 "Broadcom BCM5702 Gigabit Ethernet" },
 144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 145                 "Broadcom BCM5703X Gigabit Ethernet" },
 146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 147                 "Broadcom BCM5703 Gigabit Ethernet" },
 148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 149                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 151                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 153                 "Broadcom BCM5705 Gigabit Ethernet" },
 154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 155                 "Broadcom BCM5705K Gigabit Ethernet" },
 156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 157                 "Broadcom BCM5705M Gigabit Ethernet" },
 158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 159                 "Broadcom BCM5705M Gigabit Ethernet" },
 160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
 161                 "Broadcom BCM5714C Gigabit Ethernet" },
 162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 163                 "Broadcom BCM5721 Gigabit Ethernet" },
 164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 165                 "Broadcom BCM5750 Gigabit Ethernet" },
 166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 167                 "Broadcom BCM5750M Gigabit Ethernet" },
 168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 169                 "Broadcom BCM5751 Gigabit Ethernet" },
 170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 171                 "Broadcom BCM5751M Gigabit Ethernet" },
 172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 173                 "Broadcom BCM5782 Gigabit Ethernet" },
 174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 175                 "Broadcom BCM5788 Gigabit Ethernet" },
 176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 177                 "Broadcom BCM5789 Gigabit Ethernet" },
 178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 179                 "Broadcom BCM5901 Fast Ethernet" },
 180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 181                 "Broadcom BCM5901A2 Fast Ethernet" },
 182         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 183                 "SysKonnect Gigabit Ethernet" },
 184         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 185                 "Altima AC1000 Gigabit Ethernet" },
 186         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 187                 "Altima AC1002 Gigabit Ethernet" },
 188         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 189                 "Altima AC9100 Gigabit Ethernet" },
 190         { 0, 0, NULL }
 191 };
 192
 193 static int      bge_probe(device_t);
 194 static int      bge_attach(device_t);
 195 static int      bge_detach(device_t);
 196 static void     bge_release_resources(struct bge_softc *);
 197 static void     bge_txeof(struct bge_softc *);
 198 static void     bge_rxeof(struct bge_softc *);
 199
 200 static void     bge_tick(void *);
 201 static void     bge_tick_serialized(void *);
 202 static void     bge_stats_update(struct bge_softc *);
 203 static void     bge_stats_update_regs(struct bge_softc *);
 204 static int      bge_encap(struct bge_softc *, struct mbuf *, uint32_t *);
 205
 206 static void     bge_intr(void *);
 207 static void     bge_start(struct ifnet *);
 208 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 209 static void     bge_init(void *);
 210 static void     bge_stop(struct bge_softc *);
 211 static void     bge_watchdog(struct ifnet *);
 212 static void     bge_shutdown(device_t);
 213 static int      bge_ifmedia_upd(struct ifnet *);
 214 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 215
 216 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 217 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 218
 219 static void     bge_setmulti(struct bge_softc *);
 220
 221 static void     bge_handle_events(struct bge_softc *);
 222 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 223 static void     bge_free_jumbo_mem(struct bge_softc *);
 224 static struct bge_jslot
 225                 *bge_jalloc(struct bge_softc *);
 226 static void     bge_jfree(void *);
 227 static void     bge_jref(void *);
 228 static int      bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
 229 static int      bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
 230 static int      bge_init_rx_ring_std(struct bge_softc *);
 231 static void     bge_free_rx_ring_std(struct bge_softc *);
 232 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 233 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 234 static void     bge_free_tx_ring(struct bge_softc *);
 235 static int      bge_init_tx_ring(struct bge_softc *);
 236
 237 static int      bge_chipinit(struct bge_softc *);
 238 static int      bge_blockinit(struct bge_softc *);
 239
 240 #ifdef notdef
 241 static uint8_t  bge_vpd_readbyte(struct bge_softc *, uint32_t);
 242 static void     bge_vpd_read_res(struct bge_softc *, struct vpd_res *, uint32_t);
 243 static void     bge_vpd_read(struct bge_softc *);
 244 #endif
 245
 246 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 247 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 248 #ifdef notdef
 249 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 250 #endif
 251 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 252
 253 static int      bge_miibus_readreg(device_t, int, int);
 254 static int      bge_miibus_writereg(device_t, int, int, int);
 255 static void     bge_miibus_statchg(device_t);
 256
 257 static void     bge_reset(struct bge_softc *);
 258
 259 /*
 260  * Set following tunable to 1 for some IBM blade servers with the DNLK
 261  * switch module. Auto negotiation is broken for those configurations.
 262  */
 263 static int      bge_fake_autoneg = 0;
 264 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
 265
 266 static device_method_t bge_methods[] = {
 267         /* Device interface */
 268         DEVMETHOD(device_probe,         bge_probe),
 269         DEVMETHOD(device_attach,        bge_attach),
 270         DEVMETHOD(device_detach,        bge_detach),
 271         DEVMETHOD(device_shutdown,      bge_shutdown),
 272
 273         /* bus interface */
 274         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 275         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 276
 277         /* MII interface */
 278         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 279         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 280         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 281
 282         { 0, 0 }
 283 };
 284
 285 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 286 static devclass_t bge_devclass;
 287
 288 DECLARE_DUMMY_MODULE(if_bge);
 289 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
 290 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 291
 292 static uint32_t
 293 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 294 {
 295         device_t dev = sc->bge_dev;
 296
 297         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 298         return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
 299 }
 300
 301 static void
 302 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 303 {
 304         device_t dev = sc->bge_dev;
 305
 306         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 307         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 308 }
 309
 310 #ifdef notdef
 311 static uint32_t
 312 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 313 {
 314         device_t dev = sc->bge_dev;
 315
 316         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 317         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 318 }
 319 #endif
 320
 321 static void
 322 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 323 {
 324         device_t dev = sc->bge_dev;
 325
 326         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 327         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 328 }
 329
 330 #ifdef notdef
 331 static uint8_t
 332 bge_vpd_readbyte(struct bge_softc *sc, uint32_t addr)
 333 {
 334         device_t dev = sc->bge_dev;
 335         uint32_t val;
 336         int i;
 337
 338         pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2);
 339         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 340                 DELAY(10);
 341                 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG)
 342                         break;
 343         }
 344
 345         if (i == BGE_TIMEOUT) {
 346                 device_printf(sc->bge_dev, "VPD read timed out\n");
 347                 return(0);
 348         }
 349
 350         val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4);
 351
 352         return((val >> ((addr % 4) * 8)) & 0xFF);
 353 }
 354
 355 static void
 356 bge_vpd_read_res(struct bge_softc *sc, struct vpd_res *res, uint32_t addr)
 357 {
 358         size_t i;
 359         uint8_t *ptr;
 360
 361         ptr = (uint8_t *)res;
 362         for (i = 0; i < sizeof(struct vpd_res); i++)
 363                 ptr[i] = bge_vpd_readbyte(sc, i + addr);
 364
 365         return;
 366 }
 367
 368 static void
 369 bge_vpd_read(struct bge_softc *sc)
 370 {
 371         int pos = 0, i;
 372         struct vpd_res res;
 373
 374         if (sc->bge_vpd_prodname != NULL)
 375                 kfree(sc->bge_vpd_prodname, M_DEVBUF);
 376         if (sc->bge_vpd_readonly != NULL)
 377                 kfree(sc->bge_vpd_readonly, M_DEVBUF);
 378         sc->bge_vpd_prodname = NULL;
 379         sc->bge_vpd_readonly = NULL;
 380
 381         bge_vpd_read_res(sc, &res, pos);
 382
 383         if (res.vr_id != VPD_RES_ID) {
 384                 device_printf(sc->bge_dev,
 385                               "bad VPD resource id: expected %x got %x\n",
 386                               VPD_RES_ID, res.vr_id);
 387                 return;
 388         }
 389
 390         pos += sizeof(res);
 391         sc->bge_vpd_prodname = kmalloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT);
 392         for (i = 0; i < res.vr_len; i++)
 393                 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
 394         sc->bge_vpd_prodname[i] = '\0';
 395         pos += i;
 396
 397         bge_vpd_read_res(sc, &res, pos);
 398
 399         if (res.vr_id != VPD_RES_READ) {
 400                 device_printf(sc->bge_dev,
 401                               "bad VPD resource id: expected %x got %x\n",
 402                               VPD_RES_READ, res.vr_id);
 403                 return;
 404         }
 405
 406         pos += sizeof(res);
 407         sc->bge_vpd_readonly = kmalloc(res.vr_len, M_DEVBUF, M_INTWAIT);
 408         for (i = 0; i < res.vr_len + 1; i++)
 409                 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
 410 }
 411 #endif
 412
 413 /*
 414  * Read a byte of data stored in the EEPROM at address 'addr.' The
 415  * BCM570x supports both the traditional bitbang interface and an
 416  * auto access interface for reading the EEPROM. We use the auto
 417  * access method.
 418  */
 419 static uint8_t
 420 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 421 {
 422         int i;
 423         uint32_t byte = 0;
 424
 425         /*
 426          * Enable use of auto EEPROM access so we can avoid
 427          * having to use the bitbang method.
 428          */
 429         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 430
 431         /* Reset the EEPROM, load the clock period. */
 432         CSR_WRITE_4(sc, BGE_EE_ADDR,
 433             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 434         DELAY(20);
 435
 436         /* Issue the read EEPROM command. */
 437         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 438
 439         /* Wait for completion */
 440         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 441                 DELAY(10);
 442                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 443                         break;
 444         }
 445
 446         if (i == BGE_TIMEOUT) {
 447                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 448                 return(0);
 449         }
 450
 451         /* Get result. */
 452         byte = CSR_READ_4(sc, BGE_EE_DATA);
 453
 454         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 455
 456         return(0);
 457 }
 458
 459 /*
 460  * Read a sequence of bytes from the EEPROM.
 461  */
 462 static int
 463 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 464 {
 465         size_t i;
 466         int err;
 467         uint8_t byte;
 468
 469         for (byte = 0, err = 0, i = 0; i < len; i++) {
 470                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 471                 if (err)
 472                         break;
 473                 *(dest + i) = byte;
 474         }
 475
 476         return(err ? 1 : 0);
 477 }
 478
 479 static int
 480 bge_miibus_readreg(device_t dev, int phy, int reg)
 481 {
 482         struct bge_softc *sc;
 483         struct ifnet *ifp;
 484         uint32_t val, autopoll;
 485         int i;
 486
 487         sc = device_get_softc(dev);
 488         ifp = &sc->arpcom.ac_if;
 489
 490         /*
 491          * Broadcom's own driver always assumes the internal
 492          * PHY is at GMII address 1. On some chips, the PHY responds
 493          * to accesses at all addresses, which could cause us to
 494          * bogusly attach the PHY 32 times at probe type. Always
 495          * restricting the lookup to address 1 is simpler than
 496          * trying to figure out which chips revisions should be
 497          * special-cased.
 498          */
 499         if (phy != 1)
 500                 return(0);
 501
 502         /* Reading with autopolling on may trigger PCI errors */
 503         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 504         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 505                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 506                 DELAY(40);
 507         }
 508
 509         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
 510             BGE_MIPHY(phy)|BGE_MIREG(reg));
 511
 512         for (i = 0; i < BGE_TIMEOUT; i++) {
 513                 val = CSR_READ_4(sc, BGE_MI_COMM);
 514                 if (!(val & BGE_MICOMM_BUSY))
 515                         break;
 516         }
 517
 518         if (i == BGE_TIMEOUT) {
 519                 if_printf(ifp, "PHY read timed out\n");
 520                 val = 0;
 521                 goto done;
 522         }
 523
 524         val = CSR_READ_4(sc, BGE_MI_COMM);
 525
 526 done:
 527         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 528                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 529                 DELAY(40);
 530         }
 531
 532         if (val & BGE_MICOMM_READFAIL)
 533                 return(0);
 534
 535         return(val & 0xFFFF);
 536 }
 537
 538 static int
 539 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 540 {
 541         struct bge_softc *sc;
 542         uint32_t autopoll;
 543         int i;
 544
 545         sc = device_get_softc(dev);
 546
 547         /* Reading with autopolling on may trigger PCI errors */
 548         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 549         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 550                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 551                 DELAY(40);
 552         }
 553
 554         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
 555             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
 556
 557         for (i = 0; i < BGE_TIMEOUT; i++) {
 558                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
 559                         break;
 560         }
 561
 562         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 563                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 564                 DELAY(40);
 565         }
 566
 567         if (i == BGE_TIMEOUT) {
 568                 if_printf(&sc->arpcom.ac_if, "PHY read timed out\n");
 569                 return(0);
 570         }
 571
 572         return(0);
 573 }
 574
 575 static void
 576 bge_miibus_statchg(device_t dev)
 577 {
 578         struct bge_softc *sc;
 579         struct mii_data *mii;
 580
 581         sc = device_get_softc(dev);
 582         mii = device_get_softc(sc->bge_miibus);
 583
 584         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 585         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
 586                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 587         } else {
 588                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 589         }
 590
 591         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 592                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 593         } else {
 594                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 595         }
 596 }
 597
 598 /*
 599  * Handle events that have triggered interrupts.
 600  */
 601 static void
 602 bge_handle_events(struct bge_softc *sc)
 603 {
 604 }
 605
 606 /*
 607  * Memory management for jumbo frames.
 608  */
 609 static int
 610 bge_alloc_jumbo_mem(struct bge_softc *sc)
 611 {
 612         struct bge_jslot *entry;
 613         caddr_t ptr;
 614         int i;
 615
 616         /* Grab a big chunk o' storage. */
 617         sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF,
 618                 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
 619
 620         if (sc->bge_cdata.bge_jumbo_buf == NULL) {
 621                 if_printf(&sc->arpcom.ac_if, "no memory for jumbo buffers!\n");
 622                 return(ENOBUFS);
 623         }
 624
 625         SLIST_INIT(&sc->bge_jfree_listhead);
 626
 627         /*
 628          * Now divide it up into 9K pieces and save the addresses
 629          * in an array. Note that we play an evil trick here by using
 630          * the first few bytes in the buffer to hold the the address
 631          * of the softc structure for this interface. This is because
 632          * bge_jfree() needs it, but it is called by the mbuf management
 633          * code which will not pass it to us explicitly.
 634          */
 635         ptr = sc->bge_cdata.bge_jumbo_buf;
 636         for (i = 0; i < BGE_JSLOTS; i++) {
 637                 entry = &sc->bge_cdata.bge_jslots[i];
 638                 entry->bge_sc = sc;
 639                 entry->bge_buf = ptr;
 640                 entry->bge_inuse = 0;
 641                 entry->bge_slot = i;
 642                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 643                 ptr += BGE_JLEN;
 644         }
 645
 646         return(0);
 647 }
 648
 649 static void
 650 bge_free_jumbo_mem(struct bge_softc *sc)
 651 {
 652         if (sc->bge_cdata.bge_jumbo_buf)
 653                 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF);
 654 }
 655
 656 /*
 657  * Allocate a jumbo buffer.
 658  */
 659 static struct bge_jslot *
 660 bge_jalloc(struct bge_softc *sc)
 661 {
 662         struct bge_jslot *entry;
 663
 664         lwkt_serialize_enter(&sc->bge_jslot_serializer);
 665         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 666         if (entry) {
 667                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 668                 entry->bge_inuse = 1;
 669         } else {
 670                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 671         }
 672         lwkt_serialize_exit(&sc->bge_jslot_serializer);
 673         return(entry);
 674 }
 675
 676 /*
 677  * Adjust usage count on a jumbo buffer.
 678  */
 679 static void
 680 bge_jref(void *arg)
 681 {
 682         struct bge_jslot *entry = (struct bge_jslot *)arg;
 683         struct bge_softc *sc = entry->bge_sc;
 684
 685         if (sc == NULL)
 686                 panic("bge_jref: can't find softc pointer!");
 687
 688         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 689                 panic("bge_jref: asked to reference buffer "
 690                     "that we don't manage!");
 691         } else if (entry->bge_inuse == 0) {
 692                 panic("bge_jref: buffer already free!");
 693         } else {
 694                 atomic_add_int(&entry->bge_inuse, 1);
 695         }
 696 }
 697
 698 /*
 699  * Release a jumbo buffer.
 700  */
 701 static void
 702 bge_jfree(void *arg)
 703 {
 704         struct bge_jslot *entry = (struct bge_jslot *)arg;
 705         struct bge_softc *sc = entry->bge_sc;
 706
 707         if (sc == NULL)
 708                 panic("bge_jfree: can't find softc pointer!");
 709
 710         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 711                 panic("bge_jfree: asked to free buffer that we don't manage!");
 712         } else if (entry->bge_inuse == 0) {
 713                 panic("bge_jfree: buffer already free!");
 714         } else {
 715                 /*
 716                  * Possible MP race to 0, use the serializer.  The atomic insn
 717                  * is still needed for races against bge_jref().
 718                  */
 719                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
 720                 atomic_subtract_int(&entry->bge_inuse, 1);
 721                 if (entry->bge_inuse == 0) {
 722                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 723                                           entry, jslot_link);
 724                 }
 725                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
 726         }
 727 }
 728
 729
 730 /*
 731  * Intialize a standard receive ring descriptor.
 732  */
 733 static int
 734 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
 735 {
 736         struct mbuf *m_new = NULL;
 737         struct bge_rx_bd *r;
 738
 739         if (m == NULL) {
 740                 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
 741                 if (m_new == NULL)
 742                         return (ENOBUFS);
 743                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 744         } else {
 745                 m_new = m;
 746                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 747                 m_new->m_data = m_new->m_ext.ext_buf;
 748         }
 749
 750         if (!sc->bge_rx_alignment_bug)
 751                 m_adj(m_new, ETHER_ALIGN);
 752         sc->bge_cdata.bge_rx_std_chain[i] = m_new;
 753         r = &sc->bge_rdata->bge_rx_std_ring[i];
 754         BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
 755         r->bge_flags = BGE_RXBDFLAG_END;
 756         r->bge_len = m_new->m_len;
 757         r->bge_idx = i;
 758
 759         return(0);
 760 }
 761
 762 /*
 763  * Initialize a jumbo receive ring descriptor. This allocates
 764  * a jumbo buffer from the pool managed internally by the driver.
 765  */
 766 static int
 767 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
 768 {
 769         struct mbuf *m_new = NULL;
 770         struct bge_rx_bd *r;
 771
 772         if (m == NULL) {
 773                 struct bge_jslot *buf;
 774
 775                 /* Allocate the mbuf. */
 776                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
 777                 if (m_new == NULL)
 778                         return(ENOBUFS);
 779
 780                 /* Allocate the jumbo buffer */
 781                 buf = bge_jalloc(sc);
 782                 if (buf == NULL) {
 783                         m_freem(m_new);
 784                         if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
 785                             "-- packet dropped!\n");
 786                         return(ENOBUFS);
 787                 }
 788
 789                 /* Attach the buffer to the mbuf. */
 790                 m_new->m_ext.ext_arg = buf;
 791                 m_new->m_ext.ext_buf = buf->bge_buf;
 792                 m_new->m_ext.ext_free = bge_jfree;
 793                 m_new->m_ext.ext_ref = bge_jref;
 794                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 795
 796                 m_new->m_data = m_new->m_ext.ext_buf;
 797                 m_new->m_flags |= M_EXT;
 798                 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 799         } else {
 800                 m_new = m;
 801                 m_new->m_data = m_new->m_ext.ext_buf;
 802                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 803         }
 804
 805         if (!sc->bge_rx_alignment_bug)
 806                 m_adj(m_new, ETHER_ALIGN);
 807         /* Set up the descriptor. */
 808         r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
 809         sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
 810         BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
 811         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 812         r->bge_len = m_new->m_len;
 813         r->bge_idx = i;
 814
 815         return(0);
 816 }
 817
 818 /*
 819  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
 820  * that's 1MB or memory, which is a lot. For now, we fill only the first
 821  * 256 ring entries and hope that our CPU is fast enough to keep up with
 822  * the NIC.
 823  */
 824 static int
 825 bge_init_rx_ring_std(struct bge_softc *sc)
 826 {
 827         int i;
 828
 829         for (i = 0; i < BGE_SSLOTS; i++) {
 830                 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
 831                         return(ENOBUFS);
 832         };
 833
 834         sc->bge_std = i - 1;
 835         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
 836
 837         return(0);
 838 }
 839
 840 static void
 841 bge_free_rx_ring_std(struct bge_softc *sc)
 842 {
 843         int i;
 844
 845         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 846                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 847                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
 848                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
 849                 }
 850                 bzero(&sc->bge_rdata->bge_rx_std_ring[i],
 851                     sizeof(struct bge_rx_bd));
 852         }
 853 }
 854
 855 static int
 856 bge_init_rx_ring_jumbo(struct bge_softc *sc)
 857 {
 858         int i;
 859         struct bge_rcb *rcb;
 860
 861         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 862                 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
 863                         return(ENOBUFS);
 864         };
 865
 866         sc->bge_jumbo = i - 1;
 867
 868         rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
 869         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 870         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 871
 872         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
 873
 874         return(0);
 875 }
 876
 877 static void
 878 bge_free_rx_ring_jumbo(struct bge_softc *sc)
 879 {
 880         int i;
 881
 882         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 883                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
 884                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
 885                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
 886                 }
 887                 bzero(&sc->bge_rdata->bge_rx_jumbo_ring[i],
 888                     sizeof(struct bge_rx_bd));
 889         }
 890 }
 891
 892 static void
 893 bge_free_tx_ring(struct bge_softc *sc)
 894 {
 895         int i;
 896
 897         if (sc->bge_rdata->bge_tx_ring == NULL)
 898                 return;
 899
 900         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 901                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
 902                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
 903                         sc->bge_cdata.bge_tx_chain[i] = NULL;
 904                 }
 905                 bzero(&sc->bge_rdata->bge_tx_ring[i],
 906                     sizeof(struct bge_tx_bd));
 907         }
 908 }
 909
 910 static int
 911 bge_init_tx_ring(struct bge_softc *sc)
 912 {
 913         sc->bge_txcnt = 0;
 914         sc->bge_tx_saved_considx = 0;
 915
 916         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
 917         /* 5700 b2 errata */
 918         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
 919                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
 920
 921         CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 922         /* 5700 b2 errata */
 923         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
 924                 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 925
 926         return(0);
 927 }
 928
 929 static void
 930 bge_setmulti(struct bge_softc *sc)
 931 {
 932         struct ifnet *ifp;
 933         struct ifmultiaddr *ifma;
 934         uint32_t hashes[4] = { 0, 0, 0, 0 };
 935         int h, i;
 936
 937         ifp = &sc->arpcom.ac_if;
 938
 939         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 940                 for (i = 0; i < 4; i++)
 941                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
 942                 return;
 943         }
 944
 945         /* First, zot all the existing filters. */
 946         for (i = 0; i < 4; i++)
 947                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
 948
 949         /* Now program new ones. */
 950         LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 951                 if (ifma->ifma_addr->sa_family != AF_LINK)
 952                         continue;
 953                 h = ether_crc32_le(
 954                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 955                     ETHER_ADDR_LEN) & 0x7f;
 956                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
 957         }
 958
 959         for (i = 0; i < 4; i++)
 960                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
 961 }
 962
 963 /*
 964  * Do endian, PCI and DMA initialization. Also check the on-board ROM
 965  * self-test results.
 966  */
 967 static int
 968 bge_chipinit(struct bge_softc *sc)
 969 {
 970         int i;
 971         uint32_t dma_rw_ctl;
 972
 973         /* Set endianness before we access any non-PCI registers. */
 974 #if BYTE_ORDER == BIG_ENDIAN
 975         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
 976             BGE_BIGENDIAN_INIT, 4);
 977 #else
 978         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
 979             BGE_LITTLEENDIAN_INIT, 4);
 980 #endif
 981
 982         /*
 983          * Check the 'ROM failed' bit on the RX CPU to see if
 984          * self-tests passed.
 985          */
 986         if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
 987                 if_printf(&sc->arpcom.ac_if,
 988                           "RX CPU self-diagnostics failed!\n");
 989                 return(ENODEV);
 990         }
 991
 992         /* Clear the MAC control register */
 993         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
 994
 995         /*
 996          * Clear the MAC statistics block in the NIC's
 997          * internal memory.
 998          */
 999         for (i = BGE_STATS_BLOCK;
1000             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1001                 BGE_MEMWIN_WRITE(sc, i, 0);
1002
1003         for (i = BGE_STATUS_BLOCK;
1004             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1005                 BGE_MEMWIN_WRITE(sc, i, 0);
1006
1007         /* Set up the PCI DMA control register. */
1008         if (sc->bge_pcie) {
1009                 /* PCI Express */
1010                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1011                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1012                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1013         } else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1014                    BGE_PCISTATE_PCI_BUSMODE) {
1015                 /* Conventional PCI bus */
1016                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1017                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1018                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1019                     (0x0F);
1020         } else {
1021                 /* PCI-X bus */
1022                 /*
1023                  * The 5704 uses a different encoding of read/write
1024                  * watermarks.
1025                  */
1026                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1027                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1028                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1029                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1030                 else
1031                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1032                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1033                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1034                             (0x0F);
1035
1036                 /*
1037                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1038                  * for hardware bugs.
1039                  */
1040                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1041                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1042                         uint32_t tmp;
1043
1044                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1045                         if (tmp == 0x6 || tmp == 0x7)
1046                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1047                 }
1048         }
1049
1050         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1051             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1052             sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1053             sc->bge_asicrev == BGE_ASICREV_BCM5750)
1054                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1055         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1056
1057         /*
1058          * Set up general mode register.
1059          */
1060         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1061             BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1062             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1063             BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM);
1064
1065         /*
1066          * Disable memory write invalidate.  Apparently it is not supported
1067          * properly by these devices.
1068          */
1069         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1070
1071         /* Set the timer prescaler (always 66Mhz) */
1072         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1073
1074         return(0);
1075 }
1076
1077 static int
1078 bge_blockinit(struct bge_softc *sc)
1079 {
1080         struct bge_rcb *rcb;
1081         volatile struct bge_rcb *vrcb;
1082         int i;
1083
1084         /*
1085          * Initialize the memory window pointer register so that
1086          * we can access the first 32K of internal NIC RAM. This will
1087          * allow us to set up the TX send ring RCBs and the RX return
1088          * ring RCBs, plus other things which live in NIC memory.
1089          */
1090         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1091
1092         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1093
1094         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1095             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1096                 /* Configure mbuf memory pool */
1097                 if (sc->bge_extram) {
1098                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1099                             BGE_EXT_SSRAM);
1100                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1101                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1102                         else
1103                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1104                 } else {
1105                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1106                             BGE_BUFFPOOL_1);
1107                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1108                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1109                         else
1110                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1111                 }
1112
1113                 /* Configure DMA resource pool */
1114                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1115                     BGE_DMA_DESCRIPTORS);
1116                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1117         }
1118
1119         /* Configure mbuf pool watermarks */
1120         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1121             sc->bge_asicrev == BGE_ASICREV_BCM5750) {
1122                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1123                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1124         } else {
1125                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1126                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1127         }
1128         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1129
1130         /* Configure DMA resource watermarks */
1131         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1132         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1133
1134         /* Enable buffer manager */
1135         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1136             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1137                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1138                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1139
1140                 /* Poll for buffer manager start indication */
1141                 for (i = 0; i < BGE_TIMEOUT; i++) {
1142                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1143                                 break;
1144                         DELAY(10);
1145                 }
1146
1147                 if (i == BGE_TIMEOUT) {
1148                         if_printf(&sc->arpcom.ac_if,
1149                                   "buffer manager failed to start\n");
1150                         return(ENXIO);
1151                 }
1152         }
1153
1154         /* Enable flow-through queues */
1155         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1156         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1157
1158         /* Wait until queue initialization is complete */
1159         for (i = 0; i < BGE_TIMEOUT; i++) {
1160                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1161                         break;
1162                 DELAY(10);
1163         }
1164
1165         if (i == BGE_TIMEOUT) {
1166                 if_printf(&sc->arpcom.ac_if,
1167                           "flow-through queue init failed\n");
1168                 return(ENXIO);
1169         }
1170
1171         /* Initialize the standard RX ring control block */
1172         rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
1173         BGE_HOSTADDR(rcb->bge_hostaddr,
1174             vtophys(&sc->bge_rdata->bge_rx_std_ring));
1175         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1176             sc->bge_asicrev == BGE_ASICREV_BCM5750)
1177                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1178         else
1179                 rcb->bge_maxlen_flags =
1180                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1181         if (sc->bge_extram)
1182                 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1183         else
1184                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1185         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1186         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1187         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1188         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1189
1190         /*
1191          * Initialize the jumbo RX ring control block
1192          * We set the 'ring disabled' bit in the flags
1193          * field until we're actually ready to start
1194          * using this ring (i.e. once we set the MTU
1195          * high enough to require it).
1196          */
1197         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1198             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1199                 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1200                 BGE_HOSTADDR(rcb->bge_hostaddr,
1201                     vtophys(&sc->bge_rdata->bge_rx_jumbo_ring));
1202                 rcb->bge_maxlen_flags =
1203                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1204                     BGE_RCB_FLAG_RING_DISABLED);
1205                 if (sc->bge_extram)
1206                         rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
1207                 else
1208                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1209                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1210                     rcb->bge_hostaddr.bge_addr_hi);
1211                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1212                     rcb->bge_hostaddr.bge_addr_lo);
1213                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1214                     rcb->bge_maxlen_flags);
1215                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1216
1217                 /* Set up dummy disabled mini ring RCB */
1218                 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
1219                 rcb->bge_maxlen_flags =
1220                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1221                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1222                     rcb->bge_maxlen_flags);
1223         }
1224
1225         /*
1226          * Set the BD ring replentish thresholds. The recommended
1227          * values are 1/8th the number of descriptors allocated to
1228          * each ring.
1229          */
1230         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1231         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1232
1233         /*
1234          * Disable all unused send rings by setting the 'ring disabled'
1235          * bit in the flags field of all the TX send ring control blocks.
1236          * These are located in NIC memory.
1237          */
1238         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1239             BGE_SEND_RING_RCB);
1240         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1241                 vrcb->bge_maxlen_flags =
1242                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1243                 vrcb->bge_nicaddr = 0;
1244                 vrcb++;
1245         }
1246
1247         /* Configure TX RCB 0 (we use only the first ring) */
1248         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1249             BGE_SEND_RING_RCB);
1250         vrcb->bge_hostaddr.bge_addr_hi = 0;
1251         BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring));
1252         vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
1253         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1254             sc->bge_asicrev != BGE_ASICREV_BCM5750)
1255                 vrcb->bge_maxlen_flags =
1256                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0);
1257
1258         /* Disable all unused RX return rings */
1259         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1260             BGE_RX_RETURN_RING_RCB);
1261         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1262                 vrcb->bge_hostaddr.bge_addr_hi = 0;
1263                 vrcb->bge_hostaddr.bge_addr_lo = 0;
1264                 vrcb->bge_maxlen_flags =
1265                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1266                     BGE_RCB_FLAG_RING_DISABLED);
1267                 vrcb->bge_nicaddr = 0;
1268                 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1269                     (i * (sizeof(uint64_t))), 0);
1270                 vrcb++;
1271         }
1272
1273         /* Initialize RX ring indexes */
1274         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1275         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1276         CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1277
1278         /*
1279          * Set up RX return ring 0
1280          * Note that the NIC address for RX return rings is 0x00000000.
1281          * The return rings live entirely within the host, so the
1282          * nicaddr field in the RCB isn't used.
1283          */
1284         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1285             BGE_RX_RETURN_RING_RCB);
1286         vrcb->bge_hostaddr.bge_addr_hi = 0;
1287         BGE_HOSTADDR(vrcb->bge_hostaddr,
1288             vtophys(&sc->bge_rdata->bge_rx_return_ring));
1289         vrcb->bge_nicaddr = 0x00000000;
1290         vrcb->bge_maxlen_flags =
1291             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0);
1292
1293         /* Set random backoff seed for TX */
1294         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1295             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1296             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1297             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1298             BGE_TX_BACKOFF_SEED_MASK);
1299
1300         /* Set inter-packet gap */
1301         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1302
1303         /*
1304          * Specify which ring to use for packets that don't match
1305          * any RX rules.
1306          */
1307         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1308
1309         /*
1310          * Configure number of RX lists. One interrupt distribution
1311          * list, sixteen active lists, one bad frames class.
1312          */
1313         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1314
1315         /* Inialize RX list placement stats mask. */
1316         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1317         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1318
1319         /* Disable host coalescing until we get it set up */
1320         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1321
1322         /* Poll to make sure it's shut down. */
1323         for (i = 0; i < BGE_TIMEOUT; i++) {
1324                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1325                         break;
1326                 DELAY(10);
1327         }
1328
1329         if (i == BGE_TIMEOUT) {
1330                 if_printf(&sc->arpcom.ac_if,
1331                           "host coalescing engine failed to idle\n");
1332                 return(ENXIO);
1333         }
1334
1335         /* Set up host coalescing defaults */
1336         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1337         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1338         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1339         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1340         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1341             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1342                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1343                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1344         }
1345         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1346         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1347
1348         /* Set up address of statistics block */
1349         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1350             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1351                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0);
1352                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1353                     vtophys(&sc->bge_rdata->bge_info.bge_stats));
1354
1355                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1356                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1357                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1358         }
1359
1360         /* Set up address of status block */
1361         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0);
1362         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1363             vtophys(&sc->bge_rdata->bge_status_block));
1364
1365         sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
1366         sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
1367
1368         /* Turn on host coalescing state machine */
1369         CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1370
1371         /* Turn on RX BD completion state machine and enable attentions */
1372         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1373             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1374
1375         /* Turn on RX list placement state machine */
1376         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1377
1378         /* Turn on RX list selector state machine. */
1379         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1380             sc->bge_asicrev != BGE_ASICREV_BCM5750)
1381                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1382
1383         /* Turn on DMA, clear stats */
1384         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1385             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1386             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1387             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1388             (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1389
1390         /* Set misc. local control, enable interrupts on attentions */
1391         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1392
1393 #ifdef notdef
1394         /* Assert GPIO pins for PHY reset */
1395         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1396             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1397         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1398             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1399 #endif
1400
1401         /* Turn on DMA completion state machine */
1402         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1403             sc->bge_asicrev != BGE_ASICREV_BCM5750)
1404                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1405
1406         /* Turn on write DMA state machine */
1407         CSR_WRITE_4(sc, BGE_WDMA_MODE,
1408             BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1409
1410         /* Turn on read DMA state machine */
1411         CSR_WRITE_4(sc, BGE_RDMA_MODE,
1412             BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1413
1414         /* Turn on RX data completion state machine */
1415         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1416
1417         /* Turn on RX BD initiator state machine */
1418         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1419
1420         /* Turn on RX data and RX BD initiator state machine */
1421         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1422
1423         /* Turn on Mbuf cluster free state machine */
1424         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1425             sc->bge_asicrev != BGE_ASICREV_BCM5750)
1426                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1427
1428         /* Turn on send BD completion state machine */
1429         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1430
1431         /* Turn on send data completion state machine */
1432         CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1433
1434         /* Turn on send data initiator state machine */
1435         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1436
1437         /* Turn on send BD initiator state machine */
1438         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1439
1440         /* Turn on send BD selector state machine */
1441         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1442
1443         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1444         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1445             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1446
1447         /* ack/clear link change events */
1448         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1449             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1450             BGE_MACSTAT_LINK_CHANGED);
1451
1452         /* Enable PHY auto polling (for MII/GMII only) */
1453         if (sc->bge_tbi) {
1454                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1455         } else {
1456                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1457                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1458                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1459                             BGE_EVTENB_MI_INTERRUPT);
1460         }
1461
1462         /* Enable link state change attentions. */
1463         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1464
1465         return(0);
1466 }
1467
1468 /*
1469  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1470  * against our list and return its name if we find a match. Note
1471  * that since the Broadcom controller contains VPD support, we
1472  * can get the device name string from the controller itself instead
1473  * of the compiled-in string. This is a little slow, but it guarantees
1474  * we'll always announce the right product name.
1475  */
1476 static int
1477 bge_probe(device_t dev)
1478 {
1479         struct bge_softc *sc;
1480         struct bge_type *t;
1481         char *descbuf;
1482         uint16_t product, vendor;
1483
1484         product = pci_get_device(dev);
1485         vendor = pci_get_vendor(dev);
1486
1487         for (t = bge_devs; t->bge_name != NULL; t++) {
1488                 if (vendor == t->bge_vid && product == t->bge_did)
1489                         break;
1490         }
1491
1492         if (t->bge_name == NULL)
1493                 return(ENXIO);
1494
1495         sc = device_get_softc(dev);
1496 #ifdef notdef
1497         sc->bge_dev = dev;
1498
1499         bge_vpd_read(sc);
1500         device_set_desc(dev, sc->bge_vpd_prodname);
1501 #endif
1502         descbuf = kmalloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK);
1503         ksnprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name,
1504             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1505         device_set_desc_copy(dev, descbuf);
1506         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL)
1507                 sc->bge_no_3_led = 1;
1508         kfree(descbuf, M_TEMP);
1509         return(0);
1510 }
1511
1512 static int
1513 bge_attach(device_t dev)
1514 {
1515         struct ifnet *ifp;
1516         struct bge_softc *sc;
1517         uint32_t hwcfg = 0;
1518         uint32_t mac_addr = 0;
1519         int error = 0, rid;
1520         uint8_t ether_addr[ETHER_ADDR_LEN];
1521
1522         sc = device_get_softc(dev);
1523         sc->bge_dev = dev;
1524         callout_init(&sc->bge_stat_timer);
1525         lwkt_serialize_init(&sc->bge_jslot_serializer);
1526
1527         /*
1528          * Map control/status registers.
1529          */
1530         pci_enable_busmaster(dev);
1531
1532         rid = BGE_PCI_BAR0;
1533         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1534             RF_ACTIVE);
1535
1536         if (sc->bge_res == NULL) {
1537                 device_printf(dev, "couldn't map memory\n");
1538                 error = ENXIO;
1539                 return(error);
1540         }
1541
1542         sc->bge_btag = rman_get_bustag(sc->bge_res);
1543         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1544         sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res);
1545
1546         /* Allocate interrupt */
1547         rid = 0;
1548
1549         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1550             RF_SHAREABLE | RF_ACTIVE);
1551
1552         if (sc->bge_irq == NULL) {
1553                 device_printf(dev, "couldn't map interrupt\n");
1554                 error = ENXIO;
1555                 goto fail;
1556         }
1557
1558         /* Save ASIC rev. */
1559         sc->bge_chipid =
1560             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1561             BGE_PCIMISCCTL_ASICREV;
1562         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1563         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1564
1565         /*
1566          * Treat the 5714 like the 5750 until we have more info
1567          * on this chip.
1568          */
1569         if (sc->bge_asicrev == BGE_ASICREV_BCM5714)
1570                 sc->bge_asicrev = BGE_ASICREV_BCM5750;
1571
1572         /*
1573          * XXX: Broadcom Linux driver.  Not in specs or eratta.
1574          * PCI-Express?
1575          */
1576         if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
1577                 uint32_t v;
1578
1579                 v = pci_read_config(dev, BGE_PCI_MSI_CAPID, 4);
1580                 if (((v >> 8) & 0xff) == BGE_PCIE_MSI_CAPID) {
1581                         v = pci_read_config(dev, BGE_PCIE_MSI_CAPID, 4);
1582                         if ((v & 0xff) == BGE_PCIE_MSI_CAPID_VAL)
1583                                 sc->bge_pcie = 1;
1584                 }
1585         }
1586
1587         ifp = &sc->arpcom.ac_if;
1588         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1589
1590         /* Try to reset the chip. */
1591         bge_reset(sc);
1592
1593         if (bge_chipinit(sc)) {
1594                 device_printf(dev, "chip initialization failed\n");
1595                 error = ENXIO;
1596                 goto fail;
1597         }
1598
1599         /*
1600          * Get station address from the EEPROM.
1601          */
1602         mac_addr = bge_readmem_ind(sc, 0x0c14);
1603         if ((mac_addr >> 16) == 0x484b) {
1604                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1605                 ether_addr[1] = (uint8_t)mac_addr;
1606                 mac_addr = bge_readmem_ind(sc, 0x0c18);
1607                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1608                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1609                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1610                 ether_addr[5] = (uint8_t)mac_addr;
1611         } else if (bge_read_eeprom(sc, ether_addr,
1612             BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1613                 device_printf(dev, "failed to read station address\n");
1614                 error = ENXIO;
1615                 goto fail;
1616         }
1617
1618         /* Allocate the general information block and ring buffers. */
1619         sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF,
1620             M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
1621
1622         if (sc->bge_rdata == NULL) {
1623                 error = ENXIO;
1624                 device_printf(dev, "no memory for list buffers!\n");
1625                 goto fail;
1626         }
1627
1628         bzero(sc->bge_rdata, sizeof(struct bge_ring_data));
1629
1630         /*
1631          * Try to allocate memory for jumbo buffers.
1632          * The 5705/5750 does not appear to support jumbo frames.
1633          */
1634         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1635             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1636                 if (bge_alloc_jumbo_mem(sc)) {
1637                         device_printf(dev, "jumbo buffer allocation failed\n");
1638                         error = ENXIO;
1639                         goto fail;
1640                 }
1641         }
1642
1643         /* Set default tuneable values. */
1644         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1645         sc->bge_rx_coal_ticks = 150;
1646         sc->bge_tx_coal_ticks = 150;
1647         sc->bge_rx_max_coal_bds = 64;
1648         sc->bge_tx_max_coal_bds = 128;
1649
1650         /* 5705/5750 limits RX return ring to 512 entries. */
1651         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1652             sc->bge_asicrev == BGE_ASICREV_BCM5750)
1653                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1654         else
1655                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1656
1657         /* Set up ifnet structure */
1658         ifp->if_softc = sc;
1659         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1660         ifp->if_ioctl = bge_ioctl;
1661         ifp->if_start = bge_start;
1662         ifp->if_watchdog = bge_watchdog;
1663         ifp->if_init = bge_init;
1664         ifp->if_mtu = ETHERMTU;
1665         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1666         ifq_set_ready(&ifp->if_snd);
1667         ifp->if_hwassist = BGE_CSUM_FEATURES;
1668         ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
1669             IFCAP_VLAN_MTU;
1670         ifp->if_capenable = ifp->if_capabilities;
1671
1672         /*
1673          * Figure out what sort of media we have by checking the
1674          * hardware config word in the first 32k of NIC internal memory,
1675          * or fall back to examining the EEPROM if necessary.
1676          * Note: on some BCM5700 cards, this value appears to be unset.
1677          * If that's the case, we have to rely on identifying the NIC
1678          * by its PCI subsystem ID, as we do below for the SysKonnect
1679          * SK-9D41.
1680          */
1681         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1682                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1683         else {
1684                 bge_read_eeprom(sc, (caddr_t)&hwcfg,
1685                                 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
1686                 hwcfg = ntohl(hwcfg);
1687         }
1688
1689         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1690                 sc->bge_tbi = 1;
1691
1692         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1693         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1694                 sc->bge_tbi = 1;
1695
1696         if (sc->bge_tbi) {
1697                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1698                     bge_ifmedia_upd, bge_ifmedia_sts);
1699                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1700                 ifmedia_add(&sc->bge_ifmedia,
1701                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1702                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1703                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1704                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
1705         } else {
1706                 /*
1707                  * Do transceiver setup.
1708                  */
1709                 if (mii_phy_probe(dev, &sc->bge_miibus,
1710                     bge_ifmedia_upd, bge_ifmedia_sts)) {
1711                         device_printf(dev, "MII without any PHY!\n");
1712                         error = ENXIO;
1713                         goto fail;
1714                 }
1715         }
1716
1717         /*
1718          * When using the BCM5701 in PCI-X mode, data corruption has
1719          * been observed in the first few bytes of some received packets.
1720          * Aligning the packet buffer in memory eliminates the corruption.
1721          * Unfortunately, this misaligns the packet payloads.  On platforms
1722          * which do not support unaligned accesses, we will realign the
1723          * payloads by copying the received packets.
1724          */
1725         switch (sc->bge_chipid) {
1726         case BGE_CHIPID_BCM5701_A0:
1727         case BGE_CHIPID_BCM5701_B0:
1728         case BGE_CHIPID_BCM5701_B2:
1729         case BGE_CHIPID_BCM5701_B5:
1730                 /* If in PCI-X mode, work around the alignment bug. */
1731                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
1732                     (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) ==
1733                     BGE_PCISTATE_PCI_BUSSPEED)
1734                         sc->bge_rx_alignment_bug = 1;
1735                 break;
1736         }
1737
1738         /*
1739          * Call MI attach routine.
1740          */
1741         ether_ifattach(ifp, ether_addr, NULL);
1742
1743         error = bus_setup_intr(dev, sc->bge_irq, INTR_NETSAFE,
1744                                bge_intr, sc, &sc->bge_intrhand,
1745                                ifp->if_serializer);
1746         if (error) {
1747                 ether_ifdetach(ifp);
1748                 device_printf(dev, "couldn't set up irq\n");
1749                 goto fail;
1750         }
1751
1752         return(0);
1753
1754 fail:
1755         bge_detach(dev);
1756
1757         return(error);
1758 }
1759
1760 static int
1761 bge_detach(device_t dev)
1762 {
1763         struct bge_softc *sc = device_get_softc(dev);
1764         struct ifnet *ifp = &sc->arpcom.ac_if;
1765
1766         if (device_is_attached(dev)) {
1767                 lwkt_serialize_enter(ifp->if_serializer);
1768                 bge_stop(sc);
1769                 bge_reset(sc);
1770                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1771                 lwkt_serialize_exit(ifp->if_serializer);
1772
1773                 ether_ifdetach(ifp);
1774         }
1775         if (sc->bge_tbi)
1776                 ifmedia_removeall(&sc->bge_ifmedia);
1777         if (sc->bge_miibus)
1778                 device_delete_child(dev, sc->bge_miibus);
1779         bus_generic_detach(dev);
1780
1781         bge_release_resources(sc);
1782
1783         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1784             sc->bge_asicrev != BGE_ASICREV_BCM5750)
1785                 bge_free_jumbo_mem(sc);
1786
1787         return(0);
1788 }
1789
1790 static void
1791 bge_release_resources(struct bge_softc *sc)
1792 {
1793         device_t dev;
1794
1795         dev = sc->bge_dev;
1796
1797         if (sc->bge_vpd_prodname != NULL)
1798                 kfree(sc->bge_vpd_prodname, M_DEVBUF);
1799
1800         if (sc->bge_vpd_readonly != NULL)
1801                 kfree(sc->bge_vpd_readonly, M_DEVBUF);
1802
1803         if (sc->bge_irq != NULL)
1804                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1805
1806         if (sc->bge_res != NULL)
1807                 bus_release_resource(dev, SYS_RES_MEMORY,
1808                     BGE_PCI_BAR0, sc->bge_res);
1809
1810         if (sc->bge_rdata != NULL)
1811                 contigfree(sc->bge_rdata, sizeof(struct bge_ring_data),
1812                            M_DEVBUF);
1813
1814         return;
1815 }
1816
1817 static void
1818 bge_reset(struct bge_softc *sc)
1819 {
1820         device_t dev;
1821         uint32_t cachesize, command, pcistate, reset;
1822         int i, val = 0;
1823
1824         dev = sc->bge_dev;
1825
1826         /* Save some important PCI state. */
1827         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
1828         command = pci_read_config(dev, BGE_PCI_CMD, 4);
1829         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
1830
1831         pci_write_config(dev, BGE_PCI_MISC_CTL,
1832             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1833             BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1834
1835         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
1836
1837         /* XXX: Broadcom Linux driver. */
1838         if (sc->bge_pcie) {
1839                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
1840                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
1841                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
1842                         /* Prevent PCIE link training during global reset */
1843                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
1844                         reset |= (1<<29);
1845                 }
1846         }
1847
1848         /* Issue global reset */
1849         bge_writereg_ind(sc, BGE_MISC_CFG, reset);
1850
1851         DELAY(1000);
1852
1853         /* XXX: Broadcom Linux driver. */
1854         if (sc->bge_pcie) {
1855                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
1856                         uint32_t v;
1857
1858                         DELAY(500000); /* wait for link training to complete */
1859                         v = pci_read_config(dev, 0xc4, 4);
1860                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
1861                 }
1862                 /* Set PCIE max payload size and clear error status. */
1863                 pci_write_config(dev, 0xd8, 0xf5000, 4);
1864         }
1865
1866         /* Reset some of the PCI state that got zapped by reset */
1867         pci_write_config(dev, BGE_PCI_MISC_CTL,
1868             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1869             BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1870         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
1871         pci_write_config(dev, BGE_PCI_CMD, command, 4);
1872         bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
1873
1874         /* Enable memory arbiter. */
1875         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1876                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
1877
1878         /*
1879          * Prevent PXE restart: write a magic number to the
1880          * general communications memory at 0xB50.
1881          */
1882         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1883         /*
1884          * Poll the value location we just wrote until
1885          * we see the 1's complement of the magic number.
1886          * This indicates that the firmware initialization
1887          * is complete.
1888          */
1889         for (i = 0; i < BGE_TIMEOUT; i++) {
1890                 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
1891                 if (val == ~BGE_MAGIC_NUMBER)
1892                         break;
1893                 DELAY(10);
1894         }
1895
1896         if (i == BGE_TIMEOUT) {
1897                 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out\n");
1898                 return;
1899         }
1900
1901         /*
1902          * XXX Wait for the value of the PCISTATE register to
1903          * return to its original pre-reset state. This is a
1904          * fairly good indicator of reset completion. If we don't
1905          * wait for the reset to fully complete, trying to read
1906          * from the device's non-PCI registers may yield garbage
1907          * results.
1908          */
1909         for (i = 0; i < BGE_TIMEOUT; i++) {
1910                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
1911                         break;
1912                 DELAY(10);
1913         }
1914
1915         /* Fix up byte swapping */
1916         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|
1917             BGE_MODECTL_BYTESWAP_DATA);
1918
1919         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1920
1921         /*
1922          * The 5704 in TBI mode apparently needs some special
1923          * adjustment to insure the SERDES drive level is set
1924          * to 1.2V.
1925          */
1926         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && sc->bge_tbi) {
1927                 uint32_t serdescfg;
1928
1929                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
1930                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
1931                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
1932         }
1933
1934         /* XXX: Broadcom Linux driver. */
1935         if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
1936                 uint32_t v;
1937
1938                 v = CSR_READ_4(sc, 0x7c00);
1939                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
1940         }
1941
1942         DELAY(10000);
1943 }
1944
1945 /*
1946  * Frame reception handling. This is called if there's a frame
1947  * on the receive return list.
1948  *
1949  * Note: we have to be able to handle two possibilities here:
1950  * 1) the frame is from the jumbo recieve ring
1951  * 2) the frame is from the standard receive ring
1952  */
1953
1954 static void
1955 bge_rxeof(struct bge_softc *sc)
1956 {
1957         struct ifnet *ifp;
1958         int stdcnt = 0, jumbocnt = 0;
1959
1960         ifp = &sc->arpcom.ac_if;
1961
1962         while(sc->bge_rx_saved_considx !=
1963             sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
1964                 struct bge_rx_bd        *cur_rx;
1965                 uint32_t                rxidx;
1966                 struct mbuf             *m = NULL;
1967                 uint16_t                vlan_tag = 0;
1968                 int                     have_tag = 0;
1969
1970                 cur_rx =
1971             &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx];
1972
1973                 rxidx = cur_rx->bge_idx;
1974                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
1975
1976                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
1977                         have_tag = 1;
1978                         vlan_tag = cur_rx->bge_vlan_tag;
1979                 }
1980
1981                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
1982                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1983                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
1984                         sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
1985                         jumbocnt++;
1986                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1987                                 ifp->if_ierrors++;
1988                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1989                                 continue;
1990                         }
1991                         if (bge_newbuf_jumbo(sc,
1992                             sc->bge_jumbo, NULL) == ENOBUFS) {
1993                                 ifp->if_ierrors++;
1994                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1995                                 continue;
1996                         }
1997                 } else {
1998                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1999                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2000                         sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2001                         stdcnt++;
2002                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2003                                 ifp->if_ierrors++;
2004                                 bge_newbuf_std(sc, sc->bge_std, m);
2005                                 continue;
2006                         }
2007                         if (bge_newbuf_std(sc, sc->bge_std,
2008                             NULL) == ENOBUFS) {
2009                                 ifp->if_ierrors++;
2010                                 bge_newbuf_std(sc, sc->bge_std, m);
2011                                 continue;
2012                         }
2013                 }
2014
2015                 ifp->if_ipackets++;
2016 #ifndef __i386__
2017                 /*
2018                  * The i386 allows unaligned accesses, but for other
2019                  * platforms we must make sure the payload is aligned.
2020                  */
2021                 if (sc->bge_rx_alignment_bug) {
2022                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2023                             cur_rx->bge_len);
2024                         m->m_data += ETHER_ALIGN;
2025                 }
2026 #endif
2027                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2028                 m->m_pkthdr.rcvif = ifp;
2029
2030 #if 0 /* currently broken for some packets, possibly related to TCP options */
2031                 if (ifp->if_hwassist) {
2032                         m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2033                         if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2034                                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2035                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2036                                 m->m_pkthdr.csum_data =
2037                                     cur_rx->bge_tcp_udp_csum;
2038                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
2039                         }
2040                 }
2041 #endif
2042
2043                 /*
2044                  * If we received a packet with a vlan tag, pass it
2045                  * to vlan_input() instead of ether_input().
2046                  */
2047                 if (have_tag) {
2048                         VLAN_INPUT_TAG(m, vlan_tag);
2049                         have_tag = vlan_tag = 0;
2050                 } else {
2051                         ifp->if_input(ifp, m);
2052                 }
2053         }
2054
2055         CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2056         if (stdcnt)
2057                 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2058         if (jumbocnt)
2059                 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2060 }
2061
2062 static void
2063 bge_txeof(struct bge_softc *sc)
2064 {
2065         struct bge_tx_bd *cur_tx = NULL;
2066         struct ifnet *ifp;
2067
2068         ifp = &sc->arpcom.ac_if;
2069
2070         /*
2071          * Go through our tx ring and free mbufs for those
2072          * frames that have been sent.
2073          */
2074         while (sc->bge_tx_saved_considx !=
2075             sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
2076                 uint32_t                idx = 0;
2077
2078                 idx = sc->bge_tx_saved_considx;
2079                 cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
2080                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2081                         ifp->if_opackets++;
2082                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2083                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2084                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2085                 }
2086                 sc->bge_txcnt--;
2087                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2088                 ifp->if_timer = 0;
2089         }
2090
2091         if (cur_tx != NULL)
2092                 ifp->if_flags &= ~IFF_OACTIVE;
2093 }
2094
2095 static void
2096 bge_intr(void *xsc)
2097 {
2098         struct bge_softc *sc = xsc;
2099         struct ifnet *ifp = &sc->arpcom.ac_if;
2100         uint32_t status, statusword, mimode;
2101
2102         /* XXX */
2103         statusword = loadandclear(&sc->bge_rdata->bge_status_block.bge_status);
2104
2105 #ifdef notdef
2106         /* Avoid this for now -- checking this register is expensive. */
2107         /* Make sure this is really our interrupt. */
2108         if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
2109                 return;
2110 #endif
2111         /* Ack interrupt and stop others from occuring. */
2112         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2113
2114         /*
2115          * Process link state changes.
2116          * Grrr. The link status word in the status block does
2117          * not work correctly on the BCM5700 rev AX and BX chips,
2118          * according to all available information. Hence, we have
2119          * to enable MII interrupts in order to properly obtain
2120          * async link changes. Unfortunately, this also means that
2121          * we have to read the MAC status register to detect link
2122          * changes, thereby adding an additional register access to
2123          * the interrupt handler.
2124          */
2125
2126         if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
2127                 status = CSR_READ_4(sc, BGE_MAC_STS);
2128                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
2129                         sc->bge_link = 0;
2130                         callout_stop(&sc->bge_stat_timer);
2131                         bge_tick_serialized(sc);
2132                         /* Clear the interrupt */
2133                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2134                             BGE_EVTENB_MI_INTERRUPT);
2135                         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
2136                         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
2137                             BRGPHY_INTRS);
2138                 }
2139         } else {
2140                 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) {
2141                         /*
2142                          * Sometimes PCS encoding errors are detected in
2143                          * TBI mode (on fiber NICs), and for some reason
2144                          * the chip will signal them as link changes.
2145                          * If we get a link change event, but the 'PCS
2146                          * encoding error' bit in the MAC status register
2147                          * is set, don't bother doing a link check.
2148                          * This avoids spurious "gigabit link up" messages
2149                          * that sometimes appear on fiber NICs during
2150                          * periods of heavy traffic. (There should be no
2151                          * effect on copper NICs.)
2152                          *
2153                          * If we do have a copper NIC (bge_tbi == 0) then
2154                          * check that the AUTOPOLL bit is set before
2155                          * processing the event as a real link change.
2156                          * Turning AUTOPOLL on and off in the MII read/write
2157                          * functions will often trigger a link status
2158                          * interrupt for no reason.
2159                          */
2160                         status = CSR_READ_4(sc, BGE_MAC_STS);
2161                         mimode = CSR_READ_4(sc, BGE_MI_MODE);
2162                         if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR |
2163                                         BGE_MACSTAT_MI_COMPLETE)) &&
2164                             (!sc->bge_tbi && (mimode & BGE_MIMODE_AUTOPOLL))) {
2165                                 sc->bge_link = 0;
2166                                 callout_stop(&sc->bge_stat_timer);
2167                                 bge_tick_serialized(sc);
2168                         }
2169                         sc->bge_link = 0;
2170                         callout_stop(&sc->bge_stat_timer);
2171                         bge_tick_serialized(sc);
2172                         /* Clear the interrupt */
2173                         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
2174                             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
2175                             BGE_MACSTAT_LINK_CHANGED);
2176
2177                         /* Force flush the status block cached by PCI bridge */
2178                         CSR_READ_4(sc, BGE_MBX_IRQ0_LO);
2179                 }
2180         }
2181
2182         if (ifp->if_flags & IFF_RUNNING) {
2183                 /* Check RX return ring producer/consumer */
2184                 bge_rxeof(sc);
2185
2186                 /* Check TX ring producer/consumer */
2187                 bge_txeof(sc);
2188         }
2189
2190         bge_handle_events(sc);
2191
2192         /* Re-enable interrupts. */
2193         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2194
2195         if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
2196                 (*ifp->if_start)(ifp);
2197 }
2198
2199 static void
2200 bge_tick(void *xsc)
2201 {
2202         struct bge_softc *sc = xsc;
2203         struct ifnet *ifp = &sc->arpcom.ac_if;
2204
2205         lwkt_serialize_enter(ifp->if_serializer);
2206         bge_tick_serialized(xsc);
2207         lwkt_serialize_exit(ifp->if_serializer);
2208 }
2209
2210 static void
2211 bge_tick_serialized(void *xsc)
2212 {
2213         struct bge_softc *sc = xsc;
2214         struct ifnet *ifp = &sc->arpcom.ac_if;
2215         struct mii_data *mii = NULL;
2216         struct ifmedia *ifm = NULL;
2217
2218         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
2219             sc->bge_asicrev == BGE_ASICREV_BCM5750)
2220                 bge_stats_update_regs(sc);
2221         else
2222                 bge_stats_update(sc);
2223
2224         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2225
2226         if (sc->bge_link) {
2227                 return;
2228         }
2229
2230         if (sc->bge_tbi) {
2231                 ifm = &sc->bge_ifmedia;
2232                 if (CSR_READ_4(sc, BGE_MAC_STS) &
2233                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
2234                         sc->bge_link++;
2235                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2236                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
2237                                            BGE_MACMODE_TBI_SEND_CFGS);
2238                         }
2239                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
2240                         if_printf(ifp, "gigabit link up\n");
2241                         if (!ifq_is_empty(&ifp->if_snd))
2242                                 (*ifp->if_start)(ifp);
2243                 }
2244                 return;
2245         }
2246
2247         mii = device_get_softc(sc->bge_miibus);
2248         mii_tick(mii);
2249
2250         if (!sc->bge_link) {
2251                 mii_pollstat(mii);
2252                 if (mii->mii_media_status & IFM_ACTIVE &&
2253                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2254                         sc->bge_link++;
2255                         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
2256                             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
2257                                 if_printf(ifp, "gigabit link up\n");
2258                         if (!ifq_is_empty(&ifp->if_snd))
2259                                 (*ifp->if_start)(ifp);
2260                 }
2261         }
2262 }
2263
2264 static void
2265 bge_stats_update_regs(struct bge_softc *sc)
2266 {
2267         struct ifnet *ifp = &sc->arpcom.ac_if;
2268         struct bge_mac_stats_regs stats;
2269         uint32_t *s;
2270         int i;
2271
2272         s = (uint32_t *)&stats;
2273         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2274                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2275                 s++;
2276         }
2277
2278         ifp->if_collisions +=
2279            (stats.dot3StatsSingleCollisionFrames +
2280            stats.dot3StatsMultipleCollisionFrames +
2281            stats.dot3StatsExcessiveCollisions +
2282            stats.dot3StatsLateCollisions) -
2283            ifp->if_collisions;
2284 }
2285
2286 static void
2287 bge_stats_update(struct bge_softc *sc)
2288 {
2289         struct ifnet *ifp = &sc->arpcom.ac_if;
2290         struct bge_stats *stats;
2291
2292         stats = (struct bge_stats *)(sc->bge_vhandle +
2293             BGE_MEMWIN_START + BGE_STATS_BLOCK);
2294
2295         ifp->if_collisions +=
2296            (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo +
2297            stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo +
2298            stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo +
2299            stats->txstats.dot3StatsLateCollisions.bge_addr_lo) -
2300            ifp->if_collisions;
2301
2302 #ifdef notdef
2303         ifp->if_collisions +=
2304            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2305            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2306            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2307            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2308            ifp->if_collisions;
2309 #endif
2310 }
2311
2312 /*
2313  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2314  * pointers to descriptors.
2315  */
2316 static int
2317 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
2318 {
2319         struct bge_tx_bd *f = NULL;
2320         struct mbuf *m;
2321         uint32_t frag, cur, cnt = 0;
2322         uint16_t csum_flags = 0;
2323         struct ifvlan *ifv = NULL;
2324
2325         if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2326             m_head->m_pkthdr.rcvif != NULL &&
2327             m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2328                 ifv = m_head->m_pkthdr.rcvif->if_softc;
2329
2330         m = m_head;
2331         cur = frag = *txidx;
2332
2333         if (m_head->m_pkthdr.csum_flags) {
2334                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2335                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2336                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2337                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2338                 if (m_head->m_flags & M_LASTFRAG)
2339                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2340                 else if (m_head->m_flags & M_FRAG)
2341                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2342         }
2343         /*
2344          * Start packing the mbufs in this chain into
2345          * the fragment pointers. Stop when we run out
2346          * of fragments or hit the end of the mbuf chain.
2347          */
2348         for (m = m_head; m != NULL; m = m->m_next) {
2349                 if (m->m_len != 0) {
2350                         f = &sc->bge_rdata->bge_tx_ring[frag];
2351                         if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
2352                                 break;
2353                         BGE_HOSTADDR(f->bge_addr,
2354                             vtophys(mtod(m, vm_offset_t)));
2355                         f->bge_len = m->m_len;
2356                         f->bge_flags = csum_flags;
2357                         if (ifv != NULL) {
2358                                 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2359                                 f->bge_vlan_tag = ifv->ifv_tag;
2360                         } else {
2361                                 f->bge_vlan_tag = 0;
2362                         }
2363                         /*
2364                          * Sanity check: avoid coming within 16 descriptors
2365                          * of the end of the ring.
2366                          */
2367                         if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16)
2368                                 return(ENOBUFS);
2369                         cur = frag;
2370                         BGE_INC(frag, BGE_TX_RING_CNT);
2371                         cnt++;
2372                 }
2373         }
2374
2375         if (m != NULL)
2376                 return(ENOBUFS);
2377
2378         if (frag == sc->bge_tx_saved_considx)
2379                 return(ENOBUFS);
2380
2381         sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
2382         sc->bge_cdata.bge_tx_chain[cur] = m_head;
2383         sc->bge_txcnt += cnt;
2384
2385         *txidx = frag;
2386
2387         return(0);
2388 }
2389
2390 /*
2391  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2392  * to the mbuf data regions directly in the transmit descriptors.
2393  */
2394 static void
2395 bge_start(struct ifnet *ifp)
2396 {
2397         struct bge_softc *sc;
2398         struct mbuf *m_head = NULL;
2399         uint32_t prodidx = 0;
2400         int need_trans;
2401
2402         sc = ifp->if_softc;
2403
2404         if (!sc->bge_link)
2405                 return;
2406
2407         prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO);
2408
2409         need_trans = 0;
2410         while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2411                 m_head = ifq_poll(&ifp->if_snd);
2412                 if (m_head == NULL)
2413                         break;
2414
2415                 /*
2416                  * XXX
2417                  * safety overkill.  If this is a fragmented packet chain
2418                  * with delayed TCP/UDP checksums, then only encapsulate
2419                  * it if we have enough descriptors to handle the entire
2420                  * chain at once.
2421                  * (paranoia -- may not actually be needed)
2422                  */
2423                 if (m_head->m_flags & M_FIRSTFRAG &&
2424                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2425                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2426                             m_head->m_pkthdr.csum_data + 16) {
2427                                 ifp->if_flags |= IFF_OACTIVE;
2428                                 break;
2429                         }
2430                 }
2431
2432                 /*
2433                  * Pack the data into the transmit ring. If we
2434                  * don't have room, set the OACTIVE flag and wait
2435                  * for the NIC to drain the ring.
2436                  */
2437                 if (bge_encap(sc, m_head, &prodidx)) {
2438                         ifp->if_flags |= IFF_OACTIVE;
2439                         break;
2440                 }
2441                 ifq_dequeue(&ifp->if_snd, m_head);
2442                 need_trans = 1;
2443
2444                 BPF_MTAP(ifp, m_head);
2445         }
2446
2447         if (!need_trans)
2448                 return;
2449
2450         /* Transmit */
2451         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2452         /* 5700 b2 errata */
2453         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2454                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2455
2456         /*
2457          * Set a timeout in case the chip goes out to lunch.
2458          */
2459         ifp->if_timer = 5;
2460 }
2461
2462 static void
2463 bge_init(void *xsc)
2464 {
2465         struct bge_softc *sc = xsc;
2466         struct ifnet *ifp = &sc->arpcom.ac_if;
2467         uint16_t *m;
2468
2469         if (ifp->if_flags & IFF_RUNNING) {
2470                 return;
2471         }
2472
2473         /* Cancel pending I/O and flush buffers. */
2474         bge_stop(sc);
2475         bge_reset(sc);
2476         bge_chipinit(sc);
2477
2478         /*
2479          * Init the various state machines, ring
2480          * control blocks and firmware.
2481          */
2482         if (bge_blockinit(sc)) {
2483                 if_printf(ifp, "initialization failure\n");
2484                 return;
2485         }
2486
2487         /* Specify MTU. */
2488         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2489             ETHER_HDR_LEN + ETHER_CRC_LEN);
2490
2491         /* Load our MAC address. */
2492         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2493         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2494         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2495
2496         /* Enable or disable promiscuous mode as needed. */
2497         if (ifp->if_flags & IFF_PROMISC) {
2498                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2499         } else {
2500                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2501         }
2502
2503         /* Program multicast filter. */
2504         bge_setmulti(sc);
2505
2506         /* Init RX ring. */
2507         bge_init_rx_ring_std(sc);
2508
2509         /*
2510          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2511          * memory to insure that the chip has in fact read the first
2512          * entry of the ring.
2513          */
2514         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2515                 uint32_t                v, i;
2516                 for (i = 0; i < 10; i++) {
2517                         DELAY(20);
2518                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2519                         if (v == (MCLBYTES - ETHER_ALIGN))
2520                                 break;
2521                 }
2522                 if (i == 10)
2523                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
2524         }
2525
2526         /* Init jumbo RX ring. */
2527         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2528                 bge_init_rx_ring_jumbo(sc);
2529
2530         /* Init our RX return ring index */
2531         sc->bge_rx_saved_considx = 0;
2532
2533         /* Init TX ring. */
2534         bge_init_tx_ring(sc);
2535
2536         /* Turn on transmitter */
2537         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2538
2539         /* Turn on receiver */
2540         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2541
2542         /* Tell firmware we're alive. */
2543         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2544
2545         /* Enable host interrupts. */
2546         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2547         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2548         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2549
2550         bge_ifmedia_upd(ifp);
2551
2552         ifp->if_flags |= IFF_RUNNING;
2553         ifp->if_flags &= ~IFF_OACTIVE;
2554
2555         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2556 }
2557
2558 /*
2559  * Set media options.
2560  */
2561 static int
2562 bge_ifmedia_upd(struct ifnet *ifp)
2563 {
2564         struct bge_softc *sc = ifp->if_softc;
2565         struct ifmedia *ifm = &sc->bge_ifmedia;
2566         struct mii_data *mii;
2567
2568         /* If this is a 1000baseX NIC, enable the TBI port. */
2569         if (sc->bge_tbi) {
2570                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2571                         return(EINVAL);
2572                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2573                 case IFM_AUTO:
2574                         /*
2575                          * The BCM5704 ASIC appears to have a special
2576                          * mechanism for programming the autoneg
2577                          * advertisement registers in TBI mode.
2578                          */
2579                         if (!bge_fake_autoneg &&
2580                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2581                                 uint32_t sgdig;
2582
2583                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
2584                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
2585                                 sgdig |= BGE_SGDIGCFG_AUTO |
2586                                          BGE_SGDIGCFG_PAUSE_CAP |
2587                                          BGE_SGDIGCFG_ASYM_PAUSE;
2588                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
2589                                             sgdig | BGE_SGDIGCFG_SEND);
2590                                 DELAY(5);
2591                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
2592                         }
2593                         break;
2594                 case IFM_1000_SX:
2595                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2596                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
2597                                     BGE_MACMODE_HALF_DUPLEX);
2598                         } else {
2599                                 BGE_SETBIT(sc, BGE_MAC_MODE,
2600                                     BGE_MACMODE_HALF_DUPLEX);
2601                         }
2602                         break;
2603                 default:
2604                         return(EINVAL);
2605                 }
2606                 return(0);
2607         }
2608
2609         mii = device_get_softc(sc->bge_miibus);
2610         sc->bge_link = 0;
2611         if (mii->mii_instance) {
2612                 struct mii_softc *miisc;
2613                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2614                         mii_phy_reset(miisc);
2615         }
2616         mii_mediachg(mii);
2617
2618         return(0);
2619 }
2620
2621 /*
2622  * Report current media status.
2623  */
2624 static void
2625 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2626 {
2627         struct bge_softc *sc = ifp->if_softc;
2628         struct mii_data *mii;
2629
2630         if (sc->bge_tbi) {
2631                 ifmr->ifm_status = IFM_AVALID;
2632                 ifmr->ifm_active = IFM_ETHER;
2633                 if (CSR_READ_4(sc, BGE_MAC_STS) &
2634                     BGE_MACSTAT_TBI_PCS_SYNCHED)
2635                         ifmr->ifm_status |= IFM_ACTIVE;
2636                 ifmr->ifm_active |= IFM_1000_SX;
2637                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2638                         ifmr->ifm_active |= IFM_HDX;
2639                 else
2640                         ifmr->ifm_active |= IFM_FDX;
2641                 return;
2642         }
2643
2644         mii = device_get_softc(sc->bge_miibus);
2645         mii_pollstat(mii);
2646         ifmr->ifm_active = mii->mii_media_active;
2647         ifmr->ifm_status = mii->mii_media_status;
2648 }
2649
2650 static int
2651 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2652 {
2653         struct bge_softc *sc = ifp->if_softc;
2654         struct ifreq *ifr = (struct ifreq *) data;
2655         int mask, error = 0;
2656         struct mii_data *mii;
2657
2658         switch(command) {
2659         case SIOCSIFMTU:
2660                 /* Disallow jumbo frames on 5705/5750. */
2661                 if (((sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
2662                       sc->bge_asicrev == BGE_ASICREV_BCM5750) &&
2663                      ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU)
2664                         error = EINVAL;
2665                 else {
2666                         ifp->if_mtu = ifr->ifr_mtu;
2667                         ifp->if_flags &= ~IFF_RUNNING;
2668                         bge_init(sc);
2669                 }
2670                 break;
2671         case SIOCSIFFLAGS:
2672                 if (ifp->if_flags & IFF_UP) {
2673                         /*
2674                          * If only the state of the PROMISC flag changed,
2675                          * then just use the 'set promisc mode' command
2676                          * instead of reinitializing the entire NIC. Doing
2677                          * a full re-init means reloading the firmware and
2678                          * waiting for it to start up, which may take a
2679                          * second or two.
2680                          */
2681                         if (ifp->if_flags & IFF_RUNNING &&
2682                             ifp->if_flags & IFF_PROMISC &&
2683                             !(sc->bge_if_flags & IFF_PROMISC)) {
2684                                 BGE_SETBIT(sc, BGE_RX_MODE,
2685                                     BGE_RXMODE_RX_PROMISC);
2686                         } else if (ifp->if_flags & IFF_RUNNING &&
2687                             !(ifp->if_flags & IFF_PROMISC) &&
2688                             sc->bge_if_flags & IFF_PROMISC) {
2689                                 BGE_CLRBIT(sc, BGE_RX_MODE,
2690                                     BGE_RXMODE_RX_PROMISC);
2691                         } else
2692                                 bge_init(sc);
2693                 } else {
2694                         if (ifp->if_flags & IFF_RUNNING) {
2695                                 bge_stop(sc);
2696                         }
2697                 }
2698                 sc->bge_if_flags = ifp->if_flags;
2699                 error = 0;
2700                 break;
2701         case SIOCADDMULTI:
2702         case SIOCDELMULTI:
2703                 if (ifp->if_flags & IFF_RUNNING) {
2704                         bge_setmulti(sc);
2705                         error = 0;
2706                 }
2707                 break;
2708         case SIOCSIFMEDIA:
2709         case SIOCGIFMEDIA:
2710                 if (sc->bge_tbi) {
2711                         error = ifmedia_ioctl(ifp, ifr,
2712                             &sc->bge_ifmedia, command);
2713                 } else {
2714                         mii = device_get_softc(sc->bge_miibus);
2715                         error = ifmedia_ioctl(ifp, ifr,
2716                             &mii->mii_media, command);
2717                 }
2718                 break;
2719         case SIOCSIFCAP:
2720                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2721                 if (mask & IFCAP_HWCSUM) {
2722                         if (IFCAP_HWCSUM & ifp->if_capenable)
2723                                 ifp->if_capenable &= ~IFCAP_HWCSUM;
2724                         else
2725                                 ifp->if_capenable |= IFCAP_HWCSUM;
2726                 }
2727                 error = 0;
2728                 break;
2729         default:
2730                 error = ether_ioctl(ifp, command, data);
2731                 break;
2732         }
2733         return(error);
2734 }
2735
2736 static void
2737 bge_watchdog(struct ifnet *ifp)
2738 {
2739         struct bge_softc *sc = ifp->if_softc;
2740
2741         if_printf(ifp, "watchdog timeout -- resetting\n");
2742
2743         ifp->if_flags &= ~IFF_RUNNING;
2744         bge_init(sc);
2745
2746         ifp->if_oerrors++;
2747
2748         if (!ifq_is_empty(&ifp->if_snd))
2749                 ifp->if_start(ifp);
2750 }
2751
2752 /*
2753  * Stop the adapter and free any mbufs allocated to the
2754  * RX and TX lists.
2755  */
2756 static void
2757 bge_stop(struct bge_softc *sc)
2758 {
2759         struct ifnet *ifp = &sc->arpcom.ac_if;
2760         struct ifmedia_entry *ifm;
2761         struct mii_data *mii = NULL;
2762         int mtmp, itmp;
2763
2764         if (!sc->bge_tbi)
2765                 mii = device_get_softc(sc->bge_miibus);
2766
2767         callout_stop(&sc->bge_stat_timer);
2768
2769         /*
2770          * Disable all of the receiver blocks
2771          */
2772         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2773         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2774         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2775         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2776             sc->bge_asicrev != BGE_ASICREV_BCM5750)
2777                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2778         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
2779         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2780         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
2781
2782         /*
2783          * Disable all of the transmit blocks
2784          */
2785         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2786         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2787         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2788         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
2789         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
2790         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2791             sc->bge_asicrev != BGE_ASICREV_BCM5750)
2792                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2793         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2794
2795         /*
2796          * Shut down all of the memory managers and related
2797          * state machines.
2798          */
2799         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
2800         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
2801         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2802             sc->bge_asicrev != BGE_ASICREV_BCM5750)
2803                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2804         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2805         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2806         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2807             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
2808                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
2809                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2810         }
2811
2812         /* Disable host interrupts. */
2813         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2814         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2815
2816         /*
2817          * Tell firmware we're shutting down.
2818          */
2819         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2820
2821         /* Free the RX lists. */
2822         bge_free_rx_ring_std(sc);
2823
2824         /* Free jumbo RX list. */
2825         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2826             sc->bge_asicrev != BGE_ASICREV_BCM5750)
2827                 bge_free_rx_ring_jumbo(sc);
2828
2829         /* Free TX buffers. */
2830         bge_free_tx_ring(sc);
2831
2832         /*
2833          * Isolate/power down the PHY, but leave the media selection
2834          * unchanged so that things will be put back to normal when
2835          * we bring the interface back up.
2836          */
2837         if (!sc->bge_tbi) {
2838                 itmp = ifp->if_flags;
2839                 ifp->if_flags |= IFF_UP;
2840                 ifm = mii->mii_media.ifm_cur;
2841                 mtmp = ifm->ifm_media;
2842                 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2843                 mii_mediachg(mii);
2844                 ifm->ifm_media = mtmp;
2845                 ifp->if_flags = itmp;
2846         }
2847
2848         sc->bge_link = 0;
2849
2850         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
2851
2852         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2853 }
2854
2855 /*
2856  * Stop all chip I/O so that the kernel's probe routines don't
2857  * get confused by errant DMAs when rebooting.
2858  */
2859 static void
2860 bge_shutdown(device_t dev)
2861 {
2862         struct bge_softc *sc = device_get_softc(dev);
2863
2864         bge_stop(sc);
2865         bge_reset(sc);
2866 }