2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 1997 KATO Takenori.
5 * Copyright (c) 2001 Tamotsu Hattori.
6 * Copyright (c) 2001 Mitsuru IWASAKI.
9 * This code is derived from software contributed to Berkeley by
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.80.2.15 2003/04/11 17:06:41 jhb Exp $
42 * $DragonFly: src/sys/platform/pc32/i386/identcpu.c,v 1.15 2006/12/23 00:27:03 swildner Exp $
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/sysctl.h>
53 #include <machine/asmacros.h>
54 #include <machine/clock.h>
55 #include <machine/cputypes.h>
56 #include <machine/segments.h>
57 #include <machine/specialreg.h>
58 #include <machine/md_var.h>
60 #include <machine_base/isa/intr_machdep.h>
62 #define IDENTBLUE_CYRIX486 0
63 #define IDENTBLUE_IBMCPU 1
64 #define IDENTBLUE_CYRIXM2 2
66 /* XXX - should be in header file: */
67 void printcpuinfo(void);
68 void finishidentcpu(void);
69 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
70 void enable_K5_wt_alloc(void);
71 void enable_K6_wt_alloc(void);
72 void enable_K6_2_wt_alloc(void);
74 void panicifcpuunsupported(void);
76 static void identifycyrix(void);
77 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
78 static void print_AMD_features(void);
80 static void print_AMD_info(void);
81 static void print_AMD_assoc(int i);
82 static void print_transmeta_info(void);
83 static void setup_tmx86_longrun(void);
85 int cpu_class = CPUCLASS_386;
86 u_int cpu_exthigh; /* Highest arg to extended CPUID */
87 u_int cyrix_did; /* Device ID of Cyrix CPU */
88 char machine[] = MACHINE;
89 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
90 machine, 0, "Machine class");
92 static char cpu_model[128];
93 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
94 cpu_model, 0, "Machine model");
96 static char cpu_brand[48];
98 #define MAX_ADDITIONAL_INFO 16
100 static const char *additional_cpu_info_ary[MAX_ADDITIONAL_INFO];
101 static u_int additional_cpu_info_count;
103 #define MAX_BRAND_INDEX 23
106 * Brand ID's according to Intel document AP-485, number 241618-31, published
107 * September 2006, page 42.
109 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
113 "Intel Pentium III Xeon",
115 NULL, /* Unspecified */
116 "Mobile Intel Pentium III-M",
117 "Mobile Intel Celeron",
123 NULL, /* Unspecified */
124 "Mobile Intel Pentium 4-M",
125 "Mobile Intel Celeron",
126 NULL, /* Unspecified */
127 "Mobile Genuine Intel",
129 "Mobile Intel Celeron",
131 "Mobile Genuine Intel",
133 "Mobile Intel Celeron"
136 static struct cpu_nameclass i386_cpus[] = {
137 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
138 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
139 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
140 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
141 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
142 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
143 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
144 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
145 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
146 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
147 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
148 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
149 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
150 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
151 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
152 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
153 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
156 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
157 int has_f00f_bug = 0; /* Initialized so that it can be patched. */
163 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
168 cpu_class = i386_cpus[cpu].cpu_class;
170 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
172 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
173 /* Check for extended CPUID information and a processor name. */
175 (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
176 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
177 strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
178 strcmp(cpu_vendor, "TransmetaCPU") == 0)) {
179 do_cpuid(0x80000000, regs);
180 if (regs[0] >= 0x80000000) {
181 cpu_exthigh = regs[0];
182 if (cpu_exthigh >= 0x80000004) {
184 for (i = 0x80000002; i < 0x80000005; i++) {
186 memcpy(brand, regs, sizeof(regs));
187 brand += sizeof(regs);
193 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
194 if ((cpu_id & 0xf00) > 0x300) {
199 switch (cpu_id & 0x3000) {
201 strcpy(cpu_model, "Overdrive ");
204 strcpy(cpu_model, "Dual ");
208 switch (cpu_id & 0xf00) {
210 strcat(cpu_model, "i486 ");
211 /* Check the particular flavor of 486 */
212 switch (cpu_id & 0xf0) {
215 strcat(cpu_model, "DX");
218 strcat(cpu_model, "SX");
221 strcat(cpu_model, "DX2");
224 strcat(cpu_model, "SL");
227 strcat(cpu_model, "SX2");
231 "DX2 Write-Back Enhanced");
234 strcat(cpu_model, "DX4");
239 /* Check the particular flavor of 586 */
240 strcat(cpu_model, "Pentium");
241 switch (cpu_id & 0xf0) {
243 strcat(cpu_model, " A-step");
246 strcat(cpu_model, "/P5");
249 strcat(cpu_model, "/P54C");
252 strcat(cpu_model, "/P54T Overdrive");
255 strcat(cpu_model, "/P55C");
258 strcat(cpu_model, "/P54C");
261 strcat(cpu_model, "/P55C (quarter-micron)");
267 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
269 * XXX - If/when Intel fixes the bug, this
270 * should also check the version of the
271 * CPU, not just that it's a Pentium.
277 /* Check the particular flavor of 686 */
278 switch (cpu_id & 0xf0) {
280 strcat(cpu_model, "Pentium Pro A-step");
283 strcat(cpu_model, "Pentium Pro");
289 "Pentium II/Pentium II Xeon/Celeron");
297 "Pentium III/Pentium III Xeon/Celeron");
301 strcat(cpu_model, "Unknown 80686");
306 strcat(cpu_model, "Pentium 4");
310 strcat(cpu_model, "unknown");
315 * If we didn't get a brand name from the extended
316 * CPUID, try to look it up in the brand table.
318 if (cpu_high > 0 && *cpu_brand == '\0') {
319 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
320 if (brand_index <= MAX_BRAND_INDEX &&
321 cpu_brandtable[brand_index] != NULL)
323 cpu_brandtable[brand_index]);
326 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
328 * Values taken from AMD Processor Recognition
329 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
330 * (also describes ``Features'' encodings.
332 strcpy(cpu_model, "AMD ");
333 switch (cpu_id & 0xFF0) {
335 strcat(cpu_model, "Standard Am486DX");
338 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
341 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
344 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
347 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
350 strcat(cpu_model, "Am5x86 Write-Through");
353 strcat(cpu_model, "Am5x86 Write-Back");
356 strcat(cpu_model, "K5 model 0");
360 strcat(cpu_model, "K5 model 1");
363 strcat(cpu_model, "K5 PR166 (model 2)");
366 strcat(cpu_model, "K5 PR200 (model 3)");
369 strcat(cpu_model, "K6");
372 strcat(cpu_model, "K6 266 (model 1)");
375 strcat(cpu_model, "K6-2");
378 strcat(cpu_model, "K6-III");
381 strcat(cpu_model, "Unknown");
384 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
385 if ((cpu_id & 0xf00) == 0x500) {
386 if (((cpu_id & 0x0f0) > 0)
387 && ((cpu_id & 0x0f0) < 0x60)
388 && ((cpu_id & 0x00f) > 3))
389 enable_K5_wt_alloc();
390 else if (((cpu_id & 0x0f0) > 0x80)
391 || (((cpu_id & 0x0f0) == 0x80)
392 && (cpu_id & 0x00f) > 0x07))
393 enable_K6_2_wt_alloc();
394 else if ((cpu_id & 0x0f0) > 0x50)
395 enable_K6_wt_alloc();
398 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
399 strcpy(cpu_model, "Cyrix ");
400 switch (cpu_id & 0xff0) {
402 strcat(cpu_model, "MediaGX");
405 strcat(cpu_model, "6x86");
408 cpu_class = CPUCLASS_586;
409 strcat(cpu_model, "GXm");
412 strcat(cpu_model, "6x86MX");
416 * Even though CPU supports the cpuid
417 * instruction, it can be disabled.
418 * Therefore, this routine supports all Cyrix
421 switch (cyrix_did & 0xf0) {
423 switch (cyrix_did & 0x0f) {
425 strcat(cpu_model, "486SLC");
428 strcat(cpu_model, "486DLC");
431 strcat(cpu_model, "486SLC2");
434 strcat(cpu_model, "486DLC2");
437 strcat(cpu_model, "486SRx");
440 strcat(cpu_model, "486DRx");
443 strcat(cpu_model, "486SRx2");
446 strcat(cpu_model, "486DRx2");
449 strcat(cpu_model, "486SRu");
452 strcat(cpu_model, "486DRu");
455 strcat(cpu_model, "486SRu2");
458 strcat(cpu_model, "486DRu2");
461 strcat(cpu_model, "Unknown");
466 switch (cyrix_did & 0x0f) {
468 strcat(cpu_model, "486S");
471 strcat(cpu_model, "486S2");
474 strcat(cpu_model, "486Se");
477 strcat(cpu_model, "486S2e");
480 strcat(cpu_model, "486DX");
483 strcat(cpu_model, "486DX2");
486 strcat(cpu_model, "486DX4");
489 strcat(cpu_model, "Unknown");
494 if ((cyrix_did & 0x0f) < 8)
495 strcat(cpu_model, "6x86"); /* Where did you get it? */
497 strcat(cpu_model, "5x86");
500 strcat(cpu_model, "6x86");
503 if ((cyrix_did & 0xf000) == 0x3000) {
504 cpu_class = CPUCLASS_586;
505 strcat(cpu_model, "GXm");
507 strcat(cpu_model, "MediaGX");
510 strcat(cpu_model, "6x86MX");
513 switch (cyrix_did & 0x0f) {
515 strcat(cpu_model, "Overdrive CPU");
517 strcpy(cpu_model, "Texas Instruments 486SXL");
520 strcat(cpu_model, "486SLC/DLC");
523 strcat(cpu_model, "Unknown");
528 strcat(cpu_model, "Unknown");
533 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
534 strcpy(cpu_model, "Rise ");
535 switch (cpu_id & 0xff0) {
537 strcat(cpu_model, "mP6");
540 strcat(cpu_model, "Unknown");
542 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
543 switch (cpu_id & 0xff0) {
545 strcpy(cpu_model, "IDT WinChip C6");
549 strcpy(cpu_model, "IDT WinChip 2");
552 strcpy(cpu_model, "VIA C3 Samuel");
556 strcpy(cpu_model, "VIA C3 Ezra");
558 strcpy(cpu_model, "VIA C3 Samuel 2");
561 strcpy(cpu_model, "VIA C3 Ezra-T");
564 strcpy(cpu_model, "VIA C3 Nehemiah");
565 do_cpuid(0xc0000000, regs);
566 if (regs[0] == 0xc0000001) {
567 do_cpuid(0xc0000001, regs);
568 if ((cpu_id & 0xf) >= 3)
569 if ((regs[3] & 0x0c) == 0x0c)
570 strcat(cpu_model, "+RNG");
571 if ((cpu_id & 0xf) >= 8)
572 if ((regs[3] & 0xc0) == 0xc0)
573 strcat(cpu_model, "+ACE");
577 strcpy(cpu_model, "VIA/IDT Unknown");
579 } else if (strcmp(cpu_vendor, "IBM") == 0) {
580 strcpy(cpu_model, "Blue Lightning CPU");
584 * Replace cpu_model with cpu_brand minus leading spaces if
588 while (*brand == ' ')
591 strcpy(cpu_model, brand);
595 kprintf("%s (", cpu_model);
600 #if defined(I386_CPU)
605 #if defined(I486_CPU)
608 /* bzero = i486_bzero; */
611 #if defined(I586_CPU)
613 kprintf("%d.%02d-MHz ",
614 (tsc_freq + 4999) / 1000000,
615 ((tsc_freq + 4999) / 10000) % 100);
619 #if defined(I686_CPU)
621 kprintf("%d.%02d-MHz ",
622 (tsc_freq + 4999) / 1000000,
623 ((tsc_freq + 4999) / 10000) % 100);
628 kprintf("Unknown"); /* will panic below... */
630 kprintf("-class CPU)\n");
631 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
633 kprintf(" Origin = \"%s\"",cpu_vendor);
635 kprintf(" Id = 0x%x", cpu_id);
637 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
638 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
639 strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
640 strcmp(cpu_vendor, "CentaurHauls") == 0 ||
641 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
642 ((cpu_id & 0xf00) > 0x500))) {
643 kprintf(" Stepping = %u", cpu_id & 0xf);
644 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
645 kprintf(" DIR=0x%04x", cyrix_did);
648 * Here we should probably set up flags indicating
649 * whether or not various features are available.
650 * The interesting ones are probably VME, PSE, PAE,
651 * and PGE. The code already assumes without bothering
652 * to check that all CPUs >= Pentium have a TSC and
655 kprintf("\n Features=0x%b", cpu_feature,
657 "\001FPU" /* Integral FPU */
658 "\002VME" /* Extended VM86 mode support */
659 "\003DE" /* Debugging Extensions (CR4.DE) */
660 "\004PSE" /* 4MByte page tables */
661 "\005TSC" /* Timestamp counter */
662 "\006MSR" /* Machine specific registers */
663 "\007PAE" /* Physical address extension */
664 "\010MCE" /* Machine Check support */
665 "\011CX8" /* CMPEXCH8 instruction */
666 "\012APIC" /* SMP local APIC */
667 "\013oldMTRR" /* Previous implementation of MTRR */
668 "\014SEP" /* Fast System Call */
669 "\015MTRR" /* Memory Type Range Registers */
670 "\016PGE" /* PG_G (global bit) support */
671 "\017MCA" /* Machine Check Architecture */
672 "\020CMOV" /* CMOV instruction */
673 "\021PAT" /* Page attributes table */
674 "\022PSE36" /* 36 bit address space support */
675 "\023PN" /* Processor Serial number */
676 "\024CLFLUSH" /* Has the CLFLUSH instruction */
678 "\026DTS" /* Debug Trace Store */
679 "\027ACPI" /* ACPI support */
680 "\030MMX" /* MMX instructions */
681 "\031FXSR" /* FXSAVE/FXRSTOR */
682 "\032SSE" /* Streaming SIMD Extensions */
683 "\033SSE2" /* Streaming SIMD Extensions #2 */
684 "\034SS" /* Self snoop */
685 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
686 "\036TM" /* Thermal Monitor clock slowdown */
687 "\037IA64" /* CPU can execute IA64 instructions */
688 "\040PBE" /* Pending Break Enable */
692 * If this CPU supports hyperthreading then mention
693 * the number of logical CPU's it contains.
695 if (cpu_feature & CPUID_HTT &&
696 (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
697 kprintf("\n Hyperthreading: %d logical CPUs",
698 (cpu_procinfo & CPUID_HTT_CORES) >> 16);
700 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
701 cpu_exthigh >= 0x80000001)
702 print_AMD_features();
703 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
704 kprintf(" DIR=0x%04x", cyrix_did);
705 kprintf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
706 kprintf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
707 #ifndef CYRIX_CACHE_REALLY_WORKS
708 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
709 kprintf("\n CPU cache: write-through mode");
712 /* Avoid ugly blank lines: only print newline when we have to. */
713 if (*cpu_vendor || cpu_id)
717 if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
718 strcmp(cpu_vendor, "TransmetaCPU") == 0) {
719 setup_tmx86_longrun();
722 for (i = 0; i < additional_cpu_info_count; ++i) {
723 kprintf(" %s\n", additional_cpu_info_ary[i]);
729 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
731 else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
732 strcmp(cpu_vendor, "TransmetaCPU") == 0)
733 print_transmeta_info();
737 * XXX - Do PPro CPUID level=2 stuff here?
739 * No, but maybe in a print_Intel_info() function called from here.
745 panicifcpuunsupported(void)
748 #if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
749 #error This kernel is not configured for one of the supported CPUs
752 * Now that we have told the user what they have,
753 * let them know if that machine type isn't configured.
756 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
757 #if !defined(I386_CPU)
760 #if !defined(I486_CPU)
763 #if !defined(I586_CPU)
766 #if !defined(I686_CPU)
769 panic("CPU class not configured");
776 static volatile u_int trap_by_rdmsr;
779 * Special exception 6 handler.
780 * The rdmsr instruction generates invalid opcodes fault on 486-class
781 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
782 * function identblue() when this handler is called. Stacked eip should
789 " .p2align 2,0x90 \n"
790 " .type " __XSTRING(CNAME(bluetrap6)) ",@function \n"
791 __XSTRING(CNAME(bluetrap6)) ": \n"
793 " movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n"
794 " addl $2, (%esp) # I know rdmsr is a 2-bytes instruction. \n"
799 * Special exception 13 handler.
800 * Accessing non-existent MSR generates general protection fault.
802 inthand_t bluetrap13;
806 " .p2align 2,0x90 \n"
807 " .type " __XSTRING(CNAME(bluetrap13)) ",@function \n"
808 __XSTRING(CNAME(bluetrap13)) ": \n"
810 " movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n"
811 " popl %eax # discard errorcode. \n"
812 " addl $2, (%esp) # I know rdmsr is a 2-bytes instruction. \n"
817 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
818 * support cpuid instruction. This function should be called after
819 * loading interrupt descriptor table register.
821 * I don't like this method that handles fault, but I couldn't get
822 * information for any other methods. Does blue giant know?
831 * Cyrix 486-class CPU does not support rdmsr instruction.
832 * The rdmsr instruction generates invalid opcode fault, and exception
833 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
834 * bluetrap6() set the magic number to trap_by_rdmsr.
836 setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
839 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
840 * In this case, rdmsr generates general protection fault, and
841 * exception will be trapped by bluetrap13().
843 setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
845 rdmsr(0x1002); /* Cyrix CPU generates fault. */
847 if (trap_by_rdmsr == 0xa8c1d)
848 return IDENTBLUE_CYRIX486;
849 else if (trap_by_rdmsr == 0xa89c4)
850 return IDENTBLUE_CYRIXM2;
851 return IDENTBLUE_IBMCPU;
856 * identifycyrix() set lower 16 bits of cyrix_did as follows:
858 * F E D C B A 9 8 7 6 5 4 3 2 1 0
859 * +-------+-------+---------------+
860 * | SID | RID | Device ID |
861 * | (DIR 1) | (DIR 0) |
862 * +-------+-------+---------------+
867 int ccr2_test = 0, dir_test = 0;
872 ccr2 = read_cyrix_reg(CCR2);
873 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
874 read_cyrix_reg(CCR2);
875 if (read_cyrix_reg(CCR2) != ccr2)
877 write_cyrix_reg(CCR2, ccr2);
879 ccr3 = read_cyrix_reg(CCR3);
880 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
881 read_cyrix_reg(CCR3);
882 if (read_cyrix_reg(CCR3) != ccr3)
883 dir_test = 1; /* CPU supports DIRs. */
884 write_cyrix_reg(CCR3, ccr3);
887 /* Device ID registers are available. */
888 cyrix_did = read_cyrix_reg(DIR1) << 8;
889 cyrix_did += read_cyrix_reg(DIR0);
890 } else if (ccr2_test)
891 cyrix_did = 0x0010; /* 486S A-step */
893 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
899 * Final stage of CPU identification. -- Should I check TI?
908 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
909 if (cpu == CPU_486) {
911 * These conditions are equivalent to:
912 * - CPU does not support cpuid instruction.
913 * - Cyrix/IBM CPU is detected.
915 isblue = identblue();
916 if (isblue == IDENTBLUE_IBMCPU) {
917 strcpy(cpu_vendor, "IBM");
922 switch (cpu_id & 0xf00) {
925 * Cyrix's datasheet does not describe DIRs.
926 * Therefor, I assume it does not have them
927 * and use the result of the cpuid instruction.
928 * XXX they seem to have it for now at least. -Peter
936 * This routine contains a trick.
937 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
939 switch (cyrix_did & 0x00f0) {
948 if ((cyrix_did & 0x000f) < 8)
961 /* M2 and later CPUs are treated as M2. */
965 * enable cpuid instruction.
967 ccr3 = read_cyrix_reg(CCR3);
968 write_cyrix_reg(CCR3, CCR3_MAPEN0);
969 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
970 write_cyrix_reg(CCR3, ccr3);
973 cpu_high = regs[0]; /* eax */
975 cpu_id = regs[0]; /* eax */
976 cpu_feature = regs[3]; /* edx */
980 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
982 * There are BlueLightning CPUs that do not change
983 * undefined flags by dividing 5 by 2. In this case,
984 * the CPU identification routine in locore.s leaves
985 * cpu_vendor null string and puts CPU_486 into the
988 isblue = identblue();
989 if (isblue == IDENTBLUE_IBMCPU) {
990 strcpy(cpu_vendor, "IBM");
998 print_AMD_assoc(int i)
1001 kprintf(", fully associative\n");
1003 kprintf(", %d-way associative\n", i);
1007 print_AMD_info(void)
1011 if (cpu_exthigh >= 0x80000005) {
1014 do_cpuid(0x80000005, regs);
1015 kprintf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
1016 print_AMD_assoc(regs[1] >> 24);
1017 kprintf("Instruction TLB: %d entries", regs[1] & 0xff);
1018 print_AMD_assoc((regs[1] >> 8) & 0xff);
1019 kprintf("L1 data cache: %d kbytes", regs[2] >> 24);
1020 kprintf(", %d bytes/line", regs[2] & 0xff);
1021 kprintf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1022 print_AMD_assoc((regs[2] >> 16) & 0xff);
1023 kprintf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1024 kprintf(", %d bytes/line", regs[3] & 0xff);
1025 kprintf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1026 print_AMD_assoc((regs[3] >> 16) & 0xff);
1027 if (cpu_exthigh >= 0x80000006) { /* K6-III, or later */
1028 do_cpuid(0x80000006, regs);
1030 * Report right L2 cache size on Duron rev. A0.
1032 if ((cpu_id & 0xFF0) == 0x630)
1033 kprintf("L2 internal cache: 64 kbytes");
1035 kprintf("L2 internal cache: %d kbytes",
1038 kprintf(", %d bytes/line", regs[2] & 0xff);
1039 kprintf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1040 print_AMD_assoc((regs[2] >> 12) & 0x0f);
1043 if (((cpu_id & 0xf00) == 0x500)
1044 && (((cpu_id & 0x0f0) > 0x80)
1045 || (((cpu_id & 0x0f0) == 0x80)
1046 && (cpu_id & 0x00f) > 0x07))) {
1047 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1048 amd_whcr = rdmsr(0xc0000082);
1049 if (!(amd_whcr & (0x3ff << 22))) {
1050 kprintf("Write Allocate Disable\n");
1052 kprintf("Write Allocate Enable Limit: %dM bytes\n",
1053 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1054 kprintf("Write Allocate 15-16M bytes: %s\n",
1055 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1057 } else if (((cpu_id & 0xf00) == 0x500)
1058 && ((cpu_id & 0x0f0) > 0x50)) {
1059 /* K6, K6-2(old core) */
1060 amd_whcr = rdmsr(0xc0000082);
1061 if (!(amd_whcr & (0x7f << 1))) {
1062 kprintf("Write Allocate Disable\n");
1064 kprintf("Write Allocate Enable Limit: %dM bytes\n",
1065 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1066 kprintf("Write Allocate 15-16M bytes: %s\n",
1067 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1068 kprintf("Hardware Write Allocate Control: %s\n",
1069 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1074 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
1076 print_AMD_features(void)
1081 * Values taken from AMD Processor Recognition
1082 * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
1084 do_cpuid(0x80000001, regs);
1085 kprintf("\n AMD Features=0x%b", regs[3] &~ cpu_feature,
1087 "\001FPU" /* Integral FPU */
1088 "\002VME" /* Extended VM86 mode support */
1089 "\003DE" /* Debug extensions */
1090 "\004PSE" /* 4MByte page tables */
1091 "\005TSC" /* Timestamp counter */
1092 "\006MSR" /* Machine specific registers */
1093 "\007PAE" /* Physical address extension */
1094 "\010MCE" /* Machine Check support */
1095 "\011CX8" /* CMPEXCH8 instruction */
1096 "\012APIC" /* SMP local APIC */
1098 "\014SYSCALL" /* SYSENTER/SYSEXIT instructions */
1099 "\015MTRR" /* Memory Type Range Registers */
1100 "\016PGE" /* PG_G (global bit) support */
1101 "\017MCA" /* Machine Check Architecture */
1102 "\020ICMOV" /* CMOV instruction */
1103 "\021PAT" /* Page attributes table */
1104 "\022PGE36" /* 36 bit address space support */
1105 "\023RSVD" /* Reserved, unknown */
1106 "\024MP" /* Multiprocessor Capable */
1109 "\027AMIE" /* AMD MMX Instruction Extensions */
1111 "\031FXSAVE" /* FXSAVE/FXRSTOR */
1117 "\037DSP" /* AMD 3DNow! Instruction Extensions */
1124 * Transmeta Crusoe LongRun Support by Tamotsu Hattori.
1127 #define MSR_TMx86_LONGRUN 0x80868010
1128 #define MSR_TMx86_LONGRUN_FLAGS 0x80868011
1130 #define LONGRUN_MODE_MASK(x) ((x) & 0x000000007f)
1131 #define LONGRUN_MODE_RESERVED(x) ((x) & 0xffffff80)
1132 #define LONGRUN_MODE_WRITE(x, y) (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y))
1134 #define LONGRUN_MODE_MINFREQUENCY 0x00
1135 #define LONGRUN_MODE_ECONOMY 0x01
1136 #define LONGRUN_MODE_PERFORMANCE 0x02
1137 #define LONGRUN_MODE_MAXFREQUENCY 0x03
1138 #define LONGRUN_MODE_UNKNOWN 0x04
1139 #define LONGRUN_MODE_MAX 0x04
1146 u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
1147 /* MSR low, MSR high, flags bit0 */
1148 { 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */
1149 { 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */
1150 { 0, 100, 1}, /* LONGRUN_MODE_PERFORMANCE */
1151 { 100, 100, 1}, /* LONGRUN_MODE_MAXFREQUENCY */
1155 tmx86_get_longrun_mode(void)
1157 union msrinfo msrinfo;
1158 u_int low, high, flags, mode;
1162 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1163 low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
1164 high = LONGRUN_MODE_MASK(msrinfo.regs[1]);
1165 flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
1167 for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) {
1168 if (low == longrun_modes[mode][0] &&
1169 high == longrun_modes[mode][1] &&
1170 flags == longrun_modes[mode][2]) {
1174 mode = LONGRUN_MODE_UNKNOWN;
1181 tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
1187 do_cpuid(0x80860007, regs);
1188 *frequency = regs[0];
1190 *percentage = regs[2];
1197 tmx86_set_longrun_mode(u_int mode)
1199 union msrinfo msrinfo;
1201 if (mode >= LONGRUN_MODE_UNKNOWN) {
1207 /* Write LongRun mode values to Model Specific Register. */
1208 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1209 msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0],
1210 longrun_modes[mode][0]);
1211 msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1],
1212 longrun_modes[mode][1]);
1213 wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
1215 /* Write LongRun mode flags to Model Specific Register. */
1216 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
1217 msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
1218 wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
1224 static u_int crusoe_longrun;
1225 static u_int crusoe_frequency;
1226 static u_int crusoe_voltage;
1227 static u_int crusoe_percentage;
1228 static struct sysctl_ctx_list crusoe_sysctl_ctx;
1229 static struct sysctl_oid *crusoe_sysctl_tree;
1232 tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS)
1237 crusoe_longrun = tmx86_get_longrun_mode();
1238 mode = crusoe_longrun;
1239 error = sysctl_handle_int(oidp, &mode, 0, req);
1240 if (error || !req->newptr) {
1243 if (mode >= LONGRUN_MODE_UNKNOWN) {
1247 if (crusoe_longrun != mode) {
1248 crusoe_longrun = mode;
1249 tmx86_set_longrun_mode(crusoe_longrun);
1256 tmx86_status_sysctl(SYSCTL_HANDLER_ARGS)
1261 tmx86_get_longrun_status(&crusoe_frequency,
1262 &crusoe_voltage, &crusoe_percentage);
1263 val = *(u_int *)oidp->oid_arg1;
1264 error = sysctl_handle_int(oidp, &val, 0, req);
1269 setup_tmx86_longrun(void)
1271 static int done = 0;
1277 sysctl_ctx_init(&crusoe_sysctl_ctx);
1278 crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx,
1279 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1280 "crusoe", CTLFLAG_RD, 0,
1281 "Transmeta Crusoe LongRun support");
1282 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1283 OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW,
1284 &crusoe_longrun, 0, tmx86_longrun_sysctl, "I",
1285 "LongRun mode [0-3]");
1286 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1287 OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD,
1288 &crusoe_frequency, 0, tmx86_status_sysctl, "I",
1289 "Current frequency (MHz)");
1290 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1291 OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD,
1292 &crusoe_voltage, 0, tmx86_status_sysctl, "I",
1293 "Current voltage (mV)");
1294 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1295 OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD,
1296 &crusoe_percentage, 0, tmx86_status_sysctl, "I",
1297 "Processing performance (%)");
1301 print_transmeta_info(void)
1303 u_int regs[4], nreg = 0;
1305 do_cpuid(0x80860000, regs);
1307 if (nreg >= 0x80860001) {
1308 do_cpuid(0x80860001, regs);
1309 kprintf(" Processor revision %u.%u.%u.%u\n",
1310 (regs[1] >> 24) & 0xff,
1311 (regs[1] >> 16) & 0xff,
1312 (regs[1] >> 8) & 0xff,
1315 if (nreg >= 0x80860002) {
1316 do_cpuid(0x80860002, regs);
1317 kprintf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
1318 (regs[1] >> 24) & 0xff,
1319 (regs[1] >> 16) & 0xff,
1320 (regs[1] >> 8) & 0xff,
1324 if (nreg >= 0x80860006) {
1326 do_cpuid(0x80860003, (u_int*) &info[0]);
1327 do_cpuid(0x80860004, (u_int*) &info[16]);
1328 do_cpuid(0x80860005, (u_int*) &info[32]);
1329 do_cpuid(0x80860006, (u_int*) &info[48]);
1331 kprintf(" %s\n", info);
1334 crusoe_longrun = tmx86_get_longrun_mode();
1335 tmx86_get_longrun_status(&crusoe_frequency,
1336 &crusoe_voltage, &crusoe_percentage);
1337 kprintf(" LongRun mode: %d <%dMHz %dmV %d%%>\n", crusoe_longrun,
1338 crusoe_frequency, crusoe_voltage, crusoe_percentage);
1342 additional_cpu_info(const char *line)
1346 if ((i = additional_cpu_info_count) < MAX_ADDITIONAL_INFO) {
1347 additional_cpu_info_ary[i] = line;
1348 ++additional_cpu_info_count;