- Fix indentation in VarFind()
[dragonfly.git] / sys / dev / serial / rc / rc.c
1 /*
2  * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
3  * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  * $FreeBSD: src/sys/i386/isa/rc.c,v 1.53.2.1 2001/02/26 04:23:10 jlemon Exp $
28  * $DragonFly: src/sys/dev/serial/rc/rc.c,v 1.12 2004/09/19 01:55:06 dillon Exp $
29  *
30  */
31
32 /*
33  * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
34  *
35  */
36
37 #include "use_rc.h"
38
39 /*#define RCDEBUG*/
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/tty.h>
44 #include <sys/proc.h>
45 #include <sys/conf.h>
46 #include <sys/dkstat.h>
47 #include <sys/fcntl.h>
48 #include <sys/interrupt.h>
49 #include <sys/kernel.h>
50 #include <machine/clock.h>
51 #include <machine/ipl.h>
52
53 #include <bus/isa/i386/isa_device.h>
54
55 #include <i386/isa/ic/cd180.h>
56 #include "rcreg.h"
57
58 /* Prototypes */
59 static int     rcprobe         (struct isa_device *);
60 static int     rcattach        (struct isa_device *);
61
62 #define rcin(port)      RC_IN  (nec, port)
63 #define rcout(port,v)   RC_OUT (nec, port, v)
64
65 #define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__)
66 #define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd))
67
68 #define RC_IBUFSIZE     256
69 #define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
70 #define RC_OBUFSIZE     512
71 #define RC_IHIGHWATER   (3 * RC_IBUFSIZE / 4)
72 #define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
73 #define LOTS_OF_EVENTS  64
74
75 #define RC_FAKEID       0x10
76
77 #define RC_PROBED 1
78 #define RC_ATTACHED 2
79
80 #define GET_UNIT(dev)   (minor(dev) & 0x3F)
81 #define CALLOUT(dev)    (minor(dev) & 0x80)
82
83 /* For isa routines */
84 struct isa_driver rcdriver = {
85         rcprobe, rcattach, "rc"
86 };
87
88 static  d_open_t        rcopen;
89 static  d_close_t       rcclose;
90 static  d_ioctl_t       rcioctl;
91
92 #define CDEV_MAJOR      63
93 static struct cdevsw rc_cdevsw = {
94         /* name */      "rc",
95         /* maj */       CDEV_MAJOR,
96         /* flags */     D_TTY | D_KQFILTER,
97         /* port */      NULL,
98         /* clone */     NULL,
99
100         /* open */      rcopen,
101         /* close */     rcclose,
102         /* read */      ttyread,
103         /* write */     ttywrite,
104         /* ioctl */     rcioctl,
105         /* poll */      ttypoll,
106         /* mmap */      nommap,
107         /* strategy */  nostrategy,
108         /* dump */      nodump,
109         /* psize */     nopsize,
110         /* kqfilter */  ttykqfilter
111 };
112
113 /* Per-board structure */
114 static struct rc_softc {
115         u_int           rcb_probed;     /* 1 - probed, 2 - attached */
116         u_int           rcb_addr;       /* Base I/O addr        */
117         u_int           rcb_unit;       /* unit #               */
118         u_char          rcb_dtr;        /* DTR status           */
119         struct rc_chans *rcb_baserc;    /* base rc ptr          */
120 } rc_softc[NRC];
121
122 /* Per-channel structure */
123 static struct rc_chans  {
124         struct rc_softc *rc_rcb;                /* back ptr             */
125         u_short          rc_flags;              /* Misc. flags          */
126         int              rc_chan;               /* Channel #            */
127         u_char           rc_ier;                /* intr. enable reg     */
128         u_char           rc_msvr;               /* modem sig. status    */
129         u_char           rc_cor2;               /* options reg          */
130         u_char           rc_pendcmd;            /* special cmd pending  */
131         u_int            rc_dtrwait;            /* dtr timeout          */
132         u_int            rc_dcdwaits;           /* how many waits DCD in open */
133         u_char           rc_hotchar;            /* end packed optimize */
134         struct tty      *rc_tp;                 /* tty struct           */
135         u_char          *rc_iptr;               /* Chars input buffer         */
136         u_char          *rc_hiwat;              /* hi-water mark        */
137         u_char          *rc_bufend;             /* end of buffer        */
138         u_char          *rc_optr;               /* ptr in output buf    */
139         u_char          *rc_obufend;            /* end of output buf    */
140         struct callout   rc_dtr_ch;
141         u_char           rc_ibuf[4 * RC_IBUFSIZE];  /* input buffer         */
142         u_char           rc_obuf[RC_OBUFSIZE];  /* output buffer        */
143 } rc_chans[NRC * CD180_NCHAN];
144
145 static int rc_scheduled_event = 0;
146 static struct callout rc_wakeup_ch;
147
148 /* for pstat -t */
149 static struct tty rc_tty[NRC * CD180_NCHAN];
150 static const int  nrc_tty = NRC * CD180_NCHAN;
151
152 /* Flags */
153 #define RC_DTR_OFF      0x0001          /* DTR wait, for close/open     */
154 #define RC_ACTOUT       0x0002          /* Dial-out port active         */
155 #define RC_RTSFLOW      0x0004          /* RTS flow ctl enabled         */
156 #define RC_CTSFLOW      0x0008          /* CTS flow ctl enabled         */
157 #define RC_DORXFER      0x0010          /* RXFER event planned          */
158 #define RC_DOXXFER      0x0020          /* XXFER event planned          */
159 #define RC_MODCHG       0x0040          /* Modem status changed         */
160 #define RC_OSUSP        0x0080          /* Output suspended             */
161 #define RC_OSBUSY       0x0100          /* start() routine in progress  */
162 #define RC_WAS_BUFOVFL  0x0200          /* low-level buffer ovferflow   */
163 #define RC_WAS_SILOVFL  0x0400          /* silo buffer overflow         */
164 #define RC_SEND_RDY     0x0800          /* ready to send */
165
166 /* Table for translation of RCSR status bits to internal form */
167 static int rc_rcsrt[16] = {
168         0,             TTY_OE,               TTY_FE,
169         TTY_FE|TTY_OE, TTY_PE,               TTY_PE|TTY_OE,
170         TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
171         TTY_BI|TTY_OE, TTY_BI|TTY_FE,        TTY_BI|TTY_FE|TTY_OE,
172         TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
173         TTY_BI|TTY_PE|TTY_FE|TTY_OE
174 };
175
176 /* Static prototypes */
177 static ointhand2_t rcintr;
178 static void rc_hwreset          (int, int, unsigned int);
179 static int  rc_test             (int, int);
180 static void rc_discard_output   (struct rc_chans *);
181 static void rc_hardclose        (struct rc_chans *);
182 static int  rc_modctl           (struct rc_chans *, int, int);
183 static void rc_start            (struct tty *);
184 static void rc_stop              (struct tty *, int rw);
185 static int  rc_param            (struct tty *, struct termios *);
186 static inthand2_t rcpoll;
187 static void rc_reinit           (struct rc_softc *);
188 #ifdef RCDEBUG
189 static void printrcflags();
190 #endif
191 static timeout_t rc_dtrwakeup;
192 static timeout_t rc_wakeup;
193 static void disc_optim          (struct tty     *tp, struct termios *t, struct rc_chans *);
194 static void rc_wait0            (int nec, int unit, int chan, int line);
195
196 /**********************************************/
197
198 /* Quick device probing */
199 static int
200 rcprobe(dvp)
201         struct  isa_device      *dvp;
202 {
203         int             irq = ffs(dvp->id_irq) - 1;
204         int    nec = dvp->id_iobase;
205
206         if (dvp->id_unit > NRC)
207                 return 0;
208         if (!RC_VALIDADDR(nec)) {
209                 printf("rc%d: illegal base address %x\n", dvp->id_unit, nec);
210                 return 0;
211         }
212         if (!RC_VALIDIRQ(irq)) {
213                 printf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq);
214                 return 0;
215         }
216         rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */
217         rcout(CD180_PPRH, 0x11);
218         if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11)
219                 return 0;
220         /* Now, test the board more thoroughly, with diagnostic */
221         if (rc_test(nec, dvp->id_unit))
222                 return 0;
223         rc_softc[dvp->id_unit].rcb_probed = RC_PROBED;
224
225         return 0xF;
226 }
227
228 static int
229 rcattach(dvp)
230         struct  isa_device      *dvp;
231 {
232         int            chan, nec = dvp->id_iobase;
233         struct rc_softc         *rcb = &rc_softc[dvp->id_unit];
234         struct rc_chans         *rc  = &rc_chans[dvp->id_unit * CD180_NCHAN];
235         static int              rc_started = 0;
236         struct tty              *tp;
237
238         dvp->id_ointr = rcintr;
239
240         /* Thorooughly test the device */
241         if (rcb->rcb_probed != RC_PROBED)
242                 return 0;
243         rcb->rcb_addr   = nec;
244         rcb->rcb_dtr    = 0;
245         rcb->rcb_baserc = rc;
246         rcb->rcb_unit   = dvp->id_unit;
247         /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/
248         printf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit,
249                 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A');
250
251         for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
252                 callout_init(&rc->rc_dtr_ch);
253                 rc->rc_rcb     = rcb;
254                 rc->rc_chan    = chan;
255                 rc->rc_iptr    = rc->rc_ibuf;
256                 rc->rc_bufend  = &rc->rc_ibuf[RC_IBUFSIZE];
257                 rc->rc_hiwat   = &rc->rc_ibuf[RC_IHIGHWATER];
258                 rc->rc_flags   = rc->rc_ier = rc->rc_msvr = 0;
259                 rc->rc_cor2    = rc->rc_pendcmd = 0;
260                 rc->rc_optr    = rc->rc_obufend  = rc->rc_obuf;
261                 rc->rc_dtrwait = 3 * hz;
262                 rc->rc_dcdwaits= 0;
263                 rc->rc_hotchar = 0;
264                 tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)];
265                 ttychars(tp);
266                 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0;
267                 tp->t_cflag = TTYDEF_CFLAG;
268                 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
269         }
270         rcb->rcb_probed = RC_ATTACHED;
271         if (!rc_started) {
272                 cdevsw_add(&rc_cdevsw, -1, rcb->rcb_unit);
273                 register_swi(SWI_TTY, rcpoll, NULL, "rcpoll");
274                 callout_init(&rc_wakeup_ch);
275                 rc_wakeup(NULL);
276                 rc_started = 1;
277         }
278         return 1;
279 }
280
281 /* RC interrupt handling */
282 static void
283 rcintr(unit)
284         int             unit;
285 {
286         struct rc_softc        *rcb = &rc_softc[unit];
287         struct rc_chans        *rc;
288         int                    nec, resid;
289         u_char                 val, iack, bsr, ucnt, *optr;
290         int                             good_data, t_state;
291
292         if (rcb->rcb_probed != RC_ATTACHED) {
293                 printf("rc%d: bogus interrupt\n", unit);
294                 return;
295         }
296         nec = rcb->rcb_addr;
297
298         bsr = ~(rcin(RC_BSR));
299
300         if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
301                 printf("rc%d: extra interrupt\n", unit);
302                 rcout(CD180_EOIR, 0);
303                 return;
304         }
305
306         while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
307 #ifdef RCDEBUG_DETAILED
308                 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr,
309                         (bsr & RC_BSR_TOUT)?"TOUT ":"",
310                         (bsr & RC_BSR_RXINT)?"RXINT ":"",
311                         (bsr & RC_BSR_TXINT)?"TXINT ":"",
312                         (bsr & RC_BSR_MOINT)?"MOINT":"");
313 #endif
314                 if (bsr & RC_BSR_TOUT) {
315                         printf("rc%d: hardware failure, reset board\n", unit);
316                         rcout(RC_CTOUT, 0);
317                         rc_reinit(rcb);
318                         return;
319                 }
320                 if (bsr & RC_BSR_RXINT) {
321                         iack = rcin(RC_PILR_RX);
322                         good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
323                         if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
324                                 printf("rc%d: fake rxint: %02x\n", unit, iack);
325                                 goto more_intrs;
326                         }
327                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
328                         t_state = rc->rc_tp->t_state;
329                         /* Do RTS flow control stuff */
330                         if (  (rc->rc_flags & RC_RTSFLOW)
331                             || !(t_state & TS_ISOPEN)
332                            ) {
333                                 if (  (   !(t_state & TS_ISOPEN)
334                                        || (t_state & TS_TBLOCK)
335                                       )
336                                     && (rc->rc_msvr & MSVR_RTS)
337                                    )
338                                         rcout(CD180_MSVR,
339                                                 rc->rc_msvr &= ~MSVR_RTS);
340                                 else if (!(rc->rc_msvr & MSVR_RTS))
341                                         rcout(CD180_MSVR,
342                                                 rc->rc_msvr |= MSVR_RTS);
343                         }
344                         ucnt  = rcin(CD180_RDCR) & 0xF;
345                         resid = 0;
346
347                         if (t_state & TS_ISOPEN) {
348                                 /* check for input buffer overflow */
349                                 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
350                                         resid  = ucnt;
351                                         ucnt   = rc->rc_bufend - rc->rc_iptr;
352                                         resid -= ucnt;
353                                         if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
354                                                 rc->rc_flags |= RC_WAS_BUFOVFL;
355                                                 rc_scheduled_event++;
356                                         }
357                                 }
358                                 optr = rc->rc_iptr;
359                                 /* check foor good data */
360                                 if (good_data) {
361                                         while (ucnt-- > 0) {
362                                                 val = rcin(CD180_RDR);
363                                                 optr[0] = val;
364                                                 optr[INPUT_FLAGS_SHIFT] = 0;
365                                                 optr++;
366                                                 rc_scheduled_event++;
367                                                 if (val != 0 && val == rc->rc_hotchar)
368                                                         setsofttty();
369                                         }
370                                 } else {
371                                         /* Store also status data */
372                                         while (ucnt-- > 0) {
373                                                 iack = rcin(CD180_RCSR);
374                                                 if (iack & RCSR_Timeout)
375                                                         break;
376                                                 if (   (iack & RCSR_OE)
377                                                     && !(rc->rc_flags & RC_WAS_SILOVFL)) {
378                                                         rc->rc_flags |= RC_WAS_SILOVFL;
379                                                         rc_scheduled_event++;
380                                                 }
381                                                 val = rcin(CD180_RDR);
382                                                 /*
383                                                   Don't store PE if IGNPAR and BREAK if IGNBRK,
384                                                   this hack allows "raw" tty optimization
385                                                   works even if IGN* is set.
386                                                 */
387                                                 if (   !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
388                                                     || ((!(iack & (RCSR_PE|RCSR_FE))
389                                                     ||  !(rc->rc_tp->t_iflag & IGNPAR))
390                                                     && (!(iack & RCSR_Break)
391                                                     ||  !(rc->rc_tp->t_iflag & IGNBRK)))) {
392                                                         if (   (iack & (RCSR_PE|RCSR_FE))
393                                                             && (t_state & TS_CAN_BYPASS_L_RINT)
394                                                             && ((iack & RCSR_FE)
395                                                             ||  ((iack & RCSR_PE)
396                                                             &&  (rc->rc_tp->t_iflag & INPCK))))
397                                                                 val = 0;
398                                                         else if (val != 0 && val == rc->rc_hotchar)
399                                                                 setsofttty();
400                                                         optr[0] = val;
401                                                         optr[INPUT_FLAGS_SHIFT] = iack;
402                                                         optr++;
403                                                         rc_scheduled_event++;
404                                                 }
405                                         }
406                                 }
407                                 rc->rc_iptr = optr;
408                                 rc->rc_flags |= RC_DORXFER;
409                         } else
410                                 resid = ucnt;
411                         /* Clear FIFO if necessary */
412                         while (resid-- > 0) {
413                                 if (!good_data)
414                                         iack = rcin(CD180_RCSR);
415                                 else
416                                         iack = 0;
417                                 if (iack & RCSR_Timeout)
418                                         break;
419                                 (void) rcin(CD180_RDR);
420                         }
421                         goto more_intrs;
422                 }
423                 if (bsr & RC_BSR_MOINT) {
424                         iack = rcin(RC_PILR_MODEM);
425                         if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
426                                 printf("rc%d: fake moint: %02x\n", unit, iack);
427                                 goto more_intrs;
428                         }
429                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
430                         iack = rcin(CD180_MCR);
431                         rc->rc_msvr = rcin(CD180_MSVR);
432                         rcout(CD180_MCR, 0);
433 #ifdef RCDEBUG
434                         printrcflags(rc, "moint");
435 #endif
436                         if (rc->rc_flags & RC_CTSFLOW) {
437                                 if (rc->rc_msvr & MSVR_CTS)
438                                         rc->rc_flags |= RC_SEND_RDY;
439                                 else
440                                         rc->rc_flags &= ~RC_SEND_RDY;
441                         } else
442                                 rc->rc_flags |= RC_SEND_RDY;
443                         if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
444                                 rc_scheduled_event += LOTS_OF_EVENTS;
445                                 rc->rc_flags |= RC_MODCHG;
446                                 setsofttty();
447                         }
448                         goto more_intrs;
449                 }
450                 if (bsr & RC_BSR_TXINT) {
451                         iack = rcin(RC_PILR_TX);
452                         if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
453                                 printf("rc%d: fake txint: %02x\n", unit, iack);
454                                 goto more_intrs;
455                         }
456                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
457                         if (    (rc->rc_flags & RC_OSUSP)
458                             || !(rc->rc_flags & RC_SEND_RDY)
459                            )
460                                 goto more_intrs;
461                         /* Handle breaks and other stuff */
462                         if (rc->rc_pendcmd) {
463                                 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC);
464                                 rcout(CD180_TDR,  CD180_C_ESC);
465                                 rcout(CD180_TDR,  rc->rc_pendcmd);
466                                 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
467                                 rc->rc_pendcmd = 0;
468                                 goto more_intrs;
469                         }
470                         optr = rc->rc_optr;
471                         resid = rc->rc_obufend - optr;
472                         if (resid > CD180_NFIFO)
473                                 resid = CD180_NFIFO;
474                         while (resid-- > 0)
475                                 rcout(CD180_TDR, *optr++);
476                         rc->rc_optr = optr;
477
478                         /* output completed? */
479                         if (optr >= rc->rc_obufend) {
480                                 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy);
481 #ifdef RCDEBUG
482                                 printf("rc%d/%d: output completed\n", unit, rc->rc_chan);
483 #endif
484                                 if (!(rc->rc_flags & RC_DOXXFER)) {
485                                         rc_scheduled_event += LOTS_OF_EVENTS;
486                                         rc->rc_flags |= RC_DOXXFER;
487                                         setsofttty();
488                                 }
489                         }
490                 }
491         more_intrs:
492                 rcout(CD180_EOIR, 0);   /* end of interrupt */
493                 rcout(RC_CTOUT, 0);
494                 bsr = ~(rcin(RC_BSR));
495         }
496 }
497
498 /* Feed characters to output buffer */
499 static void rc_start(tp)
500 struct tty *tp;
501 {
502         struct rc_chans       *rc = &rc_chans[GET_UNIT(tp->t_dev)];
503         int                    nec = rc->rc_rcb->rcb_addr, s;
504
505         if (rc->rc_flags & RC_OSBUSY)
506                 return;
507         s = spltty();
508         rc->rc_flags |= RC_OSBUSY;
509         cpu_disable_intr();
510         if (tp->t_state & TS_TTSTOP)
511                 rc->rc_flags |= RC_OSUSP;
512         else
513                 rc->rc_flags &= ~RC_OSUSP;
514         /* Do RTS flow control stuff */
515         if (   (rc->rc_flags & RC_RTSFLOW)
516             && (tp->t_state & TS_TBLOCK)
517             && (rc->rc_msvr & MSVR_RTS)
518            ) {
519                 rcout(CD180_CAR, rc->rc_chan);
520                 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
521         } else if (!(rc->rc_msvr & MSVR_RTS)) {
522                 rcout(CD180_CAR, rc->rc_chan);
523                 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
524         }
525         cpu_enable_intr();
526         if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
527                 goto out;
528 #ifdef RCDEBUG
529         printrcflags(rc, "rcstart");
530 #endif
531         ttwwakeup(tp);
532 #ifdef RCDEBUG
533         printf("rcstart: outq = %d obuf = %d\n",
534                 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
535 #endif
536         if (tp->t_state & TS_BUSY)
537                 goto    out;    /* output still in progress ... */
538
539         if (tp->t_outq.c_cc > 0) {
540                 u_int   ocnt;
541
542                 tp->t_state |= TS_BUSY;
543                 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
544                 cpu_disable_intr();
545                 rc->rc_optr = rc->rc_obuf;
546                 rc->rc_obufend = rc->rc_optr + ocnt;
547                 cpu_enable_intr();
548                 if (!(rc->rc_ier & IER_TxRdy)) {
549 #ifdef RCDEBUG
550                         printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan);
551 #endif
552                         rcout(CD180_CAR, rc->rc_chan);
553                         rcout(CD180_IER, rc->rc_ier |= IER_TxRdy);
554                 }
555         }
556 out:
557         rc->rc_flags &= ~RC_OSBUSY;
558         (void) splx(s);
559 }
560
561 /* Handle delayed events. */
562 void 
563 rcpoll(void *dummy)
564 {
565         struct rc_chans *rc;
566         struct rc_softc *rcb;
567         u_char        *tptr, *eptr;
568         struct tty    *tp;
569         int            chan, icnt, nec, unit;
570
571         if (rc_scheduled_event == 0)
572                 return;
573 repeat:
574         for (unit = 0; unit < NRC; unit++) {
575                 rcb = &rc_softc[unit];
576                 rc = rcb->rcb_baserc;
577                 nec = rc->rc_rcb->rcb_addr;
578                 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
579                         tp = rc->rc_tp;
580 #ifdef RCDEBUG
581                         if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
582                             RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
583                                 printrcflags(rc, "rcevent");
584 #endif
585                         if (rc->rc_flags & RC_WAS_BUFOVFL) {
586                                 cpu_disable_intr();
587                                 rc->rc_flags &= ~RC_WAS_BUFOVFL;
588                                 rc_scheduled_event--;
589                                 cpu_enable_intr();
590                                 printf("rc%d/%d: interrupt-level buffer overflow\n",
591                                         unit, chan);
592                         }
593                         if (rc->rc_flags & RC_WAS_SILOVFL) {
594                                 cpu_disable_intr();
595                                 rc->rc_flags &= ~RC_WAS_SILOVFL;
596                                 rc_scheduled_event--;
597                                 cpu_enable_intr();
598                                 printf("rc%d/%d: silo overflow\n",
599                                         unit, chan);
600                         }
601                         if (rc->rc_flags & RC_MODCHG) {
602                                 cpu_disable_intr();
603                                 rc->rc_flags &= ~RC_MODCHG;
604                                 rc_scheduled_event -= LOTS_OF_EVENTS;
605                                 cpu_enable_intr();
606                                 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD));
607                         }
608                         if (rc->rc_flags & RC_DORXFER) {
609                                 cpu_disable_intr();
610                                 rc->rc_flags &= ~RC_DORXFER;
611                                 eptr = rc->rc_iptr;
612                                 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
613                                         tptr = &rc->rc_ibuf[RC_IBUFSIZE];
614                                 else
615                                         tptr = rc->rc_ibuf;
616                                 icnt = eptr - tptr;
617                                 if (icnt > 0) {
618                                         if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
619                                                 rc->rc_iptr   = rc->rc_ibuf;
620                                                 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
621                                                 rc->rc_hiwat  = &rc->rc_ibuf[RC_IHIGHWATER];
622                                         } else {
623                                                 rc->rc_iptr   = &rc->rc_ibuf[RC_IBUFSIZE];
624                                                 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
625                                                 rc->rc_hiwat  =
626                                                         &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
627                                         }
628                                         if (   (rc->rc_flags & RC_RTSFLOW)
629                                             && (tp->t_state & TS_ISOPEN)
630                                             && !(tp->t_state & TS_TBLOCK)
631                                             && !(rc->rc_msvr & MSVR_RTS)
632                                             ) {
633                                                 rcout(CD180_CAR, chan);
634                                                 rcout(CD180_MSVR,
635                                                         rc->rc_msvr |= MSVR_RTS);
636                                         }
637                                         rc_scheduled_event -= icnt;
638                                 }
639                                 cpu_enable_intr();
640
641                                 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
642                                         goto done1;
643
644                                 if (   (tp->t_state & TS_CAN_BYPASS_L_RINT)
645                                     && !(tp->t_state & TS_LOCAL)) {
646                                         if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER
647                                             && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
648                                             && !(tp->t_state & TS_TBLOCK))
649                                                 ttyblock(tp);
650                                         tk_nin += icnt;
651                                         tk_rawcc += icnt;
652                                         tp->t_rawcc += icnt;
653                                         if (b_to_q(tptr, icnt, &tp->t_rawq))
654                                                 printf("rc%d/%d: tty-level buffer overflow\n",
655                                                         unit, chan);
656                                         ttwakeup(tp);
657                                         if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
658                                             || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
659                                                 tp->t_state &= ~TS_TTSTOP;
660                                                 tp->t_lflag &= ~FLUSHO;
661                                                 rc_start(tp);
662                                         }
663                                 } else {
664                                         for (; tptr < eptr; tptr++)
665                                                 (*linesw[tp->t_line].l_rint)
666                                                     (tptr[0] |
667                                                     rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp);
668                                 }
669 done1: ;
670                         }
671                         if (rc->rc_flags & RC_DOXXFER) {
672                                 cpu_disable_intr();
673                                 rc_scheduled_event -= LOTS_OF_EVENTS;
674                                 rc->rc_flags &= ~RC_DOXXFER;
675                                 rc->rc_tp->t_state &= ~TS_BUSY;
676                                 cpu_enable_intr();
677                                 (*linesw[tp->t_line].l_start)(tp);
678                         }
679                 }
680                 if (rc_scheduled_event == 0)
681                         break;
682         }
683         if (rc_scheduled_event >= LOTS_OF_EVENTS)
684                 goto repeat;
685 }
686
687 static  void
688 rc_stop(tp, rw)
689         struct tty     *tp;
690         int                     rw;
691 {
692         struct rc_chans        *rc = &rc_chans[GET_UNIT(tp->t_dev)];
693         u_char *tptr, *eptr;
694
695 #ifdef RCDEBUG
696         printf("rc%d/%d: rc_stop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan,
697                 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
698 #endif
699         if (rw & FWRITE)
700                 rc_discard_output(rc);
701         cpu_disable_intr();
702         if (rw & FREAD) {
703                 rc->rc_flags &= ~RC_DORXFER;
704                 eptr = rc->rc_iptr;
705                 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
706                         tptr = &rc->rc_ibuf[RC_IBUFSIZE];
707                         rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
708                 } else {
709                         tptr = rc->rc_ibuf;
710                         rc->rc_iptr = rc->rc_ibuf;
711                 }
712                 rc_scheduled_event -= eptr - tptr;
713         }
714         if (tp->t_state & TS_TTSTOP)
715                 rc->rc_flags |= RC_OSUSP;
716         else
717                 rc->rc_flags &= ~RC_OSUSP;
718         cpu_enable_intr();
719 }
720
721 static  int
722 rcopen(dev, flag, mode, td)
723         dev_t           dev;
724         int             flag, mode;
725         struct thread *td;
726 {
727         struct rc_chans *rc;
728         struct tty      *tp;
729         int             unit, nec, s, error = 0;
730
731         unit = GET_UNIT(dev);
732         if (unit >= NRC * CD180_NCHAN)
733                 return ENXIO;
734         if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED)
735                 return ENXIO;
736         rc  = &rc_chans[unit];
737         tp  = rc->rc_tp;
738         dev->si_tty = tp;
739         nec = rc->rc_rcb->rcb_addr;
740 #ifdef RCDEBUG
741         printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
742 #endif
743         s = spltty();
744
745 again:
746         while (rc->rc_flags & RC_DTR_OFF) {
747                 error = tsleep(&(rc->rc_dtrwait), PCATCH, "rcdtr", 0);
748                 if (error != 0)
749                         goto out;
750         }
751         if (tp->t_state & TS_ISOPEN) {
752                 if (CALLOUT(dev)) {
753                         if (!(rc->rc_flags & RC_ACTOUT)) {
754                                 error = EBUSY;
755                                 goto out;
756                         }
757                 } else {
758                         if (rc->rc_flags & RC_ACTOUT) {
759                                 if (flag & O_NONBLOCK) {
760                                         error = EBUSY;
761                                         goto out;
762                                 }
763                                 error = tsleep(&rc->rc_rcb, PCATCH, "rcbi", 0);
764                                 if (error)
765                                         goto out;
766                                 goto again;
767                         }
768                 }
769                 if (tp->t_state & TS_XCLUDE &&
770                     suser(td)) {
771                         error = EBUSY;
772                         goto out;
773                 }
774         } else {
775                 tp->t_oproc   = rc_start;
776                 tp->t_param   = rc_param;
777                 tp->t_stop    = rc_stop;
778                 tp->t_dev     = dev;
779
780                 if (CALLOUT(dev))
781                         tp->t_cflag |= CLOCAL;
782                 else
783                         tp->t_cflag &= ~CLOCAL;
784
785                 error = rc_param(tp, &tp->t_termios);
786                 if (error)
787                         goto out;
788                 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET);
789
790                 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev))
791                         (*linesw[tp->t_line].l_modem)(tp, 1);
792         }
793         if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev)
794             && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
795                 rc->rc_dcdwaits++;
796                 error = tsleep(TSA_CARR_ON(tp), PCATCH, "rcdcd", 0);
797                 rc->rc_dcdwaits--;
798                 if (error != 0)
799                         goto out;
800                 goto again;
801         }
802         error = (*linesw[tp->t_line].l_open)(dev, tp);
803         disc_optim(tp, &tp->t_termios, rc);
804         if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev))
805                 rc->rc_flags |= RC_ACTOUT;
806 out:
807         (void) splx(s);
808
809         if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN))
810                 rc_hardclose(rc);
811
812         return error;
813 }
814
815 static  int
816 rcclose(dev, flag, mode, td)
817         dev_t           dev;
818         int             flag, mode;
819         struct thread *td;
820 {
821         struct rc_chans *rc;
822         struct tty      *tp;
823         int  s, unit = GET_UNIT(dev);
824
825         if (unit >= NRC * CD180_NCHAN)
826                 return ENXIO;
827         rc  = &rc_chans[unit];
828         tp  = rc->rc_tp;
829 #ifdef RCDEBUG
830         printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
831 #endif
832         s = spltty();
833         (*linesw[tp->t_line].l_close)(tp, flag);
834         disc_optim(tp, &tp->t_termios, rc);
835         rc_stop(tp, FREAD | FWRITE);
836         rc_hardclose(rc);
837         ttyclose(tp);
838         splx(s);
839         return 0;
840 }
841
842 static void rc_hardclose(rc)
843 struct rc_chans *rc;
844 {
845         int s, nec = rc->rc_rcb->rcb_addr;
846         struct tty *tp = rc->rc_tp;
847
848         s = spltty();
849         rcout(CD180_CAR, rc->rc_chan);
850
851         /* Disable rx/tx intrs */
852         rcout(CD180_IER, rc->rc_ier = 0);
853         if (   (tp->t_cflag & HUPCL)
854             || (!(rc->rc_flags & RC_ACTOUT)
855                && !(rc->rc_msvr & MSVR_CD)
856                && !(tp->t_cflag & CLOCAL))
857             || !(tp->t_state & TS_ISOPEN)
858            ) {
859                 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
860                 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
861                 (void) rc_modctl(rc, TIOCM_RTS, DMSET);
862                 if (rc->rc_dtrwait) {
863                         callout_reset(&rc->rc_dtr_ch, rc->rc_dtrwait,
864                                 rc_dtrwakeup, rc);
865                         rc->rc_flags |= RC_DTR_OFF;
866                 }
867         }
868         rc->rc_flags &= ~RC_ACTOUT;
869         wakeup((caddr_t) &rc->rc_rcb);  /* wake bi */
870         wakeup(TSA_CARR_ON(tp));
871         (void) splx(s);
872 }
873
874 /* Reset the bastard */
875 static void rc_hwreset(unit, nec, chipid)
876         int    unit, nec;
877         unsigned int    chipid;
878 {
879         CCRCMD(unit, -1, CCR_HWRESET);            /* Hardware reset */
880         DELAY(20000);
881         WAITFORCCR(unit, -1);
882
883         rcout(RC_CTOUT, 0);             /* Clear timeout  */
884         rcout(CD180_GIVR,  chipid);
885         rcout(CD180_GICR,  0);
886
887         /* Set Prescaler Registers (1 msec) */
888         rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
889         rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
890
891         /* Initialize Priority Interrupt Level Registers */
892         rcout(CD180_PILR1, RC_PILR_MODEM);
893         rcout(CD180_PILR2, RC_PILR_TX);
894         rcout(CD180_PILR3, RC_PILR_RX);
895
896         /* Reset DTR */
897         rcout(RC_DTREG, ~0);
898 }
899
900 /* Set channel parameters */
901 static int rc_param(tp, ts)
902         struct  tty    *tp;
903         struct termios          *ts;
904 {
905         struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
906         int    nec = rc->rc_rcb->rcb_addr;
907         int      idivs, odivs, s, val, cflag, iflag, lflag, inpflow;
908
909         if (   ts->c_ospeed < 0 || ts->c_ospeed > 76800
910             || ts->c_ispeed < 0 || ts->c_ispeed > 76800
911            )
912                 return (EINVAL);
913         if (ts->c_ispeed == 0)
914                 ts->c_ispeed = ts->c_ospeed;
915         odivs = RC_BRD(ts->c_ospeed);
916         idivs = RC_BRD(ts->c_ispeed);
917
918         s = spltty();
919
920         /* Select channel */
921         rcout(CD180_CAR, rc->rc_chan);
922
923         /* If speed == 0, hangup line */
924         if (ts->c_ospeed == 0) {
925                 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
926                 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
927                 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
928         }
929
930         tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
931         cflag = ts->c_cflag;
932         iflag = ts->c_iflag;
933         lflag = ts->c_lflag;
934
935         if (idivs > 0) {
936                 rcout(CD180_RBPRL, idivs & 0xFF);
937                 rcout(CD180_RBPRH, idivs >> 8);
938         }
939         if (odivs > 0) {
940                 rcout(CD180_TBPRL, odivs & 0xFF);
941                 rcout(CD180_TBPRH, odivs >> 8);
942         }
943
944         /* set timeout value */
945         if (ts->c_ispeed > 0) {
946                 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
947
948                 if (   !(lflag & ICANON)
949                     && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
950                     && ts->c_cc[VTIME] * 10 > itm)
951                         itm = ts->c_cc[VTIME] * 10;
952
953                 rcout(CD180_RTPR, itm <= 255 ? itm : 255);
954         }
955
956         switch (cflag & CSIZE) {
957                 case CS5:       val = COR1_5BITS;      break;
958                 case CS6:       val = COR1_6BITS;      break;
959                 case CS7:       val = COR1_7BITS;      break;
960                 default:
961                 case CS8:       val = COR1_8BITS;      break;
962         }
963         if (cflag & PARENB) {
964                 val |= COR1_NORMPAR;
965                 if (cflag & PARODD)
966                         val |= COR1_ODDP;
967                 if (!(cflag & INPCK))
968                         val |= COR1_Ignore;
969         } else
970                 val |= COR1_Ignore;
971         if (cflag & CSTOPB)
972                 val |= COR1_2SB;
973         rcout(CD180_COR1, val);
974
975         /* Set FIFO threshold */
976         val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
977         inpflow = 0;
978         if (   (iflag & IXOFF)
979             && (   ts->c_cc[VSTOP] != _POSIX_VDISABLE
980                 && (   ts->c_cc[VSTART] != _POSIX_VDISABLE
981                     || (iflag & IXANY)
982                    )
983                )
984            ) {
985                 inpflow = 1;
986                 val |= COR3_SCDE|COR3_FCT;
987         }
988         rcout(CD180_COR3, val);
989
990         /* Initialize on-chip automatic flow control */
991         val = 0;
992         rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
993         if (cflag & CCTS_OFLOW) {
994                 rc->rc_flags |= RC_CTSFLOW;
995                 val |= COR2_CtsAE;
996         } else
997                 rc->rc_flags |= RC_SEND_RDY;
998         if (tp->t_state & TS_TTSTOP)
999                 rc->rc_flags |= RC_OSUSP;
1000         else
1001                 rc->rc_flags &= ~RC_OSUSP;
1002         if (cflag & CRTS_IFLOW)
1003                 rc->rc_flags |= RC_RTSFLOW;
1004         else
1005                 rc->rc_flags &= ~RC_RTSFLOW;
1006
1007         if (inpflow) {
1008                 if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
1009                         rcout(CD180_SCHR1, ts->c_cc[VSTART]);
1010                 rcout(CD180_SCHR2, ts->c_cc[VSTOP]);
1011                 val |= COR2_TxIBE;
1012                 if (iflag & IXANY)
1013                         val |= COR2_IXM;
1014         }
1015
1016         rcout(CD180_COR2, rc->rc_cor2 = val);
1017
1018         CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1019                 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1020
1021         disc_optim(tp, ts, rc);
1022
1023         /* modem ctl */
1024         val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
1025         if (cflag & CCTS_OFLOW)
1026                 val |= MCOR1_CTSzd;
1027         rcout(CD180_MCOR1, val);
1028
1029         val = cflag & CLOCAL ? 0 : MCOR2_CDod;
1030         if (cflag & CCTS_OFLOW)
1031                 val |= MCOR2_CTSod;
1032         rcout(CD180_MCOR2, val);
1033
1034         /* enable i/o and interrupts */
1035         CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1036                 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1037         WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
1038
1039         rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1040         if (cflag & CCTS_OFLOW)
1041                 rc->rc_ier |= IER_CTS;
1042         if (cflag & CREAD)
1043                 rc->rc_ier |= IER_RxData;
1044         if (tp->t_state & TS_BUSY)
1045                 rc->rc_ier |= IER_TxRdy;
1046         if (ts->c_ospeed != 0)
1047                 rc_modctl(rc, TIOCM_DTR, DMBIS);
1048         if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1049                 rc->rc_flags |= RC_SEND_RDY;
1050         rcout(CD180_IER, rc->rc_ier);
1051         (void) splx(s);
1052         return 0;
1053 }
1054
1055 /* Re-initialize board after bogus interrupts */
1056 static void rc_reinit(rcb)
1057 struct rc_softc         *rcb;
1058 {
1059         struct rc_chans       *rc, *rce;
1060         int                    nec;
1061
1062         nec = rcb->rcb_addr;
1063         rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID);
1064         rc  = &rc_chans[rcb->rcb_unit * CD180_NCHAN];
1065         rce = rc + CD180_NCHAN;
1066         for (; rc < rce; rc++)
1067                 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios);
1068 }
1069
1070 static  int
1071 rcioctl(dev, cmd, data, flag, td)
1072 dev_t           dev;
1073 u_long          cmd;
1074 int             flag;
1075 caddr_t         data;
1076 struct thread *td;
1077 {
1078         struct rc_chans       *rc = &rc_chans[GET_UNIT(dev)];
1079         int                    s, error;
1080         struct tty                     *tp = rc->rc_tp;
1081
1082         error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td);
1083         if (error != ENOIOCTL)
1084                 return (error);
1085         error = ttioctl(tp, cmd, data, flag);
1086         disc_optim(tp, &tp->t_termios, rc);
1087         if (error != ENOIOCTL)
1088                 return (error);
1089         s = spltty();
1090
1091         switch (cmd) {
1092             case TIOCSBRK:
1093                 rc->rc_pendcmd = CD180_C_SBRK;
1094                 break;
1095
1096             case TIOCCBRK:
1097                 rc->rc_pendcmd = CD180_C_EBRK;
1098                 break;
1099
1100             case TIOCSDTR:
1101                 (void) rc_modctl(rc, TIOCM_DTR, DMBIS);
1102                 break;
1103
1104             case TIOCCDTR:
1105                 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1106                 break;
1107
1108             case TIOCMGET:
1109                 *(int *) data = rc_modctl(rc, 0, DMGET);
1110                 break;
1111
1112             case TIOCMSET:
1113                 (void) rc_modctl(rc, *(int *) data, DMSET);
1114                 break;
1115
1116             case TIOCMBIC:
1117                 (void) rc_modctl(rc, *(int *) data, DMBIC);
1118                 break;
1119
1120             case TIOCMBIS:
1121                 (void) rc_modctl(rc, *(int *) data, DMBIS);
1122                 break;
1123
1124             case TIOCMSDTRWAIT:
1125                 error = suser(td);
1126                 if (error != 0) {
1127                         splx(s);
1128                         return (error);
1129                 }
1130                 rc->rc_dtrwait = *(int *)data * hz / 100;
1131                 break;
1132
1133             case TIOCMGDTRWAIT:
1134                 *(int *)data = rc->rc_dtrwait * 100 / hz;
1135                 break;
1136
1137             default:
1138                 (void) splx(s);
1139                 return ENOTTY;
1140         }
1141         (void) splx(s);
1142         return 0;
1143 }
1144
1145
1146 /* Modem control routines */
1147
1148 static int rc_modctl(rc, bits, cmd)
1149 struct rc_chans       *rc;
1150 int                             bits, cmd;
1151 {
1152         int    nec = rc->rc_rcb->rcb_addr;
1153         u_char         *dtr = &rc->rc_rcb->rcb_dtr, msvr;
1154
1155         rcout(CD180_CAR, rc->rc_chan);
1156
1157         switch (cmd) {
1158             case DMSET:
1159                 rcout(RC_DTREG, (bits & TIOCM_DTR) ?
1160                                 ~(*dtr |= 1 << rc->rc_chan) :
1161                                 ~(*dtr &= ~(1 << rc->rc_chan)));
1162                 msvr = rcin(CD180_MSVR);
1163                 if (bits & TIOCM_RTS)
1164                         msvr |= MSVR_RTS;
1165                 else
1166                         msvr &= ~MSVR_RTS;
1167                 if (bits & TIOCM_DTR)
1168                         msvr |= MSVR_DTR;
1169                 else
1170                         msvr &= ~MSVR_DTR;
1171                 rcout(CD180_MSVR, msvr);
1172                 break;
1173
1174             case DMBIS:
1175                 if (bits & TIOCM_DTR)
1176                         rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1177                 msvr = rcin(CD180_MSVR);
1178                 if (bits & TIOCM_RTS)
1179                         msvr |= MSVR_RTS;
1180                 if (bits & TIOCM_DTR)
1181                         msvr |= MSVR_DTR;
1182                 rcout(CD180_MSVR, msvr);
1183                 break;
1184
1185             case DMGET:
1186                 bits = TIOCM_LE;
1187                 msvr = rc->rc_msvr = rcin(CD180_MSVR);
1188
1189                 if (msvr & MSVR_RTS)
1190                         bits |= TIOCM_RTS;
1191                 if (msvr & MSVR_CTS)
1192                         bits |= TIOCM_CTS;
1193                 if (msvr & MSVR_DSR)
1194                         bits |= TIOCM_DSR;
1195                 if (msvr & MSVR_DTR)
1196                         bits |= TIOCM_DTR;
1197                 if (msvr & MSVR_CD)
1198                         bits |= TIOCM_CD;
1199                 if (~rcin(RC_RIREG) & (1 << rc->rc_chan))
1200                         bits |= TIOCM_RI;
1201                 return bits;
1202
1203             case DMBIC:
1204                 if (bits & TIOCM_DTR)
1205                         rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1206                 msvr = rcin(CD180_MSVR);
1207                 if (bits & TIOCM_RTS)
1208                         msvr &= ~MSVR_RTS;
1209                 if (bits & TIOCM_DTR)
1210                         msvr &= ~MSVR_DTR;
1211                 rcout(CD180_MSVR, msvr);
1212                 break;
1213         }
1214         rc->rc_msvr = rcin(CD180_MSVR);
1215         return 0;
1216 }
1217
1218 /* Test the board. */
1219 int rc_test(nec, unit)
1220         int    nec;
1221         int             unit;
1222 {
1223         int     chan = 0;
1224         int     i = 0, rcnt, old_level;
1225         unsigned int    iack, chipid;
1226         unsigned short  divs;
1227         static  u_char  ctest[] = "\377\125\252\045\244\0\377";
1228 #define CTLEN   8
1229 #define ERR(s)  { \
1230                 printf("rc%d: ", unit); printf s ; printf("\n"); \
1231                 (void) splx(old_level); return 1; }
1232
1233         struct rtest {
1234                 u_char  txbuf[CD180_NFIFO];     /* TX buffer  */
1235                 u_char  rxbuf[CD180_NFIFO];     /* RX buffer  */
1236                 int     rxptr;                  /* RX pointer */
1237                 int     txptr;                  /* TX pointer */
1238         } tchans[CD180_NCHAN];
1239
1240         old_level = spltty();
1241
1242         chipid = RC_FAKEID;
1243
1244         /* First, reset board to inital state */
1245         rc_hwreset(unit, nec, chipid);
1246
1247         divs = RC_BRD(19200);
1248
1249         /* Initialize channels */
1250         for (chan = 0; chan < CD180_NCHAN; chan++) {
1251
1252                 /* Select and reset channel */
1253                 rcout(CD180_CAR, chan);
1254                 CCRCMD(unit, chan, CCR_ResetChan);
1255                 WAITFORCCR(unit, chan);
1256
1257                 /* Set speed */
1258                 rcout(CD180_RBPRL, divs & 0xFF);
1259                 rcout(CD180_RBPRH, divs >> 8);
1260                 rcout(CD180_TBPRL, divs & 0xFF);
1261                 rcout(CD180_TBPRH, divs >> 8);
1262
1263                 /* set timeout value */
1264                 rcout(CD180_RTPR,  0);
1265
1266                 /* Establish local loopback */
1267                 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1268                 rcout(CD180_COR2, COR2_LLM);
1269                 rcout(CD180_COR3, CD180_NFIFO);
1270                 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1271                 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN);
1272                 WAITFORCCR(unit, chan);
1273                 rcout(CD180_MSVR, MSVR_RTS);
1274
1275                 /* Fill TXBUF with test data */
1276                 for (i = 0; i < CD180_NFIFO; i++) {
1277                         tchans[chan].txbuf[i] = ctest[i];
1278                         tchans[chan].rxbuf[i] = 0;
1279                 }
1280                 tchans[chan].txptr = tchans[chan].rxptr = 0;
1281
1282                 /* Now, start transmit */
1283                 rcout(CD180_IER, IER_TxMpty|IER_RxData);
1284         }
1285         /* Pseudo-interrupt poll stuff */
1286         for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1287                 i = ~(rcin(RC_BSR));
1288                 if (i & RC_BSR_TOUT)
1289                         ERR(("BSR timeout bit set\n"))
1290                 else if (i & RC_BSR_TXINT) {
1291                         iack = rcin(RC_PILR_TX);
1292                         if (iack != (GIVR_IT_TDI | chipid))
1293                                 ERR(("Bad TX intr ack (%02x != %02x)\n",
1294                                         iack, GIVR_IT_TDI | chipid));
1295                         chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1296                         /* If no more data to transmit, disable TX intr */
1297                         if (tchans[chan].txptr >= CD180_NFIFO) {
1298                                 iack = rcin(CD180_IER);
1299                                 rcout(CD180_IER, iack & ~IER_TxMpty);
1300                         } else {
1301                                 for (iack = tchans[chan].txptr;
1302                                     iack < CD180_NFIFO; iack++)
1303                                         rcout(CD180_TDR,
1304                                             tchans[chan].txbuf[iack]);
1305                                 tchans[chan].txptr = iack;
1306                         }
1307                         rcout(CD180_EOIR, 0);
1308                 } else if (i & RC_BSR_RXINT) {
1309                         u_char ucnt;
1310
1311                         iack = rcin(RC_PILR_RX);
1312                         if (iack != (GIVR_IT_RGDI | chipid) &&
1313                             iack != (GIVR_IT_REI  | chipid))
1314                                 ERR(("Bad RX intr ack (%02x != %02x)\n",
1315                                         iack, GIVR_IT_RGDI | chipid))
1316                         chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1317                         ucnt = rcin(CD180_RDCR) & 0xF;
1318                         while (ucnt-- > 0) {
1319                                 iack = rcin(CD180_RCSR);
1320                                 if (iack & RCSR_Timeout)
1321                                         break;
1322                                 if (iack & 0xF)
1323                                         ERR(("Bad char chan %d (RCSR = %02X)\n",
1324                                             chan, iack))
1325                                 if (tchans[chan].rxptr > CD180_NFIFO)
1326                                         ERR(("Got extra chars chan %d\n",
1327                                             chan))
1328                                 tchans[chan].rxbuf[tchans[chan].rxptr++] =
1329                                         rcin(CD180_RDR);
1330                         }
1331                         rcout(CD180_EOIR, 0);
1332                 }
1333                 rcout(RC_CTOUT, 0);
1334                 for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1335                         if (tchans[chan].rxptr >= CD180_NFIFO)
1336                                 iack++;
1337                 if (iack == CD180_NCHAN)
1338                         break;
1339         }
1340         for (chan = 0; chan < CD180_NCHAN; chan++) {
1341                 /* Select and reset channel */
1342                 rcout(CD180_CAR, chan);
1343                 CCRCMD(unit, chan, CCR_ResetChan);
1344         }
1345
1346         if (!rcnt)
1347                 ERR(("looses characters during local loopback\n"))
1348         /* Now, check data */
1349         for (chan = 0; chan < CD180_NCHAN; chan++)
1350                 for (i = 0; i < CD180_NFIFO; i++)
1351                         if (ctest[i] != tchans[chan].rxbuf[i])
1352                                 ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1353                                     chan, i, ctest[i], tchans[chan].rxbuf[i]))
1354         (void) splx(old_level);
1355         return 0;
1356 }
1357
1358 #ifdef RCDEBUG
1359 static void printrcflags(rc, comment)
1360 struct rc_chans  *rc;
1361 char             *comment;
1362 {
1363         u_short f = rc->rc_flags;
1364         int    nec = rc->rc_rcb->rcb_addr;
1365
1366         printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
1367                 rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1368                 (f & RC_DTR_OFF)?"DTR_OFF " :"",
1369                 (f & RC_ACTOUT) ?"ACTOUT " :"",
1370                 (f & RC_RTSFLOW)?"RTSFLOW " :"",
1371                 (f & RC_CTSFLOW)?"CTSFLOW " :"",
1372                 (f & RC_DORXFER)?"DORXFER " :"",
1373                 (f & RC_DOXXFER)?"DOXXFER " :"",
1374                 (f & RC_MODCHG) ?"MODCHG "  :"",
1375                 (f & RC_OSUSP)  ?"OSUSP " :"",
1376                 (f & RC_OSBUSY) ?"OSBUSY " :"",
1377                 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1378                 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1379                 (f & RC_SEND_RDY) ?"SEND_RDY":"");
1380
1381         rcout(CD180_CAR, rc->rc_chan);
1382
1383         printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
1384                 rc->rc_rcb->rcb_unit, rc->rc_chan,
1385                 rcin(CD180_MSVR),
1386                 rcin(CD180_IER),
1387                 rcin(CD180_CCSR));
1388 }
1389 #endif /* RCDEBUG */
1390
1391 static void
1392 rc_dtrwakeup(chan)
1393         void    *chan;
1394 {
1395         struct rc_chans  *rc;
1396
1397         rc = (struct rc_chans *)chan;
1398         rc->rc_flags &= ~RC_DTR_OFF;
1399         wakeup(&rc->rc_dtrwait);
1400 }
1401
1402 static void
1403 rc_discard_output(rc)
1404         struct rc_chans  *rc;
1405 {
1406         cpu_disable_intr();
1407         if (rc->rc_flags & RC_DOXXFER) {
1408                 rc_scheduled_event -= LOTS_OF_EVENTS;
1409                 rc->rc_flags &= ~RC_DOXXFER;
1410         }
1411         rc->rc_optr = rc->rc_obufend;
1412         rc->rc_tp->t_state &= ~TS_BUSY;
1413         cpu_enable_intr();
1414         ttwwakeup(rc->rc_tp);
1415 }
1416
1417 static void
1418 rc_wakeup(chan)
1419         void    *chan;
1420 {
1421         if (rc_scheduled_event != 0) {
1422                 int     s;
1423
1424                 s = splsofttty();
1425                 rcpoll(NULL);
1426                 splx(s);
1427         }
1428         callout_reset(&rc_wakeup_ch, 1, rc_wakeup, NULL);
1429 }
1430
1431 static void
1432 disc_optim(tp, t, rc)
1433         struct tty      *tp;
1434         struct termios  *t;
1435         struct rc_chans *rc;
1436 {
1437
1438         if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
1439             && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1440             && (!(t->c_iflag & PARMRK)
1441                 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
1442             && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
1443             && linesw[tp->t_line].l_rint == ttyinput)
1444                 tp->t_state |= TS_CAN_BYPASS_L_RINT;
1445         else
1446                 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1447         rc->rc_hotchar = linesw[tp->t_line].l_hotchar;
1448 }
1449
1450 static void
1451 rc_wait0(nec, unit, chan, line)
1452         int     nec, unit, chan, line;
1453 {
1454         int rcnt;
1455
1456         for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--)
1457                 DELAY(30);
1458         if (rcnt == 0)
1459                 printf("rc%d/%d: channel command timeout, rc.c line: %d\n",
1460                       unit, chan, line);
1461 }