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38 * IGB_TXD: Maximum number of Transmit Descriptors
40 * This value is the number of transmit descriptors allocated by the driver.
41 * Increasing this value allows the driver to queue more transmits. Each
42 * descriptor is 16 bytes.
43 * Since TDLEN should be multiple of 128bytes, the number of transmit
44 * desscriptors should meet the following condition.
45 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
47 #define IGB_MIN_TXD 256
48 #define IGB_DEFAULT_TXD 1024
49 #define IGB_MAX_TXD 4096
52 * IGB_RXD: Maximum number of Transmit Descriptors
54 * This value is the number of receive descriptors allocated by the driver.
55 * Increasing this value allows the driver to buffer more incoming packets.
56 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
57 * descriptor. The maximum MTU size is 16110.
58 * Since TDLEN should be multiple of 128bytes, the number of transmit
59 * desscriptors should meet the following condition.
60 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
62 #define IGB_MIN_RXD 256
63 #define IGB_DEFAULT_RXD 1024
64 #define IGB_MAX_RXD 4096
67 * This parameter controls when the driver calls the routine to reclaim
68 * transmit descriptors. Cleaning earlier seems a win.
70 #define IGB_TX_CLEANUP_THRESHOLD(sc) ((sc)->num_tx_desc / 2)
73 * This parameter controls whether or not autonegotation is enabled.
74 * 0 - Disable autonegotiation
75 * 1 - Enable autonegotiation
80 * This parameter control whether or not the driver will wait for
81 * autonegotiation to complete.
82 * 1 - Wait for autonegotiation to complete
83 * 0 - Don't wait for autonegotiation to complete
85 #define WAIT_FOR_AUTO_NEG_DEFAULT 0
89 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
90 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
93 #define AUTO_ALL_MODES 0
95 /* PHY master/slave setting */
96 #define IGB_MASTER_SLAVE e1000_ms_hw_default
99 * Micellaneous constants
101 #define IGB_VENDOR_ID 0x8086
103 #define IGB_JUMBO_PBA 0x00000028
104 #define IGB_DEFAULT_PBA 0x00000030
105 #define IGB_SMARTSPEED_DOWNSHIFT 3
106 #define IGB_SMARTSPEED_MAX 15
107 #define IGB_MAX_LOOP 10
109 #define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8)
110 #define IGB_RX_HTHRESH 8
111 #define IGB_RX_WTHRESH 1
113 #define IGB_TX_PTHRESH 8
114 #define IGB_TX_HTHRESH 1
115 #define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \
116 sc->msix_mem) ? 1 : 16)
118 #define MAX_NUM_MULTICAST_ADDRESSES 128
119 #define IGB_FC_PAUSE_TIME 0x0680
121 #define IGB_INTR_RATE 10000
124 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
125 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
126 * also optimize cache line size effect. H/W supports up to cache line size 128.
128 #define IGB_DBA_ALIGN 128
130 /* PCI Config defines */
131 #define IGB_MSIX_BAR 3
133 #define IGB_MAX_SCATTER 64
134 #define IGB_VFTA_SIZE 128
135 #define IGB_TSO_SIZE (65535 + \
136 sizeof(struct ether_vlan_header))
137 #define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */
138 #define IGB_HDR_BUF 128
139 #define IGB_PKTTYPE_MASK 0x0000FFF0
141 #define IGB_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
142 #define IGB_IPVHL_SIZE 1 /* sizeof(ip.ip_vhl) */
143 #define IGB_TXCSUM_MINHL (ETHER_HDR_LEN + EVL_ENCAPLEN + \
146 /* One for TX csum offloading desc, the other 2 are reserved */
147 #define IGB_TX_RESERVED 3
149 /* Large enough for 64K TSO */
150 #define IGB_TX_SPARE 32
152 #define IGB_TX_OACTIVE_MAX 64
157 * Bus dma information structure
160 bus_addr_t dma_paddr;
162 bus_dma_tag_t dma_tag;
163 bus_dmamap_t dma_map;
167 * Transmit ring: one per queue
170 struct igb_softc *sc;
172 struct igb_dma txdma;
173 bus_dma_tag_t tx_hdr_dtag;
174 bus_dmamap_t tx_hdr_dmap;
175 bus_addr_t tx_hdr_paddr;
176 struct e1000_tx_desc *tx_base;
177 uint32_t next_avail_desc;
178 uint32_t next_to_clean;
181 struct igb_tx_buf *tx_buf;
182 bus_dma_tag_t tx_tag;
189 uint32_t tx_intr_mask;
191 u_long no_desc_avail;
194 u_long ctx_try_pullup;
198 u_long ctx_pullup1_failed;
200 u_long ctx_pullup2_failed;
204 * Receive ring: one per queue
207 struct igb_softc *sc;
209 struct igb_dma rxdma;
210 union e1000_adv_rx_desc *rx_base;
212 uint32_t next_to_check;
213 struct igb_rx_buf *rx_buf;
214 bus_dma_tag_t rx_tag;
215 bus_dmamap_t rx_sparemap;
217 uint32_t rx_intr_mask;
220 * First/last mbuf pointers, for
221 * collecting multisegment RX packets.
231 struct arpcom arpcom;
234 struct e1000_osdep osdep;
237 #define IGB_FLAG_SHARED_INTR 0x1
239 bus_dma_tag_t parent_tag;
242 struct resource *mem_res;
244 struct resource *msix_mem;
252 struct ifmedia media;
253 struct callout timer;
256 int msix; /* total vectors allocated */
260 struct resource *intr_res;
267 uint16_t vf_ifp; /* a VF interface */
269 /* Management and WOL features */
273 /* Info about the interface */
276 uint16_t link_duplex;
278 uint32_t dma_coalesce;
287 struct igb_tx_ring *tx_rings;
290 /* Multicast array pointer */
297 struct igb_rx_ring *rx_rings;
302 /* Misc stats maintained by the driver */
304 u_long mbuf_defrag_failed;
305 u_long no_tx_dma_setup;
306 u_long watchdog_events;
308 u_long device_control;
312 u_long packet_buf_alloc_rx;
313 u_long packet_buf_alloc_tx;
315 /* sysctl tree glue */
316 struct sysctl_ctx_list sysctl_ctx;
317 struct sysctl_oid *sysctl_tree;
324 bus_dmamap_t map; /* bus_dma map for packet */
329 bus_dmamap_t map; /* bus_dma map for packet */
333 #define UPDATE_VF_REG(reg, last, cur) \
335 uint32_t new = E1000_READ_REG(hw, reg); \
337 cur += 0x100000000LL; \
339 cur &= 0xFFFFFFFF00000000LL; \
343 #define IGB_IS_OACTIVE(txr) ((txr)->tx_avail < (txr)->oact_lo_desc)
344 #define IGB_IS_NOT_OACTIVE(txr) ((txr)->tx_avail >= (txr)->oact_hi_desc)
346 #endif /* _IF_IGB_H_ */