2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.9 2004/01/14 18:20:18 joerg Exp $
34 #include "opt_simos.h"
35 #include "opt_compat_oldpci.h"
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/fcntl.h>
43 #include <sys/kernel.h>
44 #include <sys/queue.h>
45 #include <sys/types.h>
50 #include <vm/vm_extern.h>
53 #include <machine/bus.h>
55 #include <machine/resource.h>
56 #include <machine/md_var.h> /* For the Alpha */
58 #include <machine/pci_cfgreg.h>
61 #include <sys/pciio.h>
66 #include <machine/rpb.h>
70 #include <machine/smp.h>
73 static devclass_t pci_devclass;
75 static void pci_read_extcap(pcicfgregs *cfg);
78 u_int32_t devid; /* Vendor/device of the card */
80 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
85 struct pci_quirk pci_quirks[] = {
87 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
89 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
90 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
95 /* map register information */
96 #define PCI_MAPMEM 0x01 /* memory map */
97 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
98 #define PCI_MAPPORT 0x04 /* port map */
100 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
101 u_int32_t pci_numdevs = 0;
102 static u_int32_t pci_generation = 0;
105 pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func)
107 struct pci_devinfo *dinfo;
109 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
110 if ((dinfo->cfg.bus == bus) &&
111 (dinfo->cfg.slot == slot) &&
112 (dinfo->cfg.func == func)) {
113 return (dinfo->cfg.dev);
121 pci_find_device (u_int16_t vendor, u_int16_t device)
123 struct pci_devinfo *dinfo;
125 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
126 if ((dinfo->cfg.vendor == vendor) &&
127 (dinfo->cfg.device == device)) {
128 return (dinfo->cfg.dev);
135 /* return base address of memory or port map */
138 pci_mapbase(unsigned mapreg)
141 if ((mapreg & 0x01) == 0)
143 return (mapreg & ~mask);
146 /* return map type of memory or port map */
149 pci_maptype(unsigned mapreg)
151 static u_int8_t maptype[0x10] = {
152 PCI_MAPMEM, PCI_MAPPORT,
154 PCI_MAPMEM, PCI_MAPPORT,
156 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
157 PCI_MAPMEM|PCI_MAPMEMP, 0,
158 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
162 return maptype[mapreg & 0x0f];
165 /* return log2 of map size decoded for memory or port map */
168 pci_mapsize(unsigned testval)
172 testval = pci_mapbase(testval);
175 while ((testval & 1) == 0)
184 /* return log2 of address range supported by map register */
187 pci_maprange(unsigned mapreg)
190 switch (mapreg & 0x07) {
206 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
209 pci_fixancient(pcicfgregs *cfg)
211 if (cfg->hdrtype != 0)
214 /* PCI to PCI bridges use header type 1 */
215 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
219 /* read config data specific to header type 1 device (PCI to PCI bridge) */
222 pci_readppb(pcicfgregs *cfg)
226 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK);
232 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_1, 2);
233 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_1, 2);
235 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_1, 1);
237 p->iobase = PCI_PPBIOBASE (pci_cfgread(cfg, PCIR_IOBASEH_1, 2),
238 pci_cfgread(cfg, PCIR_IOBASEL_1, 1));
239 p->iolimit = PCI_PPBIOLIMIT (pci_cfgread(cfg, PCIR_IOLIMITH_1, 2),
240 pci_cfgread(cfg, PCIR_IOLIMITL_1, 1));
242 p->membase = PCI_PPBMEMBASE (0,
243 pci_cfgread(cfg, PCIR_MEMBASE_1, 2));
244 p->memlimit = PCI_PPBMEMLIMIT (0,
245 pci_cfgread(cfg, PCIR_MEMLIMIT_1, 2));
247 p->pmembase = PCI_PPBMEMBASE (
248 (pci_addr_t)pci_cfgread(cfg, PCIR_PMBASEH_1, 4),
249 pci_cfgread(cfg, PCIR_PMBASEL_1, 2));
251 p->pmemlimit = PCI_PPBMEMLIMIT (
252 (pci_addr_t)pci_cfgread(cfg, PCIR_PMLIMITH_1, 4),
253 pci_cfgread(cfg, PCIR_PMLIMITL_1, 2));
257 /* read config data specific to header type 2 device (PCI to CardBus bridge) */
260 pci_readpcb(pcicfgregs *cfg)
264 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK);
270 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_2, 2);
271 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_2, 2);
273 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_2, 1);
275 p->membase0 = pci_cfgread(cfg, PCIR_MEMBASE0_2, 4);
276 p->memlimit0 = pci_cfgread(cfg, PCIR_MEMLIMIT0_2, 4);
277 p->membase1 = pci_cfgread(cfg, PCIR_MEMBASE1_2, 4);
278 p->memlimit1 = pci_cfgread(cfg, PCIR_MEMLIMIT1_2, 4);
280 p->iobase0 = pci_cfgread(cfg, PCIR_IOBASE0_2, 4);
281 p->iolimit0 = pci_cfgread(cfg, PCIR_IOLIMIT0_2, 4);
282 p->iobase1 = pci_cfgread(cfg, PCIR_IOBASE1_2, 4);
283 p->iolimit1 = pci_cfgread(cfg, PCIR_IOLIMIT1_2, 4);
285 p->pccardif = pci_cfgread(cfg, PCIR_PCCARDIF_2, 4);
289 /* extract header type specific config data */
292 pci_hdrtypedata(pcicfgregs *cfg)
294 switch (cfg->hdrtype) {
296 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_0, 2);
297 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_0, 2);
298 cfg->nummaps = PCI_MAXMAPS_0;
301 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_1, 2);
302 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_1, 2);
303 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_1, 1);
304 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_1, 1);
305 cfg->nummaps = PCI_MAXMAPS_1;
306 cfg->hdrspec = pci_readppb(cfg);
309 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_2, 2);
310 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_2, 2);
311 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_2, 1);
312 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_2, 1);
313 cfg->nummaps = PCI_MAXMAPS_2;
314 cfg->hdrspec = pci_readpcb(cfg);
319 /* read configuration header into pcicfgrect structure */
321 static struct pci_devinfo *
322 pci_readcfg(pcicfgregs *probe)
324 #define REG(n, w) pci_cfgread(probe, n, w)
326 pcicfgregs *cfg = NULL;
327 struct pci_devinfo *devlist_entry;
328 struct devlist *devlist_head;
330 devlist_head = &pci_devq;
332 devlist_entry = NULL;
334 if (pci_cfgread(probe, PCIR_DEVVENDOR, 4) != -1) {
336 devlist_entry = malloc(sizeof(struct pci_devinfo),
338 if (devlist_entry == NULL)
340 bzero(devlist_entry, sizeof *devlist_entry);
342 cfg = &devlist_entry->cfg;
344 cfg->hose = probe->hose;
345 cfg->bus = probe->bus;
346 cfg->slot = probe->slot;
347 cfg->func = probe->func;
348 cfg->vendor = pci_cfgread(cfg, PCIR_VENDOR, 2);
349 cfg->device = pci_cfgread(cfg, PCIR_DEVICE, 2);
350 cfg->cmdreg = pci_cfgread(cfg, PCIR_COMMAND, 2);
351 cfg->statreg = pci_cfgread(cfg, PCIR_STATUS, 2);
352 cfg->baseclass = pci_cfgread(cfg, PCIR_CLASS, 1);
353 cfg->subclass = pci_cfgread(cfg, PCIR_SUBCLASS, 1);
354 cfg->progif = pci_cfgread(cfg, PCIR_PROGIF, 1);
355 cfg->revid = pci_cfgread(cfg, PCIR_REVID, 1);
356 cfg->hdrtype = pci_cfgread(cfg, PCIR_HEADERTYPE, 1);
357 cfg->cachelnsz = pci_cfgread(cfg, PCIR_CACHELNSZ, 1);
358 cfg->lattimer = pci_cfgread(cfg, PCIR_LATTIMER, 1);
359 cfg->intpin = pci_cfgread(cfg, PCIR_INTPIN, 1);
360 cfg->intline = pci_cfgread(cfg, PCIR_INTLINE, 1);
362 alpha_platform_assign_pciintr(cfg);
366 if (cfg->intpin != 0) {
369 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
371 /* PCI specific entry found in MP table */
372 if (airq != cfg->intline) {
373 undirect_pci_irq(cfg->intline);
378 * PCI interrupts might be redirected to the
379 * ISA bus according to some MP tables. Use the
380 * same methods as used by the ISA devices
381 * devices to find the proper IOAPIC int pin.
383 airq = isa_apic_irq(cfg->intline);
384 if ((airq >= 0) && (airq != cfg->intline)) {
385 /* XXX: undirect_pci_irq() ? */
386 undirect_isa_irq(cfg->intline);
393 cfg->mingnt = pci_cfgread(cfg, PCIR_MINGNT, 1);
394 cfg->maxlat = pci_cfgread(cfg, PCIR_MAXLAT, 1);
396 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
397 cfg->hdrtype &= ~PCIM_MFDEV;
400 pci_hdrtypedata(cfg);
402 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
403 pci_read_extcap(cfg);
405 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
407 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
408 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
409 devlist_entry->conf.pc_sel.pc_func = cfg->func;
410 devlist_entry->conf.pc_hdr = cfg->hdrtype;
412 devlist_entry->conf.pc_subvendor = cfg->subvendor;
413 devlist_entry->conf.pc_subdevice = cfg->subdevice;
414 devlist_entry->conf.pc_vendor = cfg->vendor;
415 devlist_entry->conf.pc_device = cfg->device;
417 devlist_entry->conf.pc_class = cfg->baseclass;
418 devlist_entry->conf.pc_subclass = cfg->subclass;
419 devlist_entry->conf.pc_progif = cfg->progif;
420 devlist_entry->conf.pc_revid = cfg->revid;
425 return (devlist_entry);
430 pci_read_extcap(pcicfgregs *cfg)
432 #define REG(n, w) pci_cfgread(cfg, n, w)
433 int ptr, nextptr, ptrptr;
435 switch (cfg->hdrtype) {
443 return; /* no extended capabilities support */
445 nextptr = REG(ptrptr, 1); /* sanity check? */
448 * Read capability entries.
450 while (nextptr != 0) {
453 printf("illegal PCI extended capability offset %d\n",
457 /* Find the next entry */
459 nextptr = REG(ptr + 1, 1);
461 /* Process this entry */
462 switch (REG(ptr, 1)) {
463 case 0x01: /* PCI power management */
464 if (cfg->pp_cap == 0) {
465 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
466 cfg->pp_status = ptr + PCIR_POWER_STATUS;
467 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
468 if ((nextptr - ptr) > PCIR_POWER_DATA)
469 cfg->pp_data = ptr + PCIR_POWER_DATA;
480 /* free pcicfgregs structure and all depending data structures */
483 pci_freecfg(struct pci_devinfo *dinfo)
485 struct devlist *devlist_head;
487 devlist_head = &pci_devq;
489 if (dinfo->cfg.hdrspec != NULL)
490 free(dinfo->cfg.hdrspec, M_DEVBUF);
491 if (dinfo->cfg.map != NULL)
492 free(dinfo->cfg.map, M_DEVBUF);
493 /* XXX this hasn't been tested */
494 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
495 free(dinfo, M_DEVBUF);
497 /* increment the generation count */
500 /* we're losing one device */
508 * PCI power manangement
511 pci_set_powerstate_method(device_t dev, device_t child, int state)
513 struct pci_devinfo *dinfo = device_get_ivars(child);
514 pcicfgregs *cfg = &dinfo->cfg;
518 if (cfg->pp_cap != 0) {
519 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK;
522 case PCI_POWERSTATE_D0:
523 status |= PCIM_PSTAT_D0;
525 case PCI_POWERSTATE_D1:
526 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) {
527 status |= PCIM_PSTAT_D1;
532 case PCI_POWERSTATE_D2:
533 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) {
534 status |= PCIM_PSTAT_D2;
539 case PCI_POWERSTATE_D3:
540 status |= PCIM_PSTAT_D3;
546 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2);
554 pci_get_powerstate_method(device_t dev, device_t child)
556 struct pci_devinfo *dinfo = device_get_ivars(child);
557 pcicfgregs *cfg = &dinfo->cfg;
561 if (cfg->pp_cap != 0) {
562 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2);
563 switch (status & PCIM_PSTAT_DMASK) {
565 result = PCI_POWERSTATE_D0;
568 result = PCI_POWERSTATE_D1;
571 result = PCI_POWERSTATE_D2;
574 result = PCI_POWERSTATE_D3;
577 result = PCI_POWERSTATE_UNKNOWN;
581 /* No support, device is always at D0 */
582 result = PCI_POWERSTATE_D0;
588 * Some convenience functions for PCI device drivers.
592 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
596 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
598 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
602 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
606 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
608 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
612 pci_enable_busmaster_method(device_t dev, device_t child)
614 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
618 pci_disable_busmaster_method(device_t dev, device_t child)
620 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
624 pci_enable_io_method(device_t dev, device_t child, int space)
628 pci_set_command_bit(dev, child, PCIM_CMD_PORTEN);
631 pci_set_command_bit(dev, child, PCIM_CMD_MEMEN);
637 pci_disable_io_method(device_t dev, device_t child, int space)
641 pci_clear_command_bit(dev, child, PCIM_CMD_PORTEN);
644 pci_clear_command_bit(dev, child, PCIM_CMD_MEMEN);
650 * This is the user interface to PCI configuration space.
654 pci_open(dev_t dev, int oflags, int devtype, struct thread *td)
656 if ((oflags & FWRITE) && securelevel > 0) {
663 pci_close(dev_t dev, int flag, int devtype, struct thread *td)
669 * Match a single pci_conf structure against an array of pci_match_conf
670 * structures. The first argument, 'matches', is an array of num_matches
671 * pci_match_conf structures. match_buf is a pointer to the pci_conf
672 * structure that will be compared to every entry in the matches array.
673 * This function returns 1 on failure, 0 on success.
676 pci_conf_match(struct pci_match_conf *matches, int num_matches,
677 struct pci_conf *match_buf)
681 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
684 for (i = 0; i < num_matches; i++) {
686 * I'm not sure why someone would do this...but...
688 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
692 * Look at each of the match flags. If it's set, do the
693 * comparison. If the comparison fails, we don't have a
694 * match, go on to the next item if there is one.
696 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
697 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
700 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
701 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
704 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
705 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
708 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
709 && (match_buf->pc_vendor != matches[i].pc_vendor))
712 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
713 && (match_buf->pc_device != matches[i].pc_device))
716 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
717 && (match_buf->pc_class != matches[i].pc_class))
720 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
721 && (match_buf->pd_unit != matches[i].pd_unit))
724 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
725 && (strncmp(matches[i].pd_name, match_buf->pd_name,
726 sizeof(match_buf->pd_name)) != 0))
736 * Locate the parent of a PCI device by scanning the PCI devlist
737 * and return the entry for the parent.
738 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
739 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
743 pci_devlist_get_parent(pcicfgregs *cfg)
745 struct devlist *devlist_head;
746 struct pci_devinfo *dinfo;
747 pcicfgregs *bridge_cfg;
750 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
752 /* If the device is on PCI bus 0, look for the host */
754 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
755 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
756 bridge_cfg = &dinfo->cfg;
757 if (bridge_cfg->baseclass == PCIC_BRIDGE
758 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
759 && bridge_cfg->bus == cfg->bus) {
765 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
767 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
768 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
769 bridge_cfg = &dinfo->cfg;
770 if (bridge_cfg->baseclass == PCIC_BRIDGE
771 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
772 && bridge_cfg->secondarybus == cfg->bus) {
782 pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td)
788 if (!(flag & FWRITE))
795 struct pci_devinfo *dinfo;
796 struct pci_conf_io *cio;
797 struct devlist *devlist_head;
798 struct pci_match_conf *pattern_buf;
803 cio = (struct pci_conf_io *)data;
809 * Hopefully the user won't pass in a null pointer, but it
810 * can't hurt to check.
818 * If the user specified an offset into the device list,
819 * but the list has changed since they last called this
820 * ioctl, tell them that the list has changed. They will
821 * have to get the list from the beginning.
823 if ((cio->offset != 0)
824 && (cio->generation != pci_generation)){
825 cio->num_matches = 0;
826 cio->status = PCI_GETCONF_LIST_CHANGED;
832 * Check to see whether the user has asked for an offset
833 * past the end of our list.
835 if (cio->offset >= pci_numdevs) {
836 cio->num_matches = 0;
837 cio->status = PCI_GETCONF_LAST_DEVICE;
842 /* get the head of the device queue */
843 devlist_head = &pci_devq;
846 * Determine how much room we have for pci_conf structures.
847 * Round the user's buffer size down to the nearest
848 * multiple of sizeof(struct pci_conf) in case the user
849 * didn't specify a multiple of that size.
851 iolen = min(cio->match_buf_len -
852 (cio->match_buf_len % sizeof(struct pci_conf)),
853 pci_numdevs * sizeof(struct pci_conf));
856 * Since we know that iolen is a multiple of the size of
857 * the pciconf union, it's okay to do this.
859 ionum = iolen / sizeof(struct pci_conf);
862 * If this test is true, the user wants the pci_conf
863 * structures returned to match the supplied entries.
865 if ((cio->num_patterns > 0)
866 && (cio->pat_buf_len > 0)) {
868 * pat_buf_len needs to be:
869 * num_patterns * sizeof(struct pci_match_conf)
870 * While it is certainly possible the user just
871 * allocated a large buffer, but set the number of
872 * matches correctly, it is far more likely that
873 * their kernel doesn't match the userland utility
874 * they're using. It's also possible that the user
875 * forgot to initialize some variables. Yes, this
876 * may be overly picky, but I hazard to guess that
877 * it's far more likely to just catch folks that
878 * updated their kernel but not their userland.
880 if ((cio->num_patterns *
881 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
882 /* The user made a mistake, return an error*/
883 cio->status = PCI_GETCONF_ERROR;
884 printf("pci_ioctl: pat_buf_len %d != "
885 "num_patterns (%d) * sizeof(struct "
886 "pci_match_conf) (%d)\npci_ioctl: "
887 "pat_buf_len should be = %d\n",
888 cio->pat_buf_len, cio->num_patterns,
889 (int)sizeof(struct pci_match_conf),
890 (int)sizeof(struct pci_match_conf) *
892 printf("pci_ioctl: do your headers match your "
894 cio->num_matches = 0;
900 * Check the user's buffer to make sure it's readable.
902 if (!useracc((caddr_t)cio->patterns,
903 cio->pat_buf_len, VM_PROT_READ)) {
904 printf("pci_ioctl: pattern buffer %p, "
905 "length %u isn't user accessible for"
906 " READ\n", cio->patterns,
912 * Allocate a buffer to hold the patterns.
914 pattern_buf = malloc(cio->pat_buf_len, M_TEMP,
916 error = copyin(cio->patterns, pattern_buf,
920 num_patterns = cio->num_patterns;
922 } else if ((cio->num_patterns > 0)
923 || (cio->pat_buf_len > 0)) {
925 * The user made a mistake, spit out an error.
927 cio->status = PCI_GETCONF_ERROR;
928 cio->num_matches = 0;
929 printf("pci_ioctl: invalid GETCONF arguments\n");
936 * Make sure we can write to the match buffer.
938 if (!useracc((caddr_t)cio->matches,
939 cio->match_buf_len, VM_PROT_WRITE)) {
940 printf("pci_ioctl: match buffer %p, length %u "
941 "isn't user accessible for WRITE\n",
942 cio->matches, cio->match_buf_len);
948 * Go through the list of devices and copy out the devices
949 * that match the user's criteria.
951 for (cio->num_matches = 0, error = 0, i = 0,
952 dinfo = STAILQ_FIRST(devlist_head);
953 (dinfo != NULL) && (cio->num_matches < ionum)
954 && (error == 0) && (i < pci_numdevs);
955 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
960 /* Populate pd_name and pd_unit */
962 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
963 name = device_get_name(dinfo->cfg.dev);
965 strncpy(dinfo->conf.pd_name, name,
966 sizeof(dinfo->conf.pd_name));
967 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
968 dinfo->conf.pd_unit =
969 device_get_unit(dinfo->cfg.dev);
972 if ((pattern_buf == NULL) ||
973 (pci_conf_match(pattern_buf, num_patterns,
974 &dinfo->conf) == 0)) {
977 * If we've filled up the user's buffer,
978 * break out at this point. Since we've
979 * got a match here, we'll pick right back
980 * up at the matching entry. We can also
981 * tell the user that there are more matches
984 if (cio->num_matches >= ionum)
987 error = copyout(&dinfo->conf,
988 &cio->matches[cio->num_matches],
989 sizeof(struct pci_conf));
995 * Set the pointer into the list, so if the user is getting
996 * n records at a time, where n < pci_numdevs,
1001 * Set the generation, the user will need this if they make
1002 * another ioctl call with offset != 0.
1004 cio->generation = pci_generation;
1007 * If this is the last device, inform the user so he won't
1008 * bother asking for more devices. If dinfo isn't NULL, we
1009 * know that there are more matches in the list because of
1010 * the way the traversal is done.
1013 cio->status = PCI_GETCONF_LAST_DEVICE;
1015 cio->status = PCI_GETCONF_MORE_DEVS;
1017 if (pattern_buf != NULL)
1018 free(pattern_buf, M_TEMP);
1023 io = (struct pci_io *)data;
1024 switch(io->pi_width) {
1030 probe.bus = io->pi_sel.pc_bus;
1031 probe.slot = io->pi_sel.pc_dev;
1032 probe.func = io->pi_sel.pc_func;
1033 io->pi_data = pci_cfgread(&probe,
1034 io->pi_reg, io->pi_width);
1044 io = (struct pci_io *)data;
1045 switch(io->pi_width) {
1051 probe.bus = io->pi_sel.pc_bus;
1052 probe.slot = io->pi_sel.pc_dev;
1053 probe.func = io->pi_sel.pc_func;
1054 pci_cfgwrite(&probe,
1055 io->pi_reg, io->pi_data, io->pi_width);
1074 static struct cdevsw pcicdev = {
1081 /* open */ pci_open,
1082 /* close */ pci_close,
1084 /* write */ nowrite,
1085 /* ioctl */ pci_ioctl,
1088 /* strategy */ nostrategy,
1096 * New style pci driver. Parent device is either a pci-host-bridge or a
1097 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1101 pci_print_verbose(struct pci_devinfo *dinfo)
1104 pcicfgregs *cfg = &dinfo->cfg;
1106 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
1107 cfg->vendor, cfg->device, cfg->revid);
1108 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
1109 cfg->baseclass, cfg->subclass, cfg->progif,
1110 cfg->hdrtype, cfg->mfdev);
1111 printf("\tsubordinatebus=%x \tsecondarybus=%x\n",
1112 cfg->subordinatebus, cfg->secondarybus);
1114 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
1115 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
1116 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
1117 cfg->lattimer, cfg->lattimer * 30,
1118 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1119 #endif /* PCI_DEBUG */
1120 if (cfg->intpin > 0)
1121 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
1126 pci_porten(pcicfgregs *cfg)
1128 return ((cfg->cmdreg & PCIM_CMD_PORTEN) != 0);
1132 pci_memen(pcicfgregs *cfg)
1134 return ((cfg->cmdreg & PCIM_CMD_MEMEN) != 0);
1138 * Add a resource based on a pci map register. Return 1 if the map
1139 * register is a 32bit map register or 2 if it is a 64bit register.
1142 pci_add_map(device_t dev, pcicfgregs* cfg, int reg)
1144 struct pci_devinfo *dinfo = device_get_ivars(dev);
1145 struct resource_list *rl = &dinfo->resources;
1154 map = pci_cfgread(cfg, reg, 4);
1156 if (map == 0 || map == 0xffffffff)
1157 return 1; /* skip invalid entry */
1159 pci_cfgwrite(cfg, reg, 0xffffffff, 4);
1160 testval = pci_cfgread(cfg, reg, 4);
1161 pci_cfgwrite(cfg, reg, map, 4);
1163 base = pci_mapbase(map);
1164 if (pci_maptype(map) & PCI_MAPMEM)
1165 type = SYS_RES_MEMORY;
1167 type = SYS_RES_IOPORT;
1168 ln2size = pci_mapsize(testval);
1169 ln2range = pci_maprange(testval);
1170 if (ln2range == 64) {
1171 /* Read the other half of a 64bit map register */
1172 base |= (u_int64_t) pci_cfgread(cfg, reg + 4, 4) << 32;
1177 * XXX: encode hose number in the base addr,
1178 * This will go away once the bus_space functions
1179 * can deal with multiple hoses
1183 u_int32_t mask, shift, maxh;
1185 switch (hwrpb->rpb_type) {
1190 maxh = 4; /* not a hose. MCPCIA instance # */
1209 printf("base addr = 0x%llx\n", (long long) base);
1210 printf("mask addr = 0x%lx\n", (long) mask);
1211 printf("hacked addr = 0x%llx\n", (long long)
1212 (base | ((u_int64_t)cfg->hose << shift)));
1213 panic("hose encoding hack would clobber base addr");
1216 if (cfg->hose >= maxh) {
1217 panic("Hose %d - can only encode %d hose(s)",
1221 base |= ((u_int64_t)cfg->hose << shift);
1226 * This code theoretically does the right thing, but has
1227 * undesirable side effects in some cases where
1228 * peripherals respond oddly to having these bits
1229 * enabled. Leave them alone by default.
1231 #ifdef PCI_ENABLE_IO_MODES
1232 if (type == SYS_RES_IOPORT && !pci_porten(cfg)) {
1233 cfg->cmdreg |= PCIM_CMD_PORTEN;
1234 pci_cfgwrite(cfg, PCIR_COMMAND, cfg->cmdreg, 2);
1236 if (type == SYS_RES_MEMORY && !pci_memen(cfg)) {
1237 cfg->cmdreg |= PCIM_CMD_MEMEN;
1238 pci_cfgwrite(cfg, PCIR_COMMAND, cfg->cmdreg, 2);
1241 if (type == SYS_RES_IOPORT && !pci_porten(cfg))
1243 if (type == SYS_RES_MEMORY && !pci_memen(cfg))
1247 resource_list_add(rl, type, reg,
1248 base, base + (1 << ln2size) - 1,
1252 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
1253 reg, pci_maptype(base), ln2range,
1254 (unsigned int) base, ln2size);
1257 return (ln2range == 64) ? 2 : 1;
1261 pci_add_resources(device_t dev, pcicfgregs* cfg)
1263 struct pci_devinfo *dinfo = device_get_ivars(dev);
1264 struct resource_list *rl = &dinfo->resources;
1265 struct pci_quirk *q;
1268 for (i = 0; i < cfg->nummaps;) {
1269 i += pci_add_map(dev, cfg, PCIR_MAPS + i*4);
1272 for (q = &pci_quirks[0]; q->devid; q++) {
1273 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1274 && q->type == PCI_QUIRK_MAP_REG)
1275 pci_add_map(dev, cfg, q->arg1);
1278 if (cfg->intpin > 0 && cfg->intline != 255)
1279 resource_list_add(rl, SYS_RES_IRQ, 0,
1280 cfg->intline, cfg->intline, 1);
1284 pci_add_children(device_t dev, int busno)
1290 #define PCI_SLOTMAX 0
1293 bzero(&probe, sizeof probe);
1295 probe.hose = pcib_get_hose(dev);
1302 for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) {
1303 int pcifunchigh = 0;
1304 for (probe.func = 0; probe.func <= pcifunchigh; probe.func++) {
1305 struct pci_devinfo *dinfo = pci_readcfg(&probe);
1306 if (dinfo != NULL) {
1307 if (dinfo->cfg.mfdev)
1310 pci_print_verbose(dinfo);
1311 dinfo->cfg.dev = device_add_child(dev, NULL, -1);
1312 device_set_ivars(dinfo->cfg.dev, dinfo);
1313 pci_add_resources(dinfo->cfg.dev, &dinfo->cfg);
1320 pci_new_probe(device_t dev)
1324 device_set_desc(dev, "PCI bus");
1325 pci_add_children(dev, device_get_unit(dev));
1327 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci");
1335 pci_print_resources(struct resource_list *rl, const char *name, int type,
1338 struct resource_list_entry *rle;
1339 int printed, retval;
1343 /* Yes, this is kinda cheating */
1344 SLIST_FOREACH(rle, rl, link) {
1345 if (rle->type == type) {
1347 retval += printf(" %s ", name);
1348 else if (printed > 0)
1349 retval += printf(",");
1351 retval += printf(format, rle->start);
1352 if (rle->count > 1) {
1353 retval += printf("-");
1354 retval += printf(format, rle->start +
1363 pci_print_child(device_t dev, device_t child)
1365 struct pci_devinfo *dinfo;
1366 struct resource_list *rl;
1370 dinfo = device_get_ivars(child);
1372 rl = &dinfo->resources;
1374 retval += bus_print_child_header(dev, child);
1376 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1377 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1378 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1379 if (device_get_flags(dev))
1380 retval += printf(" flags %#x", device_get_flags(dev));
1382 retval += printf(" at device %d.%d", pci_get_slot(child),
1383 pci_get_function(child));
1385 retval += bus_print_child_footer(dev, child);
1391 pci_probe_nomatch(device_t dev, device_t child)
1393 struct pci_devinfo *dinfo;
1399 dinfo = device_get_ivars(child);
1401 desc = pci_ata_match(child);
1402 if (!desc) desc = pci_usb_match(child);
1403 if (!desc) desc = pci_vga_match(child);
1404 if (!desc) desc = pci_chip_match(child);
1406 desc = "unknown card";
1409 device_printf(dev, "<%s>", desc);
1410 if (bootverbose || unknown) {
1411 printf(" (vendor=0x%04x, dev=0x%04x)",
1416 pci_get_slot(child),
1417 pci_get_function(child));
1418 if (cfg->intpin > 0 && cfg->intline != 255) {
1419 printf(" irq %d", cfg->intline);
1427 pci_read_ivar(device_t dev, device_t child, int which, u_long *result)
1429 struct pci_devinfo *dinfo;
1432 dinfo = device_get_ivars(child);
1436 case PCI_IVAR_SUBVENDOR:
1437 *result = cfg->subvendor;
1439 case PCI_IVAR_SUBDEVICE:
1440 *result = cfg->subdevice;
1442 case PCI_IVAR_VENDOR:
1443 *result = cfg->vendor;
1445 case PCI_IVAR_DEVICE:
1446 *result = cfg->device;
1448 case PCI_IVAR_DEVID:
1449 *result = (cfg->device << 16) | cfg->vendor;
1451 case PCI_IVAR_CLASS:
1452 *result = cfg->baseclass;
1454 case PCI_IVAR_SUBCLASS:
1455 *result = cfg->subclass;
1457 case PCI_IVAR_PROGIF:
1458 *result = cfg->progif;
1460 case PCI_IVAR_REVID:
1461 *result = cfg->revid;
1463 case PCI_IVAR_INTPIN:
1464 *result = cfg->intpin;
1467 *result = cfg->intline;
1473 *result = cfg->slot;
1475 case PCI_IVAR_FUNCTION:
1476 *result = cfg->func;
1478 case PCI_IVAR_SECONDARYBUS:
1479 *result = cfg->secondarybus;
1481 case PCI_IVAR_SUBORDINATEBUS:
1482 *result = cfg->subordinatebus;
1486 * Pass up to parent bridge.
1488 *result = pcib_get_hose(dev);
1497 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1499 struct pci_devinfo *dinfo;
1502 dinfo = device_get_ivars(child);
1506 case PCI_IVAR_SUBVENDOR:
1507 case PCI_IVAR_SUBDEVICE:
1508 case PCI_IVAR_VENDOR:
1509 case PCI_IVAR_DEVICE:
1510 case PCI_IVAR_DEVID:
1511 case PCI_IVAR_CLASS:
1512 case PCI_IVAR_SUBCLASS:
1513 case PCI_IVAR_PROGIF:
1514 case PCI_IVAR_REVID:
1515 case PCI_IVAR_INTPIN:
1519 case PCI_IVAR_FUNCTION:
1520 return EINVAL; /* disallow for now */
1522 case PCI_IVAR_SECONDARYBUS:
1523 cfg->secondarybus = value;
1525 case PCI_IVAR_SUBORDINATEBUS:
1526 cfg->subordinatebus = value;
1534 static struct resource *
1535 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1536 u_long start, u_long end, u_long count, u_int flags)
1538 struct pci_devinfo *dinfo = device_get_ivars(child);
1539 struct resource_list *rl = &dinfo->resources;
1541 #ifdef __i386__ /* Only supported on x86 in stable */
1542 pcicfgregs *cfg = &dinfo->cfg;
1544 * Perform lazy resource allocation
1546 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY
1548 if (device_get_parent(child) == dev) {
1550 * If device doesn't have an interrupt routed, and is
1551 * deserving of an interrupt, try to assign it one.
1553 if ((type == SYS_RES_IRQ) &&
1554 (cfg->intline == 255 || cfg->intline == 0) &&
1555 (cfg->intpin != 0) && (start == 0) && (end == ~0UL)) {
1556 cfg->intline = pci_cfgintr(pci_get_bus(child),
1557 pci_get_slot(child), cfg->intpin);
1558 if (cfg->intline != 255) {
1559 pci_write_config(child, PCIR_INTLINE,
1561 resource_list_add(rl, SYS_RES_IRQ, 0,
1562 cfg->intline, cfg->intline, 1);
1567 return resource_list_alloc(rl, dev, child, type, rid,
1568 start, end, count, flags);
1572 pci_release_resource(device_t dev, device_t child, int type, int rid,
1575 struct pci_devinfo *dinfo = device_get_ivars(child);
1576 struct resource_list *rl = &dinfo->resources;
1578 return resource_list_release(rl, dev, child, type, rid, r);
1582 pci_set_resource(device_t dev, device_t child, int type, int rid,
1583 u_long start, u_long count)
1585 struct pci_devinfo *dinfo = device_get_ivars(child);
1586 struct resource_list *rl = &dinfo->resources;
1588 resource_list_add(rl, type, rid, start, start + count - 1, count);
1593 pci_get_resource(device_t dev, device_t child, int type, int rid,
1594 u_long *startp, u_long *countp)
1596 struct pci_devinfo *dinfo = device_get_ivars(child);
1597 struct resource_list *rl = &dinfo->resources;
1598 struct resource_list_entry *rle;
1600 rle = resource_list_find(rl, type, rid);
1605 *startp = rle->start;
1607 *countp = rle->count;
1613 pci_delete_resource(device_t dev, device_t child, int type, int rid)
1615 printf("pci_delete_resource: PCI resources can not be deleted\n");
1619 pci_read_config_method(device_t dev, device_t child, int reg, int width)
1621 struct pci_devinfo *dinfo = device_get_ivars(child);
1622 pcicfgregs *cfg = &dinfo->cfg;
1623 return pci_cfgread(cfg, reg, width);
1627 pci_write_config_method(device_t dev, device_t child, int reg,
1628 u_int32_t val, int width)
1630 struct pci_devinfo *dinfo = device_get_ivars(child);
1631 pcicfgregs *cfg = &dinfo->cfg;
1632 pci_cfgwrite(cfg, reg, val, width);
1636 pci_modevent(module_t mod, int what, void *arg)
1640 STAILQ_INIT(&pci_devq);
1650 static device_method_t pci_methods[] = {
1651 /* Device interface */
1652 DEVMETHOD(device_probe, pci_new_probe),
1653 DEVMETHOD(device_attach, bus_generic_attach),
1654 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1655 DEVMETHOD(device_suspend, bus_generic_suspend),
1656 DEVMETHOD(device_resume, bus_generic_resume),
1659 DEVMETHOD(bus_print_child, pci_print_child),
1660 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
1661 DEVMETHOD(bus_read_ivar, pci_read_ivar),
1662 DEVMETHOD(bus_write_ivar, pci_write_ivar),
1663 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1664 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
1665 DEVMETHOD(bus_release_resource, pci_release_resource),
1666 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1667 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1668 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1669 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1670 DEVMETHOD(bus_set_resource, pci_set_resource),
1671 DEVMETHOD(bus_get_resource, pci_get_resource),
1672 DEVMETHOD(bus_delete_resource, pci_delete_resource),
1675 DEVMETHOD(pci_read_config, pci_read_config_method),
1676 DEVMETHOD(pci_write_config, pci_write_config_method),
1677 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
1678 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
1679 DEVMETHOD(pci_enable_io, pci_enable_io_method),
1680 DEVMETHOD(pci_disable_io, pci_disable_io_method),
1681 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
1682 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
1687 static driver_t pci_driver = {
1693 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);