1 /* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */
2 /* $FreeBSD: src/sys/dev/txp/if_txp.c,v 1.4.2.4 2001/12/14 19:50:43 jlemon Exp $ */
3 /* $DragonFly: src/sys/dev/netif/txp/if_txp.c,v 1.30 2005/06/20 15:10:41 joerg Exp $ */
7 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and
8 * Aaron Campbell <aaron@monkey.org>. All rights reserved.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Jason L. Wright,
21 * Theo de Raadt and Aaron Campbell.
22 * 4. Neither the name of the author nor the names of any co-contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
36 * THE POSSIBILITY OF SUCH DAMAGE.
40 * Driver for 3c990 (Typhoon) Ethernet ASIC
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/sockio.h>
47 #include <sys/malloc.h>
48 #include <sys/kernel.h>
49 #include <sys/socket.h>
50 #include <sys/thread2.h>
53 #include <net/ifq_var.h>
54 #include <net/if_arp.h>
55 #include <net/ethernet.h>
56 #include <net/if_dl.h>
57 #include <net/if_types.h>
58 #include <net/vlan/if_vlan_var.h>
60 #include <netinet/in.h>
61 #include <netinet/in_systm.h>
62 #include <netinet/in_var.h>
63 #include <netinet/ip.h>
64 #include <netinet/if_ether.h>
65 #include <sys/in_cksum.h>
67 #include <net/if_media.h>
71 #include <vm/vm.h> /* for vtophys */
72 #include <vm/pmap.h> /* for vtophys */
73 #include <machine/bus_pio.h>
74 #include <machine/bus_memio.h>
75 #include <machine/bus.h>
76 #include <machine/resource.h>
80 #include "../mii_layer/mii.h"
81 #include "../mii_layer/miivar.h"
82 #include <bus/pci/pcireg.h>
83 #include <bus/pci/pcivar.h>
85 #define TXP_USEIOSPACE
86 #define __STRICT_ALIGNMENT
88 #include "if_txpreg.h"
92 * Various supported device vendors/types and their names.
94 static struct txp_type txp_devs[] = {
95 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_95,
96 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" },
97 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_97,
98 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" },
99 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_TXM,
100 "3Com 3cR990B-TXM Etherlink with 3XP Processor" },
101 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_95,
102 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" },
103 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_97,
104 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" },
105 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_SRV,
106 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" },
110 static int txp_probe (device_t);
111 static int txp_attach (device_t);
112 static int txp_detach (device_t);
113 static void txp_intr (void *);
114 static void txp_tick (void *);
115 static int txp_shutdown (device_t);
116 static int txp_ioctl (struct ifnet *, u_long, caddr_t, struct ucred *);
117 static void txp_start (struct ifnet *);
118 static void txp_stop (struct txp_softc *);
119 static void txp_init (void *);
120 static void txp_watchdog (struct ifnet *);
122 static void txp_release_resources (device_t);
123 static int txp_chip_init (struct txp_softc *);
124 static int txp_reset_adapter (struct txp_softc *);
125 static int txp_download_fw (struct txp_softc *);
126 static int txp_download_fw_wait (struct txp_softc *);
127 static int txp_download_fw_section (struct txp_softc *,
128 struct txp_fw_section_header *, int);
129 static int txp_alloc_rings (struct txp_softc *);
130 static int txp_rxring_fill (struct txp_softc *);
131 static void txp_rxring_empty (struct txp_softc *);
132 static void txp_set_filter (struct txp_softc *);
134 static int txp_cmd_desc_numfree (struct txp_softc *);
135 static int txp_command (struct txp_softc *, u_int16_t, u_int16_t, u_int32_t,
136 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int);
137 static int txp_command2 (struct txp_softc *, u_int16_t, u_int16_t,
138 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t,
139 struct txp_rsp_desc **, int);
140 static int txp_response (struct txp_softc *, u_int32_t, u_int16_t, u_int16_t,
141 struct txp_rsp_desc **);
142 static void txp_rsp_fixup (struct txp_softc *, struct txp_rsp_desc *,
143 struct txp_rsp_desc *);
144 static void txp_capabilities (struct txp_softc *);
146 static void txp_ifmedia_sts (struct ifnet *, struct ifmediareq *);
147 static int txp_ifmedia_upd (struct ifnet *);
149 static void txp_show_descriptor (void *);
151 static void txp_tx_reclaim (struct txp_softc *, struct txp_tx_ring *);
152 static void txp_rxbuf_reclaim (struct txp_softc *);
153 static void txp_rx_reclaim (struct txp_softc *, struct txp_rx_ring *);
155 #ifdef TXP_USEIOSPACE
156 #define TXP_RES SYS_RES_IOPORT
157 #define TXP_RID TXP_PCI_LOIO
159 #define TXP_RES SYS_RES_MEMORY
160 #define TXP_RID TXP_PCI_LOMEM
163 static device_method_t txp_methods[] = {
164 /* Device interface */
165 DEVMETHOD(device_probe, txp_probe),
166 DEVMETHOD(device_attach, txp_attach),
167 DEVMETHOD(device_detach, txp_detach),
168 DEVMETHOD(device_shutdown, txp_shutdown),
172 static driver_t txp_driver = {
175 sizeof(struct txp_softc)
178 static devclass_t txp_devclass;
180 DECLARE_DUMMY_MODULE(if_txp);
181 DRIVER_MODULE(if_txp, pci, txp_driver, txp_devclass, 0, 0);
190 vid = pci_get_vendor(dev);
191 did = pci_get_device(dev);
193 for (t = txp_devs; t->txp_name != NULL; ++t) {
194 if ((vid == t->txp_vid) && (did == t->txp_did)) {
195 device_set_desc(dev, t->txp_name);
207 struct txp_softc *sc;
211 uint8_t enaddr[ETHER_ADDR_LEN];
214 sc = device_get_softc(dev);
215 callout_init(&sc->txp_stat_timer);
217 ifp = &sc->sc_arpcom.ac_if;
218 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
220 pci_enable_busmaster(dev);
223 sc->sc_res = bus_alloc_resource_any(dev, TXP_RES, &rid, RF_ACTIVE);
225 if (sc->sc_res == NULL) {
226 device_printf(dev, "couldn't map ports/memory\n");
230 sc->sc_bt = rman_get_bustag(sc->sc_res);
231 sc->sc_bh = rman_get_bushandle(sc->sc_res);
233 /* Allocate interrupt */
235 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
236 RF_SHAREABLE | RF_ACTIVE);
238 if (sc->sc_irq == NULL) {
239 device_printf(dev, "couldn't map interrupt\n");
244 if (txp_chip_init(sc)) {
249 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF,
250 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
251 error = txp_download_fw(sc);
252 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF);
258 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF,
259 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
260 bzero(sc->sc_ldata, sizeof(struct txp_ldata));
262 if (txp_alloc_rings(sc)) {
267 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
268 NULL, NULL, NULL, 1)) {
273 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0,
274 &p1, &p2, NULL, 1)) {
281 enaddr[0] = ((uint8_t *)&p1)[1];
282 enaddr[1] = ((uint8_t *)&p1)[0];
283 enaddr[2] = ((uint8_t *)&p2)[3];
284 enaddr[3] = ((uint8_t *)&p2)[2];
285 enaddr[4] = ((uint8_t *)&p2)[1];
286 enaddr[5] = ((uint8_t *)&p2)[0];
288 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts);
289 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
290 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
291 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
292 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
293 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
294 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
295 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
297 sc->sc_xcvr = TXP_XCVR_AUTO;
298 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0,
299 NULL, NULL, NULL, 0);
300 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO);
303 ifp->if_mtu = ETHERMTU;
304 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
305 ifp->if_ioctl = txp_ioctl;
306 ifp->if_start = txp_start;
307 ifp->if_watchdog = txp_watchdog;
308 ifp->if_init = txp_init;
309 ifp->if_baudrate = 100000000;
310 ifq_set_maxlen(&ifp->if_snd, TX_ENTRIES);
311 ifq_set_ready(&ifp->if_snd);
312 ifp->if_hwassist = 0;
313 txp_capabilities(sc);
315 ether_ifattach(ifp, enaddr);
317 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET,
318 txp_intr, sc, &sc->sc_intrhand, NULL);
320 device_printf(dev, "couldn't set up irq\n");
328 txp_release_resources(dev);
336 struct txp_softc *sc;
342 sc = device_get_softc(dev);
343 ifp = &sc->sc_arpcom.ac_if;
348 ifmedia_removeall(&sc->sc_ifmedia);
351 for (i = 0; i < RXBUF_ENTRIES; i++)
352 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF);
354 txp_release_resources(dev);
362 txp_release_resources(device_t dev)
364 struct txp_softc *sc;
366 sc = device_get_softc(dev);
368 if (sc->sc_intrhand != NULL)
369 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
371 if (sc->sc_irq != NULL)
372 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
374 if (sc->sc_res != NULL)
375 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res);
377 if (sc->sc_ldata != NULL)
378 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF);
385 struct txp_softc *sc;
387 /* disable interrupts */
388 WRITE_REG(sc, TXP_IER, 0);
389 WRITE_REG(sc, TXP_IMR,
390 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
391 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
394 /* ack all interrupts */
395 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
396 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
397 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
398 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
399 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
401 if (txp_reset_adapter(sc))
404 /* disable interrupts */
405 WRITE_REG(sc, TXP_IER, 0);
406 WRITE_REG(sc, TXP_IMR,
407 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
408 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
411 /* ack all interrupts */
412 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
413 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
414 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
415 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
416 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
422 txp_reset_adapter(sc)
423 struct txp_softc *sc;
428 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL);
430 WRITE_REG(sc, TXP_SRR, 0);
432 /* Should wait max 6 seconds */
433 for (i = 0; i < 6000; i++) {
434 r = READ_REG(sc, TXP_A2H_0);
435 if (r == STAT_WAITING_FOR_HOST_REQUEST)
440 if (r != STAT_WAITING_FOR_HOST_REQUEST) {
441 if_printf(&sc->sc_arpcom.ac_if, "reset hung\n");
450 struct txp_softc *sc;
452 struct txp_fw_file_header *fileheader;
453 struct txp_fw_section_header *secthead;
455 u_int32_t r, i, ier, imr;
457 ier = READ_REG(sc, TXP_IER);
458 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0);
460 imr = READ_REG(sc, TXP_IMR);
461 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0);
463 for (i = 0; i < 10000; i++) {
464 r = READ_REG(sc, TXP_A2H_0);
465 if (r == STAT_WAITING_FOR_HOST_REQUEST)
469 if (r != STAT_WAITING_FOR_HOST_REQUEST) {
470 if_printf(&sc->sc_arpcom.ac_if,
471 "not waiting for host request\n");
476 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
478 fileheader = (struct txp_fw_file_header *)tc990image;
479 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) {
480 if_printf(&sc->sc_arpcom.ac_if, "fw invalid magic\n");
484 /* Tell boot firmware to get ready for image */
485 WRITE_REG(sc, TXP_H2A_1, fileheader->addr);
486 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE);
488 if (txp_download_fw_wait(sc)) {
489 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed, initial\n");
493 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) +
494 sizeof(struct txp_fw_file_header));
496 for (sect = 0; sect < fileheader->nsections; sect++) {
497 if (txp_download_fw_section(sc, secthead, sect))
499 secthead = (struct txp_fw_section_header *)
500 (((u_int8_t *)secthead) + secthead->nbytes +
504 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE);
506 for (i = 0; i < 10000; i++) {
507 r = READ_REG(sc, TXP_A2H_0);
508 if (r == STAT_WAITING_FOR_BOOT)
512 if (r != STAT_WAITING_FOR_BOOT) {
513 if_printf(&sc->sc_arpcom.ac_if, "not waiting for boot\n");
517 WRITE_REG(sc, TXP_IER, ier);
518 WRITE_REG(sc, TXP_IMR, imr);
524 txp_download_fw_wait(sc)
525 struct txp_softc *sc;
529 for (i = 0; i < 10000; i++) {
530 r = READ_REG(sc, TXP_ISR);
531 if (r & TXP_INT_A2H_0)
536 if (!(r & TXP_INT_A2H_0)) {
537 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed comm0\n");
541 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
543 r = READ_REG(sc, TXP_A2H_0);
544 if (r != STAT_WAITING_FOR_SEGMENT) {
545 if_printf(&sc->sc_arpcom.ac_if, "fw not waiting for segment\n");
552 txp_download_fw_section(sc, sect, sectnum)
553 struct txp_softc *sc;
554 struct txp_fw_section_header *sect;
562 /* Skip zero length sections */
563 if (sect->nbytes == 0)
566 /* Make sure we aren't past the end of the image */
567 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image);
568 if (rseg >= sizeof(tc990image)) {
569 if_printf(&sc->sc_arpcom.ac_if, "fw invalid section address, "
570 "section %d\n", sectnum);
574 /* Make sure this section doesn't go past the end */
575 rseg += sect->nbytes;
576 if (rseg >= sizeof(tc990image)) {
577 if_printf(&sc->sc_arpcom.ac_if, "fw truncated section %d\n",
582 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes);
583 dma = vtophys(sc->sc_fwbuf);
586 * dummy up mbuf and verify section checksum
589 m.m_next = m.m_nextpkt = NULL;
590 m.m_len = sect->nbytes;
591 m.m_data = sc->sc_fwbuf;
593 csum = in_cksum(&m, sect->nbytes);
594 if (csum != sect->cksum) {
595 if_printf(&sc->sc_arpcom.ac_if, "fw section %d, bad "
596 "cksum (expected 0x%x got 0x%x)\n",
597 sectnum, sect->cksum, csum);
602 WRITE_REG(sc, TXP_H2A_1, sect->nbytes);
603 WRITE_REG(sc, TXP_H2A_2, sect->cksum);
604 WRITE_REG(sc, TXP_H2A_3, sect->addr);
605 WRITE_REG(sc, TXP_H2A_4, 0);
606 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff);
607 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE);
609 if (txp_download_fw_wait(sc)) {
610 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed, "
611 "section %d\n", sectnum);
623 struct txp_softc *sc = vsc;
624 struct txp_hostvar *hv = sc->sc_hostvar;
627 /* mask all interrupts */
628 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF |
629 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
630 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
631 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
632 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH);
634 isr = READ_REG(sc, TXP_ISR);
636 WRITE_REG(sc, TXP_ISR, isr);
638 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff))
639 txp_rx_reclaim(sc, &sc->sc_rxhir);
640 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff))
641 txp_rx_reclaim(sc, &sc->sc_rxlor);
643 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx)
644 txp_rxbuf_reclaim(sc);
646 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons !=
647 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off))))
648 txp_tx_reclaim(sc, &sc->sc_txhir);
650 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons !=
651 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off))))
652 txp_tx_reclaim(sc, &sc->sc_txlor);
654 isr = READ_REG(sc, TXP_ISR);
657 /* unmask all interrupts */
658 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
660 txp_start(&sc->sc_arpcom.ac_if);
666 txp_rx_reclaim(sc, r)
667 struct txp_softc *sc;
668 struct txp_rx_ring *r;
670 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
671 struct txp_rx_desc *rxd;
673 struct txp_swdesc *sd = NULL;
674 u_int32_t roff, woff;
678 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc));
680 while (roff != woff) {
682 if (rxd->rx_flags & RX_FLAGS_ERROR) {
683 if_printf(ifp, "error 0x%x\n", rxd->rx_stat);
688 /* retrieve stashed pointer */
694 m->m_pkthdr.len = m->m_len = rxd->rx_len;
696 #ifdef __STRICT_ALIGNMENT
699 * XXX Nice chip, except it won't accept "off by 2"
700 * buffers, so we're force to copy. Supposedly
701 * this will be fixed in a newer firmware rev
702 * and this will be temporary.
706 MGETHDR(mnew, MB_DONTWAIT, MT_DATA);
711 if (m->m_len > (MHLEN - 2)) {
712 MCLGET(mnew, MB_DONTWAIT);
713 if (!(mnew->m_flags & M_EXT)) {
719 mnew->m_pkthdr.rcvif = ifp;
721 mnew->m_pkthdr.len = mnew->m_len = m->m_len;
722 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t));
728 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD)
729 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
730 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD)
731 m->m_pkthdr.csum_flags |=
732 CSUM_IP_CHECKED|CSUM_IP_VALID;
734 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) ||
735 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) {
736 m->m_pkthdr.csum_flags |=
737 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
738 m->m_pkthdr.csum_data = 0xffff;
741 if (rxd->rx_stat & RX_STAT_VLAN)
742 VLAN_INPUT_TAG(m, htons(rxd->rx_vlan >> 16));
744 (*ifp->if_input)(ifp, m);
748 roff += sizeof(struct txp_rx_desc);
749 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) {
763 txp_rxbuf_reclaim(sc)
764 struct txp_softc *sc;
766 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
767 struct txp_hostvar *hv = sc->sc_hostvar;
768 struct txp_rxbuf_desc *rbd;
769 struct txp_swdesc *sd;
772 if (!(ifp->if_flags & IFF_RUNNING))
775 i = sc->sc_rxbufprod;
776 rbd = sc->sc_rxbufs + i;
780 if (sd->sd_mbuf != NULL)
783 MGETHDR(sd->sd_mbuf, MB_DONTWAIT, MT_DATA);
784 if (sd->sd_mbuf == NULL)
787 MCLGET(sd->sd_mbuf, MB_DONTWAIT);
788 if ((sd->sd_mbuf->m_flags & M_EXT) == 0)
790 sd->sd_mbuf->m_pkthdr.rcvif = ifp;
791 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
793 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t))
797 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i);
799 if (++i == RXBUF_ENTRIES) {
806 sc->sc_rxbufprod = i;
811 m_freem(sd->sd_mbuf);
817 * Reclaim mbufs and entries from a transmit ring.
820 txp_tx_reclaim(sc, r)
821 struct txp_softc *sc;
822 struct txp_tx_ring *r;
824 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
825 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off));
826 u_int32_t cons = r->r_cons, cnt = r->r_cnt;
827 struct txp_tx_desc *txd = r->r_desc + cons;
828 struct txp_swdesc *sd = sc->sc_txd + cons;
831 while (cons != idx) {
835 if ((txd->tx_flags & TX_FLAGS_TYPE_M) ==
836 TX_FLAGS_TYPE_DATA) {
845 ifp->if_flags &= ~IFF_OACTIVE;
847 if (++cons == TX_ENTRIES) {
869 struct txp_softc *sc;
871 sc = device_get_softc(dev);
873 /* mask all interrupts */
874 WRITE_REG(sc, TXP_IMR,
875 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
876 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
879 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
880 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
881 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0);
888 struct txp_softc *sc;
890 struct txp_boot_record *boot;
891 struct txp_ldata *ld;
896 boot = &ld->txp_boot;
902 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar));
903 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar);
904 boot->br_hostvar_hi = 0;
905 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar;
907 /* hi priority tx ring */
908 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);;
909 boot->br_txhipri_hi = 0;
910 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
911 sc->sc_txhir.r_reg = TXP_H2A_1;
912 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring;
913 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0;
914 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx;
916 /* lo priority tx ring */
917 boot->br_txlopri_lo = vtophys(&ld->txp_txloring);
918 boot->br_txlopri_hi = 0;
919 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
920 sc->sc_txlor.r_reg = TXP_H2A_3;
921 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring;
922 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0;
923 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx;
925 /* high priority rx ring */
926 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring);
927 boot->br_rxhipri_hi = 0;
928 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
929 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring;
930 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx;
931 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx;
933 /* low priority rx ring */
934 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring);
935 boot->br_rxlopri_hi = 0;
936 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
937 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring;
938 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx;
939 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx;
942 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES);
943 boot->br_cmd_lo = vtophys(&ld->txp_cmdring);
945 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
946 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring;
947 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
948 sc->sc_cmdring.lastwrite = 0;
951 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES);
952 boot->br_resp_lo = vtophys(&ld->txp_rspring);
953 boot->br_resp_hi = 0;
954 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc);
955 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring;
956 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc);
957 sc->sc_rspring.lastwrite = 0;
959 /* receive buffer ring */
960 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs);
961 boot->br_rxbuf_hi = 0;
962 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc);
963 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs;
965 for (i = 0; i < RXBUF_ENTRIES; i++) {
966 struct txp_swdesc *sd;
967 if (sc->sc_rxbufs[i].rb_sd != NULL)
969 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc),
971 if (sc->sc_rxbufs[i].rb_sd == NULL)
973 sd = sc->sc_rxbufs[i].rb_sd;
976 sc->sc_rxbufprod = 0;
979 bzero(&ld->txp_zero, sizeof(u_int32_t));
980 boot->br_zero_lo = vtophys(&ld->txp_zero);
981 boot->br_zero_hi = 0;
983 /* See if it's waiting for boot, and try to boot it */
984 for (i = 0; i < 10000; i++) {
985 r = READ_REG(sc, TXP_A2H_0);
986 if (r == STAT_WAITING_FOR_BOOT)
991 if (r != STAT_WAITING_FOR_BOOT) {
992 if_printf(&sc->sc_arpcom.ac_if, "not waiting for boot\n");
996 WRITE_REG(sc, TXP_H2A_2, 0);
997 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot));
998 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD);
1000 /* See if it booted */
1001 for (i = 0; i < 10000; i++) {
1002 r = READ_REG(sc, TXP_A2H_0);
1003 if (r == STAT_RUNNING)
1007 if (r != STAT_RUNNING) {
1008 if_printf(&sc->sc_arpcom.ac_if, "fw not running\n");
1012 /* Clear TX and CMD ring write registers */
1013 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL);
1014 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL);
1015 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL);
1016 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL);
1022 txp_ioctl(ifp, command, data, cr)
1028 struct txp_softc *sc = ifp->if_softc;
1029 struct ifreq *ifr = (struct ifreq *)data;
1036 if (ifp->if_flags & IFF_UP) {
1039 if (ifp->if_flags & IFF_RUNNING)
1046 * Multicast list has changed; set the hardware
1047 * filter accordingly.
1054 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command);
1057 error = ether_ioctl(ifp, command, data);
1068 struct txp_softc *sc;
1072 struct txp_swdesc *sd;
1074 ifp = &sc->sc_arpcom.ac_if;
1076 for (i = 0; i < RXBUF_ENTRIES; i++) {
1077 sd = sc->sc_rxbufs[i].rb_sd;
1078 MGETHDR(sd->sd_mbuf, MB_DONTWAIT, MT_DATA);
1079 if (sd->sd_mbuf == NULL)
1082 MCLGET(sd->sd_mbuf, MB_DONTWAIT);
1083 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) {
1084 m_freem(sd->sd_mbuf);
1087 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
1088 sd->sd_mbuf->m_pkthdr.rcvif = ifp;
1090 sc->sc_rxbufs[i].rb_paddrlo =
1091 vtophys(mtod(sd->sd_mbuf, vm_offset_t));
1092 sc->sc_rxbufs[i].rb_paddrhi = 0;
1095 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) *
1096 sizeof(struct txp_rxbuf_desc);
1102 txp_rxring_empty(sc)
1103 struct txp_softc *sc;
1106 struct txp_swdesc *sd;
1108 if (sc->sc_rxbufs == NULL)
1111 for (i = 0; i < RXBUF_ENTRIES; i++) {
1112 if (&sc->sc_rxbufs[i] == NULL)
1114 sd = sc->sc_rxbufs[i].rb_sd;
1117 if (sd->sd_mbuf != NULL) {
1118 m_freem(sd->sd_mbuf);
1130 struct txp_softc *sc;
1136 ifp = &sc->sc_arpcom.ac_if;
1138 if (ifp->if_flags & IFF_RUNNING)
1145 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
1146 NULL, NULL, NULL, 1);
1148 /* Set station address. */
1149 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0];
1150 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1];
1151 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2];
1152 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3];
1153 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4];
1154 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5];
1155 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0,
1156 NULL, NULL, NULL, 1);
1160 txp_rxring_fill(sc);
1162 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1163 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1165 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF |
1166 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
1167 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
1168 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
1169 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH);
1170 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
1172 ifp->if_flags |= IFF_RUNNING;
1173 ifp->if_flags &= ~IFF_OACTIVE;
1176 callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc);
1185 struct txp_softc *sc = vsc;
1186 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1187 struct txp_rsp_desc *rsp = NULL;
1188 struct txp_ext_desc *ext;
1191 txp_rxbuf_reclaim(sc);
1193 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0,
1196 if (rsp->rsp_numdesc != 6)
1198 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0,
1199 NULL, NULL, NULL, 1))
1201 ext = (struct txp_ext_desc *)(rsp + 1);
1203 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 +
1204 ext[4].ext_1 + ext[4].ext_4;
1205 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 +
1207 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 +
1209 ifp->if_opackets += rsp->rsp_par2;
1210 ifp->if_ipackets += ext[2].ext_3;
1214 free(rsp, M_DEVBUF);
1216 callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc);
1224 struct txp_softc *sc = ifp->if_softc;
1225 struct txp_tx_ring *r = &sc->sc_txhir;
1226 struct txp_tx_desc *txd;
1227 struct txp_frag_desc *fxd;
1228 struct mbuf *m, *m0;
1229 struct txp_swdesc *sd;
1230 u_int32_t firstprod, firstcnt, prod, cnt;
1233 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1240 m = ifq_poll(&ifp->if_snd);
1247 sd = sc->sc_txd + prod;
1250 if ((TX_ENTRIES - cnt) < 4)
1253 txd = r->r_desc + prod;
1255 txd->tx_flags = TX_FLAGS_TYPE_DATA;
1256 txd->tx_numdesc = 0;
1262 if (++prod == TX_ENTRIES)
1265 if (++cnt >= (TX_ENTRIES - 4))
1268 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1269 m->m_pkthdr.rcvif != NULL) {
1270 ifv = m->m_pkthdr.rcvif->if_softc;
1271 txd->tx_pflags = TX_PFLAGS_VLAN |
1272 (htons(ifv->ifv_tag) << TX_PFLAGS_VLANTAG_S);
1275 if (m->m_pkthdr.csum_flags & CSUM_IP)
1276 txd->tx_pflags |= TX_PFLAGS_IPCKSUM;
1279 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1280 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM;
1281 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1282 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM;
1285 fxd = (struct txp_frag_desc *)(r->r_desc + prod);
1286 for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1289 if (++cnt >= (TX_ENTRIES - 4))
1294 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG;
1295 fxd->frag_rsvd1 = 0;
1296 fxd->frag_len = m0->m_len;
1297 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t));
1298 fxd->frag_addrhi = 0;
1299 fxd->frag_rsvd2 = 0;
1301 if (++prod == TX_ENTRIES) {
1302 fxd = (struct txp_frag_desc *)r->r_desc;
1311 m = ifq_dequeue(&ifp->if_snd);
1313 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod));
1321 ifp->if_flags |= IFF_OACTIVE;
1322 r->r_prod = firstprod;
1323 r->r_cnt = firstcnt;
1328 * Handle simple commands sent to the typhoon
1331 txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait)
1332 struct txp_softc *sc;
1333 u_int16_t id, in1, *out1;
1334 u_int32_t in2, in3, *out2, *out3;
1337 struct txp_rsp_desc *rsp = NULL;
1339 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait))
1346 *out1 = rsp->rsp_par1;
1348 *out2 = rsp->rsp_par2;
1350 *out3 = rsp->rsp_par3;
1351 free(rsp, M_DEVBUF);
1356 txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait)
1357 struct txp_softc *sc;
1360 struct txp_ext_desc *in_extp;
1362 struct txp_rsp_desc **rspp;
1365 struct txp_hostvar *hv = sc->sc_hostvar;
1366 struct txp_cmd_desc *cmd;
1367 struct txp_ext_desc *ext;
1371 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) {
1372 if_printf(&sc->sc_arpcom.ac_if, "no free cmd descriptors\n");
1376 idx = sc->sc_cmdring.lastwrite;
1377 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1378 bzero(cmd, sizeof(*cmd));
1380 cmd->cmd_numdesc = in_extn;
1381 cmd->cmd_seq = seq = sc->sc_seq++;
1383 cmd->cmd_par1 = in1;
1384 cmd->cmd_par2 = in2;
1385 cmd->cmd_par3 = in3;
1386 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD |
1387 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID;
1389 idx += sizeof(struct txp_cmd_desc);
1390 if (idx == sc->sc_cmdring.size)
1393 for (i = 0; i < in_extn; i++) {
1394 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1395 bcopy(in_extp, ext, sizeof(struct txp_ext_desc));
1397 idx += sizeof(struct txp_cmd_desc);
1398 if (idx == sc->sc_cmdring.size)
1402 sc->sc_cmdring.lastwrite = idx;
1404 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite);
1409 for (i = 0; i < 10000; i++) {
1410 idx = hv->hv_resp_read_idx;
1411 if (idx != hv->hv_resp_write_idx) {
1413 if (txp_response(sc, idx, id, seq, rspp))
1420 if (i == 1000 || (*rspp) == NULL) {
1421 if_printf(&sc->sc_arpcom.ac_if, "0x%x command failed\n", id);
1429 txp_response(sc, ridx, id, seq, rspp)
1430 struct txp_softc *sc;
1434 struct txp_rsp_desc **rspp;
1436 struct txp_hostvar *hv = sc->sc_hostvar;
1437 struct txp_rsp_desc *rsp;
1439 while (ridx != hv->hv_resp_write_idx) {
1440 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx);
1442 if (id == rsp->rsp_id && rsp->rsp_seq == seq) {
1443 *rspp = (struct txp_rsp_desc *)malloc(
1444 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1),
1445 M_DEVBUF, M_INTWAIT);
1446 if ((*rspp) == NULL)
1448 txp_rsp_fixup(sc, rsp, *rspp);
1452 if (rsp->rsp_flags & RSP_FLAGS_ERROR) {
1453 if_printf(&sc->sc_arpcom.ac_if, "response error!\n");
1454 txp_rsp_fixup(sc, rsp, NULL);
1455 ridx = hv->hv_resp_read_idx;
1459 switch (rsp->rsp_id) {
1460 case TXP_CMD_CYCLE_STATISTICS:
1461 case TXP_CMD_MEDIA_STATUS_READ:
1463 case TXP_CMD_HELLO_RESPONSE:
1464 if_printf(&sc->sc_arpcom.ac_if, "hello\n");
1467 if_printf(&sc->sc_arpcom.ac_if, "unknown id(0x%x)\n",
1471 txp_rsp_fixup(sc, rsp, NULL);
1472 ridx = hv->hv_resp_read_idx;
1473 hv->hv_resp_read_idx = ridx;
1480 txp_rsp_fixup(sc, rsp, dst)
1481 struct txp_softc *sc;
1482 struct txp_rsp_desc *rsp, *dst;
1484 struct txp_rsp_desc *src = rsp;
1485 struct txp_hostvar *hv = sc->sc_hostvar;
1488 ridx = hv->hv_resp_read_idx;
1490 for (i = 0; i < rsp->rsp_numdesc + 1; i++) {
1492 bcopy(src, dst++, sizeof(struct txp_rsp_desc));
1493 ridx += sizeof(struct txp_rsp_desc);
1494 if (ridx == sc->sc_rspring.size) {
1495 src = sc->sc_rspring.base;
1499 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx;
1502 hv->hv_resp_read_idx = ridx;
1506 txp_cmd_desc_numfree(sc)
1507 struct txp_softc *sc;
1509 struct txp_hostvar *hv = sc->sc_hostvar;
1510 struct txp_boot_record *br = sc->sc_boot;
1511 u_int32_t widx, ridx, nfree;
1513 widx = sc->sc_cmdring.lastwrite;
1514 ridx = hv->hv_cmd_read_idx;
1517 /* Ring is completely free */
1518 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc);
1521 nfree = br->br_cmd_siz -
1522 (widx - ridx + sizeof(struct txp_cmd_desc));
1524 nfree = ridx - widx - sizeof(struct txp_cmd_desc);
1527 return (nfree / sizeof(struct txp_cmd_desc));
1532 struct txp_softc *sc;
1536 ifp = &sc->sc_arpcom.ac_if;
1538 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1540 callout_stop(&sc->txp_stat_timer);
1542 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1543 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1545 txp_rxring_empty(sc);
1558 txp_ifmedia_upd(ifp)
1561 struct txp_softc *sc = ifp->if_softc;
1562 struct ifmedia *ifm = &sc->sc_ifmedia;
1565 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1568 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) {
1569 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1570 new_xcvr = TXP_XCVR_10_FDX;
1572 new_xcvr = TXP_XCVR_10_HDX;
1573 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
1574 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1575 new_xcvr = TXP_XCVR_100_FDX;
1577 new_xcvr = TXP_XCVR_100_HDX;
1578 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
1579 new_xcvr = TXP_XCVR_AUTO;
1584 if (sc->sc_xcvr == new_xcvr)
1587 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0,
1588 NULL, NULL, NULL, 0);
1589 sc->sc_xcvr = new_xcvr;
1595 txp_ifmedia_sts(ifp, ifmr)
1597 struct ifmediareq *ifmr;
1599 struct txp_softc *sc = ifp->if_softc;
1600 struct ifmedia *ifm = &sc->sc_ifmedia;
1601 u_int16_t bmsr, bmcr, anlpar;
1603 ifmr->ifm_status = IFM_AVALID;
1604 ifmr->ifm_active = IFM_ETHER;
1606 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1607 &bmsr, NULL, NULL, 1))
1609 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1610 &bmsr, NULL, NULL, 1))
1613 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0,
1614 &bmcr, NULL, NULL, 1))
1617 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0,
1618 &anlpar, NULL, NULL, 1))
1621 if (bmsr & BMSR_LINK)
1622 ifmr->ifm_status |= IFM_ACTIVE;
1624 if (bmcr & BMCR_ISO) {
1625 ifmr->ifm_active |= IFM_NONE;
1626 ifmr->ifm_status = 0;
1630 if (bmcr & BMCR_LOOP)
1631 ifmr->ifm_active |= IFM_LOOP;
1633 if (bmcr & BMCR_AUTOEN) {
1634 if ((bmsr & BMSR_ACOMP) == 0) {
1635 ifmr->ifm_active |= IFM_NONE;
1639 if (anlpar & ANLPAR_T4)
1640 ifmr->ifm_active |= IFM_100_T4;
1641 else if (anlpar & ANLPAR_TX_FD)
1642 ifmr->ifm_active |= IFM_100_TX|IFM_FDX;
1643 else if (anlpar & ANLPAR_TX)
1644 ifmr->ifm_active |= IFM_100_TX;
1645 else if (anlpar & ANLPAR_10_FD)
1646 ifmr->ifm_active |= IFM_10_T|IFM_FDX;
1647 else if (anlpar & ANLPAR_10)
1648 ifmr->ifm_active |= IFM_10_T;
1650 ifmr->ifm_active |= IFM_NONE;
1652 ifmr->ifm_active = ifm->ifm_cur->ifm_media;
1656 ifmr->ifm_active |= IFM_NONE;
1657 ifmr->ifm_status &= ~IFM_AVALID;
1662 txp_show_descriptor(d)
1665 struct txp_cmd_desc *cmd = d;
1666 struct txp_rsp_desc *rsp = d;
1667 struct txp_tx_desc *txd = d;
1668 struct txp_frag_desc *frgd = d;
1670 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) {
1671 case CMD_FLAGS_TYPE_CMD:
1672 /* command descriptor */
1673 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1674 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1675 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1677 case CMD_FLAGS_TYPE_RESP:
1678 /* response descriptor */
1679 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1680 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq,
1681 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3);
1683 case CMD_FLAGS_TYPE_DATA:
1684 /* data header (assuming tx for now) */
1685 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]",
1686 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen,
1687 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags);
1689 case CMD_FLAGS_TYPE_FRAG:
1690 /* fragment descriptor */
1691 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]",
1692 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len,
1693 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2);
1696 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1697 cmd->cmd_flags & CMD_FLAGS_TYPE_M,
1698 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1699 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1707 struct txp_softc *sc;
1709 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1711 struct ifmultiaddr *ifma;
1713 if (ifp->if_flags & IFF_PROMISC) {
1714 filter = TXP_RXFILT_PROMISC;
1718 filter = TXP_RXFILT_DIRECT;
1720 if (ifp->if_flags & IFF_BROADCAST)
1721 filter |= TXP_RXFILT_BROADCAST;
1723 if (ifp->if_flags & IFF_ALLMULTI) {
1724 filter |= TXP_RXFILT_ALLMULTI;
1726 uint32_t hashbit, hash[2];
1729 hash[0] = hash[1] = 0;
1731 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1732 if (ifma->ifma_addr->sa_family != AF_LINK)
1736 hashbit = (uint16_t)(ether_crc32_be(
1737 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1738 ETHER_ADDR_LEN) & (64 - 1));
1739 hash[hashbit / 32] |= (1 << hashbit % 32);
1743 filter |= TXP_RXFILT_HASHMULTI;
1744 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE,
1745 2, hash[0], hash[1], NULL, NULL, NULL, 0);
1750 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0,
1751 NULL, NULL, NULL, 1);
1755 txp_capabilities(sc)
1756 struct txp_softc *sc;
1758 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1759 struct txp_rsp_desc *rsp = NULL;
1760 struct txp_ext_desc *ext;
1762 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1))
1765 if (rsp->rsp_numdesc != 1)
1767 ext = (struct txp_ext_desc *)(rsp + 1);
1769 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK;
1770 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK;
1771 ifp->if_capabilities = 0;
1773 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) {
1774 sc->sc_tx_capability |= OFFLOAD_VLAN;
1775 sc->sc_rx_capability |= OFFLOAD_VLAN;
1780 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) {
1781 sc->sc_tx_capability |= OFFLOAD_IPSEC;
1782 sc->sc_rx_capability |= OFFLOAD_IPSEC;
1783 ifp->if_capabilities |= IFCAP_IPSEC;
1787 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) {
1788 sc->sc_tx_capability |= OFFLOAD_IPCKSUM;
1789 sc->sc_rx_capability |= OFFLOAD_IPCKSUM;
1790 ifp->if_capabilities |= IFCAP_HWCSUM;
1791 ifp->if_hwassist |= CSUM_IP;
1794 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) {
1796 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM;
1798 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM;
1799 ifp->if_capabilities |= IFCAP_HWCSUM;
1802 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) {
1804 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM;
1806 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM;
1807 ifp->if_capabilities |= IFCAP_HWCSUM;
1809 ifp->if_capenable = ifp->if_capabilities;
1811 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0,
1812 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1))
1817 free(rsp, M_DEVBUF);