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38 * EMX_TXD: Maximum number of Transmit Descriptors
39 * Valid Range: 256-4096 for others
41 * This value is the number of transmit descriptors allocated by the driver.
42 * Increasing this value allows the driver to queue more transmits. Each
43 * descriptor is 16 bytes.
44 * Since TDLEN should be multiple of 128bytes, the number of transmit
45 * desscriptors should meet the following condition.
46 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
48 #define EMX_MIN_TXD 256
49 #define EMX_MAX_TXD 4096
50 #define EMX_DEFAULT_TXD 512
53 * EMX_RXD - Maximum number of receive Descriptors
54 * Valid Range: 256-4096 for others
56 * This value is the number of receive descriptors allocated by the driver.
57 * Increasing this value allows the driver to buffer more incoming packets.
58 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
59 * descriptor. The maximum MTU size is 16110.
60 * Since TDLEN should be multiple of 128bytes, the number of transmit
61 * desscriptors should meet the following condition.
62 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
64 #define EMX_MIN_RXD 256
65 #define EMX_MAX_RXD 4096
66 #define EMX_DEFAULT_RXD 512
69 * Receive Interrupt Delay Timer (Packet Timer)
72 * RDTR and RADV are deprecated; use ITR instead. They are only used to
73 * workaround hardware bug on certain 82573 based NICs.
75 #define EMX_RDTR_82573 32
78 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
81 * RDTR and RADV are deprecated; use ITR instead. They are only used to
82 * workaround hardware bug on certain 82573 based NICs.
84 #define EMX_RADV_82573 64
87 * This parameter controls the duration of transmit watchdog timer.
89 #define EMX_TX_TIMEOUT 5
91 /* One for TX csum offloading desc, the other 2 are reserved */
92 #define EMX_TX_RESERVED 3
94 /* Large enough for 64K TSO segment */
95 #define EMX_TX_SPARE 33
97 #define EMX_TX_OACTIVE_MAX 64
99 /* Interrupt throttle rate */
100 #define EMX_DEFAULT_ITR 6000
103 * This parameter controls whether or not autonegotation is enabled.
104 * 0 - Disable autonegotiation
105 * 1 - Enable autonegotiation
107 #define EMX_DO_AUTO_NEG 1
109 /* Tunables -- End */
111 #define EMX_AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | \
112 ADVERTISE_10_FULL | \
113 ADVERTISE_100_HALF | \
114 ADVERTISE_100_FULL | \
117 #define EMX_AUTO_ALL_MODES 0
119 /* PHY master/slave setting */
120 #define EMX_MASTER_SLAVE e1000_ms_hw_default
123 * Micellaneous constants
125 #define EMX_VENDOR_ID 0x8086
127 #define EMX_BAR_MEM PCIR_BAR(0)
129 #define EMX_JUMBO_PBA 0x00000028
130 #define EMX_DEFAULT_PBA 0x00000030
131 #define EMX_SMARTSPEED_DOWNSHIFT 3
132 #define EMX_SMARTSPEED_MAX 15
133 #define EMX_MAX_INTR 10
135 #define EMX_MCAST_ADDR_MAX 128
136 #define EMX_FC_PAUSE_TIME 1000
137 #define EMX_EEPROM_APME 0x400;
140 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
141 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
142 * also optimize cache line size effect. H/W supports up to cache line size 128.
144 #define EMX_DBA_ALIGN 128
147 * Speed mode bit in TARC0.
148 * 82571EB/82572EI only, used to improve small packet transmit performance.
150 #define EMX_TARC_SPEED_MODE (1 << 21)
153 * Multiple TX queues arbitration count mask in TARC0/TARC1.
155 #define EMX_TARC_COUNT_MASK 0x7f
157 #define EMX_MAX_SCATTER 64
158 #define EMX_TSO_SIZE (IP_MAXPACKET + \
159 sizeof(struct ether_vlan_header))
160 #define EMX_MAX_SEGSIZE PAGE_SIZE
161 #define EMX_MSIX_MASK 0x01F00000 /* For 82574 use */
163 #define EMX_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
166 * 82574 has a nonstandard address for EIAC
167 * and since its only used in MSIX, and in
168 * the em driver only 82574 uses MSIX we can
169 * solve it just using this define.
171 #define EMX_EIAC 0x000DC
173 #define EMX_NRSSRK 10
174 #define EMX_RSSRK_SIZE 4
175 #define EMX_RSSRK_VAL(key, i) (key[(i) * EMX_RSSRK_SIZE] | \
176 key[(i) * EMX_RSSRK_SIZE + 1] << 8 | \
177 key[(i) * EMX_RSSRK_SIZE + 2] << 16 | \
178 key[(i) * EMX_RSSRK_SIZE + 3] << 24)
181 #define EMX_RETA_SIZE 4
182 #define EMX_RETA_RINGIDX_SHIFT 7
184 #define EMX_NRX_RING 2
185 #define EMX_NTX_RING 2
186 #define EMX_NSERIALIZE 5
188 typedef union e1000_rx_desc_extended emx_rxdesc_t;
190 #define rxd_bufaddr read.buffer_addr /* 64bits */
191 #define rxd_length wb.upper.length /* 16bits */
192 #define rxd_vlan wb.upper.vlan /* 16bits */
193 #define rxd_staterr wb.upper.status_error /* 32bits */
194 #define rxd_mrq wb.lower.mrq /* 32bits */
195 #define rxd_rss wb.lower.hi_dword.rss /* 32bits */
197 #define EMX_RXDMRQ_RSSTYPE_MASK 0xf
198 #define EMX_RXDMRQ_NO_HASH 0
199 #define EMX_RXDMRQ_IPV4_TCP 1
200 #define EMX_RXDMRQ_IPV4 2
201 #define EMX_RXDMRQ_IPV6_TCP 3
202 #define EMX_RXDMRQ_IPV6 5
207 struct lwkt_serialize rx_serialize;
208 struct emx_softc *sc;
212 * Receive definitions
214 * we have an array of num_rx_desc rx_desc (handled by the
215 * controller), and paired with an array of rx_buffers
216 * (at rx_buffer_area).
217 * The next pair to check on receive is at offset next_rx_desc_to_check
219 emx_rxdesc_t *rx_desc;
220 uint32_t next_rx_desc_to_check;
222 struct emx_rxbuf *rx_buf;
224 bus_dmamap_t rx_sparemap;
227 * First/last mbuf pointers, for
228 * collecting multisegment RX packets.
234 unsigned long rx_pkts;
236 bus_dma_tag_t rx_desc_dtag;
237 bus_dmamap_t rx_desc_dmap;
238 bus_addr_t rx_desc_paddr;
242 struct lwkt_serialize tx_serialize;
243 struct emx_softc *sc;
244 struct ifaltq_subque *ifsq;
247 #define EMX_TXFLAG_TSO_PULLEX 0x1
248 #define EMX_TXFLAG_ENABLED 0x2
249 #define EMX_TXFLAG_FORCECTX 0x4
252 * Transmit definitions
254 * We have an array of num_tx_desc descriptors (handled
255 * by the controller) paired with an array of tx_buffers
256 * (at tx_buffer_area).
257 * The index of the next available descriptor is next_avail_tx_desc.
258 * The number of remaining tx_desc is num_tx_desc_avail.
260 struct e1000_tx_desc *tx_desc_base;
261 struct emx_txbuf *tx_buf;
262 uint32_t next_avail_tx_desc;
263 uint32_t next_tx_to_clean;
264 int num_tx_desc_avail;
266 bus_dma_tag_t txtag; /* dma tag for tx */
270 /* Saved csum offloading context information */
275 int csum_thlen; /* TSO */
276 int csum_mss; /* TSO */
277 int csum_pktlen; /* TSO */
279 uint32_t csum_txd_upper;
280 uint32_t csum_txd_lower;
285 * Variables used to reduce TX interrupt rate and
286 * number of device's TX ring write requests.
289 * Number of TX descriptors setup so far.
292 * Once tx_nsegs > tx_int_nsegs, RS bit will be set
293 * in the last TX descriptor of the packet, and
294 * tx_nsegs will be reset to 0. So TX interrupt and
295 * TX ring write request should be generated roughly
296 * every tx_int_nsegs TX descriptors.
299 * Index of the TX descriptors which have RS bit set,
300 * i.e. DD bit will be set on this TX descriptor after
301 * the data of the TX descriptor are transfered to
302 * hardware's internal packet buffer. Only the TX
303 * descriptors listed in tx_dd[] will be checked upon
304 * TX interrupt. This array is used as circular ring.
306 * tx_dd_tail, tx_dd_head:
307 * Tail and head index of valid elements in tx_dd[].
308 * tx_dd_tail == tx_dd_head means there is no valid
309 * elements in tx_dd[]. tx_dd_tail points to the position
310 * which is one beyond the last valid element in tx_dd[].
311 * tx_dd_head points to the first valid element in
318 #define EMX_TXDD_MAX 64
319 #define EMX_TXDD_SAFE 48 /* 48 <= val < EMX_TXDD_MAX */
320 int tx_dd[EMX_TXDD_MAX];
322 struct ifsubq_watchdog tx_watchdog;
325 unsigned long tx_pkts;
326 unsigned long tso_segments;
327 unsigned long tso_ctx_reused;
329 bus_dma_tag_t tx_desc_dtag;
330 bus_dmamap_t tx_desc_dmap;
331 bus_addr_t tx_desc_paddr;
335 struct arpcom arpcom;
338 #define EMX_FLAG_SHARED_INTR 0x0001
339 #define EMX_FLAG_HAS_MGMT 0x0004
340 #define EMX_FLAG_HAS_AMT 0x0008
341 #define EMX_FLAG_HW_CTRL 0x0010
343 /* DragonFly operating-system-specific structures. */
344 struct e1000_osdep osdep;
347 bus_dma_tag_t parent_dtag;
349 struct resource *memory;
352 struct resource *intr_res;
357 struct ifmedia media;
358 struct callout timer;
363 /* WOL register value */
366 /* Multicast array memory */
369 /* Info about the board itself */
372 uint16_t link_duplex;
374 int int_throttle_ceil;
379 struct lwkt_serialize main_serialize;
380 struct lwkt_serialize *serializes[EMX_NSERIALIZE];
384 struct emx_txdata tx_data[EMX_NTX_RING];
388 struct emx_rxdata rx_data[EMX_NRX_RING];
390 /* Misc stats maintained by the driver */
391 unsigned long rx_overruns;
393 /* sysctl tree glue */
394 struct sysctl_ctx_list sysctl_ctx;
395 struct sysctl_oid *sysctl_tree;
397 struct e1000_hw_stats stats;
411 #define EMX_IS_OACTIVE(tdata) \
412 ((tdata)->num_tx_desc_avail <= (tdata)->oact_tx_desc)
414 #define EMX_INC_TXDD_IDX(idx) \
416 if (++(idx) == EMX_TXDD_MAX) \
420 #endif /* !_IF_EMX_H_ */