3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.17 2005/10/24 08:06:15 sephe Exp $
40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
64 * o TCP/IP checksum offload for both RX and TX
66 * o High and normal priority transmit DMA rings
68 * o VLAN tag insertion and extraction
70 * o TCP large send (segmentation offload)
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
85 * o GMII and TBI ports/registers for interfacing with copper
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
91 * o Slight differences in register layout from the 8139C+
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7.5K, so the max MTU possible with this
111 * driver is 7500 bytes.
114 #include "opt_polling.h"
116 #include <sys/param.h>
117 #include <sys/endian.h>
118 #include <sys/systm.h>
119 #include <sys/sockio.h>
120 #include <sys/mbuf.h>
121 #include <sys/malloc.h>
122 #include <sys/module.h>
123 #include <sys/kernel.h>
124 #include <sys/socket.h>
125 #include <sys/thread2.h>
128 #include <net/ifq_var.h>
129 #include <net/if_arp.h>
130 #include <net/ethernet.h>
131 #include <net/if_dl.h>
132 #include <net/if_media.h>
133 #include <net/if_types.h>
134 #include <net/vlan/if_vlan_var.h>
138 #include <machine/bus_pio.h>
139 #include <machine/bus_memio.h>
140 #include <machine/bus.h>
141 #include <machine/resource.h>
143 #include <sys/rman.h>
145 #include <dev/netif/mii_layer/mii.h>
146 #include <dev/netif/mii_layer/miivar.h>
148 #include <bus/pci/pcireg.h>
149 #include <bus/pci/pcivar.h>
151 /* "controller miibus0" required. See GENERIC if you get errors here. */
152 #include "miibus_if.h"
154 #include <dev/netif/re/if_rereg.h>
157 * The hardware supports checksumming but, as usual, some chipsets screw it
158 * all up and produce bogus packets, so we disable it by default.
160 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
161 #define RE_DISABLE_HWCSUM
164 * Various supported device vendors/types and their names.
166 static struct re_type re_devs[] = {
167 { RT_VENDORID, RT_DEVICEID_8139, RE_HWREV_8139CPLUS,
168 "RealTek 8139C+ 10/100BaseTX" },
169 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8169,
170 "RealTek 8169 Gigabit Ethernet" },
171 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8169S,
172 "RealTek 8169S Single-chip Gigabit Ethernet" },
173 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8110S,
174 "RealTek 8110S Single-chip Gigabit Ethernet" },
178 static struct re_hwrev re_hwrevs[] = {
179 { RE_HWREV_8139CPLUS, RE_8139CPLUS, "C+"},
180 { RE_HWREV_8169, RE_8169, "8169"},
181 { RE_HWREV_8169S, RE_8169, "8169S"},
182 { RE_HWREV_8110S, RE_8169, "8110S"},
186 static int re_probe(device_t);
187 static int re_attach(device_t);
188 static int re_detach(device_t);
190 static int re_encap(struct re_softc *, struct mbuf **, int *, int *);
192 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int);
193 static void re_dma_map_desc(void *, bus_dma_segment_t *, int,
195 static int re_allocmem(device_t, struct re_softc *);
196 static int re_newbuf(struct re_softc *, int, struct mbuf *);
197 static int re_rx_list_init(struct re_softc *);
198 static int re_tx_list_init(struct re_softc *);
199 static void re_rxeof(struct re_softc *);
200 static void re_txeof(struct re_softc *);
201 static void re_intr(void *);
202 static void re_tick(void *);
203 static void re_start(struct ifnet *);
204 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
205 static void re_init(void *);
206 static void re_stop(struct re_softc *);
207 static void re_watchdog(struct ifnet *);
208 static int re_suspend(device_t);
209 static int re_resume(device_t);
210 static void re_shutdown(device_t);
211 static int re_ifmedia_upd(struct ifnet *);
212 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
214 static void re_eeprom_putbyte(struct re_softc *, int);
215 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
216 static void re_read_eeprom(struct re_softc *, caddr_t, int, int, int);
217 static int re_gmii_readreg(device_t, int, int);
218 static int re_gmii_writereg(device_t, int, int, int);
220 static int re_miibus_readreg(device_t, int, int);
221 static int re_miibus_writereg(device_t, int, int, int);
222 static void re_miibus_statchg(device_t);
224 static void re_setmulti(struct re_softc *);
225 static void re_reset(struct re_softc *);
227 static int re_diag(struct re_softc *);
228 #ifdef DEVICE_POLLING
229 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
232 static device_method_t re_methods[] = {
233 /* Device interface */
234 DEVMETHOD(device_probe, re_probe),
235 DEVMETHOD(device_attach, re_attach),
236 DEVMETHOD(device_detach, re_detach),
237 DEVMETHOD(device_suspend, re_suspend),
238 DEVMETHOD(device_resume, re_resume),
239 DEVMETHOD(device_shutdown, re_shutdown),
242 DEVMETHOD(bus_print_child, bus_generic_print_child),
243 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
246 DEVMETHOD(miibus_readreg, re_miibus_readreg),
247 DEVMETHOD(miibus_writereg, re_miibus_writereg),
248 DEVMETHOD(miibus_statchg, re_miibus_statchg),
253 static driver_t re_driver = {
256 sizeof(struct re_softc)
259 static devclass_t re_devclass;
261 DECLARE_DUMMY_MODULE(if_re);
262 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
263 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
264 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
267 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
270 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
273 * Send a read command and address to the EEPROM, check for ACK.
276 re_eeprom_putbyte(struct re_softc *sc, int addr)
280 d = addr | sc->re_eecmd_read;
283 * Feed in each bit and strobe the clock.
285 for (i = 0x400; i != 0; i >>= 1) {
287 EE_SET(RE_EE_DATAIN);
289 EE_CLR(RE_EE_DATAIN);
299 * Read a word of data stored in the EEPROM at address 'addr.'
302 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
307 /* Enter EEPROM access mode. */
308 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL);
311 * Send address of word we want to read.
313 re_eeprom_putbyte(sc, addr);
315 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL);
318 * Start reading bits from EEPROM.
320 for (i = 0x8000; i != 0; i >>= 1) {
323 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
329 /* Turn off EEPROM access mode. */
330 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
336 * Read a sequence of words from the EEPROM.
339 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt, int swap)
342 uint16_t word = 0, *ptr;
344 for (i = 0; i < cnt; i++) {
345 re_eeprom_getword(sc, off + i, &word);
346 ptr = (u_int16_t *)(dest + (i * 2));
348 *ptr = be16toh(word);
355 re_gmii_readreg(device_t dev, int phy, int reg)
357 struct re_softc *sc = device_get_softc(dev);
364 /* Let the rgephy driver read the GMEDIASTAT register */
366 if (reg == RE_GMEDIASTAT)
367 return(CSR_READ_1(sc, RE_GMEDIASTAT));
369 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
372 for (i = 0; i < RE_TIMEOUT; i++) {
373 rval = CSR_READ_4(sc, RE_PHYAR);
374 if (rval & RE_PHYAR_BUSY)
379 if (i == RE_TIMEOUT) {
380 device_printf(dev, "PHY read failed\n");
384 return(rval & RE_PHYAR_PHYDATA);
388 re_gmii_writereg(device_t dev, int phy, int reg, int data)
390 struct re_softc *sc = device_get_softc(dev);
394 CSR_WRITE_4(sc, RE_PHYAR,
395 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
398 for (i = 0; i < RE_TIMEOUT; i++) {
399 rval = CSR_READ_4(sc, RE_PHYAR);
400 if ((rval & RE_PHYAR_BUSY) == 0)
406 device_printf(dev, "PHY write failed\n");
412 re_miibus_readreg(device_t dev, int phy, int reg)
414 struct re_softc *sc = device_get_softc(dev);
416 uint16_t re8139_reg = 0;
418 if (sc->re_type == RE_8169) {
419 rval = re_gmii_readreg(dev, phy, reg);
423 /* Pretend the internal PHY is only at address 0 */
429 re8139_reg = RE_BMCR;
432 re8139_reg = RE_BMSR;
435 re8139_reg = RE_ANAR;
438 re8139_reg = RE_ANER;
441 re8139_reg = RE_LPAR;
447 * Allow the rlphy driver to read the media status
448 * register. If we have a link partner which does not
449 * support NWAY, this is the register which will tell
450 * us the results of parallel detection.
453 return(CSR_READ_1(sc, RE_MEDIASTAT));
455 device_printf(dev, "bad phy register\n");
458 rval = CSR_READ_2(sc, re8139_reg);
463 re_miibus_writereg(device_t dev, int phy, int reg, int data)
465 struct re_softc *sc= device_get_softc(dev);
466 u_int16_t re8139_reg = 0;
468 if (sc->re_type == RE_8169)
469 return(re_gmii_writereg(dev, phy, reg, data));
471 /* Pretend the internal PHY is only at address 0 */
477 re8139_reg = RE_BMCR;
480 re8139_reg = RE_BMSR;
483 re8139_reg = RE_ANAR;
486 re8139_reg = RE_ANER;
489 re8139_reg = RE_LPAR;
495 device_printf(dev, "bad phy register\n");
498 CSR_WRITE_2(sc, re8139_reg, data);
503 re_miibus_statchg(device_t dev)
508 * Program the 64-bit multicast hash filter.
511 re_setmulti(struct re_softc *sc)
513 struct ifnet *ifp = &sc->arpcom.ac_if;
515 uint32_t hashes[2] = { 0, 0 };
516 struct ifmultiaddr *ifma;
520 rxfilt = CSR_READ_4(sc, RE_RXCFG);
522 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
523 rxfilt |= RE_RXCFG_RX_MULTI;
524 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
525 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
526 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
530 /* first, zot all the existing hash bits */
531 CSR_WRITE_4(sc, RE_MAR0, 0);
532 CSR_WRITE_4(sc, RE_MAR4, 0);
534 /* now program new ones */
535 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
536 if (ifma->ifma_addr->sa_family != AF_LINK)
538 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
539 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
541 hashes[0] |= (1 << h);
543 hashes[1] |= (1 << (h - 32));
548 rxfilt |= RE_RXCFG_RX_MULTI;
550 rxfilt &= ~RE_RXCFG_RX_MULTI;
552 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
553 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
554 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
558 re_reset(struct re_softc *sc)
562 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
564 for (i = 0; i < RE_TIMEOUT; i++) {
566 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
570 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
572 CSR_WRITE_1(sc, 0x82, 1);
576 * The following routine is designed to test for a defect on some
577 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
578 * lines connected to the bus, however for a 32-bit only card, they
579 * should be pulled high. The result of this defect is that the
580 * NIC will not work right if you plug it into a 64-bit slot: DMA
581 * operations will be done with 64-bit transfers, which will fail
582 * because the 64-bit data lines aren't connected.
584 * There's no way to work around this (short of talking a soldering
585 * iron to the board), however we can detect it. The method we use
586 * here is to put the NIC into digital loopback mode, set the receiver
587 * to promiscuous mode, and then try to send a frame. We then compare
588 * the frame data we sent to what was received. If the data matches,
589 * then the NIC is working correctly, otherwise we know the user has
590 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
591 * slot. In the latter case, there's no way the NIC can work correctly,
592 * so we print out a message on the console and abort the device attach.
596 re_diag(struct re_softc *sc)
598 struct ifnet *ifp = &sc->arpcom.ac_if;
600 struct ether_header *eh;
601 struct re_desc *cur_rx;
604 int total_len, i, error = 0;
605 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
606 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
608 /* Allocate a single mbuf */
610 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
615 * Initialize the NIC in test mode. This sets the chip up
616 * so that it can send and receive frames, but performs the
617 * following special functions:
618 * - Puts receiver in promiscuous mode
619 * - Enables digital loopback mode
620 * - Leaves interrupts turned off
623 ifp->if_flags |= IFF_PROMISC;
630 /* Put some data in the mbuf */
632 eh = mtod(m0, struct ether_header *);
633 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
634 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
635 eh->ether_type = htons(ETHERTYPE_IP);
636 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
639 * Queue the packet, start transmission.
640 * Note: ifq_handoff() ultimately calls re_start() for us.
643 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
644 error = ifq_handoff(ifp, m0, NULL);
651 /* Wait for it to propagate through the chip */
654 for (i = 0; i < RE_TIMEOUT; i++) {
655 status = CSR_READ_2(sc, RE_ISR);
656 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
657 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
662 if (i == RE_TIMEOUT) {
663 if_printf(ifp, "diagnostic failed to receive packet "
664 "in loopback mode\n");
670 * The packet should have been dumped into the first
671 * entry in the RX DMA ring. Grab it from there.
674 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
675 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
676 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0],
677 BUS_DMASYNC_POSTWRITE);
678 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]);
680 m0 = sc->re_ldata.re_rx_mbuf[0];
681 sc->re_ldata.re_rx_mbuf[0] = NULL;
682 eh = mtod(m0, struct ether_header *);
684 cur_rx = &sc->re_ldata.re_rx_list[0];
685 total_len = RE_RXBYTES(cur_rx);
686 rxstat = le32toh(cur_rx->re_cmdstat);
688 if (total_len != ETHER_MIN_LEN) {
689 if_printf(ifp, "diagnostic failed, received short packet\n");
694 /* Test that the received packet data matches what we sent. */
696 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
697 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
698 be16toh(eh->ether_type) != ETHERTYPE_IP) {
699 if_printf(ifp, "WARNING, DMA FAILURE!\n");
700 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
701 dst, ":", src, ":", ETHERTYPE_IP);
702 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
703 eh->ether_dhost, ":", eh->ether_shost, ":",
704 ntohs(eh->ether_type));
705 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
706 "into a 64-bit PCI slot.\n");
707 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
708 "for proper operation.\n");
709 if_printf(ifp, "Read the re(4) man page for more details.\n");
714 /* Turn interface off, release resources */
717 ifp->if_flags &= ~IFF_PROMISC;
726 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
727 * IDs against our list and return a device name if we find a match.
730 re_probe(device_t dev)
736 uint16_t vendor, product;
740 vendor = pci_get_vendor(dev);
741 product = pci_get_device(dev);
743 for (t = re_devs; t->re_name != NULL; t++) {
744 if (product == t->re_did && vendor == t->re_vid)
749 * Check if we found a RealTek device.
751 if (t->re_name == NULL)
755 * Temporarily map the I/O space so we can read the chip ID register.
757 sc = malloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
759 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
761 if (sc->re_res == NULL) {
762 device_printf(dev, "couldn't map ports/memory\n");
767 sc->re_btag = rman_get_bustag(sc->re_res);
768 sc->re_bhandle = rman_get_bushandle(sc->re_res);
770 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
771 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
775 * and continue matching for the specific chip...
777 for (; t->re_name != NULL; t++) {
778 if (product == t->re_did && vendor == t->re_vid &&
779 t->re_basetype == hwrev) {
780 device_set_desc(dev, t->re_name);
788 * This routine takes the segment list provided as the result of
789 * a bus_dma_map_load() operation and assigns the addresses/lengths
790 * to RealTek DMA descriptors. This can be called either by the RX
791 * code or the TX code. In the RX case, we'll probably wind up mapping
792 * at most one segment. For the TX case, there could be any number of
793 * segments since TX packets may span multiple mbufs. In either case,
794 * if the number of segments is larger than the re_maxsegs limit
795 * specified by the caller, we abort the mapping operation. Sadly,
796 * whoever designed the buffer mapping API did not provide a way to
797 * return an error from here, so we have to fake it a bit.
801 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg,
802 bus_size_t mapsize, int error)
804 struct re_dmaload_arg *ctx;
805 struct re_desc *d = NULL;
814 /* Signal error to caller if there's too many segments */
815 if (nseg > ctx->re_maxsegs) {
821 * Map the segment array into descriptors. Note that we set the
822 * start-of-frame and end-of-frame markers for either TX or RX, but
823 * they really only have meaning in the TX case. (In the RX case,
824 * it's the chip that tells us where packets begin and end.)
825 * We also keep track of the end of the ring and set the
826 * end-of-ring bits as needed, and we set the ownership bits
827 * in all except the very first descriptor. (The caller will
828 * set this descriptor later when it start transmission or
833 d = &ctx->re_ring[idx];
834 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) {
838 cmdstat = segs[i].ds_len;
839 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
840 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
842 cmdstat |= RE_TDESC_CMD_SOF;
844 cmdstat |= RE_TDESC_CMD_OWN;
845 if (idx == (RE_RX_DESC_CNT - 1))
846 cmdstat |= RE_TDESC_CMD_EOR;
847 d->re_cmdstat = htole32(cmdstat | ctx->re_flags);
854 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
855 ctx->re_maxsegs = nseg;
860 * Map a single buffer address.
864 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
871 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
873 *addr = segs->ds_addr;
877 re_allocmem(device_t dev, struct re_softc *sc)
882 * Allocate map for RX mbufs.
885 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0,
886 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
887 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
888 &sc->re_ldata.re_mtag);
890 device_printf(dev, "could not allocate dma tag\n");
895 * Allocate map for TX descriptor list.
897 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
898 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
899 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
900 &sc->re_ldata.re_tx_list_tag);
902 device_printf(dev, "could not allocate dma tag\n");
906 /* Allocate DMA'able memory for the TX ring */
908 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag,
909 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
910 &sc->re_ldata.re_tx_list_map);
912 device_printf(dev, "could not allocate TX ring\n");
916 /* Load the map for the TX ring. */
918 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag,
919 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
920 RE_TX_LIST_SZ, re_dma_map_addr,
921 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT);
923 device_printf(dev, "could not get addres of TX ring\n");
927 /* Create DMA maps for TX buffers */
929 for (i = 0; i < RE_TX_DESC_CNT; i++) {
930 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
931 &sc->re_ldata.re_tx_dmamap[i]);
933 device_printf(dev, "can't create DMA map for TX\n");
939 * Allocate map for RX descriptor list.
941 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
942 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
943 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
944 &sc->re_ldata.re_rx_list_tag);
946 device_printf(dev, "could not allocate dma tag\n");
950 /* Allocate DMA'able memory for the RX ring */
952 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag,
953 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
954 &sc->re_ldata.re_rx_list_map);
956 device_printf(dev, "could not allocate RX ring\n");
960 /* Load the map for the RX ring. */
962 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag,
963 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
964 RE_TX_LIST_SZ, re_dma_map_addr,
965 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT);
967 device_printf(dev, "could not get address of RX ring\n");
971 /* Create DMA maps for RX buffers */
973 for (i = 0; i < RE_RX_DESC_CNT; i++) {
974 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
975 &sc->re_ldata.re_rx_dmamap[i]);
977 device_printf(dev, "can't create DMA map for RX\n");
986 * Attach the interface. Allocate softc structures, do ifmedia
987 * setup and ethernet/BPF attach.
990 re_attach(device_t dev)
992 struct re_softc *sc = device_get_softc(dev);
994 struct re_hwrev *hw_rev;
995 uint8_t eaddr[ETHER_ADDR_LEN];
997 u_int16_t re_did = 0;
998 int error = 0, rid, i;
1000 callout_init(&sc->re_timer);
1002 #ifndef BURN_BRIDGES
1004 * Handle power management nonsense.
1007 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1008 uint32_t membase, irq;
1010 /* Save important PCI config data. */
1011 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1012 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1014 /* Reset the power state. */
1015 device_printf(dev, "chip is is in D%d power mode "
1016 "-- setting to D0\n", pci_get_powerstate(dev));
1018 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1020 /* Restore PCI config data. */
1021 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1022 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1026 * Map control/status registers.
1028 pci_enable_busmaster(dev);
1031 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1034 if (sc->re_res == NULL) {
1035 device_printf(dev, "couldn't map ports/memory\n");
1040 sc->re_btag = rman_get_bustag(sc->re_res);
1041 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1043 /* Allocate interrupt */
1045 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1046 RF_SHAREABLE | RF_ACTIVE);
1048 if (sc->re_irq == NULL) {
1049 device_printf(dev, "couldn't map interrupt\n");
1054 /* Reset the adapter. */
1057 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
1058 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) {
1059 if (hw_rev->re_rev == hwrev) {
1060 sc->re_type = hw_rev->re_type;
1065 if (sc->re_type == RE_8169) {
1066 /* Set RX length mask */
1067 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1069 /* Force station address autoload from the EEPROM */
1070 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_AUTOLOAD);
1071 for (i = 0; i < RE_TIMEOUT; i++) {
1072 if ((CSR_READ_1(sc, RE_EECMD) & RE_EEMODE_AUTOLOAD) == 0)
1076 if (i == RE_TIMEOUT)
1077 device_printf(dev, "eeprom autoload timed out\n");
1079 for (i = 0; i < ETHER_ADDR_LEN; i++)
1080 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i);
1084 /* Set RX length mask */
1085 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1087 sc->re_eecmd_read = RE_EECMD_READ_6BIT;
1088 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0);
1089 if (re_did != 0x8129)
1090 sc->re_eecmd_read = RE_EECMD_READ_8BIT;
1093 * Get station address from the EEPROM.
1095 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3, 0);
1096 for (i = 0; i < 3; i++) {
1097 eaddr[(i * 2) + 0] = as[i] & 0xff;
1098 eaddr[(i * 2) + 1] = as[i] >> 8;
1103 * Allocate the parent bus DMA tag appropriate for PCI.
1105 #define RE_NSEG_NEW 32
1106 error = bus_dma_tag_create(NULL, /* parent */
1107 1, 0, /* alignment, boundary */
1108 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1109 BUS_SPACE_MAXADDR, /* highaddr */
1110 NULL, NULL, /* filter, filterarg */
1111 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */
1112 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1113 BUS_DMA_ALLOCNOW, /* flags */
1114 &sc->re_parent_tag);
1118 error = re_allocmem(dev, sc);
1124 if (mii_phy_probe(dev, &sc->re_miibus,
1125 re_ifmedia_upd, re_ifmedia_sts)) {
1126 device_printf(dev, "MII without any phy!\n");
1131 ifp = &sc->arpcom.ac_if;
1133 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1134 ifp->if_mtu = ETHERMTU;
1135 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1136 ifp->if_ioctl = re_ioctl;
1137 ifp->if_capabilities = IFCAP_VLAN_MTU;
1138 ifp->if_start = re_start;
1139 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1140 #ifdef DEVICE_POLLING
1141 ifp->if_poll = re_poll;
1143 ifp->if_watchdog = re_watchdog;
1144 ifp->if_init = re_init;
1145 if (sc->re_type == RE_8169)
1146 ifp->if_baudrate = 1000000000;
1148 ifp->if_baudrate = 100000000;
1149 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN);
1150 ifq_set_ready(&ifp->if_snd);
1151 #ifdef RE_DISABLE_HWCSUM
1152 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1153 ifp->if_hwassist = 0;
1155 ifp->if_capenable = ifp->if_capabilities;
1156 ifp->if_hwassist = RE_CSUM_FEATURES;
1160 * Call MI attach routine.
1162 ether_ifattach(ifp, eaddr);
1164 /* Perform hardware diagnostic. */
1165 error = re_diag(sc);
1168 device_printf(dev, "hardware diagnostic failure\n");
1169 ether_ifdetach(ifp);
1173 /* Hook interrupt last to avoid having to lock softc */
1174 error = bus_setup_intr(dev, sc->re_irq, 0, re_intr, sc,
1175 &sc->re_intrhand, NULL);
1178 device_printf(dev, "couldn't set up irq\n");
1179 ether_ifdetach(ifp);
1191 * Shutdown hardware and free up resources. This can be called any
1192 * time after the mutex has been initialized. It is called in both
1193 * the error case in attach and the normal detach case so it needs
1194 * to be careful about only freeing resources that have actually been
1198 re_detach(device_t dev)
1200 struct re_softc *sc = device_get_softc(dev);
1201 struct ifnet *ifp = &sc->arpcom.ac_if;
1206 /* These should only be active if attach succeeded */
1207 if (device_is_attached(dev)) {
1209 ether_ifdetach(ifp);
1212 device_delete_child(dev, sc->re_miibus);
1213 bus_generic_detach(dev);
1215 if (sc->re_intrhand)
1216 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1221 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1223 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1226 /* Unload and free the RX DMA ring memory and map */
1228 if (sc->re_ldata.re_rx_list_tag) {
1229 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1230 sc->re_ldata.re_rx_list_map);
1231 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1232 sc->re_ldata.re_rx_list,
1233 sc->re_ldata.re_rx_list_map);
1234 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1237 /* Unload and free the TX DMA ring memory and map */
1239 if (sc->re_ldata.re_tx_list_tag) {
1240 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1241 sc->re_ldata.re_tx_list_map);
1242 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1243 sc->re_ldata.re_tx_list,
1244 sc->re_ldata.re_tx_list_map);
1245 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1248 /* Destroy all the RX and TX buffer maps */
1250 if (sc->re_ldata.re_mtag) {
1251 for (i = 0; i < RE_TX_DESC_CNT; i++)
1252 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1253 sc->re_ldata.re_tx_dmamap[i]);
1254 for (i = 0; i < RE_RX_DESC_CNT; i++)
1255 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1256 sc->re_ldata.re_rx_dmamap[i]);
1257 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1260 /* Unload and free the stats buffer and map */
1262 if (sc->re_ldata.re_stag) {
1263 bus_dmamap_unload(sc->re_ldata.re_stag,
1264 sc->re_ldata.re_rx_list_map);
1265 bus_dmamem_free(sc->re_ldata.re_stag,
1266 sc->re_ldata.re_stats,
1267 sc->re_ldata.re_smap);
1268 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1271 if (sc->re_parent_tag)
1272 bus_dma_tag_destroy(sc->re_parent_tag);
1278 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m)
1280 struct re_dmaload_arg arg;
1281 struct mbuf *n = NULL;
1285 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1290 m->m_data = m->m_ext.ext_buf;
1293 * Initialize mbuf length fields and fixup
1294 * alignment so that the frame payload is
1297 m->m_len = m->m_pkthdr.len = MCLBYTES;
1298 m_adj(m, ETHER_ALIGN);
1304 arg.re_ring = sc->re_ldata.re_rx_list;
1306 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag,
1307 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc,
1308 &arg, BUS_DMA_NOWAIT);
1309 if (error || arg.re_maxsegs != 1) {
1315 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN);
1316 sc->re_ldata.re_rx_mbuf[idx] = m;
1318 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx],
1319 BUS_DMASYNC_PREREAD);
1325 re_tx_list_init(struct re_softc *sc)
1327 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ);
1328 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *));
1330 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1331 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1332 sc->re_ldata.re_tx_prodidx = 0;
1333 sc->re_ldata.re_tx_considx = 0;
1334 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT;
1340 re_rx_list_init(struct re_softc *sc)
1344 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ);
1345 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *));
1347 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1348 error = re_newbuf(sc, i, NULL);
1353 /* Flush the RX descriptors */
1355 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1356 sc->re_ldata.re_rx_list_map,
1357 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1359 sc->re_ldata.re_rx_prodidx = 0;
1360 sc->re_head = sc->re_tail = NULL;
1366 * RX handler for C+ and 8169. For the gigE chips, we support
1367 * the reception of jumbo frames that have been fragmented
1368 * across multiple 2K mbuf cluster buffers.
1371 re_rxeof(struct re_softc *sc)
1373 struct ifnet *ifp = &sc->arpcom.ac_if;
1375 struct re_desc *cur_rx;
1376 uint32_t rxstat, rxvlan;
1379 /* Invalidate the descriptor memory */
1381 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1382 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
1384 for (i = sc->re_ldata.re_rx_prodidx;
1385 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) {
1386 cur_rx = &sc->re_ldata.re_rx_list[i];
1387 m = sc->re_ldata.re_rx_mbuf[i];
1388 total_len = RE_RXBYTES(cur_rx);
1389 rxstat = le32toh(cur_rx->re_cmdstat);
1390 rxvlan = le32toh(cur_rx->re_vlanctl);
1392 /* Invalidate the RX mbuf and unload its map */
1394 bus_dmamap_sync(sc->re_ldata.re_mtag,
1395 sc->re_ldata.re_rx_dmamap[i],
1396 BUS_DMASYNC_POSTWRITE);
1397 bus_dmamap_unload(sc->re_ldata.re_mtag,
1398 sc->re_ldata.re_rx_dmamap[i]);
1400 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1401 m->m_len = MCLBYTES - ETHER_ALIGN;
1402 if (sc->re_head == NULL) {
1403 sc->re_head = sc->re_tail = m;
1405 sc->re_tail->m_next = m;
1408 re_newbuf(sc, i, NULL);
1413 * NOTE: for the 8139C+, the frame length field
1414 * is always 12 bits in size, but for the gigE chips,
1415 * it is 13 bits (since the max RX frame length is 16K).
1416 * Unfortunately, all 32 bits in the status word
1417 * were already used, so to make room for the extra
1418 * length bit, RealTek took out the 'frame alignment
1419 * error' bit and shifted the other status bits
1420 * over one slot. The OWN, EOR, FS and LS bits are
1421 * still in the same places. We have already extracted
1422 * the frame length and checked the OWN bit, so rather
1423 * than using an alternate bit mapping, we shift the
1424 * status bits one space to the right so we can evaluate
1425 * them using the 8169 status as though it was in the
1426 * same format as that of the 8139C+.
1428 if (sc->re_type == RE_8169)
1431 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1434 * If this is part of a multi-fragment packet,
1435 * discard all the pieces.
1437 if (sc->re_head != NULL) {
1438 m_freem(sc->re_head);
1439 sc->re_head = sc->re_tail = NULL;
1441 re_newbuf(sc, i, m);
1446 * If allocating a replacement mbuf fails,
1447 * reload the current one.
1450 if (re_newbuf(sc, i, NULL)) {
1452 if (sc->re_head != NULL) {
1453 m_freem(sc->re_head);
1454 sc->re_head = sc->re_tail = NULL;
1456 re_newbuf(sc, i, m);
1460 if (sc->re_head != NULL) {
1461 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN);
1463 * Special case: if there's 4 bytes or less
1464 * in this buffer, the mbuf can be discarded:
1465 * the last 4 bytes is the CRC, which we don't
1466 * care about anyway.
1468 if (m->m_len <= ETHER_CRC_LEN) {
1469 sc->re_tail->m_len -=
1470 (ETHER_CRC_LEN - m->m_len);
1473 m->m_len -= ETHER_CRC_LEN;
1474 sc->re_tail->m_next = m;
1477 sc->re_head = sc->re_tail = NULL;
1478 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1480 m->m_pkthdr.len = m->m_len =
1481 (total_len - ETHER_CRC_LEN);
1484 m->m_pkthdr.rcvif = ifp;
1486 /* Do RX checksumming if enabled */
1488 if (ifp->if_capenable & IFCAP_RXCSUM) {
1490 /* Check IP header checksum */
1491 if (rxstat & RE_RDESC_STAT_PROTOID)
1492 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1493 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1494 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1496 /* Check TCP/UDP checksum */
1497 if ((RE_TCPPKT(rxstat) &&
1498 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
1499 (RE_UDPPKT(rxstat) &&
1500 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) {
1501 m->m_pkthdr.csum_flags |=
1502 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1503 m->m_pkthdr.csum_data = 0xffff;
1507 if (rxvlan & RE_RDESC_VLANCTL_TAG)
1509 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA)));
1511 (*ifp->if_input)(ifp, m);
1514 /* Flush the RX DMA ring */
1516 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1517 sc->re_ldata.re_rx_list_map,
1518 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1520 sc->re_ldata.re_rx_prodidx = i;
1524 re_txeof(struct re_softc *sc)
1526 struct ifnet *ifp = &sc->arpcom.ac_if;
1530 /* Invalidate the TX descriptor list */
1532 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1533 sc->re_ldata.re_tx_list_map,
1534 BUS_DMASYNC_POSTREAD);
1536 for (idx = sc->re_ldata.re_tx_considx;
1537 idx != sc->re_ldata.re_tx_prodidx; RE_DESC_INC(idx)) {
1538 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
1539 if (txstat & RE_TDESC_CMD_OWN)
1543 * We only stash mbufs in the last descriptor
1544 * in a fragment chain, which also happens to
1545 * be the only place where the TX status bits
1548 if (txstat & RE_TDESC_CMD_EOF) {
1549 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
1550 sc->re_ldata.re_tx_mbuf[idx] = NULL;
1551 bus_dmamap_unload(sc->re_ldata.re_mtag,
1552 sc->re_ldata.re_tx_dmamap[idx]);
1553 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
1554 RE_TDESC_STAT_COLCNT))
1555 ifp->if_collisions++;
1556 if (txstat & RE_TDESC_STAT_TXERRSUM)
1561 sc->re_ldata.re_tx_free++;
1564 /* No changes made to the TX ring, so no flush needed */
1565 if (idx != sc->re_ldata.re_tx_considx) {
1566 sc->re_ldata.re_tx_considx = idx;
1567 ifp->if_flags &= ~IFF_OACTIVE;
1572 * If not all descriptors have been released reaped yet,
1573 * reload the timer so that we will eventually get another
1574 * interrupt that will cause us to re-enter this routine.
1575 * This is done in case the transmitter has gone idle.
1577 if (sc->re_ldata.re_tx_free != RE_TX_DESC_CNT)
1578 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1584 struct re_softc *sc = xsc;
1585 struct mii_data *mii;
1589 mii = device_get_softc(sc->re_miibus);
1592 callout_reset(&sc->re_timer, hz, re_tick, sc);
1597 #ifdef DEVICE_POLLING
1600 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1602 struct re_softc *sc = ifp->if_softc;
1606 /* disable interrupts */
1607 CSR_WRITE_2(sc, RE_IMR, 0x0000);
1609 case POLL_DEREGISTER:
1610 /* enable interrupts */
1611 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS);
1614 sc->rxcycles = count;
1618 if (!ifq_is_empty(&ifp->if_snd))
1619 (*ifp->if_start)(ifp);
1621 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1624 status = CSR_READ_2(sc, RE_ISR);
1625 if (status == 0xffff)
1628 CSR_WRITE_2(sc, RE_ISR, status);
1631 * XXX check behaviour on receiver stalls.
1634 if (status & RE_ISR_SYSTEM_ERR) {
1642 #endif /* DEVICE_POLLING */
1647 struct re_softc *sc = arg;
1648 struct ifnet *ifp = &sc->arpcom.ac_if;
1651 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0)
1655 status = CSR_READ_2(sc, RE_ISR);
1656 /* If the card has gone away the read returns 0xffff. */
1657 if (status == 0xffff)
1660 CSR_WRITE_2(sc, RE_ISR, status);
1662 if ((status & RE_INTRS_CPLUS) == 0)
1665 if (status & RE_ISR_RX_OK)
1668 if (status & RE_ISR_RX_ERR)
1671 if ((status & RE_ISR_TIMEOUT_EXPIRED) ||
1672 (status & RE_ISR_TX_ERR) ||
1673 (status & RE_ISR_TX_DESC_UNAVAIL))
1676 if (status & RE_ISR_SYSTEM_ERR) {
1681 if (status & RE_ISR_LINKCHG)
1685 if (!ifq_is_empty(&ifp->if_snd))
1686 (*ifp->if_start)(ifp);
1690 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag)
1692 struct ifnet *ifp = &sc->arpcom.ac_if;
1693 struct mbuf *m, *m_new = NULL;
1694 struct re_dmaload_arg arg;
1699 if (sc->re_ldata.re_tx_free <= 4)
1705 * Set up checksum offload. Note: checksum offload bits must
1706 * appear in all descriptors of a multi-descriptor transmit
1707 * attempt. (This is according to testing done with an 8169
1708 * chip. I'm not sure if this is a requirement or a bug.)
1713 if (m->m_pkthdr.csum_flags & CSUM_IP)
1714 arg.re_flags |= RE_TDESC_CMD_IPCSUM;
1715 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1716 arg.re_flags |= RE_TDESC_CMD_TCPCSUM;
1717 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1718 arg.re_flags |= RE_TDESC_CMD_UDPCSUM;
1722 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1723 if (arg.re_maxsegs > 4)
1724 arg.re_maxsegs -= 4;
1725 arg.re_ring = sc->re_ldata.re_tx_list;
1727 map = sc->re_ldata.re_tx_dmamap[*idx];
1728 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1729 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1731 if (error && error != EFBIG) {
1732 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1736 /* Too many segments to map, coalesce into a single mbuf */
1738 if (error || arg.re_maxsegs == 0) {
1739 m_new = m_defrag_nofree(m, MB_DONTWAIT);
1750 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1751 arg.re_ring = sc->re_ldata.re_tx_list;
1753 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1754 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1757 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1763 * Insure that the map for this transmission
1764 * is placed at the array index of the last descriptor
1767 sc->re_ldata.re_tx_dmamap[*idx] =
1768 sc->re_ldata.re_tx_dmamap[arg.re_idx];
1769 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map;
1771 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m;
1772 sc->re_ldata.re_tx_free -= arg.re_maxsegs;
1775 * Set up hardware VLAN tagging. Note: vlan tag info must
1776 * appear in the first descriptor of a multi-descriptor
1777 * transmission attempt.
1780 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1781 m->m_pkthdr.rcvif != NULL &&
1782 m->m_pkthdr.rcvif->if_type == IFT_L2VLAN) {
1784 ifv = m->m_pkthdr.rcvif->if_softc;
1786 sc->re_ldata.re_tx_list[*idx].re_vlanctl =
1787 htole32(htobe16(ifv->ifv_tag) | RE_TDESC_VLANCTL_TAG);
1790 /* Transfer ownership of packet to the chip. */
1792 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |=
1793 htole32(RE_TDESC_CMD_OWN);
1794 if (*idx != arg.re_idx)
1795 sc->re_ldata.re_tx_list[*idx].re_cmdstat |=
1796 htole32(RE_TDESC_CMD_OWN);
1798 RE_DESC_INC(arg.re_idx);
1805 * Main transmit routine for C+ and gigE NICs.
1809 re_start(struct ifnet *ifp)
1811 struct re_softc *sc = ifp->if_softc;
1812 struct mbuf *m_head = NULL, *m_head2;
1813 int called_defrag, idx, need_trans;
1817 idx = sc->re_ldata.re_tx_prodidx;
1820 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
1821 m_head = ifq_poll(&ifp->if_snd);
1825 if (re_encap(sc, &m_head, &idx, &called_defrag)) {
1826 if (called_defrag) {
1827 m_head2 = ifq_dequeue(&ifp->if_snd);
1830 ifp->if_flags |= IFF_OACTIVE;
1834 m_head2 = ifq_dequeue(&ifp->if_snd);
1840 * If there's a BPF listener, bounce a copy of this frame
1843 BPF_MTAP(ifp, m_head);
1851 /* Flush the TX descriptors */
1852 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1853 sc->re_ldata.re_tx_list_map,
1854 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1856 sc->re_ldata.re_tx_prodidx = idx;
1859 * RealTek put the TX poll request register in a different
1860 * location on the 8169 gigE chip. I don't know why.
1862 if (sc->re_type == RE_8169)
1863 CSR_WRITE_2(sc, RE_GTXSTART, RE_TXSTART_START);
1865 CSR_WRITE_2(sc, RE_TXSTART, RE_TXSTART_START);
1868 * Use the countdown timer for interrupt moderation.
1869 * 'TX done' interrupts are disabled. Instead, we reset the
1870 * countdown timer, which will begin counting until it hits
1871 * the value in the TIMERINT register, and then trigger an
1872 * interrupt. Each time we write to the TIMERCNT register,
1873 * the timer count is reset to 0.
1875 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1878 * Set a timeout in case the chip goes out to lunch.
1888 struct re_softc *sc = xsc;
1889 struct ifnet *ifp = &sc->arpcom.ac_if;
1890 struct mii_data *mii;
1895 mii = device_get_softc(sc->re_miibus);
1898 * Cancel pending I/O and free all RX/TX buffers.
1903 * Enable C+ RX and TX mode, as well as VLAN stripping and
1904 * RX checksum offload. We must configure the C+ register
1905 * before all others.
1907 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
1908 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP |
1909 (ifp->if_capenable & IFCAP_RXCSUM ?
1910 RE_CPLUSCMD_RXCSUM_ENB : 0));
1913 * Init our MAC address. Even though the chipset
1914 * documentation doesn't mention it, we need to enter "Config
1915 * register write enable" mode to modify the ID registers.
1917 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
1918 CSR_WRITE_STREAM_4(sc, RE_IDR0,
1919 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1920 CSR_WRITE_STREAM_4(sc, RE_IDR4,
1921 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1922 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
1925 * For C+ mode, initialize the RX descriptors and mbufs.
1927 re_rx_list_init(sc);
1928 re_tx_list_init(sc);
1931 * Enable transmit and receive.
1933 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
1936 * Set the initial TX and RX configuration.
1938 if (sc->re_testmode) {
1939 if (sc->re_type == RE_8169)
1940 CSR_WRITE_4(sc, RE_TXCFG,
1941 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
1943 CSR_WRITE_4(sc, RE_TXCFG,
1944 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
1946 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
1947 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
1949 /* Set the individual bit to receive frames for this host only. */
1950 rxcfg = CSR_READ_4(sc, RE_RXCFG);
1951 rxcfg |= RE_RXCFG_RX_INDIV;
1953 /* If we want promiscuous mode, set the allframes bit. */
1954 if (ifp->if_flags & IFF_PROMISC) {
1955 rxcfg |= RE_RXCFG_RX_ALLPHYS;
1956 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1958 rxcfg &= ~RE_RXCFG_RX_ALLPHYS;
1959 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1963 * Set capture broadcast bit to capture broadcast frames.
1965 if (ifp->if_flags & IFF_BROADCAST) {
1966 rxcfg |= RE_RXCFG_RX_BROAD;
1967 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1969 rxcfg &= ~RE_RXCFG_RX_BROAD;
1970 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1974 * Program the multicast filter, if necessary.
1978 #ifdef DEVICE_POLLING
1980 * Disable interrupts if we are polling.
1982 if (ifp->if_flags & IFF_POLLING)
1983 CSR_WRITE_2(sc, RE_IMR, 0);
1984 else /* otherwise ... */
1985 #endif /* DEVICE_POLLING */
1987 * Enable interrupts.
1989 if (sc->re_testmode)
1990 CSR_WRITE_2(sc, RE_IMR, 0);
1992 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS);
1994 /* Set initial TX threshold */
1995 sc->re_txthresh = RE_TX_THRESH_INIT;
1997 /* Start RX/TX process. */
1998 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
2000 /* Enable receiver and transmitter. */
2001 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2004 * Load the addresses of the RX and TX lists into the chip.
2007 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2008 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2009 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2010 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2012 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2013 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2014 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2015 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2017 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16);
2020 * Initialize the timer interrupt register so that
2021 * a timer interrupt will be generated once the timer
2022 * reaches a certain number of ticks. The timer is
2023 * reloaded on each transmit. This gives us TX interrupt
2024 * moderation, which dramatically improves TX frame rate.
2027 if (sc->re_type == RE_8169)
2028 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800);
2030 CSR_WRITE_4(sc, RE_TIMERINT, 0x400);
2033 * For 8169 gigE NICs, set the max allowed RX packet
2034 * size so we can receive jumbo frames.
2036 if (sc->re_type == RE_8169)
2037 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2039 if (sc->re_testmode) {
2046 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2048 ifp->if_flags |= IFF_RUNNING;
2049 ifp->if_flags &= ~IFF_OACTIVE;
2051 callout_reset(&sc->re_timer, hz, re_tick, sc);
2057 * Set media options.
2060 re_ifmedia_upd(struct ifnet *ifp)
2062 struct re_softc *sc = ifp->if_softc;
2063 struct mii_data *mii;
2065 mii = device_get_softc(sc->re_miibus);
2072 * Report current media status.
2075 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2077 struct re_softc *sc = ifp->if_softc;
2078 struct mii_data *mii;
2080 mii = device_get_softc(sc->re_miibus);
2083 ifmr->ifm_active = mii->mii_media_active;
2084 ifmr->ifm_status = mii->mii_media_status;
2088 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2090 struct re_softc *sc = ifp->if_softc;
2091 struct ifreq *ifr = (struct ifreq *) data;
2092 struct mii_data *mii;
2099 if (ifr->ifr_mtu > RE_JUMBO_MTU)
2101 ifp->if_mtu = ifr->ifr_mtu;
2104 if (ifp->if_flags & IFF_UP)
2106 else if (ifp->if_flags & IFF_RUNNING)
2117 mii = device_get_softc(sc->re_miibus);
2118 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2121 ifp->if_capenable &= ~(IFCAP_HWCSUM);
2122 ifp->if_capenable |=
2123 ifr->ifr_reqcap & (IFCAP_HWCSUM);
2124 if (ifp->if_capenable & IFCAP_TXCSUM)
2125 ifp->if_hwassist = RE_CSUM_FEATURES;
2127 ifp->if_hwassist = 0;
2128 if (ifp->if_flags & IFF_RUNNING)
2132 error = ether_ioctl(ifp, command, data);
2142 re_watchdog(struct ifnet *ifp)
2144 struct re_softc *sc = ifp->if_softc;
2146 if_printf(ifp, "watchdog timeout\n");
2157 if (!ifq_is_empty(&ifp->if_snd))
2164 * Stop the adapter and free any mbufs allocated to the
2168 re_stop(struct re_softc *sc)
2170 struct ifnet *ifp = &sc->arpcom.ac_if;
2176 callout_stop(&sc->re_timer);
2178 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2180 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2181 CSR_WRITE_2(sc, RE_IMR, 0x0000);
2183 if (sc->re_head != NULL) {
2184 m_freem(sc->re_head);
2185 sc->re_head = sc->re_tail = NULL;
2188 /* Free the TX list buffers. */
2189 for (i = 0; i < RE_TX_DESC_CNT; i++) {
2190 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2191 bus_dmamap_unload(sc->re_ldata.re_mtag,
2192 sc->re_ldata.re_tx_dmamap[i]);
2193 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2194 sc->re_ldata.re_tx_mbuf[i] = NULL;
2198 /* Free the RX list buffers. */
2199 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2200 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2201 bus_dmamap_unload(sc->re_ldata.re_mtag,
2202 sc->re_ldata.re_rx_dmamap[i]);
2203 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2204 sc->re_ldata.re_rx_mbuf[i] = NULL;
2212 * Device suspend routine. Stop the interface and save some PCI
2213 * settings in case the BIOS doesn't restore them properly on
2217 re_suspend(device_t dev)
2219 #ifndef BURN_BRIDGES
2222 struct re_softc *sc = device_get_softc(dev);
2226 #ifndef BURN_BRIDGES
2227 for (i = 0; i < 5; i++)
2228 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2229 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2230 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2231 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2232 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2241 * Device resume routine. Restore some PCI settings in case the BIOS
2242 * doesn't, re-enable busmastering, and restart the interface if
2246 re_resume(device_t dev)
2248 struct re_softc *sc = device_get_softc(dev);
2249 struct ifnet *ifp = &sc->arpcom.ac_if;
2250 #ifndef BURN_BRIDGES
2254 #ifndef BURN_BRIDGES
2255 /* better way to do this? */
2256 for (i = 0; i < 5; i++)
2257 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2258 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2259 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2260 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2261 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2263 /* reenable busmastering */
2264 pci_enable_busmaster(dev);
2265 pci_enable_io(dev, SYS_RES_IOPORT);
2268 /* reinitialize interface if necessary */
2269 if (ifp->if_flags & IFF_UP)
2278 * Stop all chip I/O so that the kernel's probe routines don't
2279 * get confused by errant DMAs when rebooting.
2282 re_shutdown(device_t dev)
2284 struct re_softc *sc = device_get_softc(dev);