2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $
33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.39 2005/10/21 06:42:43 sephe Exp $
37 * 3Com 3c90x Etherlink XL PCI NIC driver
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
79 * The 3c90x series chips use a bus-master DMA interface for transfering
80 * packets to and from the controller chip. Some of the "vortex" cards
81 * (3c59x) also supported a bus master mode, however for those chips
82 * you could only DMA packets to/from a contiguous memory buffer. For
83 * transmission this would mean copying the contents of the queued mbuf
84 * chain into an mbuf cluster and then DMAing the cluster. This extra
85 * copy would sort of defeat the purpose of the bus master support for
86 * any packet that doesn't fit into a single mbuf.
88 * By contrast, the 3c90x cards support a fragment-based bus master
89 * mode where mbuf chains can be encapsulated using TX descriptors.
90 * This is similar to other PCI chips such as the Texas Instruments
91 * ThunderLAN and the Intel 82557/82558.
93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
94 * bus master chips because they maintain the old PIO interface for
95 * backwards compatibility, but starting with the 3c905B and the
96 * "cyclone" chips, the compatibility interface has been dropped.
97 * Since using bus master DMA is a big win, we use this driver to
98 * support the PCI "boomerang" chips even though they work with the
99 * "vortex" driver in order to obtain better performance.
102 #include <sys/param.h>
103 #include <sys/systm.h>
104 #include <sys/sockio.h>
105 #include <sys/endian.h>
106 #include <sys/mbuf.h>
107 #include <sys/kernel.h>
108 #include <sys/socket.h>
109 #include <sys/thread2.h>
112 #include <net/ifq_var.h>
113 #include <net/if_arp.h>
114 #include <net/ethernet.h>
115 #include <net/if_dl.h>
116 #include <net/if_media.h>
117 #include <net/vlan/if_vlan_var.h>
121 #include <machine/bus_memio.h>
122 #include <machine/bus_pio.h>
123 #include <machine/bus.h>
124 #include <machine/resource.h>
126 #include <sys/rman.h>
128 #include "../mii_layer/mii.h"
129 #include "../mii_layer/miivar.h"
131 #include <bus/pci/pcireg.h>
132 #include <bus/pci/pcivar.h>
134 /* "controller miibus0" required. See GENERIC if you get errors here. */
135 #include "miibus_if.h"
137 #include "if_xlreg.h"
139 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
142 * Various supported device vendors/types and their names.
144 static struct xl_type xl_devs[] = {
145 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
146 "3Com 3c900-TPO Etherlink XL" },
147 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
148 "3Com 3c900-COMBO Etherlink XL" },
149 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
150 "3Com 3c905-TX Fast Etherlink XL" },
151 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
152 "3Com 3c905-T4 Fast Etherlink XL" },
153 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
154 "3Com 3c900B-TPO Etherlink XL" },
155 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
156 "3Com 3c900B-COMBO Etherlink XL" },
157 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
158 "3Com 3c900B-TPC Etherlink XL" },
159 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
160 "3Com 3c900B-FL Etherlink XL" },
161 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
162 "3Com 3c905B-TX Fast Etherlink XL" },
163 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
164 "3Com 3c905B-T4 Fast Etherlink XL" },
165 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
166 "3Com 3c905B-FX/SC Fast Etherlink XL" },
167 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
168 "3Com 3c905B-COMBO Fast Etherlink XL" },
169 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
170 "3Com 3c905C-TX Fast Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
172 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
174 "3Com 3c980 Fast Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
176 "3Com 3c980C Fast Etherlink XL" },
177 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
178 "3Com 3cSOHO100-TX OfficeConnect" },
179 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
180 "3Com 3c450-TX HomeConnect" },
181 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
182 "3Com 3c555 Fast Etherlink XL" },
183 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
184 "3Com 3c556 Fast Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
186 "3Com 3c556B Fast Etherlink XL" },
187 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
188 "3Com 3c575TX Fast Etherlink XL" },
189 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
190 "3Com 3c575B Fast Etherlink XL" },
191 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
192 "3Com 3c575C Fast Etherlink XL" },
193 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
194 "3Com 3c656 Fast Etherlink XL" },
195 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
196 "3Com 3c656B Fast Etherlink XL" },
197 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
198 "3Com 3c656C Fast Etherlink XL" },
202 static int xl_probe (device_t);
203 static int xl_attach (device_t);
204 static int xl_detach (device_t);
206 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *);
207 static void xl_stats_update (void *);
208 static int xl_encap (struct xl_softc *, struct xl_chain *,
210 static void xl_rxeof (struct xl_softc *, int);
211 static int xl_rx_resync (struct xl_softc *);
212 static void xl_txeof (struct xl_softc *);
213 static void xl_txeof_90xB (struct xl_softc *);
214 static void xl_txeoc (struct xl_softc *);
215 static void xl_intr (void *);
216 static void xl_start_body (struct ifnet *, int);
217 static void xl_start (struct ifnet *);
218 static void xl_start_90xB (struct ifnet *);
219 static int xl_ioctl (struct ifnet *, u_long, caddr_t,
221 static void xl_init (void *);
222 static void xl_stop (struct xl_softc *);
223 static void xl_watchdog (struct ifnet *);
224 static void xl_shutdown (device_t);
225 static int xl_suspend (device_t);
226 static int xl_resume (device_t);
227 #ifdef DEVICE_POLLING
228 static void xl_poll (struct ifnet *, enum poll_cmd, int);
230 static void xl_enable_intrs (struct xl_softc *, uint16_t);
232 static int xl_ifmedia_upd (struct ifnet *);
233 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
235 static int xl_eeprom_wait (struct xl_softc *);
236 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int);
237 static void xl_mii_sync (struct xl_softc *);
238 static void xl_mii_send (struct xl_softc *, u_int32_t, int);
239 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *);
240 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *);
242 static void xl_setcfg (struct xl_softc *);
243 static void xl_setmode (struct xl_softc *, int);
244 static void xl_setmulti (struct xl_softc *);
245 static void xl_setmulti_hash (struct xl_softc *);
246 static void xl_reset (struct xl_softc *);
247 static int xl_list_rx_init (struct xl_softc *);
248 static void xl_list_tx_init (struct xl_softc *);
249 static void xl_list_tx_init_90xB(struct xl_softc *);
250 static void xl_wait (struct xl_softc *);
251 static void xl_mediacheck (struct xl_softc *);
252 static void xl_choose_xcvr (struct xl_softc *, int);
253 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int);
254 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t,
256 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t,
259 static int xl_dma_alloc (device_t);
260 static void xl_dma_free (device_t);
263 static void xl_testpacket (struct xl_softc *);
266 static int xl_miibus_readreg (device_t, int, int);
267 static int xl_miibus_writereg (device_t, int, int, int);
268 static void xl_miibus_statchg (device_t);
269 static void xl_miibus_mediainit (device_t);
271 static device_method_t xl_methods[] = {
272 /* Device interface */
273 DEVMETHOD(device_probe, xl_probe),
274 DEVMETHOD(device_attach, xl_attach),
275 DEVMETHOD(device_detach, xl_detach),
276 DEVMETHOD(device_shutdown, xl_shutdown),
277 DEVMETHOD(device_suspend, xl_suspend),
278 DEVMETHOD(device_resume, xl_resume),
281 DEVMETHOD(bus_print_child, bus_generic_print_child),
282 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
285 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
286 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
287 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
288 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
293 static driver_t xl_driver = {
296 sizeof(struct xl_softc)
299 static devclass_t xl_devclass;
301 DECLARE_DUMMY_MODULE(if_xl);
302 MODULE_DEPEND(if_xl, miibus, 1, 1, 1);
303 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0);
304 DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0);
305 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
308 xl_enable_intrs(struct xl_softc *sc, uint16_t intrs)
310 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK | 0xFF);
311 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB | intrs);
312 if (sc->xl_flags & XL_FLAG_FUNCREG)
313 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
317 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
322 *paddr = segs->ds_addr;
326 xl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg,
327 bus_size_t mapsize, int error)
333 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments"));
335 *paddr = segs->ds_addr;
339 xl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg,
340 bus_size_t mapsize, int error)
348 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments"));
352 for (i = 0; i < nseg; i++) {
353 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
354 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr);
355 l->xl_frag[i].xl_len = htole32(segs[i].ds_len);
356 total_len += segs[i].ds_len;
358 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len |
360 l->xl_status = htole32(total_len);
365 * Murphy's law says that it's possible the chip can wedge and
366 * the 'command in progress' bit may never clear. Hence, we wait
367 * only a finite amount of time to avoid getting caught in an
368 * infinite loop. Normally this delay routine would be a macro,
369 * but it isn't called during normal operation so we can afford
370 * to make it a function.
373 xl_wait(struct xl_softc *sc)
377 for (i = 0; i < XL_TIMEOUT; i++) {
378 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
383 if_printf(&sc->arpcom.ac_if, "command never completed!");
389 * MII access routines are provided for adapters with external
390 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
391 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
392 * Note: if you don't perform the MDIO operations just right,
393 * it's possible to end up with code that works correctly with
394 * some chips/CPUs/processor speeds/bus speeds/etc but not
398 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
399 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
402 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
403 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
406 * Sync the PHYs by setting data bit and strobing the clock 32 times.
409 xl_mii_sync(struct xl_softc *sc)
414 MII_SET(XL_MII_DIR|XL_MII_DATA);
416 for (i = 0; i < 32; i++) {
418 MII_SET(XL_MII_DATA);
419 MII_SET(XL_MII_DATA);
421 MII_SET(XL_MII_DATA);
422 MII_SET(XL_MII_DATA);
429 * Clock a series of bits through the MII.
432 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt)
439 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
441 MII_SET(XL_MII_DATA);
443 MII_CLR(XL_MII_DATA);
451 * Read an PHY register through the MII.
454 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame)
461 * Set up frame for RX.
463 frame->mii_stdelim = XL_MII_STARTDELIM;
464 frame->mii_opcode = XL_MII_READOP;
465 frame->mii_turnaround = 0;
469 * Select register window 4.
474 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
483 * Send command/address info.
485 xl_mii_send(sc, frame->mii_stdelim, 2);
486 xl_mii_send(sc, frame->mii_opcode, 2);
487 xl_mii_send(sc, frame->mii_phyaddr, 5);
488 xl_mii_send(sc, frame->mii_regaddr, 5);
491 MII_CLR((XL_MII_CLK|XL_MII_DATA));
499 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
503 * Now try reading data bits. If the ack failed, we still
504 * need to clock through 16 cycles to keep the PHY(s) in sync.
507 for(i = 0; i < 16; i++) {
514 for (i = 0x8000; i; i >>= 1) {
517 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
518 frame->mii_data |= i;
536 * Write to a PHY register through the MII.
539 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame)
544 * Set up frame for TX.
547 frame->mii_stdelim = XL_MII_STARTDELIM;
548 frame->mii_opcode = XL_MII_WRITEOP;
549 frame->mii_turnaround = XL_MII_TURNAROUND;
552 * Select the window 4.
557 * Turn on data output.
563 xl_mii_send(sc, frame->mii_stdelim, 2);
564 xl_mii_send(sc, frame->mii_opcode, 2);
565 xl_mii_send(sc, frame->mii_phyaddr, 5);
566 xl_mii_send(sc, frame->mii_regaddr, 5);
567 xl_mii_send(sc, frame->mii_turnaround, 2);
568 xl_mii_send(sc, frame->mii_data, 16);
585 xl_miibus_readreg(device_t dev, int phy, int reg)
588 struct xl_mii_frame frame;
590 sc = device_get_softc(dev);
593 * Pretend that PHYs are only available at MII address 24.
594 * This is to guard against problems with certain 3Com ASIC
595 * revisions that incorrectly map the internal transceiver
596 * control registers at all MII addresses. This can cause
597 * the miibus code to attach the same PHY several times over.
599 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
602 bzero((char *)&frame, sizeof(frame));
604 frame.mii_phyaddr = phy;
605 frame.mii_regaddr = reg;
606 xl_mii_readreg(sc, &frame);
608 return(frame.mii_data);
612 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
615 struct xl_mii_frame frame;
617 sc = device_get_softc(dev);
619 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
622 bzero((char *)&frame, sizeof(frame));
624 frame.mii_phyaddr = phy;
625 frame.mii_regaddr = reg;
626 frame.mii_data = data;
628 xl_mii_writereg(sc, &frame);
634 xl_miibus_statchg(device_t dev)
637 struct mii_data *mii;
640 sc = device_get_softc(dev);
641 mii = device_get_softc(sc->xl_miibus);
645 /* Set ASIC's duplex mode to match the PHY. */
647 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
648 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
650 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
651 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
657 * Special support for the 3c905B-COMBO. This card has 10/100 support
658 * plus BNC and AUI ports. This means we will have both an miibus attached
659 * plus some non-MII media settings. In order to allow this, we have to
660 * add the extra media to the miibus's ifmedia struct, but we can't do
661 * that during xl_attach() because the miibus hasn't been attached yet.
662 * So instead, we wait until the miibus probe/attach is done, at which
663 * point we will get a callback telling is that it's safe to add our
667 xl_miibus_mediainit(device_t dev)
670 struct mii_data *mii;
673 sc = device_get_softc(dev);
674 mii = device_get_softc(sc->xl_miibus);
675 ifm = &mii->mii_media;
677 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
679 * Check for a 10baseFL board in disguise.
681 if (sc->xl_type == XL_TYPE_905B &&
682 sc->xl_media == XL_MEDIAOPT_10FL) {
684 device_printf(dev, "found 10baseFL\n");
685 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL);
686 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL);
687 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
689 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
692 device_printf(dev, "found AUI\n");
693 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL);
697 if (sc->xl_media & XL_MEDIAOPT_BNC) {
699 device_printf(dev, "found BNC\n");
700 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL);
707 * The EEPROM is slow: give it time to come ready after issuing
711 xl_eeprom_wait(struct xl_softc *sc)
715 for (i = 0; i < 100; i++) {
716 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
723 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n");
731 * Read a sequence of words from the EEPROM. Note that ethernet address
732 * data is stored in the EEPROM in network byte order.
735 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
738 u_int16_t word = 0, *ptr;
739 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
740 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
742 * It's easy to accidentally overwrite the rom content!
743 * Note: the 3c575 uses 8bit EEPROM offsets.
747 if (xl_eeprom_wait(sc))
750 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
753 for (i = 0; i < cnt; i++) {
754 if (sc->xl_flags & XL_FLAG_8BITROM)
755 CSR_WRITE_2(sc, XL_W0_EE_CMD,
756 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
758 CSR_WRITE_2(sc, XL_W0_EE_CMD,
759 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
760 err = xl_eeprom_wait(sc);
763 word = CSR_READ_2(sc, XL_W0_EE_DATA);
764 ptr = (u_int16_t *)(dest + (i * 2));
775 * NICs older than the 3c905B have only one multicast option, which
776 * is to enable reception of all multicast frames.
779 xl_setmulti(struct xl_softc *sc)
782 struct ifmultiaddr *ifma;
786 ifp = &sc->arpcom.ac_if;
789 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
791 if (ifp->if_flags & IFF_ALLMULTI) {
792 rxfilt |= XL_RXFILTER_ALLMULTI;
793 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
797 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
801 rxfilt |= XL_RXFILTER_ALLMULTI;
803 rxfilt &= ~XL_RXFILTER_ALLMULTI;
805 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
811 * 3c905B adapters have a hash filter that we can program.
814 xl_setmulti_hash(struct xl_softc *sc)
818 struct ifmultiaddr *ifma;
822 ifp = &sc->arpcom.ac_if;
825 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
827 if (ifp->if_flags & IFF_ALLMULTI) {
828 rxfilt |= XL_RXFILTER_ALLMULTI;
829 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
832 rxfilt &= ~XL_RXFILTER_ALLMULTI;
835 /* first, zot all the existing hash bits */
836 for (i = 0; i < XL_HASHFILT_SIZE; i++)
837 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
839 /* now program new ones */
840 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
841 if (ifma->ifma_addr->sa_family != AF_LINK)
845 * Note: the 3c905B currently only supports a 64-bit
846 * hash table, which means we really only need 6 bits,
847 * but the manual indicates that future chip revisions
848 * will have a 256-bit hash table, hence the routine is
849 * set up to calculate 8 bits of position info in case
850 * we need it some day.
851 * Note II, The Sequel: _CURRENT_ versions of the 3c905B
852 * have a 256 bit hash table. This means we have to use
853 * all 8 bits regardless. On older cards, the upper 2
854 * bits will be ignored. Grrrr....
857 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
858 ETHER_ADDR_LEN) & 0xff;
859 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
864 rxfilt |= XL_RXFILTER_MULTIHASH;
866 rxfilt &= ~XL_RXFILTER_MULTIHASH;
868 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
875 xl_testpacket(struct xl_softc *sc)
880 ifp = &sc->arpcom.ac_if;
882 MGETHDR(m, MB_DONTWAIT, MT_DATA);
887 bcopy(&sc->arpcom.ac_enaddr,
888 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
889 bcopy(&sc->arpcom.ac_enaddr,
890 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
891 mtod(m, struct ether_header *)->ether_type = htons(3);
892 mtod(m, unsigned char *)[14] = 0;
893 mtod(m, unsigned char *)[15] = 0;
894 mtod(m, unsigned char *)[16] = 0xE3;
895 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
896 IF_ENQUEUE(&ifp->if_snd, m);
904 xl_setcfg(struct xl_softc *sc)
909 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
910 icfg &= ~XL_ICFG_CONNECTOR_MASK;
911 if (sc->xl_media & XL_MEDIAOPT_MII ||
912 sc->xl_media & XL_MEDIAOPT_BT4)
913 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
914 if (sc->xl_media & XL_MEDIAOPT_BTX)
915 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
917 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
918 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
924 xl_setmode(struct xl_softc *sc, int media)
926 struct ifnet *ifp = &sc->arpcom.ac_if;
930 if_printf(ifp, "selecting ");
933 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
935 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
937 if (sc->xl_media & XL_MEDIAOPT_BT) {
938 if (IFM_SUBTYPE(media) == IFM_10_T) {
939 printf("10baseT transceiver, ");
940 sc->xl_xcvr = XL_XCVR_10BT;
941 icfg &= ~XL_ICFG_CONNECTOR_MASK;
942 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
943 mediastat |= XL_MEDIASTAT_LINKBEAT|
944 XL_MEDIASTAT_JABGUARD;
945 mediastat &= ~XL_MEDIASTAT_SQEENB;
949 if (sc->xl_media & XL_MEDIAOPT_BFX) {
950 if (IFM_SUBTYPE(media) == IFM_100_FX) {
951 printf("100baseFX port, ");
952 sc->xl_xcvr = XL_XCVR_100BFX;
953 icfg &= ~XL_ICFG_CONNECTOR_MASK;
954 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
955 mediastat |= XL_MEDIASTAT_LINKBEAT;
956 mediastat &= ~XL_MEDIASTAT_SQEENB;
960 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
961 if (IFM_SUBTYPE(media) == IFM_10_5) {
962 printf("AUI port, ");
963 sc->xl_xcvr = XL_XCVR_AUI;
964 icfg &= ~XL_ICFG_CONNECTOR_MASK;
965 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
966 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
967 XL_MEDIASTAT_JABGUARD);
968 mediastat |= ~XL_MEDIASTAT_SQEENB;
970 if (IFM_SUBTYPE(media) == IFM_10_FL) {
971 printf("10baseFL transceiver, ");
972 sc->xl_xcvr = XL_XCVR_AUI;
973 icfg &= ~XL_ICFG_CONNECTOR_MASK;
974 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
975 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
976 XL_MEDIASTAT_JABGUARD);
977 mediastat |= ~XL_MEDIASTAT_SQEENB;
981 if (sc->xl_media & XL_MEDIAOPT_BNC) {
982 if (IFM_SUBTYPE(media) == IFM_10_2) {
983 printf("BNC port, ");
984 sc->xl_xcvr = XL_XCVR_COAX;
985 icfg &= ~XL_ICFG_CONNECTOR_MASK;
986 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
987 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
988 XL_MEDIASTAT_JABGUARD|
989 XL_MEDIASTAT_SQEENB);
993 if ((media & IFM_GMASK) == IFM_FDX ||
994 IFM_SUBTYPE(media) == IFM_100_FX) {
995 printf("full duplex\n");
997 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
999 printf("half duplex\n");
1001 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
1002 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
1005 if (IFM_SUBTYPE(media) == IFM_10_2)
1006 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
1008 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
1009 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
1011 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
1017 xl_reset(struct xl_softc *sc)
1022 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
1023 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
1024 XL_RESETOPT_DISADVFD:0));
1027 * If we're using memory mapped register mode, pause briefly
1028 * after issuing the reset command before trying to access any
1029 * other registers. With my 3c575C cardbus card, failing to do
1030 * this results in the system locking up while trying to poll
1031 * the command busy bit in the status register.
1033 if (sc->xl_flags & XL_FLAG_USE_MMIO)
1036 for (i = 0; i < XL_TIMEOUT; i++) {
1038 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
1042 if (i == XL_TIMEOUT)
1043 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n");
1045 /* Reset TX and RX. */
1046 /* Note: the RX reset takes an absurd amount of time
1047 * on newer versions of the Tornado chips such as those
1048 * on the 3c905CX and newer 3c908C cards. We wait an
1049 * extra amount of time so that xl_wait() doesn't complain
1050 * and annoy the users.
1052 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1055 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1058 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
1059 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
1061 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,
1062 XL_W2_RESET_OPTIONS)
1063 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0)
1064 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0)
1068 /* Wait a little while for the chip to get its brains in order. */
1074 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1075 * IDs against our list and return a device name if we find a match.
1078 xl_probe(device_t dev)
1083 vid = pci_get_vendor(dev);
1084 did = pci_get_device(dev);
1085 for (t = xl_devs; t->xl_name != NULL; t++) {
1086 if (vid == t->xl_vid && did == t->xl_did) {
1087 device_set_desc(dev, t->xl_name);
1095 * This routine is a kludge to work around possible hardware faults
1096 * or manufacturing defects that can cause the media options register
1097 * (or reset options register, as it's called for the first generation
1098 * 3c90x adapters) to return an incorrect result. I have encountered
1099 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1100 * which doesn't have any of the 'mediaopt' bits set. This screws up
1101 * the attach routine pretty badly because it doesn't know what media
1102 * to look for. If we find ourselves in this predicament, this routine
1103 * will try to guess the media options values and warn the user of a
1104 * possible manufacturing defect with his adapter/system/whatever.
1107 xl_mediacheck(struct xl_softc *sc)
1109 struct ifnet *ifp = &sc->arpcom.ac_if;
1112 * If some of the media options bits are set, assume they are
1113 * correct. If not, try to figure it out down below.
1114 * XXX I should check for 10baseFL, but I don't have an adapter
1117 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1119 * Check the XCVR value. If it's not in the normal range
1120 * of values, we need to fake it up here.
1122 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1125 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n",
1128 "choosing new default based on card type\n");
1131 if (sc->xl_type == XL_TYPE_905B &&
1132 sc->xl_media & XL_MEDIAOPT_10FL)
1134 if_printf(ifp, "WARNING: no media options bits set in "
1135 "the media options register!!\n");
1136 if_printf(ifp, "this could be a manufacturing defect in "
1137 "your adapter or system\n");
1138 if_printf(ifp, "attempting to guess media type; you "
1139 "should probably consult your vendor\n");
1142 xl_choose_xcvr(sc, 1);
1146 xl_choose_xcvr(struct xl_softc *sc, int verbose)
1148 struct ifnet *ifp = &sc->arpcom.ac_if;
1152 * Read the device ID from the EEPROM.
1153 * This is what's loaded into the PCI device ID register, so it has
1154 * to be correct otherwise we wouldn't have gotten this far.
1156 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1159 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1160 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1161 sc->xl_media = XL_MEDIAOPT_BT;
1162 sc->xl_xcvr = XL_XCVR_10BT;
1164 if_printf(ifp, "guessing 10BaseT transceiver\n");
1166 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1167 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1168 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1169 sc->xl_xcvr = XL_XCVR_10BT;
1171 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n");
1173 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1174 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1175 sc->xl_xcvr = XL_XCVR_10BT;
1177 if_printf(ifp, "guessing TPC (BNC/TP)\n");
1179 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1180 sc->xl_media = XL_MEDIAOPT_10FL;
1181 sc->xl_xcvr = XL_XCVR_AUI;
1183 if_printf(ifp, "guessing 10baseFL\n");
1185 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1186 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1187 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1188 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1189 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1190 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1191 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1192 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1193 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1194 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1195 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1196 sc->xl_media = XL_MEDIAOPT_MII;
1197 sc->xl_xcvr = XL_XCVR_MII;
1199 if_printf(ifp, "guessing MII\n");
1201 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1202 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1203 sc->xl_media = XL_MEDIAOPT_BT4;
1204 sc->xl_xcvr = XL_XCVR_MII;
1206 if_printf(ifp, "guessing 100BaseT4/MII\n");
1208 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1209 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1210 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1211 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1212 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1213 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1214 sc->xl_media = XL_MEDIAOPT_BTX;
1215 sc->xl_xcvr = XL_XCVR_AUTO;
1217 if_printf(ifp, "guessing 10/100 internal\n");
1219 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1220 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1221 sc->xl_xcvr = XL_XCVR_AUTO;
1223 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n");
1227 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1228 sc->xl_media = XL_MEDIAOPT_BT;
1236 * Attach the interface. Allocate softc structures, do ifmedia
1237 * setup and ethernet/BPF attach.
1240 xl_attach(device_t dev)
1242 u_char eaddr[ETHER_ADDR_LEN];
1244 struct xl_softc *sc;
1246 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1247 int error = 0, rid, res;
1249 sc = device_get_softc(dev);
1251 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1254 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555)
1255 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1256 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 ||
1257 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1258 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1259 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1260 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1261 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555 ||
1262 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556)
1263 sc->xl_flags |= XL_FLAG_8BITROM;
1264 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1265 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1266 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B ||
1267 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C ||
1268 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B ||
1269 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1270 sc->xl_flags |= XL_FLAG_FUNCREG;
1271 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A ||
1272 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B ||
1273 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C ||
1274 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B ||
1275 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1276 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1278 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656)
1279 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1280 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B)
1281 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1282 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C)
1283 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1284 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1285 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1286 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 ||
1287 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B)
1288 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1289 XL_FLAG_INVERT_LED_PWR;
1290 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_10_100BT_920B)
1291 sc->xl_flags |= XL_FLAG_PHYOK;
1292 #ifndef BURN_BRIDGES
1294 * If this is a 3c905B, we have to check one extra thing.
1295 * The 905B supports power management and may be placed in
1296 * a low-power mode (D3 mode), typically by certain operating
1297 * systems which shall not be named. The PCI BIOS is supposed
1298 * to reset the NIC and bring it out of low-power mode, but
1299 * some do not. Consequently, we have to see if this chip
1300 * supports power management, and if so, make sure it's not
1301 * in low-power mode. If power management is available, the
1302 * capid byte will be 0x01.
1304 * I _think_ that what actually happens is that the chip
1305 * loses its PCI configuration during the transition from
1306 * D3 back to D0; this means that it should be possible for
1307 * us to save the PCI iobase, membase and IRQ, put the chip
1308 * back in the D0 state, then restore the PCI config ourselves.
1311 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1312 u_int32_t iobase, membase, irq;
1314 /* Save important PCI config data. */
1315 iobase = pci_read_config(dev, XL_PCI_LOIO, 4);
1316 membase = pci_read_config(dev, XL_PCI_LOMEM, 4);
1317 irq = pci_read_config(dev, XL_PCI_INTLINE, 4);
1319 /* Reset the power state. */
1320 device_printf(dev, "chip is in D%d power mode "
1321 "-- setting to D0\n", pci_get_powerstate(dev));
1323 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1325 /* Restore PCI config data. */
1326 pci_write_config(dev, XL_PCI_LOIO, iobase, 4);
1327 pci_write_config(dev, XL_PCI_LOMEM, membase, 4);
1328 pci_write_config(dev, XL_PCI_INTLINE, irq, 4);
1332 * Map control/status registers.
1334 pci_enable_busmaster(dev);
1337 res = SYS_RES_MEMORY;
1340 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1343 if (sc->xl_res != NULL) {
1344 sc->xl_flags |= XL_FLAG_USE_MMIO;
1346 device_printf(dev, "using memory mapped I/O\n");
1349 res = SYS_RES_IOPORT;
1350 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1351 if (sc->xl_res == NULL) {
1352 device_printf(dev, "couldn't map ports/memory\n");
1357 device_printf(dev, "using port I/O\n");
1360 sc->xl_btag = rman_get_bustag(sc->xl_res);
1361 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1363 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1364 rid = XL_PCI_FUNCMEM;
1365 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1368 if (sc->xl_fres == NULL) {
1369 device_printf(dev, "couldn't map funcreg memory\n");
1374 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1375 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1378 /* Allocate interrupt */
1380 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1381 RF_SHAREABLE | RF_ACTIVE);
1382 if (sc->xl_irq == NULL) {
1383 device_printf(dev, "couldn't map interrupt\n");
1388 ifp = &sc->arpcom.ac_if;
1389 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1391 /* Reset the adapter. */
1395 * Get station address from the EEPROM.
1397 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1398 device_printf(dev, "failed to read station address\n");
1403 callout_init(&sc->xl_stat_timer);
1405 error = xl_dma_alloc(dev);
1410 * Figure out the card type. 3c905B adapters have the
1411 * 'supportsNoTxLength' bit set in the capabilities
1412 * word in the EEPROM.
1413 * Note: my 3c575C cardbus card lies. It returns a value
1414 * of 0x1578 for its capabilities word, which is somewhat
1415 * nonsensical. Another way to distinguish a 3c90x chip
1416 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1417 * bit. This will only be set for 3c90x boomerage chips.
1419 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1420 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1421 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1422 sc->xl_type = XL_TYPE_905B;
1424 sc->xl_type = XL_TYPE_90X;
1426 device_printf(dev, "type %s\n",
1427 sc->xl_type == XL_TYPE_905B ? "90XB" : "90X");
1431 ifp->if_mtu = ETHERMTU;
1432 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1433 ifp->if_ioctl = xl_ioctl;
1434 ifp->if_capabilities = 0;
1435 if (sc->xl_type == XL_TYPE_905B) {
1436 ifp->if_start = xl_start_90xB;
1437 ifp->if_capabilities |= IFCAP_HWCSUM;
1439 ifp->if_start = xl_start;
1441 ifp->if_watchdog = xl_watchdog;
1442 ifp->if_init = xl_init;
1443 #ifdef DEVICE_POLLING
1444 ifp->if_poll = xl_poll;
1446 ifp->if_baudrate = 10000000;
1447 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1448 ifq_set_ready(&ifp->if_snd);
1450 * NOTE: features disabled by default. This seems to corrupt
1451 * tx packet data one out of a million packets or so and then
1452 * generates a good checksum so the receiver doesn't
1453 * know the packet is bad
1455 ifp->if_capenable = 0; /*ifp->if_capabilities;*/
1456 if (ifp->if_capenable & IFCAP_TXCSUM)
1457 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1460 * Now we have to see what sort of media we have.
1461 * This includes probing for an MII interace and a
1465 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1467 if_printf(ifp, "media options word: %x\n", sc->xl_media);
1469 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1470 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1471 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1472 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1476 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
1477 || sc->xl_media & XL_MEDIAOPT_BT4) {
1479 if_printf(ifp, "found MII/AUTO\n");
1482 error = mii_phy_probe(dev, &sc->xl_miibus,
1483 xl_ifmedia_upd, xl_ifmedia_sts);
1485 if_printf(ifp, "no PHY found!\n");
1493 * Sanity check. If the user has selected "auto" and this isn't
1494 * a 10/100 card of some kind, we need to force the transceiver
1495 * type to something sane.
1497 if (sc->xl_xcvr == XL_XCVR_AUTO)
1498 xl_choose_xcvr(sc, bootverbose);
1503 if (sc->xl_media & XL_MEDIAOPT_BT) {
1505 if_printf(ifp, "found 10baseT\n");
1506 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1507 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1508 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1509 ifmedia_add(&sc->ifmedia,
1510 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1513 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1515 * Check for a 10baseFL board in disguise.
1517 if (sc->xl_type == XL_TYPE_905B &&
1518 sc->xl_media == XL_MEDIAOPT_10FL) {
1520 if_printf(ifp, "found 10baseFL\n");
1521 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1522 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1524 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1525 ifmedia_add(&sc->ifmedia,
1526 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1529 if_printf(ifp, "found AUI\n");
1530 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1534 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1536 if_printf(ifp, "found BNC\n");
1537 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1540 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1542 if_printf(ifp, "found 100baseFX\n");
1543 ifp->if_baudrate = 100000000;
1544 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1547 /* Choose a default media. */
1548 switch(sc->xl_xcvr) {
1550 media = IFM_ETHER|IFM_10_T;
1551 xl_setmode(sc, media);
1554 if (sc->xl_type == XL_TYPE_905B &&
1555 sc->xl_media == XL_MEDIAOPT_10FL) {
1556 media = IFM_ETHER|IFM_10_FL;
1557 xl_setmode(sc, media);
1559 media = IFM_ETHER|IFM_10_5;
1560 xl_setmode(sc, media);
1564 media = IFM_ETHER|IFM_10_2;
1565 xl_setmode(sc, media);
1568 case XL_XCVR_100BTX:
1570 /* Chosen by miibus */
1572 case XL_XCVR_100BFX:
1573 media = IFM_ETHER|IFM_100_FX;
1576 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr);
1578 * This will probably be wrong, but it prevents
1579 * the ifmedia code from panicking.
1581 media = IFM_ETHER|IFM_10_T;
1585 if (sc->xl_miibus == NULL)
1586 ifmedia_set(&sc->ifmedia, media);
1590 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1592 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1596 * Call MI attach routine.
1598 ether_ifattach(ifp, eaddr);
1601 * Tell the upper layer(s) we support long frames.
1603 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1605 /* Hook interrupt last to avoid having to lock softc */
1606 error = bus_setup_intr(dev, sc->xl_irq, 0,
1607 xl_intr, sc, &sc->xl_intrhand, NULL);
1609 if_printf(ifp, "couldn't set up irq\n");
1610 ether_ifdetach(ifp);
1622 * Shutdown hardware and free up resources. This can be called any
1623 * time after the mutex has been initialized. It is called in both
1624 * the error case in attach and the normal detach case so it needs
1625 * to be careful about only freeing resources that have actually been
1629 xl_detach(device_t dev)
1631 struct xl_softc *sc;
1635 sc = device_get_softc(dev);
1636 ifp = &sc->arpcom.ac_if;
1638 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1640 res = SYS_RES_MEMORY;
1643 res = SYS_RES_IOPORT;
1648 if (device_is_attached(dev)) {
1651 ether_ifdetach(ifp);
1655 device_delete_child(dev, sc->xl_miibus);
1656 bus_generic_detach(dev);
1657 ifmedia_removeall(&sc->ifmedia);
1659 if (sc->xl_intrhand)
1660 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1665 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1666 if (sc->xl_fres != NULL)
1667 bus_release_resource(dev, SYS_RES_MEMORY,
1668 XL_PCI_FUNCMEM, sc->xl_fres);
1670 bus_release_resource(dev, res, rid, sc->xl_res);
1678 xl_dma_alloc(device_t dev)
1680 struct xl_softc *sc;
1681 struct xl_chain_data *cd;
1682 struct xl_list_data *ld;
1685 sc = device_get_softc(dev);
1690 * Now allocate a tag for the DMA descriptor lists and a chunk
1691 * of DMA-able memory based on the tag. Also obtain the DMA
1692 * addresses of the RX and TX ring, which we'll need later.
1693 * All of our lists are allocated as a contiguous block
1696 error = bus_dma_tag_create(NULL, 8, 0,
1697 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1699 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ,
1702 device_printf(dev, "failed to allocate rx dma tag\n");
1706 error = bus_dmamem_alloc(ld->xl_rx_tag, (void **)&ld->xl_rx_list,
1707 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1710 device_printf(dev, "no memory for rx list buffers!\n");
1711 bus_dma_tag_destroy(ld->xl_rx_tag);
1712 ld->xl_rx_tag = NULL;
1716 error = bus_dmamap_load(ld->xl_rx_tag, ld->xl_rx_dmamap,
1717 ld->xl_rx_list, XL_RX_LIST_SZ,
1718 xl_dma_map_addr, &ld->xl_rx_dmaaddr,
1721 device_printf(dev, "cannot get dma address of the rx ring!\n");
1722 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list,
1724 bus_dma_tag_destroy(ld->xl_rx_tag);
1725 ld->xl_rx_tag = NULL;
1729 error = bus_dma_tag_create(NULL, 8, 0,
1730 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1732 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ,
1735 device_printf(dev, "failed to allocate tx dma tag\n");
1739 error = bus_dmamem_alloc(ld->xl_tx_tag, (void **)&ld->xl_tx_list,
1740 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1743 device_printf(dev, "no memory for list buffers!\n");
1744 bus_dma_tag_destroy(ld->xl_tx_tag);
1745 ld->xl_tx_tag = NULL;
1749 error = bus_dmamap_load(ld->xl_tx_tag, ld->xl_tx_dmamap,
1750 ld->xl_tx_list, XL_TX_LIST_SZ,
1751 xl_dma_map_addr, &ld->xl_tx_dmaaddr,
1754 device_printf(dev, "cannot get dma address of the tx ring!\n");
1755 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list,
1757 bus_dma_tag_destroy(ld->xl_tx_tag);
1758 ld->xl_tx_tag = NULL;
1763 * Allocate a DMA tag for the mapping of mbufs.
1765 error = bus_dma_tag_create(NULL, 1, 0,
1766 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1768 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS,
1769 MCLBYTES, 0, &sc->xl_mtag);
1771 device_printf(dev, "failed to allocate mbuf dma tag\n");
1776 * Allocate a spare DMA map for the RX ring.
1778 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1780 device_printf(dev, "failed to create mbuf dma map\n");
1781 bus_dma_tag_destroy(sc->xl_mtag);
1786 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1787 error = bus_dmamap_create(sc->xl_mtag, 0,
1788 &cd->xl_rx_chain[i].xl_map);
1790 device_printf(dev, "failed to create %dth "
1791 "rx descriptor dma map!\n", i);
1794 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1797 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1798 error = bus_dmamap_create(sc->xl_mtag, 0,
1799 &cd->xl_tx_chain[i].xl_map);
1801 device_printf(dev, "failed to create %dth "
1802 "tx descriptor dma map!\n", i);
1805 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1811 xl_dma_free(device_t dev)
1813 struct xl_softc *sc;
1814 struct xl_chain_data *cd;
1815 struct xl_list_data *ld;
1818 sc = device_get_softc(dev);
1822 for (i = 0; i < XL_RX_LIST_CNT; ++i) {
1823 if (cd->xl_rx_chain[i].xl_ptr != NULL) {
1824 if (cd->xl_rx_chain[i].xl_mbuf != NULL) {
1825 bus_dmamap_unload(sc->xl_mtag,
1826 cd->xl_rx_chain[i].xl_map);
1827 m_free(cd->xl_rx_chain[i].xl_mbuf);
1829 bus_dmamap_destroy(sc->xl_mtag,
1830 cd->xl_rx_chain[i].xl_map);
1834 for (i = 0; i < XL_TX_LIST_CNT; ++i) {
1835 if (cd->xl_tx_chain[i].xl_ptr != NULL) {
1836 if (cd->xl_tx_chain[i].xl_mbuf != NULL) {
1837 bus_dmamap_unload(sc->xl_mtag,
1838 cd->xl_tx_chain[i].xl_map);
1839 m_free(cd->xl_tx_chain[i].xl_mbuf);
1841 bus_dmamap_destroy(sc->xl_mtag,
1842 cd->xl_tx_chain[i].xl_map);
1846 if (ld->xl_rx_tag) {
1847 bus_dmamap_unload(ld->xl_rx_tag, ld->xl_rx_dmamap);
1848 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list,
1850 bus_dma_tag_destroy(ld->xl_rx_tag);
1853 if (ld->xl_tx_tag) {
1854 bus_dmamap_unload(ld->xl_tx_tag, ld->xl_tx_dmamap);
1855 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list,
1857 bus_dma_tag_destroy(ld->xl_tx_tag);
1861 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1862 bus_dma_tag_destroy(sc->xl_mtag);
1867 * Initialize the transmit descriptors.
1870 xl_list_tx_init(struct xl_softc *sc)
1872 struct xl_chain_data *cd;
1873 struct xl_list_data *ld;
1878 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1879 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1880 i * sizeof(struct xl_list);
1881 if (i == (XL_TX_LIST_CNT - 1))
1882 cd->xl_tx_chain[i].xl_next = NULL;
1884 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1887 cd->xl_tx_free = &cd->xl_tx_chain[0];
1888 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1890 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1894 * Initialize the transmit descriptors.
1897 xl_list_tx_init_90xB(struct xl_softc *sc)
1899 struct xl_chain_data *cd;
1900 struct xl_list_data *ld;
1905 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1906 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1907 i * sizeof(struct xl_list);
1908 if (i == (XL_TX_LIST_CNT - 1))
1909 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1911 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1913 cd->xl_tx_chain[i].xl_prev =
1914 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1916 cd->xl_tx_chain[i].xl_prev =
1917 &cd->xl_tx_chain[i - 1];
1921 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1927 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1931 * Initialize the RX descriptors and allocate mbufs for them. Note that
1932 * we arrange the descriptors in a closed ring, so that the last descriptor
1933 * points back to the first.
1936 xl_list_rx_init(struct xl_softc *sc)
1938 struct xl_chain_data *cd;
1939 struct xl_list_data *ld;
1946 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1947 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1950 if (i == (XL_RX_LIST_CNT - 1))
1954 nextptr = ld->xl_rx_dmaaddr +
1955 next * sizeof(struct xl_list_onefrag);
1956 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1957 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1960 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1961 cd->xl_rx_head = &cd->xl_rx_chain[0];
1967 * Initialize an RX descriptor and attach an MBUF cluster.
1968 * If we fail to do so, we need to leave the old mbuf and
1969 * the old DMA map untouched so that it can be reused.
1972 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1979 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1983 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1985 /* Force longword alignment for packet payload. */
1986 m_adj(m_new, ETHER_ALIGN);
1988 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new,
1989 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT);
1992 if_printf(&sc->arpcom.ac_if, "can't map mbuf (error %d)\n",
1997 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1999 c->xl_map = sc->xl_tmpmap;
2000 sc->xl_tmpmap = map;
2002 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
2003 c->xl_ptr->xl_status = 0;
2004 c->xl_ptr->xl_frag.xl_addr = htole32(baddr);
2005 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
2010 xl_rx_resync(struct xl_softc *sc)
2012 struct xl_chain_onefrag *pos;
2015 pos = sc->xl_cdata.xl_rx_head;
2017 for (i = 0; i < XL_RX_LIST_CNT; i++) {
2018 if (pos->xl_ptr->xl_status)
2023 if (i == XL_RX_LIST_CNT)
2026 sc->xl_cdata.xl_rx_head = pos;
2032 * A frame has been uploaded: pass the resulting mbuf chain up to
2033 * the higher level protocols.
2036 xl_rxeof(struct xl_softc *sc, int count)
2040 struct xl_chain_onefrag *cur_rx;
2044 ifp = &sc->arpcom.ac_if;
2048 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
2049 BUS_DMASYNC_POSTREAD);
2050 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
2051 #ifdef DEVICE_POLLING
2052 if (count >= 0 && count-- == 0)
2055 cur_rx = sc->xl_cdata.xl_rx_head;
2056 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
2057 total_len = rxstat & XL_RXSTAT_LENMASK;
2060 * Since we have told the chip to allow large frames,
2061 * we need to trap giant frame errors in software. We allow
2062 * a little more than the normal frame size to account for
2063 * frames with VLAN tags.
2065 if (total_len > XL_MAX_FRAMELEN)
2066 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
2069 * If an error occurs, update stats, clear the
2070 * status word and leave the mbuf cluster in place:
2071 * it should simply get re-used next time this descriptor
2072 * comes up in the ring.
2074 if (rxstat & XL_RXSTAT_UP_ERROR) {
2076 cur_rx->xl_ptr->xl_status = 0;
2077 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2078 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2083 * If the error bit was not set, the upload complete
2084 * bit should be set which means we have a valid packet.
2085 * If not, something truly strange has happened.
2087 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
2089 "bad receive status -- packet dropped\n");
2091 cur_rx->xl_ptr->xl_status = 0;
2092 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2093 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2097 /* No errors; receive the packet. */
2098 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
2099 BUS_DMASYNC_POSTREAD);
2100 m = cur_rx->xl_mbuf;
2103 * Try to conjure up a new mbuf cluster. If that
2104 * fails, it means we have an out of memory condition and
2105 * should leave the buffer in place and continue. This will
2106 * result in a lost packet, but there's little else we
2107 * can do in this situation.
2109 if (xl_newbuf(sc, cur_rx)) {
2111 cur_rx->xl_ptr->xl_status = 0;
2112 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2113 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2116 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2117 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2120 m->m_pkthdr.rcvif = ifp;
2121 m->m_pkthdr.len = m->m_len = total_len;
2123 if (ifp->if_capenable & IFCAP_RXCSUM) {
2124 /* Do IP checksum checking. */
2125 if (rxstat & XL_RXSTAT_IPCKOK)
2126 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2127 if (!(rxstat & XL_RXSTAT_IPCKERR))
2128 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2129 if ((rxstat & XL_RXSTAT_TCPCOK &&
2130 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
2131 (rxstat & XL_RXSTAT_UDPCKOK &&
2132 !(rxstat & XL_RXSTAT_UDPCKERR))) {
2133 m->m_pkthdr.csum_flags |=
2134 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2135 m->m_pkthdr.csum_data = 0xffff;
2139 (*ifp->if_input)(ifp, m);
2142 if (sc->xl_type != XL_TYPE_905B) {
2144 * Handle the 'end of channel' condition. When the upload
2145 * engine hits the end of the RX ring, it will stall. This
2146 * is our cue to flush the RX ring, reload the uplist pointer
2147 * register and unstall the engine.
2148 * XXX This is actually a little goofy. With the ThunderLAN
2149 * chip, you get an interrupt when the receiver hits the end
2150 * of the receive ring, which tells you exactly when you
2151 * you need to reload the ring pointer. Here we have to
2152 * fake it. I'm mad at myself for not being clever enough
2153 * to avoid the use of a goto here.
2155 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2156 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2157 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2159 CSR_WRITE_4(sc, XL_UPLIST_PTR,
2160 sc->xl_ldata.xl_rx_dmaaddr);
2161 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2162 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2169 * A frame was downloaded to the chip. It's safe for us to clean up
2173 xl_txeof(struct xl_softc *sc)
2175 struct xl_chain *cur_tx;
2178 ifp = &sc->arpcom.ac_if;
2180 /* Clear the timeout timer. */
2184 * Go through our tx list and free mbufs for those
2185 * frames that have been uploaded. Note: the 3c905B
2186 * sets a special bit in the status word to let us
2187 * know that a frame has been downloaded, but the
2188 * original 3c900/3c905 adapters don't do that.
2189 * Consequently, we have to use a different test if
2190 * xl_type != XL_TYPE_905B.
2192 while(sc->xl_cdata.xl_tx_head != NULL) {
2193 cur_tx = sc->xl_cdata.xl_tx_head;
2195 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2198 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2199 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2200 BUS_DMASYNC_POSTWRITE);
2201 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2202 m_freem(cur_tx->xl_mbuf);
2203 cur_tx->xl_mbuf = NULL;
2206 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2207 sc->xl_cdata.xl_tx_free = cur_tx;
2210 if (sc->xl_cdata.xl_tx_head == NULL) {
2211 ifp->if_flags &= ~IFF_OACTIVE;
2212 sc->xl_cdata.xl_tx_tail = NULL;
2214 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2215 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2216 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2217 sc->xl_cdata.xl_tx_head->xl_phys);
2218 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2226 xl_txeof_90xB(struct xl_softc *sc)
2228 struct xl_chain *cur_tx = NULL;
2232 ifp = &sc->arpcom.ac_if;
2234 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2235 BUS_DMASYNC_POSTREAD);
2236 idx = sc->xl_cdata.xl_tx_cons;
2237 while(idx != sc->xl_cdata.xl_tx_prod) {
2239 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2241 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2242 XL_TXSTAT_DL_COMPLETE))
2245 if (cur_tx->xl_mbuf != NULL) {
2246 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2247 BUS_DMASYNC_POSTWRITE);
2248 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2249 m_freem(cur_tx->xl_mbuf);
2250 cur_tx->xl_mbuf = NULL;
2255 sc->xl_cdata.xl_tx_cnt--;
2256 XL_INC(idx, XL_TX_LIST_CNT);
2260 sc->xl_cdata.xl_tx_cons = idx;
2263 ifp->if_flags &= ~IFF_OACTIVE;
2269 * TX 'end of channel' interrupt handler. Actually, we should
2270 * only get a 'TX complete' interrupt if there's a transmit error,
2271 * so this is really TX error handler.
2274 xl_txeoc(struct xl_softc *sc)
2276 struct ifnet *ifp = &sc->arpcom.ac_if;
2279 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2280 if (txstat & XL_TXSTATUS_UNDERRUN ||
2281 txstat & XL_TXSTATUS_JABBER ||
2282 txstat & XL_TXSTATUS_RECLAIM) {
2283 if_printf(ifp, "transmission error: %x\n", txstat);
2284 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2286 if (sc->xl_type == XL_TYPE_905B) {
2287 if (sc->xl_cdata.xl_tx_cnt) {
2290 i = sc->xl_cdata.xl_tx_cons;
2291 c = &sc->xl_cdata.xl_tx_chain[i];
2292 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2294 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2297 if (sc->xl_cdata.xl_tx_head != NULL)
2298 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2299 sc->xl_cdata.xl_tx_head->xl_phys);
2302 * Remember to set this for the
2303 * first generation 3c90X chips.
2305 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2306 if (txstat & XL_TXSTATUS_UNDERRUN &&
2307 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2308 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2309 if_printf(ifp, "tx underrun, increasing tx start"
2310 " threshold to %d bytes\n",
2313 CSR_WRITE_2(sc, XL_COMMAND,
2314 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2315 if (sc->xl_type == XL_TYPE_905B) {
2316 CSR_WRITE_2(sc, XL_COMMAND,
2317 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2319 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2320 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2322 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2323 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2326 * Write an arbitrary byte to the TX_STATUS register
2327 * to clear this interrupt/error and advance to the next.
2329 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2335 #ifdef DEVICE_POLLING
2338 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2340 struct xl_softc *sc = ifp->if_softc;
2344 xl_enable_intrs(sc, 0);
2346 case POLL_DEREGISTER:
2347 xl_enable_intrs(sc, XL_INTRS);
2350 case POLL_AND_CHECK_STATUS:
2351 xl_rxeof(sc, count);
2352 if (sc->xl_type == XL_TYPE_905B)
2357 if (!ifq_is_empty(&ifp->if_snd)) {
2358 if (sc->xl_type == XL_TYPE_905B)
2361 xl_start_body(ifp, 0);
2364 if (cmd == POLL_AND_CHECK_STATUS) {
2367 /* XXX copy & pasted from xl_intr() */
2368 status = CSR_READ_2(sc, XL_STATUS);
2369 if ((status & XL_INTRS) && status != 0xFFFF) {
2370 CSR_WRITE_2(sc, XL_COMMAND,
2371 XL_CMD_INTR_ACK | (status & XL_INTRS));
2373 if (status & XL_STAT_TX_COMPLETE) {
2378 if (status & XL_STAT_ADFAIL) {
2383 if (status & XL_STAT_STATSOFLOW) {
2384 sc->xl_stats_no_timeout = 1;
2385 xl_stats_update(sc);
2386 sc->xl_stats_no_timeout = 0;
2394 #endif /* DEVICE_POLLING */
2399 struct xl_softc *sc;
2404 ifp = &sc->arpcom.ac_if;
2406 while(((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS) &&
2409 CSR_WRITE_2(sc, XL_COMMAND,
2410 XL_CMD_INTR_ACK|(status & XL_INTRS));
2412 if (status & XL_STAT_UP_COMPLETE) {
2415 curpkts = ifp->if_ipackets;
2417 if (curpkts == ifp->if_ipackets) {
2418 while (xl_rx_resync(sc))
2423 if (status & XL_STAT_DOWN_COMPLETE) {
2424 if (sc->xl_type == XL_TYPE_905B)
2430 if (status & XL_STAT_TX_COMPLETE) {
2435 if (status & XL_STAT_ADFAIL) {
2440 if (status & XL_STAT_STATSOFLOW) {
2441 sc->xl_stats_no_timeout = 1;
2442 xl_stats_update(sc);
2443 sc->xl_stats_no_timeout = 0;
2447 if (!ifq_is_empty(&ifp->if_snd))
2448 (*ifp->if_start)(ifp);
2454 xl_stats_update(void *xsc)
2456 struct xl_softc *sc;
2458 struct xl_stats xl_stats;
2461 struct mii_data *mii = NULL;
2463 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2466 ifp = &sc->arpcom.ac_if;
2467 if (sc->xl_miibus != NULL)
2468 mii = device_get_softc(sc->xl_miibus);
2470 p = (u_int8_t *)&xl_stats;
2472 /* Read all the stats registers. */
2475 for (i = 0; i < 16; i++)
2476 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2478 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2480 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2481 xl_stats.xl_tx_single_collision +
2482 xl_stats.xl_tx_late_collision;
2485 * Boomerang and cyclone chips have an extra stats counter
2486 * in window 4 (BadSSD). We have to read this too in order
2487 * to clear out all the stats registers and avoid a statsoflow
2491 CSR_READ_1(sc, XL_W4_BADSSD);
2493 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2498 if (!sc->xl_stats_no_timeout)
2499 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
2505 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2506 * pointers to the fragment pointers.
2509 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head)
2515 ifp = &sc->arpcom.ac_if;
2518 * Start packing the mbufs in this chain into
2519 * the fragment pointers. Stop when we run out
2520 * of fragments or hit the end of the mbuf chain.
2522 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head,
2523 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2525 if (error && error != EFBIG) {
2527 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2532 * Handle special case: we used up all 63 fragments,
2533 * but we have more mbufs left in the chain. Copy the
2534 * data into an mbuf cluster. Note that we don't
2535 * bother clearing the values in the other fragment
2536 * pointers/counters; it wouldn't gain us anything,
2537 * and would waste cycles.
2542 m_new = m_defrag(m_head, MB_DONTWAIT);
2543 if (m_new == NULL) {
2550 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map,
2551 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2554 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2559 if (sc->xl_type == XL_TYPE_905B) {
2560 status = XL_TXSTAT_RND_DEFEAT;
2562 if (m_head->m_pkthdr.csum_flags) {
2563 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2564 status |= XL_TXSTAT_IPCKSUM;
2565 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2566 status |= XL_TXSTAT_TCPCKSUM;
2567 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2568 status |= XL_TXSTAT_UDPCKSUM;
2570 c->xl_ptr->xl_status = htole32(status);
2573 c->xl_mbuf = m_head;
2574 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2579 xl_start(struct ifnet *ifp)
2581 xl_start_body(ifp, 1);
2585 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2586 * to the mbuf data regions directly in the transmit lists. We also save a
2587 * copy of the pointers since the transmit list fragment pointers are
2588 * physical addresses.
2591 xl_start_body(struct ifnet *ifp, int proc_rx)
2593 struct xl_softc *sc;
2594 struct mbuf *m_head = NULL;
2595 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2596 struct xl_chain *prev_tx;
2602 * Check for an available queue slot. If there are none,
2605 if (sc->xl_cdata.xl_tx_free == NULL) {
2608 if (sc->xl_cdata.xl_tx_free == NULL) {
2609 ifp->if_flags |= IFF_OACTIVE;
2614 start_tx = sc->xl_cdata.xl_tx_free;
2616 while(sc->xl_cdata.xl_tx_free != NULL) {
2617 m_head = ifq_dequeue(&ifp->if_snd);
2621 /* Pick a descriptor off the free list. */
2623 cur_tx = sc->xl_cdata.xl_tx_free;
2625 /* Pack the data into the descriptor. */
2626 error = xl_encap(sc, cur_tx, m_head);
2632 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2633 cur_tx->xl_next = NULL;
2635 /* Chain it together. */
2637 prev->xl_next = cur_tx;
2638 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2642 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2646 * If there are no packets queued, bail.
2652 * Place the request for the upload interrupt
2653 * in the last descriptor in the chain. This way, if
2654 * we're chaining several packets at once, we'll only
2655 * get an interupt once for the whole chain rather than
2656 * once for each packet.
2658 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2662 * Queue the packets. If the TX channel is clear, update
2663 * the downlist pointer register.
2665 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2668 if (sc->xl_cdata.xl_tx_head != NULL) {
2669 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2670 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2671 htole32(start_tx->xl_phys);
2672 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2673 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2674 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2675 sc->xl_cdata.xl_tx_tail = cur_tx;
2677 sc->xl_cdata.xl_tx_head = start_tx;
2678 sc->xl_cdata.xl_tx_tail = cur_tx;
2680 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2681 BUS_DMASYNC_PREWRITE);
2683 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2684 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2686 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2691 * Set a timeout in case the chip goes out to lunch.
2697 * XXX Under certain conditions, usually on slower machines
2698 * where interrupts may be dropped, it's possible for the
2699 * adapter to chew up all the buffers in the receive ring
2700 * and stall, without us being able to do anything about it.
2701 * To guard against this, we need to make a pass over the
2702 * RX queue to make sure there aren't any packets pending.
2703 * Doing it here means we can flush the receive ring at the
2704 * same time the chip is DMAing the transmit descriptors we
2707 * 3Com goes to some lengths to emphasize the Parallel
2708 * Tasking (tm) nature of their chips in all their marketing
2709 * literature; we may as well take advantage of it. :)
2716 xl_start_90xB(struct ifnet *ifp)
2718 struct xl_softc *sc;
2719 struct mbuf *m_head = NULL;
2720 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2721 struct xl_chain *prev_tx;
2726 if (ifp->if_flags & IFF_OACTIVE)
2729 idx = sc->xl_cdata.xl_tx_prod;
2730 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2732 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2734 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2735 ifp->if_flags |= IFF_OACTIVE;
2739 m_head = ifq_dequeue(&ifp->if_snd);
2744 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2746 /* Pack the data into the descriptor. */
2747 error = xl_encap(sc, cur_tx, m_head);
2753 /* Chain it together. */
2755 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2758 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2760 XL_INC(idx, XL_TX_LIST_CNT);
2761 sc->xl_cdata.xl_tx_cnt++;
2765 * If there are no packets queued, bail.
2771 * Place the request for the upload interrupt
2772 * in the last descriptor in the chain. This way, if
2773 * we're chaining several packets at once, we'll only
2774 * get an interupt once for the whole chain rather than
2775 * once for each packet.
2777 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2780 /* Start transmission */
2781 sc->xl_cdata.xl_tx_prod = idx;
2782 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2784 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2785 BUS_DMASYNC_PREWRITE);
2788 * Set a timeout in case the chip goes out to lunch.
2796 struct xl_softc *sc = xsc;
2797 struct ifnet *ifp = &sc->arpcom.ac_if;
2799 u_int16_t rxfilt = 0;
2800 struct mii_data *mii = NULL;
2805 * Cancel pending I/O and free all RX/TX buffers.
2809 if (sc->xl_miibus == NULL) {
2810 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2813 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2817 if (sc->xl_miibus != NULL)
2818 mii = device_get_softc(sc->xl_miibus);
2820 /* Init our MAC address */
2822 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2823 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2824 sc->arpcom.ac_enaddr[i]);
2827 /* Clear the station mask. */
2828 for (i = 0; i < 3; i++)
2829 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2831 /* Reset TX and RX. */
2832 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2834 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2837 /* Init circular RX list. */
2838 error = xl_list_rx_init(sc);
2840 if_printf(ifp, "initialization of the rx ring failed (%d)\n",
2847 /* Init TX descriptors. */
2848 if (sc->xl_type == XL_TYPE_905B)
2849 xl_list_tx_init_90xB(sc);
2851 xl_list_tx_init(sc);
2854 * Set the TX freethresh value.
2855 * Note that this has no effect on 3c905B "cyclone"
2856 * cards but is required for 3c900/3c905 "boomerang"
2857 * cards in order to enable the download engine.
2859 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2861 /* Set the TX start threshold for best performance. */
2862 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2863 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2866 * If this is a 3c905B, also set the tx reclaim threshold.
2867 * This helps cut down on the number of tx reclaim errors
2868 * that could happen on a busy network. The chip multiplies
2869 * the register value by 16 to obtain the actual threshold
2870 * in bytes, so we divide by 16 when setting the value here.
2871 * The existing threshold value can be examined by reading
2872 * the register at offset 9 in window 5.
2874 if (sc->xl_type == XL_TYPE_905B) {
2875 CSR_WRITE_2(sc, XL_COMMAND,
2876 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2879 /* Set RX filter bits. */
2881 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2883 /* Set the individual bit to receive frames for this host only. */
2884 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2886 /* If we want promiscuous mode, set the allframes bit. */
2887 if (ifp->if_flags & IFF_PROMISC) {
2888 rxfilt |= XL_RXFILTER_ALLFRAMES;
2889 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2891 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2892 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2896 * Set capture broadcast bit to capture broadcast frames.
2898 if (ifp->if_flags & IFF_BROADCAST) {
2899 rxfilt |= XL_RXFILTER_BROADCAST;
2900 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2902 rxfilt &= ~XL_RXFILTER_BROADCAST;
2903 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2907 * Program the multicast filter, if necessary.
2909 if (sc->xl_type == XL_TYPE_905B)
2910 xl_setmulti_hash(sc);
2914 if (sc->xl_type == XL_TYPE_905B) {
2915 /* Set UP polling interval */
2916 CSR_WRITE_1(sc, XL_UP_POLL, 64);
2920 * Load the address of the RX list. We have to
2921 * stall the upload engine before we can manipulate
2922 * the uplist pointer register, then unstall it when
2923 * we're finished. We also have to wait for the
2924 * stall command to complete before proceeding.
2925 * Note that we have to do this after any RX resets
2926 * have completed since the uplist register is cleared
2929 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2931 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2932 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2935 if (sc->xl_type == XL_TYPE_905B) {
2936 /* Set DN polling interval */
2937 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2939 /* Load the address of the TX list */
2940 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2942 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2943 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2944 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2949 * If the coax transceiver is on, make sure to enable
2950 * the DC-DC converter.
2953 if (sc->xl_xcvr == XL_XCVR_COAX)
2954 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2956 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2959 * increase packet size to allow reception of 802.1q or ISL packets.
2960 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2961 * control register. For 3c90xB/C chips, use the RX packet size
2965 if (sc->xl_type == XL_TYPE_905B) {
2966 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2969 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2970 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2971 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2974 /* Clear out the stats counters. */
2975 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2976 sc->xl_stats_no_timeout = 1;
2977 xl_stats_update(sc);
2978 sc->xl_stats_no_timeout = 0;
2980 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2981 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2984 * Enable interrupts.
2986 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB | XL_INTRS);
2987 #ifdef DEVICE_POLLING
2988 /* Do not enable interrupt if polling(4) is enabled */
2989 if ((ifp->if_flags & IFF_POLLING) != 0)
2990 xl_enable_intrs(sc, 0);
2993 xl_enable_intrs(sc, XL_INTRS);
2995 /* Set the RX early threshold */
2996 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2997 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2999 /* Enable receiver and transmitter. */
3000 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
3002 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
3008 /* Select window 7 for normal operations. */
3011 ifp->if_flags |= IFF_RUNNING;
3012 ifp->if_flags &= ~IFF_OACTIVE;
3014 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
3020 * Set media options.
3023 xl_ifmedia_upd(struct ifnet *ifp)
3025 struct xl_softc *sc;
3026 struct ifmedia *ifm = NULL;
3027 struct mii_data *mii = NULL;
3030 if (sc->xl_miibus != NULL)
3031 mii = device_get_softc(sc->xl_miibus);
3035 ifm = &mii->mii_media;
3037 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3042 xl_setmode(sc, ifm->ifm_media);
3049 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
3050 || sc->xl_media & XL_MEDIAOPT_BT4) {
3053 xl_setmode(sc, ifm->ifm_media);
3060 * Report current media status.
3063 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3065 struct xl_softc *sc;
3067 struct mii_data *mii = NULL;
3070 if (sc->xl_miibus != NULL)
3071 mii = device_get_softc(sc->xl_miibus);
3074 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
3075 icfg >>= XL_ICFG_CONNECTOR_BITS;
3077 ifmr->ifm_active = IFM_ETHER;
3081 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
3082 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3083 ifmr->ifm_active |= IFM_FDX;
3085 ifmr->ifm_active |= IFM_HDX;
3088 if (sc->xl_type == XL_TYPE_905B &&
3089 sc->xl_media == XL_MEDIAOPT_10FL) {
3090 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3091 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3092 ifmr->ifm_active |= IFM_FDX;
3094 ifmr->ifm_active |= IFM_HDX;
3096 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3099 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3102 * XXX MII and BTX/AUTO should be separate cases.
3105 case XL_XCVR_100BTX:
3110 ifmr->ifm_active = mii->mii_media_active;
3111 ifmr->ifm_status = mii->mii_media_status;
3114 case XL_XCVR_100BFX:
3115 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3118 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
3126 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3128 struct xl_softc *sc = ifp->if_softc;
3129 struct ifreq *ifr = (struct ifreq *) data;
3131 struct mii_data *mii = NULL;
3139 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3140 if (ifp->if_flags & IFF_UP) {
3141 if (ifp->if_flags & IFF_RUNNING &&
3142 ifp->if_flags & IFF_PROMISC &&
3143 !(sc->xl_if_flags & IFF_PROMISC)) {
3144 rxfilt |= XL_RXFILTER_ALLFRAMES;
3145 CSR_WRITE_2(sc, XL_COMMAND,
3146 XL_CMD_RX_SET_FILT|rxfilt);
3148 } else if (ifp->if_flags & IFF_RUNNING &&
3149 !(ifp->if_flags & IFF_PROMISC) &&
3150 sc->xl_if_flags & IFF_PROMISC) {
3151 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3152 CSR_WRITE_2(sc, XL_COMMAND,
3153 XL_CMD_RX_SET_FILT|rxfilt);
3158 if (ifp->if_flags & IFF_RUNNING)
3161 sc->xl_if_flags = ifp->if_flags;
3166 if (sc->xl_type == XL_TYPE_905B)
3167 xl_setmulti_hash(sc);
3174 if (sc->xl_miibus != NULL)
3175 mii = device_get_softc(sc->xl_miibus);
3177 error = ifmedia_ioctl(ifp, ifr,
3178 &sc->ifmedia, command);
3180 error = ifmedia_ioctl(ifp, ifr,
3181 &mii->mii_media, command);
3184 ifp->if_capenable = ifr->ifr_reqcap;
3185 if (ifp->if_capenable & IFCAP_TXCSUM)
3186 ifp->if_hwassist = XL905B_CSUM_FEATURES;
3188 ifp->if_hwassist = 0;
3191 error = ether_ioctl(ifp, command, data);
3201 xl_watchdog(struct ifnet *ifp)
3203 struct xl_softc *sc;
3204 u_int16_t status = 0;
3210 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3211 if_printf(ifp, "watchdog timeout\n");
3213 if (status & XL_MEDIASTAT_CARRIER)
3214 if_printf(ifp, "no carrier - transceiver cable problem?\n");
3221 if (!ifq_is_empty(&ifp->if_snd))
3222 (*ifp->if_start)(ifp);
3226 * Stop the adapter and free any mbufs allocated to the
3230 xl_stop(struct xl_softc *sc)
3235 ifp = &sc->arpcom.ac_if;
3238 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3239 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3240 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3241 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3243 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3244 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3248 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3250 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3254 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3255 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3256 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3257 if (sc->xl_flags & XL_FLAG_FUNCREG)
3258 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3260 /* Stop the stats updater. */
3261 callout_stop(&sc->xl_stat_timer);
3264 * Free data in the RX lists.
3266 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3267 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3268 bus_dmamap_unload(sc->xl_mtag,
3269 sc->xl_cdata.xl_rx_chain[i].xl_map);
3270 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3271 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3274 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3277 * Free the TX list buffers.
3279 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3280 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3281 bus_dmamap_unload(sc->xl_mtag,
3282 sc->xl_cdata.xl_tx_chain[i].xl_map);
3283 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3284 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3287 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3289 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3293 * Stop all chip I/O so that the kernel's probe routines don't
3294 * get confused by errant DMAs when rebooting.
3297 xl_shutdown(device_t dev)
3299 struct xl_softc *sc;
3301 sc = device_get_softc(dev);
3310 xl_suspend(device_t dev)
3312 struct xl_softc *sc = device_get_softc(dev);
3324 xl_resume(device_t dev)
3326 struct xl_softc *sc;
3329 sc = device_get_softc(dev);
3330 ifp = &sc->arpcom.ac_if;
3335 if (ifp->if_flags & IFF_UP)