2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
64 #include <machine/pmap_inval.h>
66 #include <machine/md_var.h> /* setidt() */
67 #include <machine_base/icu/icu.h> /* IPIs */
68 #include <machine_base/isa/intr_machdep.h> /* IPIs */
70 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
72 #define WARMBOOT_TARGET 0
73 #define WARMBOOT_OFF (KERNBASE + 0x0467)
74 #define WARMBOOT_SEG (KERNBASE + 0x0469)
76 #define BIOS_BASE (0xf0000)
77 #define BIOS_SIZE (0x10000)
78 #define BIOS_COUNT (BIOS_SIZE/4)
80 #define CMOS_REG (0x70)
81 #define CMOS_DATA (0x71)
82 #define BIOS_RESET (0x0f)
83 #define BIOS_WARM (0x0a)
85 #define PROCENTRY_FLAG_EN 0x01
86 #define PROCENTRY_FLAG_BP 0x02
87 #define IOAPICENTRY_FLAG_EN 0x01
90 /* MP Floating Pointer Structure */
91 typedef struct MPFPS {
104 /* MP Configuration Table Header */
105 typedef struct MPCTH {
107 u_short base_table_length;
111 u_char product_id[12];
112 u_int32_t oem_table_pointer;
113 u_short oem_table_size;
115 u_int32_t apic_address;
116 u_short extended_table_length;
117 u_char extended_table_checksum;
122 typedef struct PROCENTRY {
127 u_int32_t cpu_signature;
128 u_int32_t feature_flags;
133 typedef struct BUSENTRY {
139 typedef struct IOAPICENTRY {
144 u_int32_t apic_address;
145 } *io_apic_entry_ptr;
147 typedef struct INTENTRY {
157 /* descriptions of MP basetable entries */
158 typedef struct BASETABLE_ENTRY {
167 vm_size_t mp_cth_mapsz;
170 typedef int (*mptable_iter_func)(void *, const void *, int);
173 * this code MUST be enabled here and in mpboot.s.
174 * it follows the very early stages of AP boot by placing values in CMOS ram.
175 * it NORMALLY will never be needed and thus the primitive method for enabling.
178 #if defined(CHECK_POINTS)
179 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
180 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
182 #define CHECK_INIT(D); \
183 CHECK_WRITE(0x34, (D)); \
184 CHECK_WRITE(0x35, (D)); \
185 CHECK_WRITE(0x36, (D)); \
186 CHECK_WRITE(0x37, (D)); \
187 CHECK_WRITE(0x38, (D)); \
188 CHECK_WRITE(0x39, (D));
190 #define CHECK_PRINT(S); \
191 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
200 #else /* CHECK_POINTS */
202 #define CHECK_INIT(D)
203 #define CHECK_PRINT(S)
205 #endif /* CHECK_POINTS */
208 * Values to send to the POST hardware.
210 #define MP_BOOTADDRESS_POST 0x10
211 #define MP_PROBE_POST 0x11
212 #define MPTABLE_PASS1_POST 0x12
214 #define MP_START_POST 0x13
215 #define MP_ENABLE_POST 0x14
216 #define MPTABLE_PASS2_POST 0x15
218 #define START_ALL_APS_POST 0x16
219 #define INSTALL_AP_TRAMP_POST 0x17
220 #define START_AP_POST 0x18
222 #define MP_ANNOUNCE_POST 0x19
224 static int need_hyperthreading_fixup;
225 static u_int logical_cpus;
226 u_int logical_cpus_mask;
228 static int madt_probe_test;
229 TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
231 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
232 int current_postcode;
234 /** XXX FIXME: what system files declare these??? */
235 extern struct region_descriptor r_gdt, r_idt;
237 int mp_naps; /* # of Applications processors */
239 static int mp_nbusses; /* # of busses */
240 int mp_napics; /* # of IO APICs */
242 vm_offset_t cpu_apic_address;
244 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
245 u_int32_t *io_apic_versions;
249 u_int32_t cpu_apic_versions[MAXCPU];
251 extern int64_t tsc_offsets[];
253 extern u_long ebda_addr;
256 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
260 * APIC ID logical/physical mapping structures.
261 * We oversize these to simplify boot-time config.
263 int cpu_num_to_apic_id[NAPICID];
265 int io_num_to_apic_id[NAPICID];
267 int apic_id_to_logical[NAPICID];
269 /* AP uses this during bootstrap. Do not staticize. */
274 * SMP page table page. Setup by locore to point to a page table
275 * page from which we allocate per-cpu privatespace areas io_apics,
279 #define IO_MAPPING_START_INDEX \
280 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
282 extern pt_entry_t *SMPpt;
284 struct pcb stoppcbs[MAXCPU];
286 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
288 static basetable_entry basetable_entry_types[] =
290 {0, 20, "Processor"},
298 * Local data and functions.
301 static u_int boot_address;
302 static u_int base_memory;
303 static int mp_finish;
305 static void mp_enable(u_int boot_addr);
307 static int mptable_iterate_entries(const mpcth_t,
308 mptable_iter_func, void *);
309 static int mptable_probe(void);
310 static int mptable_check(vm_paddr_t);
311 static long mptable_search_sig(u_int32_t target, int count);
312 static void mptable_hyperthread_fixup(u_int id_mask);
313 static void mptable_pass1(struct mptable_pos *);
314 static int mptable_pass2(struct mptable_pos *);
315 static void mptable_default(int type);
316 static void mptable_fix(void);
317 static int mptable_map(struct mptable_pos *, vm_paddr_t);
318 static void mptable_unmap(struct mptable_pos *);
321 static void setup_apic_irq_mapping(void);
322 static int apic_int_is_bus_type(int intr, int bus_type);
324 static int start_all_aps(u_int boot_addr);
326 static void install_ap_tramp(u_int boot_addr);
328 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
329 static int smitest(void);
331 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
332 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
333 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
334 static u_int bootMP_size;
337 * Calculate usable address in base memory for AP trampoline code.
340 mp_bootaddress(u_int basemem)
342 POSTCODE(MP_BOOTADDRESS_POST);
344 base_memory = basemem;
346 bootMP_size = mptramp_end - mptramp_start;
347 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
348 if (((basemem * 1024) - boot_address) < bootMP_size)
349 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
350 /* 3 levels of page table pages */
351 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
353 return mptramp_pagetables;
358 * Look for an Intel MP spec table (ie, SMP capable hardware).
367 * Make sure our SMPpt[] page table is big enough to hold all the
370 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
372 POSTCODE(MP_PROBE_POST);
374 /* see if EBDA exists */
375 if (ebda_addr != 0) {
376 /* search first 1K of EBDA */
377 target = (u_int32_t)ebda_addr;
378 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
381 /* last 1K of base memory, effective 'top of base' passed in */
382 target = (u_int32_t)(base_memory - 0x400);
383 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
387 /* search the BIOS */
388 target = (u_int32_t)BIOS_BASE;
389 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
396 struct mptable_check_cbarg {
402 mptable_check_callback(void *xarg, const void *pos, int type)
404 const struct PROCENTRY *ent;
405 struct mptable_check_cbarg *arg = xarg;
411 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
415 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
416 if (arg->found_bsp) {
417 kprintf("more than one BSP in base MP table\n");
426 mptable_check(vm_paddr_t mpfps_paddr)
428 struct mptable_pos mpt;
429 struct mptable_check_cbarg arg;
433 if (mpfps_paddr == 0)
436 error = mptable_map(&mpt, mpfps_paddr);
440 if (mpt.mp_fps->mpfb1 != 0)
448 if (cth->apic_address == 0)
451 bzero(&arg, sizeof(arg));
452 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
454 if (arg.cpu_count == 0) {
455 kprintf("MP table contains no processor entries\n");
457 } else if (!arg.found_bsp) {
458 kprintf("MP table does not contains BSP entry\n");
468 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
470 int count, total_size;
471 const void *position;
473 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
474 total_size = cth->base_table_length - sizeof(struct MPCTH);
475 position = (const uint8_t *)cth + sizeof(struct MPCTH);
476 count = cth->entry_count;
481 KKASSERT(total_size >= 0);
482 if (total_size == 0) {
483 kprintf("invalid base MP table, "
484 "entry count and length mismatch\n");
488 type = *(const uint8_t *)position;
490 case 0: /* processor_entry */
491 case 1: /* bus_entry */
492 case 2: /* io_apic_entry */
493 case 3: /* int_entry */
494 case 4: /* int_entry */
497 kprintf("unknown base MP table entry type %d\n", type);
501 if (total_size < basetable_entry_types[type].length) {
502 kprintf("invalid base MP table length, "
503 "does not contain all entries\n");
506 total_size -= basetable_entry_types[type].length;
508 error = func(arg, position, type);
512 position = (const uint8_t *)position +
513 basetable_entry_types[type].length;
520 * Startup the SMP processors.
525 POSTCODE(MP_START_POST);
526 mp_enable(boot_address);
531 * Print various information about the SMP system hardware and setup.
538 POSTCODE(MP_ANNOUNCE_POST);
540 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
541 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
542 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
543 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
544 for (x = 1; x <= mp_naps; ++x) {
545 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
546 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
547 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
551 for (x = 0; x < mp_napics; ++x) {
552 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
553 kprintf(", version: 0x%08x", io_apic_versions[x]);
554 kprintf(", at 0x%08lx\n", io_apic_address[x]);
557 kprintf(" Warning: APIC I/O disabled\n");
562 * AP cpu's call this to sync up protected mode.
564 * WARNING! %gs is not set up on entry. This routine sets up %gs.
570 int x, myid = bootAP;
572 struct mdglobaldata *md;
573 struct privatespace *ps;
575 ps = &CPU_prvspace[myid];
577 gdt_segs[GPROC0_SEL].ssd_base =
578 (long) &ps->mdglobaldata.gd_common_tss;
579 ps->mdglobaldata.mi.gd_prvspace = ps;
581 /* We fill the 32-bit segment descriptors */
582 for (x = 0; x < NGDT; x++) {
583 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
584 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
586 /* And now a 64-bit one */
587 ssdtosyssd(&gdt_segs[GPROC0_SEL],
588 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
590 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
591 r_gdt.rd_base = (long) &gdt[myid * NGDT];
592 lgdt(&r_gdt); /* does magic intra-segment return */
594 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
595 wrmsr(MSR_FSBASE, 0); /* User value */
596 wrmsr(MSR_GSBASE, (u_int64_t)ps);
597 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
603 mdcpu->gd_currentldt = _default_ldt;
606 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
607 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
609 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
611 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
613 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
615 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
616 md->gd_common_tssd = *md->gd_tss_gdt;
618 md->gd_common_tss.tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
623 * Set to a known state:
624 * Set by mpboot.s: CR0_PG, CR0_PE
625 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
628 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
631 /* Set up the fast syscall stuff */
632 msr = rdmsr(MSR_EFER) | EFER_SCE;
633 wrmsr(MSR_EFER, msr);
634 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
635 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
636 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
637 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
638 wrmsr(MSR_STAR, msr);
639 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
641 pmap_set_opt(); /* PSE/4MB pages, etc */
643 /* Initialize the PAT MSR. */
647 /* set up CPU registers and state */
650 /* set up SSE/NX registers */
653 /* set up FPU state on the AP */
654 npxinit(__INITIAL_NPXCW__);
656 /* disable the APIC, just to be SURE */
657 lapic->svr &= ~APIC_SVR_ENABLE;
659 /* data returned to BSP */
660 cpu_apic_versions[0] = lapic->version;
663 /*******************************************************************
664 * local functions and data
668 * start the SMP system
671 mp_enable(u_int boot_addr)
678 vm_paddr_t mpfps_paddr;
680 POSTCODE(MP_ENABLE_POST);
682 if (madt_probe_test) {
685 mpfps_paddr = mptable_probe();
686 if (mptable_check(mpfps_paddr))
691 struct mptable_pos mpt;
693 mptable_map(&mpt, mpfps_paddr);
696 * We can safely map physical memory into SMPpt after
697 * mptable_pass1() completes.
701 if (cpu_apic_address == 0)
702 panic("mp_enable: no local apic!\n");
704 /* examine the MP table for needed info */
705 x = mptable_pass2(&mpt);
710 * can't process default configs till the
711 * CPU APIC is pmapped
716 /* post scan cleanup */
720 * lapic not mapped yet (pmap_init is called too late)
722 lapic = pmap_mapdev_uncacheable(cpu_apic_address,
723 sizeof(struct LAPIC));
725 vm_paddr_t madt_paddr;
728 madt_paddr = madt_probe();
730 panic("mp_enable: madt_probe failed\n");
732 cpu_apic_address = madt_pass1(madt_paddr);
733 if (cpu_apic_address == 0)
734 panic("mp_enable: no local apic (madt)!\n");
737 * lapic not mapped yet (pmap_init is called too late)
739 * XXX: where is the best place to set lapic?
741 lapic = pmap_mapdev_uncacheable(cpu_apic_address,
742 sizeof(struct LAPIC));
744 bsp_apic_id = (lapic->id & 0xff000000) >> 24;
745 if (madt_pass2(madt_paddr, bsp_apic_id))
746 panic("mp_enable: madt_pass2 failed\n");
751 setup_apic_irq_mapping();
753 /* fill the LOGICAL io_apic_versions table */
754 for (apic = 0; apic < mp_napics; ++apic) {
755 ux = io_apic_read(apic, IOAPIC_VER);
756 io_apic_versions[apic] = ux;
757 io_apic_set_id(apic, IO_TO_ID(apic));
760 /* program each IO APIC in the system */
761 for (apic = 0; apic < mp_napics; ++apic)
762 if (io_apic_setup(apic) < 0)
763 panic("IO APIC setup failure");
768 * These are required for SMP operation
771 /* install a 'Spurious INTerrupt' vector */
772 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
773 SDT_SYSIGT, SEL_KPL, 0);
775 /* install an inter-CPU IPI for TLB invalidation */
776 setidt(XINVLTLB_OFFSET, Xinvltlb,
777 SDT_SYSIGT, SEL_KPL, 0);
779 /* install an inter-CPU IPI for IPIQ messaging */
780 setidt(XIPIQ_OFFSET, Xipiq,
781 SDT_SYSIGT, SEL_KPL, 0);
783 /* install a timer vector */
784 setidt(XTIMER_OFFSET, Xtimer,
785 SDT_SYSIGT, SEL_KPL, 0);
787 /* install an inter-CPU IPI for CPU stop/restart */
788 setidt(XCPUSTOP_OFFSET, Xcpustop,
789 SDT_SYSIGT, SEL_KPL, 0);
791 /* start each Application Processor */
792 start_all_aps(boot_addr);
797 * look for the MP spec signature
800 /* string defined by the Intel MP Spec as identifying the MP table */
801 #define MP_SIG 0x5f504d5f /* _MP_ */
802 #define NEXT(X) ((X) += 4)
804 mptable_search_sig(u_int32_t target, int count)
810 KKASSERT(target != 0);
812 map_size = count * sizeof(u_int32_t);
813 addr = pmap_mapdev((vm_paddr_t)target, map_size);
816 for (x = 0; x < count; NEXT(x)) {
817 if (addr[x] == MP_SIG) {
818 /* make array index a byte index */
819 ret = target + (x * sizeof(u_int32_t));
824 pmap_unmapdev((vm_offset_t)addr, map_size);
829 typedef struct BUSDATA {
831 enum busTypes bus_type;
834 typedef struct INTDATA {
844 typedef struct BUSTYPENAME {
851 static bus_type_name bus_type_table[] =
857 {UNKNOWN_BUSTYPE, "---"},
860 {UNKNOWN_BUSTYPE, "---"},
861 {UNKNOWN_BUSTYPE, "---"},
862 {UNKNOWN_BUSTYPE, "---"},
863 {UNKNOWN_BUSTYPE, "---"},
864 {UNKNOWN_BUSTYPE, "---"},
866 {UNKNOWN_BUSTYPE, "---"},
867 {UNKNOWN_BUSTYPE, "---"},
868 {UNKNOWN_BUSTYPE, "---"},
869 {UNKNOWN_BUSTYPE, "---"},
871 {UNKNOWN_BUSTYPE, "---"}
874 /* from MP spec v1.4, table 5-1 */
875 static int default_data[7][5] =
877 /* nbus, id0, type0, id1, type1 */
878 {1, 0, ISA, 255, 255},
879 {1, 0, EISA, 255, 255},
880 {1, 0, EISA, 255, 255},
881 {1, 0, MCA, 255, 255},
883 {2, 0, EISA, 1, PCI},
888 static bus_datum *bus_data;
890 /* the IO INT data, one entry per possible APIC INTerrupt */
891 static io_int *io_apic_ints;
896 static int processor_entry (proc_entry_ptr entry, int cpu);
898 static int bus_entry (bus_entry_ptr entry, int bus);
899 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
900 static int int_entry (int_entry_ptr entry, int intr);
901 static int lookup_bus_type (char *name);
906 * 1st pass on motherboard's Intel MP specification table.
909 * cpu_apic_address (common to all CPUs)
915 * need_hyperthreading_fixup
919 mptable_pass1(struct mptable_pos *mpt)
932 POSTCODE(MPTABLE_PASS1_POST);
935 KKASSERT(fps != NULL);
938 /* clear various tables */
939 for (x = 0; x < NAPICID; ++x) {
940 io_apic_address[x] = ~0; /* IO APIC address table */
944 /* init everything to empty */
953 /* check for use of 'default' configuration */
954 if (fps->mpfb1 != 0) {
955 /* use default addresses */
956 cpu_apic_address = DEFAULT_APIC_BASE;
958 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
961 /* fill in with defaults */
962 mp_naps = 2; /* includes BSP */
964 mp_nbusses = default_data[fps->mpfb1 - 1][0];
972 panic("MP Configuration Table Header MISSING!");
974 cpu_apic_address = (vm_offset_t) cth->apic_address;
976 /* walk the table, recording info of interest */
977 totalSize = cth->base_table_length - sizeof(struct MPCTH);
978 position = (u_char *) cth + sizeof(struct MPCTH);
979 count = cth->entry_count;
982 switch (type = *(u_char *) position) {
983 case 0: /* processor_entry */
984 if (((proc_entry_ptr)position)->cpu_flags
985 & PROCENTRY_FLAG_EN) {
988 ((proc_entry_ptr)position)->apic_id;
991 case 1: /* bus_entry */
996 case 2: /* io_apic_entry */
998 if (((io_apic_entry_ptr)position)->apic_flags
999 & IOAPICENTRY_FLAG_EN)
1000 io_apic_address[mp_napics++] =
1001 (vm_offset_t)((io_apic_entry_ptr)
1002 position)->apic_address;
1005 case 3: /* int_entry */
1010 case 4: /* int_entry */
1013 panic("mpfps Base Table HOSED!");
1017 totalSize -= basetable_entry_types[type].length;
1018 position = (uint8_t *)position +
1019 basetable_entry_types[type].length;
1023 /* qualify the numbers */
1024 if (mp_naps > MAXCPU) {
1025 kprintf("Warning: only using %d of %d available CPUs!\n",
1030 /* See if we need to fixup HT logical CPUs. */
1031 mptable_hyperthread_fixup(id_mask);
1033 --mp_naps; /* subtract the BSP */
1038 * 2nd pass on motherboard's Intel MP specification table.
1042 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
1043 * CPU_TO_ID(N), logical CPU to APIC ID table
1044 * IO_TO_ID(N), logical IO to APIC ID table
1049 mptable_pass2(struct mptable_pos *mpt)
1051 struct PROCENTRY proc;
1059 int apic, bus, cpu, intr;
1062 POSTCODE(MPTABLE_PASS2_POST);
1065 KKASSERT(fps != NULL);
1067 /* Initialize fake proc entry for use with HT fixup. */
1068 bzero(&proc, sizeof(proc));
1070 proc.cpu_flags = PROCENTRY_FLAG_EN;
1073 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
1074 M_DEVBUF, M_WAITOK);
1075 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
1076 M_DEVBUF, M_WAITOK | M_ZERO);
1077 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
1078 M_DEVBUF, M_WAITOK);
1079 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
1080 M_DEVBUF, M_WAITOK);
1084 for (i = 0; i < mp_napics; i++) {
1085 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
1089 /* clear various tables */
1090 for (x = 0; x < NAPICID; ++x) {
1091 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
1093 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
1094 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
1099 /* clear bus data table */
1100 for (x = 0; x < mp_nbusses; ++x)
1101 bus_data[x].bus_id = 0xff;
1103 /* clear IO APIC INT table */
1104 for (x = 0; x < (nintrs + 1); ++x) {
1105 io_apic_ints[x].int_type = 0xff;
1106 io_apic_ints[x].int_vector = 0xff;
1110 /* record whether PIC or virtual-wire mode */
1111 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, fps->mpfb2 & 0x80);
1113 /* check for use of 'default' configuration */
1114 if (fps->mpfb1 != 0)
1115 return fps->mpfb1; /* return default configuration type */
1119 panic("MP Configuration Table Header MISSING!");
1121 /* walk the table, recording info of interest */
1122 totalSize = cth->base_table_length - sizeof(struct MPCTH);
1123 position = (u_char *) cth + sizeof(struct MPCTH);
1124 count = cth->entry_count;
1125 apic = bus = intr = 0;
1126 cpu = 1; /* pre-count the BSP */
1129 switch (type = *(u_char *) position) {
1131 if (processor_entry(position, cpu))
1134 if (need_hyperthreading_fixup) {
1136 * Create fake mptable processor entries
1137 * and feed them to processor_entry() to
1138 * enumerate the logical CPUs.
1140 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
1141 for (i = 1; i < logical_cpus; i++) {
1143 processor_entry(&proc, cpu);
1144 logical_cpus_mask |= (1 << cpu);
1151 if (bus_entry(position, bus))
1157 if (io_apic_entry(position, apic))
1163 if (int_entry(position, intr))
1168 /* int_entry(position); */
1171 panic("mpfps Base Table HOSED!");
1175 totalSize -= basetable_entry_types[type].length;
1176 position = (uint8_t *)position + basetable_entry_types[type].length;
1179 if (CPU_TO_ID(0) < 0)
1180 panic("NO BSP found!");
1182 /* report fact that its NOT a default configuration */
1188 * Check if we should perform a hyperthreading "fix-up" to
1189 * enumerate any logical CPU's that aren't already listed
1192 * XXX: We assume that all of the physical CPUs in the
1193 * system have the same number of logical CPUs.
1195 * XXX: We assume that APIC ID's are allocated such that
1196 * the APIC ID's for a physical processor are aligned
1197 * with the number of logical CPU's in the processor.
1200 mptable_hyperthread_fixup(u_int id_mask)
1202 int i, id, lcpus_max;
1204 if ((cpu_feature & CPUID_HTT) == 0)
1207 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1211 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1213 * INSTRUCTION SET REFERENCE, A-M (#253666)
1214 * Page 3-181, Table 3-20
1215 * "The nearest power-of-2 integer that is not smaller
1216 * than EBX[23:16] is the number of unique initial APIC
1217 * IDs reserved for addressing different logical
1218 * processors in a physical package."
1220 for (i = 0; ; ++i) {
1221 if ((1 << i) >= lcpus_max) {
1228 if (mp_naps == lcpus_max) {
1229 /* We have nothing to fix */
1231 } else if (mp_naps == 1) {
1232 /* XXX this may be incorrect */
1233 logical_cpus = lcpus_max;
1235 int cur, prev, dist;
1238 * Calculate the distances between two nearest
1239 * APIC IDs. If all such distances are same,
1240 * then it is the number of missing cpus that
1241 * we are going to fill later.
1243 dist = cur = prev = -1;
1244 for (id = 0; id < MAXCPU; ++id) {
1245 if ((id_mask & 1 << id) == 0)
1250 int new_dist = cur - prev;
1256 * Make sure that all distances
1257 * between two nearest APIC IDs
1260 if (dist != new_dist)
1268 /* Must be power of 2 */
1269 if (dist & (dist - 1))
1272 /* Can't exceed CPU package capacity */
1273 if (dist > lcpus_max)
1274 logical_cpus = lcpus_max;
1276 logical_cpus = dist;
1280 * For each APIC ID of a CPU that is set in the mask,
1281 * scan the other candidate APIC ID's for this
1282 * physical processor. If any of those ID's are
1283 * already in the table, then kill the fixup.
1285 for (id = 0; id < MAXCPU; id++) {
1286 if ((id_mask & 1 << id) == 0)
1288 /* First, make sure we are on a logical_cpus boundary. */
1289 if (id % logical_cpus != 0)
1291 for (i = id + 1; i < id + logical_cpus; i++)
1292 if ((id_mask & 1 << i) != 0)
1297 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1298 * mp_naps right now.
1300 need_hyperthreading_fixup = 1;
1301 mp_naps *= logical_cpus;
1305 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1309 vm_size_t cth_mapsz = 0;
1311 bzero(mpt, sizeof(*mpt));
1313 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1314 if (fps->pap != 0) {
1316 * Map configuration table header to get
1317 * the base table size
1319 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1320 cth_mapsz = cth->base_table_length;
1321 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1323 if (cth_mapsz < sizeof(*cth)) {
1324 kprintf("invalid base MP table length %d\n",
1326 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1331 * Map the base table
1333 cth = pmap_mapdev(fps->pap, cth_mapsz);
1338 mpt->mp_cth_mapsz = cth_mapsz;
1344 mptable_unmap(struct mptable_pos *mpt)
1346 if (mpt->mp_cth != NULL) {
1347 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1349 mpt->mp_cth_mapsz = 0;
1351 if (mpt->mp_fps != NULL) {
1352 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1360 assign_apic_irq(int apic, int intpin, int irq)
1364 if (int_to_apicintpin[irq].ioapic != -1)
1365 panic("assign_apic_irq: inconsistent table");
1367 int_to_apicintpin[irq].ioapic = apic;
1368 int_to_apicintpin[irq].int_pin = intpin;
1369 int_to_apicintpin[irq].apic_address = ioapic[apic];
1370 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1372 for (x = 0; x < nintrs; x++) {
1373 if ((io_apic_ints[x].int_type == 0 ||
1374 io_apic_ints[x].int_type == 3) &&
1375 io_apic_ints[x].int_vector == 0xff &&
1376 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1377 io_apic_ints[x].dst_apic_int == intpin)
1378 io_apic_ints[x].int_vector = irq;
1383 revoke_apic_irq(int irq)
1389 if (int_to_apicintpin[irq].ioapic == -1)
1390 panic("revoke_apic_irq: inconsistent table");
1392 oldapic = int_to_apicintpin[irq].ioapic;
1393 oldintpin = int_to_apicintpin[irq].int_pin;
1395 int_to_apicintpin[irq].ioapic = -1;
1396 int_to_apicintpin[irq].int_pin = 0;
1397 int_to_apicintpin[irq].apic_address = NULL;
1398 int_to_apicintpin[irq].redirindex = 0;
1400 for (x = 0; x < nintrs; x++) {
1401 if ((io_apic_ints[x].int_type == 0 ||
1402 io_apic_ints[x].int_type == 3) &&
1403 io_apic_ints[x].int_vector != 0xff &&
1404 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1405 io_apic_ints[x].dst_apic_int == oldintpin)
1406 io_apic_ints[x].int_vector = 0xff;
1414 allocate_apic_irq(int intr)
1420 if (io_apic_ints[intr].int_vector != 0xff)
1421 return; /* Interrupt handler already assigned */
1423 if (io_apic_ints[intr].int_type != 0 &&
1424 (io_apic_ints[intr].int_type != 3 ||
1425 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1426 io_apic_ints[intr].dst_apic_int == 0)))
1427 return; /* Not INT or ExtInt on != (0, 0) */
1430 while (irq < APIC_INTMAPSIZE &&
1431 int_to_apicintpin[irq].ioapic != -1)
1434 if (irq >= APIC_INTMAPSIZE)
1435 return; /* No free interrupt handlers */
1437 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1438 intpin = io_apic_ints[intr].dst_apic_int;
1440 assign_apic_irq(apic, intpin, irq);
1445 swap_apic_id(int apic, int oldid, int newid)
1452 return; /* Nothing to do */
1454 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1455 apic, oldid, newid);
1457 /* Swap physical APIC IDs in interrupt entries */
1458 for (x = 0; x < nintrs; x++) {
1459 if (io_apic_ints[x].dst_apic_id == oldid)
1460 io_apic_ints[x].dst_apic_id = newid;
1461 else if (io_apic_ints[x].dst_apic_id == newid)
1462 io_apic_ints[x].dst_apic_id = oldid;
1465 /* Swap physical APIC IDs in IO_TO_ID mappings */
1466 for (oapic = 0; oapic < mp_napics; oapic++)
1467 if (IO_TO_ID(oapic) == newid)
1470 if (oapic < mp_napics) {
1471 kprintf("Changing APIC ID for IO APIC #%d from "
1472 "%d to %d in MP table\n",
1473 oapic, newid, oldid);
1474 IO_TO_ID(oapic) = oldid;
1476 IO_TO_ID(apic) = newid;
1481 fix_id_to_io_mapping(void)
1485 for (x = 0; x < NAPICID; x++)
1488 for (x = 0; x <= mp_naps; x++)
1489 if (CPU_TO_ID(x) < NAPICID)
1490 ID_TO_IO(CPU_TO_ID(x)) = x;
1492 for (x = 0; x < mp_napics; x++)
1493 if (IO_TO_ID(x) < NAPICID)
1494 ID_TO_IO(IO_TO_ID(x)) = x;
1499 first_free_apic_id(void)
1503 for (freeid = 0; freeid < NAPICID; freeid++) {
1504 for (x = 0; x <= mp_naps; x++)
1505 if (CPU_TO_ID(x) == freeid)
1509 for (x = 0; x < mp_napics; x++)
1510 if (IO_TO_ID(x) == freeid)
1521 io_apic_id_acceptable(int apic, int id)
1523 int cpu; /* Logical CPU number */
1524 int oapic; /* Logical IO APIC number for other IO APIC */
1527 return 0; /* Out of range */
1529 for (cpu = 0; cpu <= mp_naps; cpu++)
1530 if (CPU_TO_ID(cpu) == id)
1531 return 0; /* Conflict with CPU */
1533 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1534 if (IO_TO_ID(oapic) == id)
1535 return 0; /* Conflict with other APIC */
1537 return 1; /* ID is acceptable for IO APIC */
1542 io_apic_find_int_entry(int apic, int pin)
1546 /* search each of the possible INTerrupt sources */
1547 for (x = 0; x < nintrs; ++x) {
1548 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1549 (pin == io_apic_ints[x].dst_apic_int))
1550 return (&io_apic_ints[x]);
1558 * parse an Intel MP specification table
1566 int apic; /* IO APIC unit number */
1567 int freeid; /* Free physical APIC ID */
1568 int physid; /* Current physical IO APIC ID */
1570 int bus_0 = 0; /* Stop GCC warning */
1571 int bus_pci = 0; /* Stop GCC warning */
1575 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1576 * did it wrong. The MP spec says that when more than 1 PCI bus
1577 * exists the BIOS must begin with bus entries for the PCI bus and use
1578 * actual PCI bus numbering. This implies that when only 1 PCI bus
1579 * exists the BIOS can choose to ignore this ordering, and indeed many
1580 * MP motherboards do ignore it. This causes a problem when the PCI
1581 * sub-system makes requests of the MP sub-system based on PCI bus
1582 * numbers. So here we look for the situation and renumber the
1583 * busses and associated INTs in an effort to "make it right".
1586 /* find bus 0, PCI bus, count the number of PCI busses */
1587 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1588 if (bus_data[x].bus_id == 0) {
1591 if (bus_data[x].bus_type == PCI) {
1597 * bus_0 == slot of bus with ID of 0
1598 * bus_pci == slot of last PCI bus encountered
1601 /* check the 1 PCI bus case for sanity */
1602 /* if it is number 0 all is well */
1603 if (num_pci_bus == 1 &&
1604 bus_data[bus_pci].bus_id != 0) {
1606 /* mis-numbered, swap with whichever bus uses slot 0 */
1608 /* swap the bus entry types */
1609 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1610 bus_data[bus_0].bus_type = PCI;
1612 /* swap each relavant INTerrupt entry */
1613 id = bus_data[bus_pci].bus_id;
1614 for (x = 0; x < nintrs; ++x) {
1615 if (io_apic_ints[x].src_bus_id == id) {
1616 io_apic_ints[x].src_bus_id = 0;
1618 else if (io_apic_ints[x].src_bus_id == 0) {
1619 io_apic_ints[x].src_bus_id = id;
1624 /* Assign IO APIC IDs.
1626 * First try the existing ID. If a conflict is detected, try
1627 * the ID in the MP table. If a conflict is still detected, find
1630 * We cannot use the ID_TO_IO table before all conflicts has been
1631 * resolved and the table has been corrected.
1633 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1635 /* First try to use the value set by the BIOS */
1636 physid = io_apic_get_id(apic);
1637 if (io_apic_id_acceptable(apic, physid)) {
1638 if (IO_TO_ID(apic) != physid)
1639 swap_apic_id(apic, IO_TO_ID(apic), physid);
1643 /* Then check if the value in the MP table is acceptable */
1644 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1647 /* Last resort, find a free APIC ID and use it */
1648 freeid = first_free_apic_id();
1649 if (freeid >= NAPICID)
1650 panic("No free physical APIC IDs found");
1652 if (io_apic_id_acceptable(apic, freeid)) {
1653 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1656 panic("Free physical APIC ID not usable");
1658 fix_id_to_io_mapping();
1660 /* detect and fix broken Compaq MP table */
1661 if (apic_int_type(0, 0) == -1) {
1662 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1663 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1664 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1665 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1666 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1667 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1669 } else if (apic_int_type(0, 0) == 0) {
1670 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1671 for (x = 0; x < nintrs; ++x)
1672 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1673 (0 == io_apic_ints[x].dst_apic_int)) {
1674 io_apic_ints[x].int_type = 3;
1675 io_apic_ints[x].int_vector = 0xff;
1681 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1682 * controllers universally come in pairs. If IRQ 14 is specified
1683 * as an ISA interrupt, then IRQ 15 had better be too.
1685 * [ Shuttle XPC / AMD Athlon X2 ]
1686 * The MPTable is missing an entry for IRQ 15. Note that the
1687 * ACPI table has an entry for both 14 and 15.
1689 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1690 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1691 io14 = io_apic_find_int_entry(0, 14);
1692 io_apic_ints[nintrs] = *io14;
1693 io_apic_ints[nintrs].src_bus_irq = 15;
1694 io_apic_ints[nintrs].dst_apic_int = 15;
1702 /* Assign low level interrupt handlers */
1704 setup_apic_irq_mapping(void)
1710 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1711 int_to_apicintpin[x].ioapic = -1;
1712 int_to_apicintpin[x].int_pin = 0;
1713 int_to_apicintpin[x].apic_address = NULL;
1714 int_to_apicintpin[x].redirindex = 0;
1717 /* First assign ISA/EISA interrupts */
1718 for (x = 0; x < nintrs; x++) {
1719 int_vector = io_apic_ints[x].src_bus_irq;
1720 if (int_vector < APIC_INTMAPSIZE &&
1721 io_apic_ints[x].int_vector == 0xff &&
1722 int_to_apicintpin[int_vector].ioapic == -1 &&
1723 (apic_int_is_bus_type(x, ISA) ||
1724 apic_int_is_bus_type(x, EISA)) &&
1725 io_apic_ints[x].int_type == 0) {
1726 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1727 io_apic_ints[x].dst_apic_int,
1732 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1733 for (x = 0; x < nintrs; x++) {
1734 if (io_apic_ints[x].dst_apic_int == 0 &&
1735 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1736 io_apic_ints[x].int_vector == 0xff &&
1737 int_to_apicintpin[0].ioapic == -1 &&
1738 io_apic_ints[x].int_type == 3) {
1739 assign_apic_irq(0, 0, 0);
1744 /* Assign PCI interrupts */
1745 for (x = 0; x < nintrs; ++x) {
1746 if (io_apic_ints[x].int_type == 0 &&
1747 io_apic_ints[x].int_vector == 0xff &&
1748 apic_int_is_bus_type(x, PCI))
1749 allocate_apic_irq(x);
1756 mp_set_cpuids(int cpu_id, int apic_id)
1758 CPU_TO_ID(cpu_id) = apic_id;
1759 ID_TO_CPU(apic_id) = cpu_id;
1763 processor_entry(proc_entry_ptr entry, int cpu)
1767 /* check for usability */
1768 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1771 if(entry->apic_id >= NAPICID)
1772 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1773 /* check for BSP flag */
1774 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1775 mp_set_cpuids(0, entry->apic_id);
1776 return 0; /* its already been counted */
1779 /* add another AP to list, if less than max number of CPUs */
1780 else if (cpu < MAXCPU) {
1781 mp_set_cpuids(cpu, entry->apic_id);
1791 bus_entry(bus_entry_ptr entry, int bus)
1796 /* encode the name into an index */
1797 for (x = 0; x < 6; ++x) {
1798 if ((c = entry->bus_type[x]) == ' ')
1804 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1805 panic("unknown bus type: '%s'", name);
1807 bus_data[bus].bus_id = entry->bus_id;
1808 bus_data[bus].bus_type = x;
1814 io_apic_entry(io_apic_entry_ptr entry, int apic)
1816 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1819 IO_TO_ID(apic) = entry->apic_id;
1820 if (entry->apic_id < NAPICID)
1821 ID_TO_IO(entry->apic_id) = apic;
1827 lookup_bus_type(char *name)
1831 for (x = 0; x < MAX_BUSTYPE; ++x)
1832 if (strcmp(bus_type_table[x].name, name) == 0)
1833 return bus_type_table[x].type;
1835 return UNKNOWN_BUSTYPE;
1839 int_entry(int_entry_ptr entry, int intr)
1843 io_apic_ints[intr].int_type = entry->int_type;
1844 io_apic_ints[intr].int_flags = entry->int_flags;
1845 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1846 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1847 if (entry->dst_apic_id == 255) {
1848 /* This signal goes to all IO APICS. Select an IO APIC
1849 with sufficient number of interrupt pins */
1850 for (apic = 0; apic < mp_napics; apic++)
1851 if (((io_apic_read(apic, IOAPIC_VER) &
1852 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1853 entry->dst_apic_int)
1855 if (apic < mp_napics)
1856 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1858 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1860 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1861 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1867 apic_int_is_bus_type(int intr, int bus_type)
1871 for (bus = 0; bus < mp_nbusses; ++bus)
1872 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1873 && ((int) bus_data[bus].bus_type == bus_type))
1880 * Given a traditional ISA INT mask, return an APIC mask.
1883 isa_apic_mask(u_int isa_mask)
1888 #if defined(SKIP_IRQ15_REDIRECT)
1889 if (isa_mask == (1 << 15)) {
1890 kprintf("skipping ISA IRQ15 redirect\n");
1893 #endif /* SKIP_IRQ15_REDIRECT */
1895 isa_irq = ffs(isa_mask); /* find its bit position */
1896 if (isa_irq == 0) /* doesn't exist */
1898 --isa_irq; /* make it zero based */
1900 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1904 return (1 << apic_pin); /* convert pin# to a mask */
1908 * Determine which APIC pin an ISA/EISA INT is attached to.
1910 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1911 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1912 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1913 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1915 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1917 isa_apic_irq(int isa_irq)
1921 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1922 if (INTTYPE(intr) == 0) { /* standard INT */
1923 if (SRCBUSIRQ(intr) == isa_irq) {
1924 if (apic_int_is_bus_type(intr, ISA) ||
1925 apic_int_is_bus_type(intr, EISA)) {
1926 if (INTIRQ(intr) == 0xff)
1927 return -1; /* unassigned */
1928 return INTIRQ(intr); /* found */
1933 return -1; /* NOT found */
1938 * Determine which APIC pin a PCI INT is attached to.
1940 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1941 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1942 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1944 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1948 --pciInt; /* zero based */
1950 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1951 if ((INTTYPE(intr) == 0) /* standard INT */
1952 && (SRCBUSID(intr) == pciBus)
1953 && (SRCBUSDEVICE(intr) == pciDevice)
1954 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1955 if (apic_int_is_bus_type(intr, PCI)) {
1956 if (INTIRQ(intr) == 0xff) {
1957 kprintf("IOAPIC: pci_apic_irq() "
1959 return -1; /* unassigned */
1961 return INTIRQ(intr); /* exact match */
1966 return -1; /* NOT found */
1970 next_apic_irq(int irq)
1977 for (intr = 0; intr < nintrs; intr++) {
1978 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1980 bus = SRCBUSID(intr);
1981 bustype = apic_bus_type(bus);
1982 if (bustype != ISA &&
1988 if (intr >= nintrs) {
1991 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1992 if (INTTYPE(ointr) != 0)
1994 if (bus != SRCBUSID(ointr))
1996 if (bustype == PCI) {
1997 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1999 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
2002 if (bustype == ISA || bustype == EISA) {
2003 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
2006 if (INTPIN(intr) == INTPIN(ointr))
2010 if (ointr >= nintrs) {
2013 return INTIRQ(ointr);
2028 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
2031 * Exactly what this means is unclear at this point. It is a solution
2032 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
2033 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
2034 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
2038 undirect_isa_irq(int rirq)
2042 kprintf("Freeing redirected ISA irq %d.\n", rirq);
2043 /** FIXME: tickle the MB redirector chip */
2047 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
2054 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
2057 undirect_pci_irq(int rirq)
2061 kprintf("Freeing redirected PCI irq %d.\n", rirq);
2063 /** FIXME: tickle the MB redirector chip */
2067 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
2077 * given a bus ID, return:
2078 * the bus type if found
2082 apic_bus_type(int id)
2086 for (x = 0; x < mp_nbusses; ++x)
2087 if (bus_data[x].bus_id == id)
2088 return bus_data[x].bus_type;
2094 * given a LOGICAL APIC# and pin#, return:
2095 * the associated src bus ID if found
2099 apic_src_bus_id(int apic, int pin)
2103 /* search each of the possible INTerrupt sources */
2104 for (x = 0; x < nintrs; ++x)
2105 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2106 (pin == io_apic_ints[x].dst_apic_int))
2107 return (io_apic_ints[x].src_bus_id);
2109 return -1; /* NOT found */
2113 * given a LOGICAL APIC# and pin#, return:
2114 * the associated src bus IRQ if found
2118 apic_src_bus_irq(int apic, int pin)
2122 for (x = 0; x < nintrs; x++)
2123 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2124 (pin == io_apic_ints[x].dst_apic_int))
2125 return (io_apic_ints[x].src_bus_irq);
2127 return -1; /* NOT found */
2132 * given a LOGICAL APIC# and pin#, return:
2133 * the associated INTerrupt type if found
2137 apic_int_type(int apic, int pin)
2141 /* search each of the possible INTerrupt sources */
2142 for (x = 0; x < nintrs; ++x) {
2143 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2144 (pin == io_apic_ints[x].dst_apic_int))
2145 return (io_apic_ints[x].int_type);
2147 return -1; /* NOT found */
2151 * Return the IRQ associated with an APIC pin
2154 apic_irq(int apic, int pin)
2159 for (x = 0; x < nintrs; ++x) {
2160 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2161 (pin == io_apic_ints[x].dst_apic_int)) {
2162 res = io_apic_ints[x].int_vector;
2165 if (apic != int_to_apicintpin[res].ioapic)
2166 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
2167 if (pin != int_to_apicintpin[res].int_pin)
2168 panic("apic_irq inconsistent table (2)");
2177 * given a LOGICAL APIC# and pin#, return:
2178 * the associated trigger mode if found
2182 apic_trigger(int apic, int pin)
2186 /* search each of the possible INTerrupt sources */
2187 for (x = 0; x < nintrs; ++x)
2188 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2189 (pin == io_apic_ints[x].dst_apic_int))
2190 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2192 return -1; /* NOT found */
2197 * given a LOGICAL APIC# and pin#, return:
2198 * the associated 'active' level if found
2202 apic_polarity(int apic, int pin)
2206 /* search each of the possible INTerrupt sources */
2207 for (x = 0; x < nintrs; ++x)
2208 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2209 (pin == io_apic_ints[x].dst_apic_int))
2210 return (io_apic_ints[x].int_flags & 0x03);
2212 return -1; /* NOT found */
2218 * set data according to MP defaults
2219 * FIXME: probably not complete yet...
2222 mptable_default(int type)
2224 int ap_cpu_id, boot_cpu_id;
2225 #if defined(APIC_IO)
2228 #endif /* APIC_IO */
2231 kprintf(" MP default config type: %d\n", type);
2234 kprintf(" bus: ISA, APIC: 82489DX\n");
2237 kprintf(" bus: EISA, APIC: 82489DX\n");
2240 kprintf(" bus: EISA, APIC: 82489DX\n");
2243 kprintf(" bus: MCA, APIC: 82489DX\n");
2246 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2249 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2252 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2255 kprintf(" future type\n");
2261 boot_cpu_id = (lapic->id & APIC_ID_MASK) >> 24;
2262 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
2265 CPU_TO_ID(0) = boot_cpu_id;
2266 ID_TO_CPU(boot_cpu_id) = 0;
2268 /* one and only AP */
2269 CPU_TO_ID(1) = ap_cpu_id;
2270 ID_TO_CPU(ap_cpu_id) = 1;
2272 #if defined(APIC_IO)
2273 /* one and only IO APIC */
2274 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2277 * sanity check, refer to MP spec section 3.6.6, last paragraph
2278 * necessary as some hardware isn't properly setting up the IO APIC
2280 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2281 if (io_apic_id != 2) {
2283 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2284 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2285 io_apic_set_id(0, 2);
2288 IO_TO_ID(0) = io_apic_id;
2289 ID_TO_IO(io_apic_id) = 0;
2290 #endif /* APIC_IO */
2292 /* fill out bus entries */
2302 bus_data[0].bus_id = default_data[type - 1][1];
2303 bus_data[0].bus_type = default_data[type - 1][2];
2304 bus_data[1].bus_id = default_data[type - 1][3];
2305 bus_data[1].bus_type = default_data[type - 1][4];
2309 /* case 4: case 7: MCA NOT supported */
2310 default: /* illegal/reserved */
2311 panic("BAD default MP config: %d", type);
2315 #if defined(APIC_IO)
2316 /* general cases from MP v1.4, table 5-2 */
2317 for (pin = 0; pin < 16; ++pin) {
2318 io_apic_ints[pin].int_type = 0;
2319 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2320 io_apic_ints[pin].src_bus_id = 0;
2321 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2322 io_apic_ints[pin].dst_apic_id = io_apic_id;
2323 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2326 /* special cases from MP v1.4, table 5-2 */
2328 io_apic_ints[2].int_type = 0xff; /* N/C */
2329 io_apic_ints[13].int_type = 0xff; /* N/C */
2330 #if !defined(APIC_MIXED_MODE)
2332 panic("sorry, can't support type 2 default yet");
2333 #endif /* APIC_MIXED_MODE */
2336 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2339 io_apic_ints[0].int_type = 0xff; /* N/C */
2341 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2342 #endif /* APIC_IO */
2346 * Map a physical memory address representing I/O into KVA. The I/O
2347 * block is assumed not to cross a page boundary.
2350 permanent_io_mapping(vm_paddr_t pa)
2352 KKASSERT(pa < 0x100000000LL);
2354 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2358 * start each AP in our list
2361 start_all_aps(u_int boot_addr)
2363 vm_offset_t va = boot_address + KERNBASE;
2364 u_int64_t *pt4, *pt3, *pt2;
2370 u_char mpbiosreason;
2371 u_long mpbioswarmvec;
2372 struct mdglobaldata *gd;
2373 struct privatespace *ps;
2375 POSTCODE(START_ALL_APS_POST);
2377 /* Initialize BSP's local APIC */
2378 apic_initialize(TRUE);
2380 /* install the AP 1st level boot code */
2381 pmap_kenter(va, boot_address);
2382 cpu_invlpg((void *)va); /* JG XXX */
2383 bcopy(mptramp_start, (void *)va, bootMP_size);
2385 /* Locate the page tables, they'll be below the trampoline */
2386 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2387 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2388 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2390 /* Create the initial 1GB replicated page tables */
2391 for (i = 0; i < 512; i++) {
2392 /* Each slot of the level 4 pages points to the same level 3 page */
2393 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2394 pt4[i] |= PG_V | PG_RW | PG_U;
2396 /* Each slot of the level 3 pages points to the same level 2 page */
2397 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2398 pt3[i] |= PG_V | PG_RW | PG_U;
2400 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2401 pt2[i] = i * (2 * 1024 * 1024);
2402 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2405 /* save the current value of the warm-start vector */
2406 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2407 outb(CMOS_REG, BIOS_RESET);
2408 mpbiosreason = inb(CMOS_DATA);
2410 /* setup a vector to our boot code */
2411 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2412 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2413 outb(CMOS_REG, BIOS_RESET);
2414 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2417 * If we have a TSC we can figure out the SMI interrupt rate.
2418 * The SMI does not necessarily use a constant rate. Spend
2419 * up to 250ms trying to figure it out.
2422 if (cpu_feature & CPUID_TSC) {
2423 set_apic_timer(275000);
2424 smilast = read_apic_timer();
2425 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2426 smicount = smitest();
2427 if (smibest == 0 || smilast - smicount < smibest)
2428 smibest = smilast - smicount;
2431 if (smibest > 250000)
2434 smibest = smibest * (int64_t)1000000 /
2435 get_apic_timer_frequency();
2439 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2440 1000000 / smibest, smibest);
2443 for (x = 1; x <= mp_naps; ++x) {
2445 /* This is a bit verbose, it will go away soon. */
2447 /* first page of AP's private space */
2448 pg = x * x86_64_btop(sizeof(struct privatespace));
2450 /* allocate new private data page(s) */
2451 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2452 MDGLOBALDATA_BASEALLOC_SIZE);
2454 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2455 bzero(gd, sizeof(*gd));
2456 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2458 /* prime data page for it to use */
2459 mi_gdinit(&gd->mi, x);
2461 gd->gd_CMAP1 = &SMPpt[pg + 0];
2462 gd->gd_CMAP2 = &SMPpt[pg + 1];
2463 gd->gd_CMAP3 = &SMPpt[pg + 2];
2464 gd->gd_PMAP1 = &SMPpt[pg + 3];
2465 gd->gd_CADDR1 = ps->CPAGE1;
2466 gd->gd_CADDR2 = ps->CPAGE2;
2467 gd->gd_CADDR3 = ps->CPAGE3;
2468 gd->gd_PADDR1 = (pt_entry_t *)ps->PPAGE1;
2469 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2470 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2472 /* setup a vector to our boot code */
2473 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2474 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2475 outb(CMOS_REG, BIOS_RESET);
2476 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2479 * Setup the AP boot stack
2481 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2484 /* attempt to start the Application Processor */
2485 CHECK_INIT(99); /* setup checkpoints */
2486 if (!start_ap(gd, boot_addr, smibest)) {
2487 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2488 CHECK_PRINT("trace"); /* show checkpoints */
2489 /* better panic as the AP may be running loose */
2490 kprintf("panic y/n? [y] ");
2491 if (cngetc() != 'n')
2494 CHECK_PRINT("trace"); /* show checkpoints */
2496 /* record its version info */
2497 cpu_apic_versions[x] = cpu_apic_versions[0];
2500 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2503 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2504 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2507 ncpus2_shift = shift;
2508 ncpus2 = 1 << shift;
2509 ncpus2_mask = ncpus2 - 1;
2511 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2512 if ((1 << shift) < ncpus)
2514 ncpus_fit = 1 << shift;
2515 ncpus_fit_mask = ncpus_fit - 1;
2517 /* build our map of 'other' CPUs */
2518 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2519 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2520 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2522 /* fill in our (BSP) APIC version */
2523 cpu_apic_versions[0] = lapic->version;
2525 /* restore the warmstart vector */
2526 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2527 outb(CMOS_REG, BIOS_RESET);
2528 outb(CMOS_DATA, mpbiosreason);
2531 * NOTE! The idlestack for the BSP was setup by locore. Finish
2532 * up, clean out the P==V mapping we did earlier.
2536 /* number of APs actually started */
2542 * load the 1st level AP boot code into base memory.
2545 /* targets for relocation */
2546 extern void bigJump(void);
2547 extern void bootCodeSeg(void);
2548 extern void bootDataSeg(void);
2549 extern void MPentry(void);
2550 extern u_int MP_GDT;
2551 extern u_int mp_gdtbase;
2556 install_ap_tramp(u_int boot_addr)
2559 int size = *(int *) ((u_long) & bootMP_size);
2560 u_char *src = (u_char *) ((u_long) bootMP);
2561 u_char *dst = (u_char *) boot_addr + KERNBASE;
2562 u_int boot_base = (u_int) bootMP;
2567 POSTCODE(INSTALL_AP_TRAMP_POST);
2569 for (x = 0; x < size; ++x)
2573 * modify addresses in code we just moved to basemem. unfortunately we
2574 * need fairly detailed info about mpboot.s for this to work. changes
2575 * to mpboot.s might require changes here.
2578 /* boot code is located in KERNEL space */
2579 dst = (u_char *) boot_addr + KERNBASE;
2581 /* modify the lgdt arg */
2582 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2583 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2585 /* modify the ljmp target for MPentry() */
2586 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2587 *dst32 = ((u_int) MPentry - KERNBASE);
2589 /* modify the target for boot code segment */
2590 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2591 dst8 = (u_int8_t *) (dst16 + 1);
2592 *dst16 = (u_int) boot_addr & 0xffff;
2593 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2595 /* modify the target for boot data segment */
2596 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2597 dst8 = (u_int8_t *) (dst16 + 1);
2598 *dst16 = (u_int) boot_addr & 0xffff;
2599 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2605 * This function starts the AP (application processor) identified
2606 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2607 * to accomplish this. This is necessary because of the nuances
2608 * of the different hardware we might encounter. It ain't pretty,
2609 * but it seems to work.
2611 * NOTE: eventually an AP gets to ap_init(), which is called just
2612 * before the AP goes into the LWKT scheduler's idle loop.
2615 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2619 u_long icr_lo, icr_hi;
2621 POSTCODE(START_AP_POST);
2623 /* get the PHYSICAL APIC ID# */
2624 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2626 /* calculate the vector */
2627 vector = (boot_addr >> 12) & 0xff;
2629 /* We don't want anything interfering */
2632 /* Make sure the target cpu sees everything */
2636 * Try to detect when a SMI has occurred, wait up to 200ms.
2638 * If a SMI occurs during an AP reset but before we issue
2639 * the STARTUP command, the AP may brick. To work around
2640 * this problem we hold off doing the AP startup until
2641 * after we have detected the SMI. Hopefully another SMI
2642 * will not occur before we finish the AP startup.
2644 * Retries don't seem to help. SMIs have a window of opportunity
2645 * and if USB->legacy keyboard emulation is enabled in the BIOS
2646 * the interrupt rate can be quite high.
2648 * NOTE: Don't worry about the L1 cache load, it might bloat
2649 * ldelta a little but ndelta will be so huge when the SMI
2650 * occurs the detection logic will still work fine.
2653 set_apic_timer(200000);
2658 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2659 * and running the target CPU. OR this INIT IPI might be latched (P5
2660 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2663 * see apic/apicreg.h for icr bit definitions.
2665 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2669 * Setup the address for the target AP. We can setup
2670 * icr_hi once and then just trigger operations with
2673 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2674 icr_hi |= (physical_cpu << 24);
2675 icr_lo = lapic->icr_lo & 0xfff00000;
2676 lapic->icr_hi = icr_hi;
2679 * Do an INIT IPI: assert RESET
2681 * Use edge triggered mode to assert INIT
2683 lapic->icr_lo = icr_lo | 0x00004500;
2684 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2688 * The spec calls for a 10ms delay but we may have to use a
2689 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2690 * interrupt. We have other loops here too and dividing by 2
2691 * doesn't seem to be enough even after subtracting 350us,
2692 * so we divide by 4.
2694 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2695 * interrupt was detected we use the full 10ms.
2699 else if (smibest < 150 * 4 + 350)
2701 else if ((smibest - 350) / 4 < 10000)
2702 u_sleep((smibest - 350) / 4);
2707 * Do an INIT IPI: deassert RESET
2709 * Use level triggered mode to deassert. It is unclear
2710 * why we need to do this.
2712 lapic->icr_lo = icr_lo | 0x00008500;
2713 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2715 u_sleep(150); /* wait 150us */
2718 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2719 * latched, (P5 bug) this 1st STARTUP would then terminate
2720 * immediately, and the previously started INIT IPI would continue. OR
2721 * the previous INIT IPI has already run. and this STARTUP IPI will
2722 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2725 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2726 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2728 u_sleep(200); /* wait ~200uS */
2731 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2732 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2733 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2734 * recognized after hardware RESET or INIT IPI.
2736 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2737 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2740 /* Resume normal operation */
2743 /* wait for it to start, see ap_init() */
2744 set_apic_timer(5000000);/* == 5 seconds */
2745 while (read_apic_timer()) {
2746 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2747 return 1; /* return SUCCESS */
2750 return 0; /* return FAILURE */
2765 while (read_apic_timer()) {
2767 for (count = 0; count < 100; ++count)
2768 ntsc = rdtsc(); /* force loop to occur */
2770 ndelta = ntsc - ltsc;
2771 if (ldelta > ndelta)
2773 if (ndelta > ldelta * 2)
2776 ldelta = ntsc - ltsc;
2779 return(read_apic_timer());
2783 * Synchronously flush the TLB on all other CPU's. The current cpu's
2784 * TLB is not flushed. If the caller wishes to flush the current cpu's
2785 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
2787 * NOTE: If for some reason we were unable to start all cpus we cannot
2788 * safely use broadcast IPIs.
2791 static cpumask_t smp_invltlb_req;
2797 struct mdglobaldata *md = mdcpu;
2798 #ifdef SMP_INVLTLB_DEBUG
2803 crit_enter_gd(&md->mi);
2804 md->gd_invltlb_ret = 0;
2805 ++md->mi.gd_cnt.v_smpinvltlb;
2806 atomic_set_int(&smp_invltlb_req, md->mi.gd_cpumask);
2807 #ifdef SMP_INVLTLB_DEBUG
2810 if (smp_startup_mask == smp_active_mask) {
2811 all_but_self_ipi(XINVLTLB_OFFSET);
2813 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2814 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
2817 #ifdef SMP_INVLTLB_DEBUG
2819 kprintf("smp_invltlb: ipi sent\n");
2821 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2822 (smp_active_mask & ~md->mi.gd_cpumask)) {
2825 #ifdef SMP_INVLTLB_DEBUG
2827 if (++count == 400000000) {
2828 print_backtrace(-1);
2829 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2830 "rflags %016jx retry",
2831 (long)md->gd_invltlb_ret,
2832 (long)smp_invltlb_req,
2833 (intmax_t)read_rflags());
2834 __asm __volatile ("sti");
2837 lwkt_process_ipiq();
2839 int bcpu = bsfl(~md->gd_invltlb_ret & ~md->mi.gd_cpumask & smp_active_mask);
2842 kprintf("bcpu %d\n", bcpu);
2843 xgd = globaldata_find(bcpu);
2844 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2847 Debugger("giving up");
2853 atomic_clear_int(&smp_invltlb_req, md->mi.gd_cpumask);
2854 crit_exit_gd(&md->mi);
2861 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2862 * bother to bump the critical section count or nested interrupt count
2863 * so only do very low level operations here.
2866 smp_invltlb_intr(void)
2868 struct mdglobaldata *md = mdcpu;
2869 struct mdglobaldata *omd;
2874 mask = smp_invltlb_req;
2878 mask &= ~(1 << cpu);
2879 omd = (struct mdglobaldata *)globaldata_find(cpu);
2880 atomic_set_int(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2887 * When called the executing CPU will send an IPI to all other CPUs
2888 * requesting that they halt execution.
2890 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2892 * - Signals all CPUs in map to stop.
2893 * - Waits for each to stop.
2900 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2901 * from executing at same time.
2904 stop_cpus(u_int map)
2906 map &= smp_active_mask;
2908 /* send the Xcpustop IPI to all CPUs in map */
2909 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2911 while ((stopped_cpus & map) != map)
2919 * Called by a CPU to restart stopped CPUs.
2921 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2923 * - Signals all CPUs in map to restart.
2924 * - Waits for each to restart.
2932 restart_cpus(u_int map)
2934 /* signal other cpus to restart */
2935 started_cpus = map & smp_active_mask;
2937 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2944 * This is called once the mpboot code has gotten us properly relocated
2945 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2946 * and when it returns the scheduler will call the real cpu_idle() main
2947 * loop for the idlethread. Interrupts are disabled on entry and should
2948 * remain disabled at return.
2956 * Adjust smp_startup_mask to signal the BSP that we have started
2957 * up successfully. Note that we do not yet hold the BGL. The BSP
2958 * is waiting for our signal.
2960 * We can't set our bit in smp_active_mask yet because we are holding
2961 * interrupts physically disabled and remote cpus could deadlock
2962 * trying to send us an IPI.
2964 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2968 * Interlock for finalization. Wait until mp_finish is non-zero,
2969 * then get the MP lock.
2971 * Note: We are in a critical section.
2973 * Note: We have to synchronize td_mpcount to our desired MP state
2974 * before calling cpu_try_mplock().
2976 * Note: we are the idle thread, we can only spin.
2978 * Note: The load fence is memory volatile and prevents the compiler
2979 * from improperly caching mp_finish, and the cpu from improperly
2982 while (mp_finish == 0)
2984 ++curthread->td_mpcount;
2985 while (cpu_try_mplock() == 0)
2988 if (cpu_feature & CPUID_TSC) {
2990 * The BSP is constantly updating tsc0_offset, figure out the
2991 * relative difference to synchronize ktrdump.
2993 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2996 /* BSP may have changed PTD while we're waiting for the lock */
2999 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
3003 /* Build our map of 'other' CPUs. */
3004 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
3006 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
3008 /* A quick check from sanity claus */
3009 apic_id = (apic_id_to_logical[(lapic->id & 0x0f000000) >> 24]);
3010 if (mycpu->gd_cpuid != apic_id) {
3011 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
3012 kprintf("SMP: apic_id = %d\n", apic_id);
3014 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
3016 panic("cpuid mismatch! boom!!");
3019 /* Initialize AP's local APIC for irq's */
3020 apic_initialize(FALSE);
3022 /* Set memory range attributes for this CPU to match the BSP */
3023 mem_range_AP_init();
3026 * Once we go active we must process any IPIQ messages that may
3027 * have been queued, because no actual IPI will occur until we
3028 * set our bit in the smp_active_mask. If we don't the IPI
3029 * message interlock could be left set which would also prevent
3032 * The idle loop doesn't expect the BGL to be held and while
3033 * lwkt_switch() normally cleans things up this is a special case
3034 * because we returning almost directly into the idle loop.
3036 * The idle thread is never placed on the runq, make sure
3037 * nothing we've done put it there.
3039 KKASSERT(curthread->td_mpcount == 1);
3040 smp_active_mask |= 1 << mycpu->gd_cpuid;
3043 * Enable interrupts here. idle_restore will also do it, but
3044 * doing it here lets us clean up any strays that got posted to
3045 * the CPU during the AP boot while we are still in a critical
3048 __asm __volatile("sti; pause; pause"::);
3049 mdcpu->gd_fpending = 0;
3051 initclocks_pcpu(); /* clock interrupts (via IPIs) */
3052 lwkt_process_ipiq();
3055 * Releasing the mp lock lets the BSP finish up the SMP init
3058 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
3062 * Get SMP fully working before we start initializing devices.
3070 kprintf("Finish MP startup\n");
3071 if (cpu_feature & CPUID_TSC)
3072 tsc0_offset = rdtsc();
3075 while (smp_active_mask != smp_startup_mask) {
3077 if (cpu_feature & CPUID_TSC)
3078 tsc0_offset = rdtsc();
3080 while (try_mplock() == 0)
3083 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
3086 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
3089 cpu_send_ipiq(int dcpu)
3091 if ((1 << dcpu) & smp_active_mask)
3092 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
3095 #if 0 /* single_apic_ipi_passive() not working yet */
3097 * Returns 0 on failure, 1 on success
3100 cpu_send_ipiq_passive(int dcpu)
3103 if ((1 << dcpu) & smp_active_mask) {
3104 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
3105 APIC_DELMODE_FIXED);