1 /**************************************************************************
3 ** $FreeBSD: src/sys/pci/pcisupport.c,v 1.154.2.15 2003/04/29 15:55:06 simokawa Exp $
4 ** $DragonFly: src/sys/bus/pci/pcisupport.c,v 1.8 2004/01/15 20:35:06 joerg Exp $
6 ** Device driver for DEC/INTEL PCI chipsets.
10 **-------------------------------------------------------------------------
12 ** Written for FreeBSD by
13 ** wolf@cologne.de Wolfgang Stanglmeier
14 ** se@mi.Uni-Koeln.de Stefan Esser
16 **-------------------------------------------------------------------------
18 ** Copyright (c) 1994,1995 Stefan Esser. All rights reserved.
20 ** Redistribution and use in source and binary forms, with or without
21 ** modification, are permitted provided that the following conditions
23 ** 1. Redistributions of source code must retain the above copyright
24 ** notice, this list of conditions and the following disclaimer.
25 ** 2. Redistributions in binary form must reproduce the above copyright
26 ** notice, this list of conditions and the following disclaimer in the
27 ** documentation and/or other materials provided with the distribution.
28 ** 3. The name of the author may not be used to endorse or promote products
29 ** derived from this software without specific prior written permission.
31 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
32 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
33 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
34 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
35 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
36 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
40 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 ***************************************************************************
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/malloc.h>
51 #include <sys/kernel.h>
58 #include <vm/vm_object.h>
63 /*---------------------------------------------------------
65 ** Intel chipsets for 486 / Pentium processor
67 **---------------------------------------------------------
70 static void chipset_attach(device_t dev, int unit);
82 fixbushigh_i1225(device_t dev)
86 sublementarybus = pci_read_config(dev, 0x41, 1);
87 if (sublementarybus != 0xff) {
88 pci_set_secondarybus(dev, sublementarybus + 1);
89 pci_set_subordinatebus(dev, sublementarybus + 1);
94 fixwsc_natoma(device_t dev)
98 pmccfg = pci_read_config(dev, 0x50, 2);
100 if (pmccfg & 0x8000) {
101 printf("Correcting Natoma config for SMP\n");
103 pci_write_config(dev, 0x50, pmccfg, 2);
106 if ((pmccfg & 0x8000) == 0) {
107 printf("Correcting Natoma config for non-SMP\n");
109 pci_write_config(dev, 0x50, pmccfg, 2);
116 #define M_XX 0 /* end of list */
117 #define M_EQ 1 /* mask and return true if equal */
118 #define M_NE 2 /* mask and return true if not equal */
119 #define M_TR 3 /* don't read config, always true */
120 #define M_EN 4 /* mask and print "enabled" if true, "disabled" if false */
121 #define M_NN 5 /* opposite sense of M_EN */
123 static const struct condmsg conf82425ex[] =
125 { 0x00, 0x00, 0x00, M_TR, "\tClock " },
126 { 0x50, 0x06, 0x00, M_EQ, "25" },
127 { 0x50, 0x06, 0x02, M_EQ, "33" },
128 { 0x50, 0x04, 0x04, M_EQ, "??", },
129 { 0x00, 0x00, 0x00, M_TR, "MHz, L1 Cache " },
130 { 0x50, 0x01, 0x00, M_EQ, "Disabled\n" },
131 { 0x50, 0x09, 0x01, M_EQ, "Write-through\n" },
132 { 0x50, 0x09, 0x09, M_EQ, "Write-back\n" },
134 { 0x00, 0x00, 0x00, M_TR, "\tL2 Cache " },
135 { 0x52, 0x07, 0x00, M_EQ, "Disabled" },
136 { 0x52, 0x0f, 0x01, M_EQ, "64KB Write-through" },
137 { 0x52, 0x0f, 0x02, M_EQ, "128KB Write-through" },
138 { 0x52, 0x0f, 0x03, M_EQ, "256KB Write-through" },
139 { 0x52, 0x0f, 0x04, M_EQ, "512KB Write-through" },
140 { 0x52, 0x0f, 0x01, M_EQ, "64KB Write-back" },
141 { 0x52, 0x0f, 0x02, M_EQ, "128KB Write-back" },
142 { 0x52, 0x0f, 0x03, M_EQ, "256KB Write-back" },
143 { 0x52, 0x0f, 0x04, M_EQ, "512KB Write-back" },
144 { 0x53, 0x01, 0x00, M_EQ, ", 3-" },
145 { 0x53, 0x01, 0x01, M_EQ, ", 2-" },
146 { 0x53, 0x06, 0x00, M_EQ, "3-3-3" },
147 { 0x53, 0x06, 0x02, M_EQ, "2-2-2" },
148 { 0x53, 0x06, 0x04, M_EQ, "1-1-1" },
149 { 0x53, 0x06, 0x06, M_EQ, "?-?-?" },
150 { 0x53, 0x18, 0x00, M_EQ, "/4-2-2-2\n" },
151 { 0x53, 0x18, 0x08, M_EQ, "/3-2-2-2\n" },
152 { 0x53, 0x18, 0x10, M_EQ, "/?-?-?-?\n" },
153 { 0x53, 0x18, 0x18, M_EQ, "/2-1-1-1\n" },
155 { 0x56, 0x00, 0x00, M_TR, "\tDRAM: " },
156 { 0x56, 0x02, 0x02, M_EQ, "Fast Code Read, " },
157 { 0x56, 0x04, 0x04, M_EQ, "Fast Data Read, " },
158 { 0x56, 0x08, 0x08, M_EQ, "Fast Write, " },
159 { 0x57, 0x20, 0x20, M_EQ, "Pipelined CAS" },
160 { 0x57, 0x2e, 0x00, M_NE, "\n\t" },
161 { 0x57, 0x00, 0x00, M_TR, "Timing: RAS: " },
162 { 0x57, 0x07, 0x00, M_EQ, "4" },
163 { 0x57, 0x07, 0x01, M_EQ, "3" },
164 { 0x57, 0x07, 0x02, M_EQ, "2" },
165 { 0x57, 0x07, 0x04, M_EQ, "1.5" },
166 { 0x57, 0x07, 0x05, M_EQ, "1" },
167 { 0x57, 0x00, 0x00, M_TR, " Clocks, CAS Read: " },
168 { 0x57, 0x18, 0x00, M_EQ, "3/1", },
169 { 0x57, 0x18, 0x00, M_EQ, "2/1", },
170 { 0x57, 0x18, 0x00, M_EQ, "1.5/0.5", },
171 { 0x57, 0x18, 0x00, M_EQ, "1/1", },
172 { 0x57, 0x00, 0x00, M_TR, ", CAS Write: " },
173 { 0x57, 0x20, 0x00, M_EQ, "2/1", },
174 { 0x57, 0x20, 0x20, M_EQ, "1/1", },
175 { 0x57, 0x00, 0x00, M_TR, "\n" },
177 { 0x40, 0x01, 0x01, M_EQ, "\tCPU-to-PCI Byte Merging\n" },
178 { 0x40, 0x02, 0x02, M_EQ, "\tCPU-to-PCI Bursting\n" },
179 { 0x40, 0x04, 0x04, M_EQ, "\tPCI Posted Writes\n" },
180 { 0x40, 0x20, 0x00, M_EQ, "\tDRAM Parity Disabled\n" },
182 { 0x48, 0x03, 0x01, M_EQ, "\tPCI IDE controller: Primary (1F0h-1F7h,3F6h,3F7h)" },
183 { 0x48, 0x03, 0x02, M_EQ, "\tPCI IDE controller: Secondary (170h-177h,376h,377h)" },
184 { 0x4d, 0x01, 0x01, M_EQ, "\tRTC (70-77h)\n" },
185 { 0x4d, 0x02, 0x02, M_EQ, "\tKeyboard (60,62,64,66h)\n" },
186 { 0x4d, 0x08, 0x08, M_EQ, "\tIRQ12/M Mouse Function\n" },
192 static const struct condmsg conf82424zx[] =
194 { 0x00, 0x00, 0x00, M_TR, "\tCPU: " },
195 { 0x50, 0xe0, 0x00, M_EQ, "486DX" },
196 { 0x50, 0xe0, 0x20, M_EQ, "486SX" },
197 { 0x50, 0xe0, 0x40, M_EQ, "486DX2 or 486DX4" },
198 { 0x50, 0xe0, 0x80, M_EQ, "Overdrive (writeback)" },
200 { 0x00, 0x00, 0x00, M_TR, ", bus=" },
201 { 0x50, 0x03, 0x00, M_EQ, "25MHz" },
202 { 0x50, 0x03, 0x01, M_EQ, "33MHz" },
203 { 0x53, 0x01, 0x01, M_TR, ", CPU->Memory posting "},
204 { 0x53, 0x01, 0x00, M_EQ, "OFF" },
205 { 0x53, 0x01, 0x01, M_EQ, "ON" },
207 { 0x56, 0x30, 0x00, M_NE, "\n\tWarning:" },
208 { 0x56, 0x20, 0x00, M_NE, " NO cache parity!" },
209 { 0x56, 0x10, 0x00, M_NE, " NO DRAM parity!" },
210 { 0x55, 0x04, 0x04, M_EQ, "\n\tWarning: refresh OFF! " },
212 { 0x00, 0x00, 0x00, M_TR, "\n\tCache: " },
213 { 0x52, 0x01, 0x00, M_EQ, "None" },
214 { 0x52, 0xc1, 0x01, M_EQ, "64KB" },
215 { 0x52, 0xc1, 0x41, M_EQ, "128KB" },
216 { 0x52, 0xc1, 0x81, M_EQ, "256KB" },
217 { 0x52, 0xc1, 0xc1, M_EQ, "512KB" },
218 { 0x52, 0x03, 0x01, M_EQ, " writethrough" },
219 { 0x52, 0x03, 0x03, M_EQ, " writeback" },
221 { 0x52, 0x01, 0x01, M_EQ, ", cache clocks=" },
222 { 0x52, 0x05, 0x01, M_EQ, "3-1-1-1" },
223 { 0x52, 0x05, 0x05, M_EQ, "2-1-1-1" },
225 { 0x00, 0x00, 0x00, M_TR, "\n\tDRAM:" },
226 { 0x55, 0x43, 0x00, M_NE, " page mode" },
227 { 0x55, 0x02, 0x02, M_EQ, " code fetch" },
228 { 0x55, 0x43, 0x43, M_EQ, "," },
229 { 0x55, 0x43, 0x42, M_EQ, " and" },
230 { 0x55, 0x40, 0x40, M_EQ, " read" },
231 { 0x55, 0x03, 0x03, M_EQ, " and" },
232 { 0x55, 0x43, 0x41, M_EQ, " and" },
233 { 0x55, 0x01, 0x01, M_EQ, " write" },
234 { 0x55, 0x43, 0x00, M_NE, "," },
236 { 0x00, 0x00, 0x00, M_TR, " memory clocks=" },
237 { 0x55, 0x20, 0x00, M_EQ, "X-2-2-2" },
238 { 0x55, 0x20, 0x20, M_EQ, "X-1-2-1" },
240 { 0x00, 0x00, 0x00, M_TR, "\n\tCPU->PCI: posting " },
241 { 0x53, 0x02, 0x00, M_NE, "ON" },
242 { 0x53, 0x02, 0x00, M_EQ, "OFF" },
243 { 0x00, 0x00, 0x00, M_TR, ", burst mode " },
244 { 0x54, 0x02, 0x00, M_NE, "ON" },
245 { 0x54, 0x02, 0x00, M_EQ, "OFF" },
246 { 0x00, 0x00, 0x00, M_TR, "\n\tPCI->Memory: posting " },
247 { 0x54, 0x01, 0x00, M_NE, "ON" },
248 { 0x54, 0x01, 0x00, M_EQ, "OFF" },
250 { 0x00, 0x00, 0x00, M_TR, "\n" },
256 static const struct condmsg conf82434lx[] =
258 { 0x00, 0x00, 0x00, M_TR, "\tCPU: " },
259 { 0x50, 0xe3, 0x82, M_EQ, "Pentium, 60MHz" },
260 { 0x50, 0xe3, 0x83, M_EQ, "Pentium, 66MHz" },
261 { 0x50, 0xe3, 0xa2, M_EQ, "Pentium, 90MHz" },
262 { 0x50, 0xe3, 0xa3, M_EQ, "Pentium, 100MHz" },
263 { 0x50, 0xc2, 0x82, M_NE, "(unknown)" },
264 { 0x50, 0x04, 0x00, M_EQ, " (primary cache OFF)" },
266 { 0x53, 0x01, 0x01, M_TR, ", CPU->Memory posting "},
267 { 0x53, 0x01, 0x01, M_NE, "OFF" },
268 { 0x53, 0x01, 0x01, M_EQ, "ON" },
270 { 0x53, 0x08, 0x00, M_NE, ", read around write"},
272 { 0x70, 0x04, 0x00, M_EQ, "\n\tWarning: Cache parity disabled!" },
273 { 0x57, 0x20, 0x00, M_NE, "\n\tWarning: DRAM parity mask!" },
274 { 0x57, 0x01, 0x00, M_EQ, "\n\tWarning: refresh OFF! " },
276 { 0x00, 0x00, 0x00, M_TR, "\n\tCache: " },
277 { 0x52, 0x01, 0x00, M_EQ, "None" },
278 { 0x52, 0x81, 0x01, M_EQ, "" },
279 { 0x52, 0xc1, 0x81, M_EQ, "256KB" },
280 { 0x52, 0xc1, 0xc1, M_EQ, "512KB" },
281 { 0x52, 0x03, 0x01, M_EQ, " writethrough" },
282 { 0x52, 0x03, 0x03, M_EQ, " writeback" },
284 { 0x52, 0x01, 0x01, M_EQ, ", cache clocks=" },
285 { 0x52, 0x21, 0x01, M_EQ, "3-2-2-2/4-2-2-2" },
286 { 0x52, 0x21, 0x21, M_EQ, "3-1-1-1" },
288 { 0x52, 0x01, 0x01, M_EQ, "\n\tCache flags: " },
289 { 0x52, 0x11, 0x11, M_EQ, " cache-all" },
290 { 0x52, 0x09, 0x09, M_EQ, " byte-control" },
291 { 0x52, 0x05, 0x05, M_EQ, " powersaver" },
293 { 0x00, 0x00, 0x00, M_TR, "\n\tDRAM:" },
294 { 0x57, 0x10, 0x00, M_EQ, " page mode" },
296 { 0x00, 0x00, 0x00, M_TR, " memory clocks=" },
297 { 0x57, 0xc0, 0x00, M_EQ, "X-4-4-4 (70ns)" },
298 { 0x57, 0xc0, 0x40, M_EQ, "X-4-4-4/X-3-3-3 (60ns)" },
299 { 0x57, 0xc0, 0x80, M_EQ, "???" },
300 { 0x57, 0xc0, 0xc0, M_EQ, "X-3-3-3 (50ns)" },
301 { 0x58, 0x02, 0x02, M_EQ, ", RAS-wait" },
302 { 0x58, 0x01, 0x01, M_EQ, ", CAS-wait" },
304 { 0x00, 0x00, 0x00, M_TR, "\n\tCPU->PCI: posting " },
305 { 0x53, 0x02, 0x02, M_EQ, "ON" },
306 { 0x53, 0x02, 0x00, M_EQ, "OFF" },
307 { 0x00, 0x00, 0x00, M_TR, ", burst mode " },
308 { 0x54, 0x02, 0x00, M_NE, "ON" },
309 { 0x54, 0x02, 0x00, M_EQ, "OFF" },
310 { 0x54, 0x04, 0x00, M_TR, ", PCI clocks=" },
311 { 0x54, 0x04, 0x00, M_EQ, "2-2-2-2" },
312 { 0x54, 0x04, 0x00, M_NE, "2-1-1-1" },
313 { 0x00, 0x00, 0x00, M_TR, "\n\tPCI->Memory: posting " },
314 { 0x54, 0x01, 0x00, M_NE, "ON" },
315 { 0x54, 0x01, 0x00, M_EQ, "OFF" },
317 { 0x57, 0x01, 0x01, M_EQ, "\n\tRefresh:" },
318 { 0x57, 0x03, 0x03, M_EQ, " CAS#/RAS#(Hidden)" },
319 { 0x57, 0x03, 0x01, M_EQ, " RAS#Only" },
320 { 0x57, 0x05, 0x05, M_EQ, " BurstOf4" },
322 { 0x00, 0x00, 0x00, M_TR, "\n" },
328 static const struct condmsg conf82378[] =
330 { 0x00, 0x00, 0x00, M_TR, "\tBus Modes:" },
331 { 0x41, 0x04, 0x04, M_EQ, " Bus Park," },
332 { 0x41, 0x02, 0x02, M_EQ, " Bus Lock," },
333 { 0x41, 0x02, 0x00, M_EQ, " Resource Lock," },
334 { 0x41, 0x01, 0x01, M_EQ, " GAT" },
335 { 0x4d, 0x20, 0x20, M_EQ, "\n\tCoprocessor errors enabled" },
336 { 0x4d, 0x10, 0x10, M_EQ, "\n\tMouse function enabled" },
338 { 0x4e, 0x30, 0x10, M_EQ, "\n\tIDE controller: Primary (1F0h-1F7h,3F6h,3F7h)" },
339 { 0x4e, 0x30, 0x30, M_EQ, "\n\tIDE controller: Secondary (170h-177h,376h,377h)" },
340 { 0x4e, 0x28, 0x08, M_EQ, "\n\tFloppy controller: 3F0h,3F1h " },
341 { 0x4e, 0x24, 0x04, M_EQ, "\n\tFloppy controller: 3F2h-3F7h " },
342 { 0x4e, 0x28, 0x28, M_EQ, "\n\tFloppy controller: 370h,371h " },
343 { 0x4e, 0x24, 0x24, M_EQ, "\n\tFloppy controller: 372h-377h " },
344 { 0x4e, 0x02, 0x02, M_EQ, "\n\tKeyboard controller: 60h,62h,64h,66h" },
345 { 0x4e, 0x01, 0x01, M_EQ, "\n\tRTC: 70h-77h" },
347 { 0x4f, 0x80, 0x80, M_EQ, "\n\tConfiguration RAM: 0C00h,0800h-08FFh" },
348 { 0x4f, 0x40, 0x40, M_EQ, "\n\tPort 92: enabled" },
349 { 0x4f, 0x03, 0x00, M_EQ, "\n\tSerial Port A: COM1 (3F8h-3FFh)" },
350 { 0x4f, 0x03, 0x01, M_EQ, "\n\tSerial Port A: COM2 (2F8h-2FFh)" },
351 { 0x4f, 0x0c, 0x00, M_EQ, "\n\tSerial Port B: COM1 (3F8h-3FFh)" },
352 { 0x4f, 0x0c, 0x04, M_EQ, "\n\tSerial Port B: COM2 (2F8h-2FFh)" },
353 { 0x4f, 0x30, 0x00, M_EQ, "\n\tParallel Port: LPT1 (3BCh-3BFh)" },
354 { 0x4f, 0x30, 0x04, M_EQ, "\n\tParallel Port: LPT2 (378h-37Fh)" },
355 { 0x4f, 0x30, 0x20, M_EQ, "\n\tParallel Port: LPT3 (278h-27Fh)" },
356 { 0x00, 0x00, 0x00, M_TR, "\n" },
362 static const struct condmsg conf82437fx[] =
364 /* PCON -- PCI Control Register */
365 { 0x00, 0x00, 0x00, M_TR, "\tCPU Inactivity timer: " },
366 { 0x50, 0xe0, 0xe0, M_EQ, "8" },
367 { 0x50, 0xe0, 0xd0, M_EQ, "7" },
368 { 0x50, 0xe0, 0xc0, M_EQ, "6" },
369 { 0x50, 0xe0, 0xb0, M_EQ, "5" },
370 { 0x50, 0xe0, 0xa0, M_EQ, "4" },
371 { 0x50, 0xe0, 0x90, M_EQ, "3" },
372 { 0x50, 0xe0, 0x80, M_EQ, "2" },
373 { 0x50, 0xe0, 0x00, M_EQ, "1" },
374 { 0x00, 0x00, 0x00, M_TR, " clocks\n\tPeer Concurrency: " },
375 { 0x50, 0x08, 0x08, M_EN, 0 },
376 { 0x00, 0x00, 0x00, M_TR, "\n\tCPU-to-PCI Write Bursting: " },
377 { 0x50, 0x04, 0x00, M_NN, 0 },
378 { 0x00, 0x00, 0x00, M_TR, "\n\tPCI Streaming: " },
379 { 0x50, 0x02, 0x00, M_NN, 0 },
380 { 0x00, 0x00, 0x00, M_TR, "\n\tBus Concurrency: " },
381 { 0x50, 0x01, 0x00, M_NN, 0 },
383 /* CC -- Cache Control Regsiter */
384 { 0x00, 0x00, 0x00, M_TR, "\n\tCache:" },
385 { 0x52, 0xc0, 0x80, M_EQ, " 512K" },
386 { 0x52, 0xc0, 0x40, M_EQ, " 256K" },
387 { 0x52, 0xc0, 0x00, M_EQ, " NO" },
388 { 0x52, 0x30, 0x00, M_EQ, " pipelined-burst" },
389 { 0x52, 0x30, 0x10, M_EQ, " burst" },
390 { 0x52, 0x30, 0x20, M_EQ, " asynchronous" },
391 { 0x52, 0x30, 0x30, M_EQ, " dual-bank pipelined-burst" },
392 { 0x00, 0x00, 0x00, M_TR, " secondary; L1 " },
393 { 0x52, 0x01, 0x00, M_EN, 0 },
394 { 0x00, 0x00, 0x00, M_TR, "\n" },
396 /* DRAMC -- DRAM Control Register */
397 { 0x57, 0x07, 0x00, M_EQ, "Warning: refresh OFF!\n" },
398 { 0x00, 0x00, 0x00, M_TR, "\tDRAM:" },
399 { 0x57, 0xc0, 0x00, M_EQ, " no memory hole" },
400 { 0x57, 0xc0, 0x40, M_EQ, " 512K-640K memory hole" },
401 { 0x57, 0xc0, 0x80, M_EQ, " 15M-16M memory hole" },
402 { 0x57, 0x07, 0x01, M_EQ, ", 50 MHz refresh" },
403 { 0x57, 0x07, 0x02, M_EQ, ", 60 MHz refresh" },
404 { 0x57, 0x07, 0x03, M_EQ, ", 66 MHz refresh" },
406 /* DRAMT = DRAM Timing Register */
407 { 0x00, 0x00, 0x00, M_TR, "\n\tRead burst timing: " },
408 { 0x58, 0x60, 0x00, M_EQ, "x-4-4-4/x-4-4-4" },
409 { 0x58, 0x60, 0x20, M_EQ, "x-3-3-3/x-4-4-4" },
410 { 0x58, 0x60, 0x40, M_EQ, "x-2-2-2/x-3-3-3" },
411 { 0x58, 0x60, 0x60, M_EQ, "???" },
412 { 0x00, 0x00, 0x00, M_TR, "\n\tWrite burst timing: " },
413 { 0x58, 0x18, 0x00, M_EQ, "x-4-4-4" },
414 { 0x58, 0x18, 0x08, M_EQ, "x-3-3-3" },
415 { 0x58, 0x18, 0x10, M_EQ, "x-2-2-2" },
416 { 0x58, 0x18, 0x18, M_EQ, "???" },
417 { 0x00, 0x00, 0x00, M_TR, "\n\tRAS-CAS delay: " },
418 { 0x58, 0x04, 0x00, M_EQ, "3" },
419 { 0x58, 0x04, 0x04, M_EQ, "2" },
420 { 0x00, 0x00, 0x00, M_TR, " clocks\n" },
426 static const struct condmsg conf82437vx[] =
428 /* PCON -- PCI Control Register */
429 { 0x00, 0x00, 0x00, M_TR, "\n\tPCI Concurrency: " },
430 { 0x50, 0x08, 0x08, M_EN, 0 },
432 /* CC -- Cache Control Regsiter */
433 { 0x00, 0x00, 0x00, M_TR, "\n\tCache:" },
434 { 0x52, 0xc0, 0x80, M_EQ, " 512K" },
435 { 0x52, 0xc0, 0x40, M_EQ, " 256K" },
436 { 0x52, 0xc0, 0x00, M_EQ, " NO" },
437 { 0x52, 0x30, 0x00, M_EQ, " pipelined-burst" },
438 { 0x52, 0x30, 0x10, M_EQ, " burst" },
439 { 0x52, 0x30, 0x20, M_EQ, " asynchronous" },
440 { 0x52, 0x30, 0x30, M_EQ, " dual-bank pipelined-burst" },
441 { 0x00, 0x00, 0x00, M_TR, " secondary; L1 " },
442 { 0x52, 0x01, 0x00, M_EN, 0 },
443 { 0x00, 0x00, 0x00, M_TR, "\n" },
445 /* DRAMC -- DRAM Control Register */
446 { 0x57, 0x07, 0x00, M_EQ, "Warning: refresh OFF!\n" },
447 { 0x00, 0x00, 0x00, M_TR, "\tDRAM:" },
448 { 0x57, 0xc0, 0x00, M_EQ, " no memory hole" },
449 { 0x57, 0xc0, 0x40, M_EQ, " 512K-640K memory hole" },
450 { 0x57, 0xc0, 0x80, M_EQ, " 15M-16M memory hole" },
451 { 0x57, 0x07, 0x01, M_EQ, ", 50 MHz refresh" },
452 { 0x57, 0x07, 0x02, M_EQ, ", 60 MHz refresh" },
453 { 0x57, 0x07, 0x03, M_EQ, ", 66 MHz refresh" },
455 /* DRAMT = DRAM Timing Register */
456 { 0x00, 0x00, 0x00, M_TR, "\n\tRead burst timing: " },
457 { 0x58, 0x60, 0x00, M_EQ, "x-4-4-4/x-4-4-4" },
458 { 0x58, 0x60, 0x20, M_EQ, "x-3-3-3/x-4-4-4" },
459 { 0x58, 0x60, 0x40, M_EQ, "x-2-2-2/x-3-3-3" },
460 { 0x58, 0x60, 0x60, M_EQ, "???" },
461 { 0x00, 0x00, 0x00, M_TR, "\n\tWrite burst timing: " },
462 { 0x58, 0x18, 0x00, M_EQ, "x-4-4-4" },
463 { 0x58, 0x18, 0x08, M_EQ, "x-3-3-3" },
464 { 0x58, 0x18, 0x10, M_EQ, "x-2-2-2" },
465 { 0x58, 0x18, 0x18, M_EQ, "???" },
466 { 0x00, 0x00, 0x00, M_TR, "\n\tRAS-CAS delay: " },
467 { 0x58, 0x04, 0x00, M_EQ, "3" },
468 { 0x58, 0x04, 0x04, M_EQ, "2" },
469 { 0x00, 0x00, 0x00, M_TR, " clocks\n" },
475 static const struct condmsg conf82371fb[] =
477 /* IORT -- ISA I/O Recovery Timer Register */
478 { 0x00, 0x00, 0x00, M_TR, "\tI/O Recovery Timing: 8-bit " },
479 { 0x4c, 0x40, 0x00, M_EQ, "3.5" },
480 { 0x4c, 0x78, 0x48, M_EQ, "1" },
481 { 0x4c, 0x78, 0x50, M_EQ, "2" },
482 { 0x4c, 0x78, 0x58, M_EQ, "3" },
483 { 0x4c, 0x78, 0x60, M_EQ, "4" },
484 { 0x4c, 0x78, 0x68, M_EQ, "5" },
485 { 0x4c, 0x78, 0x70, M_EQ, "6" },
486 { 0x4c, 0x78, 0x78, M_EQ, "7" },
487 { 0x4c, 0x78, 0x40, M_EQ, "8" },
488 { 0x00, 0x00, 0x00, M_TR, " clocks, 16-bit " },
489 { 0x4c, 0x04, 0x00, M_EQ, "3.5" },
490 { 0x4c, 0x07, 0x05, M_EQ, "1" },
491 { 0x4c, 0x07, 0x06, M_EQ, "2" },
492 { 0x4c, 0x07, 0x07, M_EQ, "3" },
493 { 0x4c, 0x07, 0x04, M_EQ, "4" },
494 { 0x00, 0x00, 0x00, M_TR, " clocks\n" },
496 /* XBCS -- X-Bus Chip Select Register */
497 { 0x00, 0x00, 0x00, M_TR, "\tExtended BIOS: " },
498 { 0x4e, 0x80, 0x80, M_EN, 0 },
499 { 0x00, 0x00, 0x00, M_TR, "\n\tLower BIOS: " },
500 { 0x4e, 0x40, 0x40, M_EN, 0 },
501 { 0x00, 0x00, 0x00, M_TR, "\n\tCoprocessor IRQ13: " },
502 { 0x4e, 0x20, 0x20, M_EN, 0 },
503 { 0x00, 0x00, 0x00, M_TR, "\n\tMouse IRQ12: " },
504 { 0x4e, 0x10, 0x10, M_EN, 0 },
505 { 0x00, 0x00, 0x00, M_TR, "\n" },
507 { 0x00, 0x00, 0x00, M_TR, "\tInterrupt Routing: " },
509 { 0x00, 0x00, 0x00, M_TR, n ": " }, \
510 { x, 0x80, 0x80, M_EQ, "disabled" }, \
511 { x, 0xc0, 0x40, M_EQ, "[shared] " }, \
512 { x, 0x8f, 0x03, M_EQ, "IRQ3" }, \
513 { x, 0x8f, 0x04, M_EQ, "IRQ4" }, \
514 { x, 0x8f, 0x05, M_EQ, "IRQ5" }, \
515 { x, 0x8f, 0x06, M_EQ, "IRQ6" }, \
516 { x, 0x8f, 0x07, M_EQ, "IRQ7" }, \
517 { x, 0x8f, 0x09, M_EQ, "IRQ9" }, \
518 { x, 0x8f, 0x0a, M_EQ, "IRQ10" }, \
519 { x, 0x8f, 0x0b, M_EQ, "IRQ11" }, \
520 { x, 0x8f, 0x0c, M_EQ, "IRQ12" }, \
521 { x, 0x8f, 0x0e, M_EQ, "IRQ14" }, \
522 { x, 0x8f, 0x0f, M_EQ, "IRQ15" }
524 /* Interrupt routing */
529 PIRQ(0x70, "\n\t\tMB0"),
532 { 0x00, 0x00, 0x00, M_TR, "\n" },
536 /* XXX - do DMA routing, too? */
540 static const struct condmsg conf82371fb2[] =
542 /* IDETM -- IDE Timing Register */
543 { 0x00, 0x00, 0x00, M_TR, "\tPrimary IDE: " },
544 { 0x41, 0x80, 0x80, M_EN, 0 },
545 { 0x00, 0x00, 0x00, M_TR, "\n\tSecondary IDE: " },
546 { 0x43, 0x80, 0x80, M_EN, 0 },
547 { 0x00, 0x00, 0x00, M_TR, "\n" },
554 writeconfig (device_t dev, const struct condmsg *tbl)
556 while (tbl->flags != M_XX) {
557 const char *text = 0;
559 if (tbl->flags == M_TR) {
562 unsigned char v = pci_read_config(dev, tbl->port, 1);
563 switch (tbl->flags) {
565 if ((v & tbl->mask) == tbl->value) text = tbl->text;
568 if ((v & tbl->mask) != tbl->value) text = tbl->text;
571 text = (v & tbl->mask) ? "enabled" : "disabled";
574 text = (v & tbl->mask) ? "disabled" : "enabled";
577 if (text) printf ("%s", text);
582 #ifdef DUMPCONFIGSPACE
584 dumpconfigspace (device_t dev)
587 printf ("configuration space registers:");
588 for (reg = 0; reg < 0x100; reg+=4) {
589 if ((reg & 0x0f) == 0)
590 printf ("\n%02x:\t", reg);
591 printf ("%08x ", pci_read_config(dev, reg, 4));
595 #endif /* DUMPCONFIGSPACE */
597 #endif /* PCI_QUIET */
601 chipset_attach (device_t dev, int unit)
607 switch (pci_get_devid(dev)) {
609 writeconfig (dev, conf82425ex);
612 writeconfig (dev, conf82424zx);
615 writeconfig (dev, conf82434lx);
618 writeconfig (dev, conf82378);
621 writeconfig (dev, conf82437fx);
624 writeconfig (dev, conf82437vx);
628 writeconfig (dev, conf82371fb);
632 writeconfig (dev, conf82371fb2);
635 case 0x00011011: /* DEC 21050 */
636 case 0x00221014: /* IBM xxx */
637 writeconfig (dev, conf_pci2pci);
641 #endif /* PCI_QUIET */
645 pci_bridge_type(device_t dev)
647 char *descr, tmpbuf[120];
649 if (pci_get_class(dev) != PCIC_BRIDGE)
652 switch (pci_get_subclass(dev)) {
653 case PCIS_BRIDGE_HOST: strcpy(tmpbuf, "Host to PCI"); break;
654 case PCIS_BRIDGE_ISA: strcpy(tmpbuf, "PCI to ISA"); break;
655 case PCIS_BRIDGE_EISA: strcpy(tmpbuf, "PCI to EISA"); break;
656 case PCIS_BRIDGE_MCA: strcpy(tmpbuf, "PCI to MCA"); break;
657 case PCIS_BRIDGE_PCI: strcpy(tmpbuf, "PCI to PCI"); break;
658 case PCIS_BRIDGE_PCMCIA: strcpy(tmpbuf, "PCI to PCMCIA"); break;
659 case PCIS_BRIDGE_NUBUS: strcpy(tmpbuf, "PCI to NUBUS"); break;
660 case PCIS_BRIDGE_CARDBUS: strcpy(tmpbuf, "PCI to CardBus"); break;
661 case PCIS_BRIDGE_OTHER: strcpy(tmpbuf, "PCI to Other"); break;
663 snprintf(tmpbuf, sizeof(tmpbuf),
664 "PCI to 0x%x", pci_get_subclass(dev));
667 snprintf(tmpbuf+strlen(tmpbuf), sizeof(tmpbuf)-strlen(tmpbuf),
668 " bridge (vendor=%04x device=%04x)",
669 pci_get_vendor(dev), pci_get_device(dev));
670 descr = malloc (strlen(tmpbuf) +1, M_DEVBUF, M_WAITOK);
671 strcpy(descr, tmpbuf);
676 pcib_match(device_t dev)
678 switch (pci_get_devid(dev)) {
679 /* Intel -- vendor 0x8086 */
681 return ("Intel 82443LX (440 LX) PCI-PCI (AGP) bridge");
683 return ("Intel 82443BX (440 BX) PCI-PCI (AGP) bridge");
685 return ("Intel 82443GX (440 GX) PCI-PCI (AGP) bridge");
687 return ("Intel 82454NX PCI Expander Bridge");
689 return ("Intel 82801BA/BAM (ICH2) PCI-PCI (AGP) bridge");
691 return ("Intel 82380FB mobile PCI to PCI bridge");
693 return ("Intel 82801AA (ICH) Hub to PCI bridge");
695 return ("Intel 82801AB (ICH0) Hub to PCI bridge");
697 return ("Intel 82801BA/BAM (ICH2) Hub to PCI bridge");
699 return ("Intel 82845 PCI-PCI (AGP) bridge");
701 /* VLSI -- vendor 0x1004 */
703 return ("VLSI 82C534 Eagle II PCI Bus bridge");
705 return ("VLSI 82C538 Eagle II PCI Docking bridge");
707 /* VIA Technologies -- vendor 0x1106 */
709 return ("VIA 8363 (Apollo KT133) PCI-PCI (AGP) bridge");
711 return ("VIA 82C598MVP (Apollo MVP3) PCI-PCI (AGP) bridge");
712 /* Exclude the ACPI function of VT82Cxxx series */
718 /* AcerLabs -- vendor 0x10b9 */
719 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
720 /* id is '10b9" but the register always shows "10b9". -Foxfair */
722 return ("AcerLabs M5247 PCI-PCI(AGP Supported) bridge");
723 case 0x524310b9:/* 5243 seems like 5247, need more info to divide*/
724 return ("AcerLabs M5243 PCI-PCI bridge");
726 /* AMD -- vendor 0x1022 */
728 return ("AMD-751 PCI-PCI (1x/2x AGP) bridge");
730 return ("AMD-761 PCI-PCI (4x AGP) bridge");
732 /* DEC -- vendor 0x1011 */
734 return ("DEC 21050 PCI-PCI bridge");
736 return ("DEC 21052 PCI-PCI bridge");
738 return ("DEC 21150 PCI-PCI bridge");
740 return ("DEC 21152 PCI-PCI bridge");
742 return ("DEC 21153 PCI-PCI bridge");
744 return ("DEC 21154 PCI-PCI bridge");
746 /* NVIDIA -- vendor 0x10de */
749 return ("NVIDIA nForce2 PCI-PCI bridge");
753 return ("IBM 82351 PCI-PCI bridge");
754 /* UMC United Microelectronics 0x1060 */
756 return ("UMC UM8881 HB4 486 PCI Chipset");
759 if (pci_get_class(dev) == PCIC_BRIDGE
760 && pci_get_subclass(dev) == PCIS_BRIDGE_PCI)
761 return pci_bridge_type(dev);
766 static int pcib_probe(device_t dev)
770 desc = pcib_match(dev);
772 device_set_desc_copy(dev, desc);
779 static int pcib_attach(device_t dev)
784 chipset_attach(dev, device_get_unit(dev));
786 secondary = pci_get_secondarybus(dev);
788 child = device_add_child(dev, "pci", -1);
789 *(int*) device_get_softc(dev) = secondary;
790 return bus_generic_attach(dev);
796 pcib_read_ivar(device_t dev, device_t child, int which, u_long *result)
800 *result = *(int*) device_get_softc(dev);
807 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
811 *(int*) device_get_softc(dev) = value;
818 pcib_maxslots(device_t dev)
824 pcib_read_config(device_t dev, int b, int s, int f,
828 * Pass through to the next ppb up the chain (i.e. our
831 return PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)),
832 b, s, f, reg, width);
836 pcib_write_config(device_t dev, int b, int s, int f,
837 int reg, int val, int width)
840 * Pass through to the next ppb up the chain (i.e. our
843 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)),
844 b, s, f, reg, val, width);
848 * Route an interrupt across a PCI bridge.
851 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
857 device_printf(pcib, "Hi!\n");
861 * The PCI standard defines a swizzle of the child-side device/intpin
862 * to the parent-side intpin as follows.
864 * device = device on child bus
865 * child_intpin = intpin on child bus slot (0-3)
866 * parent_intpin = intpin on parent bus slot (0-3)
868 * parent_intpin = (device + child_intpin) % 4
870 parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4;
873 * Our parent is a PCI bus. Its parent must export the pci interface
874 * which includes the ability to route interrupts.
876 bus = device_get_parent(pcib);
877 intnum = PCI_ROUTE_INTERRUPT(device_get_parent(bus), pcib,
879 device_printf(pcib, "routed slot %d INT%c to irq %d\n",
880 pci_get_slot(dev), 'A' + pin - 1, intnum);
884 static device_method_t pcib_methods[] = {
885 /* Device interface */
886 DEVMETHOD(device_probe, pcib_probe),
887 DEVMETHOD(device_attach, pcib_attach),
888 DEVMETHOD(device_shutdown, bus_generic_shutdown),
889 DEVMETHOD(device_suspend, bus_generic_suspend),
890 DEVMETHOD(device_resume, bus_generic_resume),
893 DEVMETHOD(bus_print_child, bus_generic_print_child),
894 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
895 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
896 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
897 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
898 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
899 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
900 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
901 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
904 DEVMETHOD(pci_route_interrupt, pcib_route_interrupt),
907 DEVMETHOD(pcib_maxslots, pcib_maxslots),
908 DEVMETHOD(pcib_read_config, pcib_read_config),
909 DEVMETHOD(pcib_write_config, pcib_write_config),
914 static driver_t pcib_driver = {
920 static devclass_t pcib_devclass;
922 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
925 eisab_match(device_t dev)
927 switch (pci_get_devid(dev)) {
929 /* Recognize this specifically, it has PCI-HOST class (!) */
930 return ("Intel 82375EB PCI-EISA bridge");
932 if (pci_get_class(dev) == PCIC_BRIDGE
933 && pci_get_subclass(dev) == PCIS_BRIDGE_EISA)
934 return pci_bridge_type(dev);
940 isab_match(device_t dev)
944 switch (pci_get_devid(dev)) {
946 rev = pci_get_revid(dev);
948 return ("Intel 82378ZB PCI to ISA bridge");
949 return ("Intel 82378IB PCI to ISA bridge");
951 return ("Intel 82371FB PCI to ISA bridge");
953 return ("Intel 82371SB PCI to ISA bridge");
955 return ("Intel 82371AB PCI to ISA bridge");
957 return ("Intel 82443MX PCI to ISA bridge");
959 return ("Intel 82801AA (ICH) PCI to LPC bridge");
961 return ("Intel 82801AB (ICH0) PCI to LPC bridge");
963 return ("Intel 82801BA/BAM (ICH2) PCI to LPC bridge");
965 /* NVIDIA -- vendor 0x10de */
967 return ("NVIDIA nForce2 PCI to ISA bridge");
969 /* VLSI -- vendor 0x1004 */
971 return ("VLSI 82C593 PCI to ISA bridge");
973 /* VIA Technologies -- vendor 0x1106 */
974 case 0x05861106: /* south bridge section */
975 return ("VIA 82C586 PCI-ISA bridge");
977 return ("VIA 82C596B PCI-ISA bridge");
979 return ("VIA 82C686 PCI-ISA bridge");
981 /* AcerLabs -- vendor 0x10b9 */
982 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
983 /* id is '10b9" but the register always shows "10b9". -Foxfair */
985 return ("AcerLabs M1533 portable PCI-ISA bridge");
987 return ("AcerLabs M1543 desktop PCI-ISA bridge");
989 /* SiS -- vendor 0x1039 */
991 return ("SiS 85c503 PCI-ISA bridge");
993 /* Cyrix -- vendor 0x1078 */
995 return ("Cyrix Cx5510 PCI-ISA bridge");
997 return ("Cyrix Cx5530 PCI-ISA bridge");
999 /* NEC -- vendor 0x1033 */
1000 /* The "C-bus" is 16-bits bus on PC98. */
1002 return ("NEC 0001 PCI to PC-98 C-bus bridge");
1004 return ("NEC 002C PCI to PC-98 C-bus bridge");
1006 return ("NEC 003B PCI to PC-98 C-bus bridge");
1007 /* UMC United Microelectronics 0x1060 */
1009 return ("UMC UM8886 ISA Bridge with EIDE");
1011 /* Cypress -- vendor 0x1080 */
1013 if (pci_get_class(dev) == PCIC_BRIDGE
1014 && pci_get_subclass(dev) == PCIS_BRIDGE_ISA)
1015 return ("Cypress 82C693 PCI-ISA bridge");
1018 /* ServerWorks -- vendor 0x1166 */
1020 return ("ServerWorks IB6566 PCI to ISA bridge");
1023 if (pci_get_class(dev) == PCIC_BRIDGE
1024 && pci_get_subclass(dev) == PCIS_BRIDGE_ISA)
1025 return pci_bridge_type(dev);
1031 isab_probe(device_t dev)
1037 desc = eisab_match(dev);
1041 desc = isab_match(dev);
1044 * For a PCI-EISA bridge, add both eisa and isa.
1045 * Only add one instance of eisa or isa for now.
1047 device_set_desc_copy(dev, desc);
1048 if (is_eisa && !devclass_get_device(devclass_find("eisa"), 0))
1049 device_add_child(dev, "eisa", -1);
1051 if (!devclass_get_device(devclass_find("isa"), 0))
1052 device_add_child(dev, "isa", -1);
1059 isab_attach(device_t dev)
1061 chipset_attach(dev, device_get_unit(dev));
1062 return bus_generic_attach(dev);
1065 static device_method_t isab_methods[] = {
1066 /* Device interface */
1067 DEVMETHOD(device_probe, isab_probe),
1068 DEVMETHOD(device_attach, isab_attach),
1069 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1070 DEVMETHOD(device_suspend, bus_generic_suspend),
1071 DEVMETHOD(device_resume, bus_generic_resume),
1074 DEVMETHOD(bus_print_child, bus_generic_print_child),
1075 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
1076 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
1077 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1078 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1079 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1080 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1085 static driver_t isab_driver = {
1091 static devclass_t isab_devclass;
1093 DRIVER_MODULE(isab, pci, isab_driver, isab_devclass, 0, 0);
1096 pci_usb_match(device_t dev)
1098 switch (pci_get_devid(dev)) {
1100 /* Intel -- vendor 0x8086 */
1102 return ("Intel 82371SB (PIIX3) USB controller");
1104 return ("Intel 82371AB/EB (PIIX4) USB controller");
1106 return ("Intel 82801AA (ICH) USB controller");
1108 return ("Intel 82801AB (ICH0) USB controller");
1110 return ("Intel 82801BA/BAM (ICH2) USB controller USB-A");
1112 return ("Intel 82801BA/BAM (ICH2) USB controller USB-B");
1114 /* VIA Technologies -- vendor 0x1106 (0x1107 on the Apollo Master) */
1116 return ("VIA 83C572 USB controller");
1118 /* AcerLabs -- vendor 0x10b9 */
1120 return ("AcerLabs M5237 (Aladdin-V) USB controller");
1122 /* OPTi -- vendor 0x1045 */
1124 return ("OPTi 82C861 (FireLink) USB controller");
1126 /* NEC -- vendor 0x1033 */
1128 return ("NEC uPD 9210 USB controller");
1130 /* CMD Tech -- vendor 0x1095 */
1132 return ("CMD Tech 670 (USB0670) USB controller");
1134 return ("CMD Tech 673 (USB0673) USB controller");
1137 if (pci_get_class(dev) == PCIC_SERIALBUS
1138 && pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
1139 if (pci_get_progif(dev) == 0x00 /* UHCI */ ) {
1140 return ("UHCI USB controller");
1141 } else if (pci_get_progif(dev) == 0x10 /* OHCI */ ) {
1142 return ("OHCI USB controller");
1144 return ("USB controller");
1151 pci_ata_match(device_t dev)
1154 switch (pci_get_devid(dev)) {
1156 /* Intel -- vendor 0x8086 */
1158 return ("Intel PIIX ATA controller");
1160 return ("Intel PIIX3 ATA controller");
1162 return ("Intel PIIX4 ATA controller");
1164 return ("Intel 82371MX mobile PCI ATA accelerator (MPIIX)");
1166 /* Promise -- vendor 0x105a */
1168 return ("Promise Ultra/33 ATA controller");
1170 return ("Promise Ultra/66 ATA controller");
1172 /* AcerLabs -- vendor 0x10b9 */
1174 return ("AcerLabs Aladdin ATA controller");
1176 /* VIA Technologies -- vendor 0x1106 (0x1107 on the Apollo Master) */
1178 switch (pci_read_config(dev, 0x08, 1)) {
1180 return ("VIA 85C586 ATA controller");
1182 return ("VIA 85C586 ATA controller");
1186 return ("VIA Apollo ATA controller");
1188 /* CMD Tech -- vendor 0x1095 */
1190 return ("CMD 640 ATA controller");
1192 return ("CMD 646 ATA controller");
1194 /* Cypress -- vendor 0x1080 */
1196 return ("Cypress 82C693 ATA controller");
1198 /* Cyrix -- vendor 0x1078 */
1200 return ("Cyrix 5530 ATA controller");
1202 /* SiS -- vendor 0x1039 */
1204 return ("SiS 5591 ATA controller");
1206 /* Highpoint tech -- vendor 0x1103 */
1208 return ("HighPoint HPT366 ATA controller");
1211 if (pci_get_class(dev) == PCIC_STORAGE &&
1212 pci_get_subclass(dev) == PCIS_STORAGE_IDE)
1213 return ("Unknown PCI ATA controller");
1220 pci_chip_match(device_t dev)
1224 switch (pci_get_devid(dev)) {
1225 /* Intel -- vendor 0x8086 */
1227 /* Silently ignore this one! What is it, anyway ??? */
1231 * On my laptop (Tecra 8000DVD), this device has a
1232 * bogus subclass 0x80 so make sure that it doesn't
1233 * match the generic 'chip' driver by accident.
1237 fixbushigh_i1225(dev);
1238 return ("Intel 824?? host to PCI bridge");
1240 return ("Intel 82443LX (440 LX) host to PCI bridge");
1242 return ("Intel 82443BX (440 BX) host to PCI bridge");
1244 return ("Intel 82443BX host to PCI bridge (AGP disabled)");
1246 return ("Intel 82443GX host to PCI bridge");
1248 return ("Intel 82443GX host to AGP bridge");
1250 return ("Intel 82443GX host to PCI bridge (AGP disabled)");
1252 return ("Intel 82454KX/GX (Orion) host to PCI bridge");
1254 return ("Intel 82451NX Memory and I/O controller");
1256 return ("Intel 82425EX PCI system controller");
1258 return ("Intel 82424ZX (Saturn) cache DRAM controller");
1260 rev = pci_get_revid(dev);
1261 if (rev == 16 || rev == 17)
1262 return ("Intel 82434NX (Neptune) PCI cache memory controller");
1263 return ("Intel 82434LX (Mercury) PCI cache memory controller");
1265 return ("Intel 82437FX PCI cache memory controller");
1267 return ("Intel 82437MX mobile PCI cache memory controller");
1269 return ("Intel 82439HX PCI cache memory controller");
1271 return ("Intel 82437VX PCI cache memory controller");
1273 return ("Intel 82439TX System controller (MTXC)");
1275 return ("Intel 82371AB Power management controller");
1277 return ("Intel 82443MX Power management controller");
1280 return ("Intel 82440FX (Natoma) PCI and memory controller");
1282 return ("Intel 82453KX/GX (Orion) PCI memory controller");
1284 return ("Intel 82810 (i810 GMCH) Host To Hub bridge");
1286 return ("Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge");
1288 return ("Intel 82810E (i810E GMCH) Host To Hub bridge");
1290 return ("Intel 82801AA (ICH) AC'97 Audio Controller");
1292 return ("Intel 82801AB (ICH0) AC'97 Audio Controller");
1294 /* Sony -- vendor 0x104d */
1296 return ("Sony CXD1947A FireWire Host Controller");
1298 /* SiS -- vendor 0x1039 */
1300 return ("SiS 85c496 PCI/VL Bridge");
1302 return ("SiS 85c501");
1304 return ("SiS 85c601");
1306 return ("SiS 5591 host to PCI bridge");
1308 return ("SiS 5591 host to AGP bridge");
1310 /* VLSI -- vendor 0x1004 */
1312 return ("VLSI 82C592 Host to PCI bridge");
1314 return ("VLSI 82C532 Eagle II Peripheral controller");
1316 return ("VLSI 82C535 Eagle II System controller");
1318 return ("VLSI 82C147 IrDA controller");
1320 /* VIA Technologies -- vendor 0x1106 (0x1107 on the Apollo Master) */
1322 return ("VIA 82C570 (Apollo Master) system controller");
1324 return ("VIA 82C585 (Apollo VP1/VPX) system controller");
1327 return ("VIA 82C595 (Apollo VP2) system controller");
1329 return ("VIA 82C597 (Apollo VP3) system controller");
1330 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */
1331 /* totally. Please let me know if anything wrong. -F */
1332 /* XXX need info on the MVP3 -- any takers? */
1334 return ("VIA 82C598MVP (Apollo MVP3) host bridge");
1340 return ("VIA 82C686 AC97 Audio");
1342 return ("VIA 82C686 AC97 Modem");
1344 /* AMD -- vendor 0x1022 */
1346 return ("AMD-751 host to PCI bridge");
1348 return ("AMD-761 host to PCI bridge");
1350 /* NEC -- vendor 0x1033 */
1352 return ("NEC 0002 PCI to PC-98 local bus bridge");
1354 return ("NEC 0016 PCI to PC-98 local bus bridge");
1356 /* AcerLabs -- vendor 0x10b9 */
1357 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
1358 /* id is '10b9" but the register always shows "10b9". -Foxfair */
1360 return ("AcerLabs M1541 (Aladdin-V) PCI host bridge");
1362 return ("AcerLabs M15x3 Power Management Unit");
1364 /* OPTi -- vendor 0x1045 */
1366 return ("Opti 82C557 (Viper-M) host to PCI bridge");
1368 return ("Opti 82C558 (Viper-M) ISA+IDE");
1370 return ("OPTi 82C822 host to PCI Bridge");
1372 /* Texas Instruments -- vendor 0x104c */
1374 return ("Texas Instruments PCI1225 CardBus controller");
1376 return ("Texas Instruments PCI1410 CardBus controller");
1378 return ("Texas Instruments PCI1420 CardBus controller");
1380 return ("Texas Instruments PCI1450 CardBus controller");
1382 return ("Texas Instruments PCI1451 CardBus controller");
1384 /* NeoMagic -- vendor 0x10c8 */
1386 return ("NeoMagic MagicMedia 256AX Audio controller");
1388 return ("NeoMagic MagicMedia 256ZX Audio controller");
1390 /* ESS Technology Inc -- vendor 0x125d */
1392 return ("ESS Technology Maestro 2E Audio controller");
1394 /* Toshiba -- vendor 0x1179 */
1396 return ("Toshiba Fast Infra Red controller");
1398 /* NEC -- vendor 0x1033 */
1400 /* PCI to C-bus bridge */
1401 /* The following chipsets are PCI to PC98 C-bus bridge.
1402 * The C-bus is the 16-bits bus on PC98 and it should be probed as
1403 * PCI to ISA bridge. Because class of the C-bus is not defined,
1404 * C-bus bridges are recognized as "other bridge." To make C-bus
1405 * bridge be recognized as ISA bridge, this function returns NULL.
1413 if (pci_get_class(dev) == PCIC_BRIDGE
1414 && pci_get_subclass(dev) != PCIS_BRIDGE_PCI
1415 && pci_get_subclass(dev) != PCIS_BRIDGE_ISA
1416 && pci_get_subclass(dev) != PCIS_BRIDGE_EISA)
1417 return pci_bridge_type(dev);
1422 /*---------------------------------------------------------
1424 ** Catchall driver for VGA devices
1426 ** By Garrett Wollman
1427 ** <wollman@halloran-eldar.lcs.mit.edu>
1429 **---------------------------------------------------------
1432 const char* pci_vga_match(device_t dev)
1434 u_int id = pci_get_devid(dev);
1435 const char *vendor, *chip, *type;
1437 vendor = chip = type = 0;
1438 switch (id & 0xffff) {
1443 chip = "i740"; break;
1447 vendor = "NeoMagic";
1450 chip = "MagicGraph 128ZV"; break;
1452 chip = "MagicGraph 128XD"; break;
1454 chip = "MagicMedia 256AV"; break;
1456 chip = "MagicMedia 256ZX"; break;
1461 type = "graphics accelerator";
1464 chip = "Voodoo"; break;
1466 chip = "Voodoo 2"; break;
1468 chip = "Voodoo Banshee"; break;
1470 chip = "Voodoo 3"; break;
1475 type = "graphics accelerator";
1478 chip = "MGA 2085PX"; break;
1480 chip = "MGA Millennium 2064W"; break;
1482 chip = "MGA 1024SG/1064SG/1164SG"; break;
1484 chip = "MGA Millennium II 2164W"; break;
1486 chip = "MGA Millennium II 2164WA-B AG"; break;
1488 chip = "MGA G200"; break;
1490 chip = "MGA G200 AGP"; break;
1492 chip = "MGA G400 AGP"; break;
1494 chip = "MGA Impression"; break;
1496 chip = "MGA G100"; break;
1498 chip = "MGA G100 AGP"; break;
1500 chip = "MGA G550 AGP"; break;
1506 type = "graphics accelerator";
1509 chip = "Mach32"; break;
1511 chip = "Mach64-CT"; break;
1513 chip = "Mach64-CX"; break;
1515 chip = "Mach64-ET"; break;
1518 chip = "Mach64-VT"; break;
1520 chip = "Mach64-GB"; break;
1522 chip = "Mach64-GD"; break;
1524 chip = "Mach64-GI"; break;
1526 chip = "Mach64-GM"; break;
1528 chip = "Mach64-GN"; break;
1530 chip = "Mach64-GO"; break;
1532 chip = "Mach64-GP"; break;
1534 chip = "Mach64-GQ"; break;
1536 chip = "Mach64-GR"; break;
1538 chip = "Mach64-GS"; break;
1540 chip = "Mach64-GT"; break;
1542 chip = "Mach64-GU"; break;
1544 chip = "Mach64-GV"; break;
1546 chip = "Mach64-GW"; break;
1548 chip = "Mach64-GX"; break;
1550 chip = "Mobility-1"; break;
1552 chip = "RageMobility-P/M"; break;
1554 chip = "Mach64-GZ"; break;
1556 chip = "Rage128-RE"; break;
1558 chip = "Rage128-RF"; break;
1560 chip = "Rage128-RK"; break;
1562 chip = "Rage128-RL"; break;
1566 vendor = "Avance Logic";
1569 chip = "ALG2301"; break;
1571 chip = "ALG2302"; break;
1575 vendor = "Tseng Labs";
1576 type = "graphics accelerator";
1582 chip = "ET4000 W32P"; break;
1584 chip = "ET6000/ET6100"; break;
1586 chip = "ET6300"; break;
1591 type = "graphics accelerator";
1594 chip = "P9000"; break;
1596 chip = "P9100"; break;
1600 vendor = "Cirrus Logic";
1603 chip = "GD7548"; break;
1605 chip = "GD7555"; break;
1607 chip = "GD7556"; break;
1609 chip = "GD5430"; break;
1612 chip = "GD5434"; break;
1614 chip = "GD5436"; break;
1616 chip = "GD5446"; break;
1618 chip = "GD5480"; break;
1620 chip = "GD5462"; break;
1623 chip = "GD5464"; break;
1625 chip = "GD5465"; break;
1627 chip = "GD7542"; break;
1629 chip = "GD7543"; break;
1631 chip = "GD7541"; break;
1636 break; /* let default deal with it */
1638 vendor = "Chips & Technologies";
1641 chip = "64310"; break;
1643 chip = "65545"; break;
1645 chip = "65548"; break;
1647 chip = "69000"; break;
1649 chip = "65550"; break;
1651 chip = "65554"; break;
1653 chip = "65555"; break;
1655 chip = "68554"; break;
1662 type = "PCI to PC-98 Core Graph bridge";
1670 chip = "86c201"; break;
1672 chip = "86c202"; break;
1674 chip = "86c205"; break;
1676 chip = "86c215"; break;
1678 chip = "86c225"; break;
1680 chip = "5597/98"; break;
1682 chip = "6326"; break;
1684 chip = "530/620"; break;
1688 vendor = "Number Nine";
1689 type = "graphics accelerator";
1692 chip = "Imagine 128"; break;
1694 chip = "Imagine 128 II"; break;
1698 vendor = "Alliance";
1701 chip = "PM6410"; break;
1703 chip = "PM6422"; break;
1705 chip = "PMAT24"; break;
1709 vendor = "Rendition Verite";
1712 chip = "V1000"; break;
1714 chip = "V2000"; break;
1718 vendor = "Sigma Designs";
1719 if ((id >> 16) == 0x6401)
1720 chip = "REALmagic64/GX";
1724 type = "graphics accelerator";
1727 chip = "Trio"; break;
1729 chip = "Aurora 64"; break;
1731 chip = "Trio 64UV+"; break;
1733 chip = "Trio 64V2/DX/GX"; break;
1735 chip = "Plato"; break;
1737 chip = "Trio3D"; break;
1739 chip = "868"; break;
1741 chip = "928"; break;
1744 chip = "864"; break;
1747 chip = "964"; break;
1749 chip = "968"; break;
1751 chip = "ViRGE"; break;
1753 chip = "ViRGE VX"; break;
1755 chip = "ViRGE DX/GX"; break;
1757 chip = "ViRGE GX2"; break;
1759 chip = "Trio3D/2X"; break;
1762 chip = "Savage3D"; break;
1764 chip = "Savage 4"; break;
1766 chip = "ViRGE MX"; break;
1768 chip = "ViRGE MX+"; break;
1772 vendor = "ARK Logic";
1775 chip = "1000PV"; break;
1777 chip = "2000PV"; break;
1779 chip = "2000MT"; break;
1781 chip = "2000MI"; break;
1786 type = "graphics accelerator";
1789 chip = "300SX"; break;
1791 chip = "500TX"; break;
1793 chip = "Delta"; break;
1795 chip = "PerMedia"; break;
1800 type = "graphics accelerator";
1803 chip = "NV1"; break;
1805 chip = "Riva TNT"; break;
1807 chip = "Riva TNT2"; break;
1809 chip = "Riva Ultra TNT2"; break;
1811 chip = "Riva Vanta TNT2"; break;
1813 chip = "Riva Ultra Vanta TNT2"; break;
1815 chip = "Riva Integrated TNT2"; break;
1817 chip = "GeForce 256"; break;
1819 chip = "GeForce DDR"; break;
1821 chip = "Quadro"; break;
1825 chip = "GeForce2 GTS"; break;
1827 chip = "Quadro2"; break;
1831 vendor = "NVidia/SGS-Thomson";
1832 type = "graphics accelerator";
1835 chip = "Riva128"; break;
1839 vendor = "SGS-Thomson";
1842 chip = "STG2000"; break;
1849 chip = "82810 (i810 GMCH)"; break;
1851 chip = "82810-DC100 (i810-DC100 GMCH)"; break;
1853 chip = "82810E (i810E GMCH)"; break;
1855 chip = "i740 AGP"; break;
1859 vendor = "Intergraphics";
1862 chip = "IGA-1680"; break;
1864 chip = "IGA-1682"; break;
1869 if (vendor && chip) {
1874 type = "SVGA controller";
1876 len = strlen(vendor) + strlen(chip) + strlen(type) + 4;
1877 MALLOC(buf, char *, len, M_TEMP, M_NOWAIT);
1879 sprintf(buf, "%s %s %s", vendor, chip, type);
1883 switch (pci_get_class(dev)) {
1886 if (pci_get_subclass(dev) != PCIS_OLD_VGA)
1889 type = "VGA-compatible display device";
1894 if (pci_get_subclass(dev) == PCIS_DISPLAY_VGA)
1895 type = "VGA-compatible display device";
1898 * If it isn't a vga display device,
1899 * don't pretend we found one.
1910 * If we got here, we know for sure it's some sort of display
1911 * device, but we weren't able to identify it specifically.
1912 * At a minimum we can return the type, but we'd like to
1913 * identify the vendor and chip ID if at all possible.
1914 * (Some of the checks above intentionally don't bother for
1915 * vendors where we know the chip ID is the same as the
1922 len = strlen(vendor) + strlen(type) + 2 + 6 + 4 + 1;
1923 MALLOC(buf, char *, len, M_TEMP, M_NOWAIT);
1925 sprintf(buf, "%s model %04x %s", vendor, id >> 16, type);
1931 /*---------------------------------------------------------
1933 ** Devices to ignore
1935 **---------------------------------------------------------
1939 ign_match(device_t dev)
1941 switch (pci_get_devid(dev)) {
1943 case 0x10001042ul: /* wd */
1944 return ("SMC FDC 37c665");
1951 ign_probe(device_t dev)
1957 device_set_desc(dev, s);
1965 ign_attach(device_t dev)
1970 static device_method_t ign_methods[] = {
1971 /* Device interface */
1972 DEVMETHOD(device_probe, ign_probe),
1973 DEVMETHOD(device_attach, ign_attach),
1978 static driver_t ign_driver = {
1984 static devclass_t ign_devclass;
1986 DRIVER_MODULE(ign, pci, ign_driver, ign_devclass, 0, 0);