sys/dev/drm/r600_cp.c

   1 /*-
   2  * Copyright 2008-2009 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *     Dave Airlie <airlied@redhat.com>
  26  *     Alex Deucher <alexander.deucher@amd.com>
  27  */
  28
  29 #include "dev/drm/drmP.h"
  30 #include "dev/drm/drm.h"
  31 #include "dev/drm/radeon_drm.h"
  32 #include "dev/drm/radeon_drv.h"
  33
  34 #include "dev/drm/r600_microcode.h"
  35
  36 # define ATI_PCIGART_PAGE_SIZE          4096    /**< PCI GART page size */
  37 # define ATI_PCIGART_PAGE_MASK          (~(ATI_PCIGART_PAGE_SIZE-1))
  38
  39 #define R600_PTE_VALID     (1 << 0)
  40 #define R600_PTE_SYSTEM    (1 << 1)
  41 #define R600_PTE_SNOOPED   (1 << 2)
  42 #define R600_PTE_READABLE  (1 << 5)
  43 #define R600_PTE_WRITEABLE (1 << 6)
  44
  45 /* MAX values used for gfx init */
  46 #define R6XX_MAX_SH_GPRS           256
  47 #define R6XX_MAX_TEMP_GPRS         16
  48 #define R6XX_MAX_SH_THREADS        256
  49 #define R6XX_MAX_SH_STACK_ENTRIES  4096
  50 #define R6XX_MAX_BACKENDS          8
  51 #define R6XX_MAX_BACKENDS_MASK     0xff
  52 #define R6XX_MAX_SIMDS             8
  53 #define R6XX_MAX_SIMDS_MASK        0xff
  54 #define R6XX_MAX_PIPES             8
  55 #define R6XX_MAX_PIPES_MASK        0xff
  56
  57 #define R7XX_MAX_SH_GPRS           256
  58 #define R7XX_MAX_TEMP_GPRS         16
  59 #define R7XX_MAX_SH_THREADS        256
  60 #define R7XX_MAX_SH_STACK_ENTRIES  4096
  61 #define R7XX_MAX_BACKENDS          8
  62 #define R7XX_MAX_BACKENDS_MASK     0xff
  63 #define R7XX_MAX_SIMDS             16
  64 #define R7XX_MAX_SIMDS_MASK        0xffff
  65 #define R7XX_MAX_PIPES             8
  66 #define R7XX_MAX_PIPES_MASK        0xff
  67
  68 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
  69 {
  70         int i;
  71
  72         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
  73
  74         for (i = 0; i < dev_priv->usec_timeout; i++) {
  75                 int slots;
  76                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
  77                         slots = (RADEON_READ(R600_GRBM_STATUS)
  78                                  & R700_CMDFIFO_AVAIL_MASK);
  79                 else
  80                         slots = (RADEON_READ(R600_GRBM_STATUS)
  81                                  & R600_CMDFIFO_AVAIL_MASK);
  82                 if (slots >= entries)
  83                         return 0;
  84                 DRM_UDELAY(1);
  85         }
  86         DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
  87                  RADEON_READ(R600_GRBM_STATUS),
  88                  RADEON_READ(R600_GRBM_STATUS2));
  89
  90         return -EBUSY;
  91 }
  92
  93 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
  94 {
  95         int i, ret;
  96
  97         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
  98
  99         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 100                 ret = r600_do_wait_for_fifo(dev_priv, 8);
 101         else
 102                 ret = r600_do_wait_for_fifo(dev_priv, 16);
 103         if (ret)
 104                 return ret;
 105         for (i = 0; i < dev_priv->usec_timeout; i++) {
 106                 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
 107                         return 0;
 108                 DRM_UDELAY(1);
 109         }
 110         DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
 111                  RADEON_READ(R600_GRBM_STATUS),
 112                  RADEON_READ(R600_GRBM_STATUS2));
 113
 114         return -EBUSY;
 115 }
 116
 117 void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
 118 {
 119 #ifdef __linux__
 120         struct drm_sg_mem *entry = dev->sg;
 121         int max_pages;
 122         int pages;
 123         int i;
 124 #endif
 125         if (gart_info->bus_addr) {
 126 #ifdef __linux__
 127                 max_pages = (gart_info->table_size / sizeof(u32));
 128                 pages = (entry->pages <= max_pages)
 129                   ? entry->pages : max_pages;
 130
 131                 for (i = 0; i < pages; i++) {
 132                         if (!entry->busaddr[i])
 133                                 break;
 134                         pci_unmap_single(dev->pdev, entry->busaddr[i],
 135                                          PAGE_SIZE, PCI_DMA_TODEVICE);
 136                 }
 137 #endif
 138                 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
 139                         gart_info->bus_addr = 0;
 140         }
 141 }
 142
 143 /* R600 has page table setup */
 144 int r600_page_table_init(struct drm_device *dev)
 145 {
 146         drm_radeon_private_t *dev_priv = dev->dev_private;
 147         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
 148         struct drm_sg_mem *entry = dev->sg;
 149         int ret = 0;
 150         int i, j;
 151         int max_pages, pages;
 152         u64 *pci_gart, page_base;
 153         dma_addr_t entry_addr;
 154
 155         /* okay page table is available - lets rock */
 156
 157         /* PTEs are 64-bits */
 158         pci_gart = (u64 *)gart_info->addr;
 159
 160         max_pages = (gart_info->table_size / sizeof(u64));
 161         pages = (entry->pages <= max_pages) ? entry->pages : max_pages;
 162
 163         memset(pci_gart, 0, max_pages * sizeof(u64));
 164
 165         for (i = 0; i < pages; i++) {
 166 #ifdef __linux__
 167                 entry->busaddr[i] = pci_map_single(dev->pdev,
 168                                                    page_address(entry->
 169                                                                 pagelist[i]),
 170                                                    PAGE_SIZE, PCI_DMA_TODEVICE);
 171                 if (entry->busaddr[i] == 0) {
 172                         DRM_ERROR("unable to map PCIGART pages!\n");
 173                         r600_page_table_cleanup(dev, gart_info);
 174                         goto done;
 175                 }
 176 #endif
 177                 entry_addr = entry->busaddr[i];
 178                 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
 179                         page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK;
 180                         page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
 181                         page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
 182
 183                         *pci_gart = page_base;
 184
 185                         if ((i % 128) == 0)
 186                                 DRM_DEBUG("page entry %d: 0x%016llx\n",
 187                                     i, (unsigned long long)page_base);
 188                         pci_gart++;
 189                         entry_addr += ATI_PCIGART_PAGE_SIZE;
 190                 }
 191         }
 192         ret = 1;
 193 #ifdef __linux__
 194 done:
 195 #endif
 196         return ret;
 197 }
 198
 199 static void r600_vm_flush_gart_range(struct drm_device *dev)
 200 {
 201         drm_radeon_private_t *dev_priv = dev->dev_private;
 202         u32 resp, countdown = 1000;
 203         RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 204         RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 205         RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
 206
 207         do {
 208                 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
 209                 countdown--;
 210                 DRM_UDELAY(1);
 211         } while (((resp & 0xf0) == 0) && countdown);
 212 }
 213
 214 static void r600_vm_init(struct drm_device *dev)
 215 {
 216         drm_radeon_private_t *dev_priv = dev->dev_private;
 217         /* initialise the VM to use the page table we constructed up there */
 218         u32 vm_c0, i;
 219         u32 mc_rd_a;
 220         u32 vm_l2_cntl, vm_l2_cntl3;
 221         /* okay set up the PCIE aperture type thingo */
 222         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 223         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 224         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 225
 226         /* setup MC RD a */
 227         mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS |
 228                 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
 229                 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY;
 230
 231         RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
 232         RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
 233
 234         RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
 235         RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a);
 236
 237         RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a);
 238         RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a);
 239
 240         RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a);
 241         RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a);
 242
 243         RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING);
 244         RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/);
 245
 246         RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a);
 247         RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a);
 248
 249         RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE);
 250         RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a);
 251
 252         vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
 253         vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7);
 254         RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
 255
 256         RADEON_WRITE(R600_VM_L2_CNTL2, 0);
 257         vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
 258                        R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
 259                        R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
 260         RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
 261
 262         vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
 263
 264         RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
 265
 266         vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
 267
 268         /* disable all other contexts */
 269         for (i = 1; i < 8; i++)
 270                 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
 271
 272         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
 273         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
 274         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 275
 276         r600_vm_flush_gart_range(dev);
 277 }
 278
 279 /* load r600 microcode */
 280 static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
 281 {
 282         const u32 (*cp)[3];
 283         const u32 *pfp;
 284         int i;
 285
 286         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 287         case CHIP_R600:
 288                 DRM_INFO("Loading R600 Microcode\n");
 289                 cp  = R600_cp_microcode;
 290                 pfp = R600_pfp_microcode;
 291                 break;
 292         case CHIP_RV610:
 293                 DRM_INFO("Loading RV610 Microcode\n");
 294                 cp  = RV610_cp_microcode;
 295                 pfp = RV610_pfp_microcode;
 296                 break;
 297         case CHIP_RV630:
 298                 DRM_INFO("Loading RV630 Microcode\n");
 299                 cp  = RV630_cp_microcode;
 300                 pfp = RV630_pfp_microcode;
 301                 break;
 302         case CHIP_RV620:
 303                 DRM_INFO("Loading RV620 Microcode\n");
 304                 cp  = RV620_cp_microcode;
 305                 pfp = RV620_pfp_microcode;
 306                 break;
 307         case CHIP_RV635:
 308                 DRM_INFO("Loading RV635 Microcode\n");
 309                 cp  = RV635_cp_microcode;
 310                 pfp = RV635_pfp_microcode;
 311                 break;
 312         case CHIP_RV670:
 313                 DRM_INFO("Loading RV670 Microcode\n");
 314                 cp  = RV670_cp_microcode;
 315                 pfp = RV670_pfp_microcode;
 316                 break;
 317         case CHIP_RS780:
 318                 DRM_INFO("Loading RS780 Microcode\n");
 319                 cp  = RS780_cp_microcode;
 320                 pfp = RS780_pfp_microcode;
 321                 break;
 322         default:
 323                 return;
 324         }
 325
 326         r600_do_cp_stop(dev_priv);
 327
 328         RADEON_WRITE(R600_CP_RB_CNTL,
 329                      R600_RB_NO_UPDATE |
 330                      R600_RB_BLKSZ(15) |
 331                      R600_RB_BUFSZ(3));
 332
 333         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
 334         RADEON_READ(R600_GRBM_SOFT_RESET);
 335         DRM_UDELAY(15000);
 336         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 337
 338         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 339
 340         for (i = 0; i < PM4_UCODE_SIZE; i++) {
 341                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][0]);
 342                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][1]);
 343                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][2]);
 344         }
 345
 346         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 347         for (i = 0; i < PFP_UCODE_SIZE; i++)
 348                 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
 349
 350         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 351         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 352         RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
 353 }
 354
 355 static void r700_vm_init(struct drm_device *dev)
 356 {
 357         drm_radeon_private_t *dev_priv = dev->dev_private;
 358         /* initialise the VM to use the page table we constructed up there */
 359         u32 vm_c0, i;
 360         u32 mc_vm_md_l1;
 361         u32 vm_l2_cntl, vm_l2_cntl3;
 362         /* okay set up the PCIE aperture type thingo */
 363         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 364         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 365         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 366
 367         mc_vm_md_l1 = R700_ENABLE_L1_TLB |
 368             R700_ENABLE_L1_FRAGMENT_PROCESSING |
 369             R700_SYSTEM_ACCESS_MODE_IN_SYS |
 370             R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 371             R700_EFFECTIVE_L1_TLB_SIZE(5) |
 372             R700_EFFECTIVE_L1_QUEUE_SIZE(5);
 373
 374         RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1);
 375         RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1);
 376         RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1);
 377         RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1);
 378         RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1);
 379         RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1);
 380         RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1);
 381
 382         vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
 383         vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7);
 384         RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
 385
 386         RADEON_WRITE(R600_VM_L2_CNTL2, 0);
 387         vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
 388         RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
 389
 390         vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
 391
 392         RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
 393
 394         vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
 395
 396         /* disable all other contexts */
 397         for (i = 1; i < 8; i++)
 398                 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
 399
 400         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
 401         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
 402         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 403
 404         r600_vm_flush_gart_range(dev);
 405 }
 406
 407 /* load r600 microcode */
 408 static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
 409 {
 410         const u32 *pfp;
 411         const u32 *cp;
 412         int i;
 413
 414         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 415         case CHIP_RV770:
 416                 DRM_INFO("Loading RV770/RV790 Microcode\n");
 417                 pfp = RV770_pfp_microcode;
 418                 cp  = RV770_cp_microcode;
 419                 break;
 420         case CHIP_RV730:
 421                 DRM_INFO("Loading RV730 Microcode\n");
 422                 pfp = RV730_pfp_microcode;
 423                 cp  = RV730_cp_microcode;
 424                 break;
 425         case CHIP_RV710:
 426                 DRM_INFO("Loading RV710 Microcode\n");
 427                 pfp = RV710_pfp_microcode;
 428                 cp  = RV710_cp_microcode;
 429                 break;
 430         default:
 431                 return;
 432         }
 433
 434         r600_do_cp_stop(dev_priv);
 435
 436         RADEON_WRITE(R600_CP_RB_CNTL,
 437                      R600_RB_NO_UPDATE |
 438                      (15 << 8) |
 439                      (3 << 0));
 440
 441         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
 442         RADEON_READ(R600_GRBM_SOFT_RESET);
 443         DRM_UDELAY(15000);
 444         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 445
 446         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 447         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
 448                 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
 449         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 450
 451         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 452         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
 453                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i]);
 454         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 455
 456         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 457         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 458         RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
 459 }
 460
 461 static void r600_test_writeback(drm_radeon_private_t *dev_priv)
 462 {
 463         u32 tmp;
 464
 465         /* Start with assuming that writeback doesn't work */
 466         dev_priv->writeback_works = 0;
 467
 468         /* Writeback doesn't seem to work everywhere, test it here and possibly
 469          * enable it if it appears to work
 470          */
 471         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
 472
 473         RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef);
 474
 475         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 476                 u32 val;
 477
 478                 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
 479                 if (val == 0xdeadbeef)
 480                         break;
 481                 DRM_UDELAY(1);
 482         }
 483
 484         if (tmp < dev_priv->usec_timeout) {
 485                 dev_priv->writeback_works = 1;
 486                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 487         } else {
 488                 dev_priv->writeback_works = 0;
 489                 DRM_INFO("writeback test failed\n");
 490         }
 491         if (radeon_no_wb == 1) {
 492                 dev_priv->writeback_works = 0;
 493                 DRM_INFO("writeback forced off\n");
 494         }
 495
 496         if (!dev_priv->writeback_works) {
 497                 /* Disable writeback to avoid unnecessary bus master transfer */
 498                 RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) |
 499                              RADEON_RB_NO_UPDATE);
 500                 RADEON_WRITE(R600_SCRATCH_UMSK, 0);
 501         }
 502 }
 503
 504 int r600_do_engine_reset(struct drm_device *dev)
 505 {
 506         drm_radeon_private_t *dev_priv = dev->dev_private;
 507         u32 cp_ptr, cp_me_cntl, cp_rb_cntl;
 508
 509         DRM_INFO("Resetting GPU\n");
 510
 511         cp_ptr = RADEON_READ(R600_CP_RB_WPTR);
 512         cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);
 513         RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT);
 514
 515         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff);
 516         RADEON_READ(R600_GRBM_SOFT_RESET);
 517         DRM_UDELAY(50);
 518         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 519         RADEON_READ(R600_GRBM_SOFT_RESET);
 520
 521         RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
 522         cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
 523         RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA);
 524
 525         RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
 526         RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
 527         RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl);
 528         RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl);
 529
 530         /* Reset the CP ring */
 531         r600_do_cp_reset(dev_priv);
 532
 533         /* The CP is no longer running after an engine reset */
 534         dev_priv->cp_running = 0;
 535
 536         /* Reset any pending vertex, indirect buffers */
 537         radeon_freelist_reset(dev);
 538
 539         return 0;
 540
 541 }
 542
 543 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 544                                              u32 num_backends,
 545                                              u32 backend_disable_mask)
 546 {
 547         u32 backend_map = 0;
 548         u32 enabled_backends_mask;
 549         u32 enabled_backends_count;
 550         u32 cur_pipe;
 551         u32 swizzle_pipe[R6XX_MAX_PIPES];
 552         u32 cur_backend;
 553         u32 i;
 554
 555         if (num_tile_pipes > R6XX_MAX_PIPES)
 556                 num_tile_pipes = R6XX_MAX_PIPES;
 557         if (num_tile_pipes < 1)
 558                 num_tile_pipes = 1;
 559         if (num_backends > R6XX_MAX_BACKENDS)
 560                 num_backends = R6XX_MAX_BACKENDS;
 561         if (num_backends < 1)
 562                 num_backends = 1;
 563
 564         enabled_backends_mask = 0;
 565         enabled_backends_count = 0;
 566         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
 567                 if (((backend_disable_mask >> i) & 1) == 0) {
 568                         enabled_backends_mask |= (1 << i);
 569                         ++enabled_backends_count;
 570                 }
 571                 if (enabled_backends_count == num_backends)
 572                         break;
 573         }
 574
 575         if (enabled_backends_count == 0) {
 576                 enabled_backends_mask = 1;
 577                 enabled_backends_count = 1;
 578         }
 579
 580         if (enabled_backends_count != num_backends)
 581                 num_backends = enabled_backends_count;
 582
 583         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
 584         switch (num_tile_pipes) {
 585         case 1:
 586                 swizzle_pipe[0] = 0;
 587                 break;
 588         case 2:
 589                 swizzle_pipe[0] = 0;
 590                 swizzle_pipe[1] = 1;
 591                 break;
 592         case 3:
 593                 swizzle_pipe[0] = 0;
 594                 swizzle_pipe[1] = 1;
 595                 swizzle_pipe[2] = 2;
 596                 break;
 597         case 4:
 598                 swizzle_pipe[0] = 0;
 599                 swizzle_pipe[1] = 1;
 600                 swizzle_pipe[2] = 2;
 601                 swizzle_pipe[3] = 3;
 602                 break;
 603         case 5:
 604                 swizzle_pipe[0] = 0;
 605                 swizzle_pipe[1] = 1;
 606                 swizzle_pipe[2] = 2;
 607                 swizzle_pipe[3] = 3;
 608                 swizzle_pipe[4] = 4;
 609                 break;
 610         case 6:
 611                 swizzle_pipe[0] = 0;
 612                 swizzle_pipe[1] = 2;
 613                 swizzle_pipe[2] = 4;
 614                 swizzle_pipe[3] = 5;
 615                 swizzle_pipe[4] = 1;
 616                 swizzle_pipe[5] = 3;
 617                 break;
 618         case 7:
 619                 swizzle_pipe[0] = 0;
 620                 swizzle_pipe[1] = 2;
 621                 swizzle_pipe[2] = 4;
 622                 swizzle_pipe[3] = 6;
 623                 swizzle_pipe[4] = 1;
 624                 swizzle_pipe[5] = 3;
 625                 swizzle_pipe[6] = 5;
 626                 break;
 627         case 8:
 628                 swizzle_pipe[0] = 0;
 629                 swizzle_pipe[1] = 2;
 630                 swizzle_pipe[2] = 4;
 631                 swizzle_pipe[3] = 6;
 632                 swizzle_pipe[4] = 1;
 633                 swizzle_pipe[5] = 3;
 634                 swizzle_pipe[6] = 5;
 635                 swizzle_pipe[7] = 7;
 636                 break;
 637         }
 638
 639         cur_backend = 0;
 640         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 641                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 642                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 643
 644                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 645
 646                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 647         }
 648
 649         return backend_map;
 650 }
 651
 652 static int r600_count_pipe_bits(uint32_t val)
 653 {
 654         int i, ret = 0;
 655         for (i = 0; i < 32; i++) {
 656                 ret += val & 1;
 657                 val >>= 1;
 658         }
 659         return ret;
 660 }
 661
 662 static void r600_gfx_init(struct drm_device *dev,
 663                           drm_radeon_private_t *dev_priv)
 664 {
 665         int i, j, num_qd_pipes;
 666         u32 sx_debug_1;
 667         u32 tc_cntl;
 668         u32 arb_pop;
 669         u32 num_gs_verts_per_thread;
 670         u32 vgt_gs_per_es;
 671         u32 gs_prim_buffer_depth = 0;
 672         u32 sq_ms_fifo_sizes;
 673         u32 sq_config;
 674         u32 sq_gpr_resource_mgmt_1 = 0;
 675         u32 sq_gpr_resource_mgmt_2 = 0;
 676         u32 sq_thread_resource_mgmt = 0;
 677         u32 sq_stack_resource_mgmt_1 = 0;
 678         u32 sq_stack_resource_mgmt_2 = 0;
 679         u32 hdp_host_path_cntl;
 680         u32 backend_map;
 681         u32 gb_tiling_config = 0;
 682         u32 cc_rb_backend_disable = 0;
 683         u32 cc_gc_shader_pipe_config = 0;
 684         u32 ramcfg;
 685
 686         /* setup chip specs */
 687         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 688         case CHIP_R600:
 689                 dev_priv->r600_max_pipes = 4;
 690                 dev_priv->r600_max_tile_pipes = 8;
 691                 dev_priv->r600_max_simds = 4;
 692                 dev_priv->r600_max_backends = 4;
 693                 dev_priv->r600_max_gprs = 256;
 694                 dev_priv->r600_max_threads = 192;
 695                 dev_priv->r600_max_stack_entries = 256;
 696                 dev_priv->r600_max_hw_contexts = 8;
 697                 dev_priv->r600_max_gs_threads = 16;
 698                 dev_priv->r600_sx_max_export_size = 128;
 699                 dev_priv->r600_sx_max_export_pos_size = 16;
 700                 dev_priv->r600_sx_max_export_smx_size = 128;
 701                 dev_priv->r600_sq_num_cf_insts = 2;
 702                 break;
 703         case CHIP_RV630:
 704         case CHIP_RV635:
 705                 dev_priv->r600_max_pipes = 2;
 706                 dev_priv->r600_max_tile_pipes = 2;
 707                 dev_priv->r600_max_simds = 3;
 708                 dev_priv->r600_max_backends = 1;
 709                 dev_priv->r600_max_gprs = 128;
 710                 dev_priv->r600_max_threads = 192;
 711                 dev_priv->r600_max_stack_entries = 128;
 712                 dev_priv->r600_max_hw_contexts = 8;
 713                 dev_priv->r600_max_gs_threads = 4;
 714                 dev_priv->r600_sx_max_export_size = 128;
 715                 dev_priv->r600_sx_max_export_pos_size = 16;
 716                 dev_priv->r600_sx_max_export_smx_size = 128;
 717                 dev_priv->r600_sq_num_cf_insts = 2;
 718                 break;
 719         case CHIP_RV610:
 720         case CHIP_RS780:
 721         case CHIP_RV620:
 722                 dev_priv->r600_max_pipes = 1;
 723                 dev_priv->r600_max_tile_pipes = 1;
 724                 dev_priv->r600_max_simds = 2;
 725                 dev_priv->r600_max_backends = 1;
 726                 dev_priv->r600_max_gprs = 128;
 727                 dev_priv->r600_max_threads = 192;
 728                 dev_priv->r600_max_stack_entries = 128;
 729                 dev_priv->r600_max_hw_contexts = 4;
 730                 dev_priv->r600_max_gs_threads = 4;
 731                 dev_priv->r600_sx_max_export_size = 128;
 732                 dev_priv->r600_sx_max_export_pos_size = 16;
 733                 dev_priv->r600_sx_max_export_smx_size = 128;
 734                 dev_priv->r600_sq_num_cf_insts = 1;
 735                 break;
 736         case CHIP_RV670:
 737                 dev_priv->r600_max_pipes = 4;
 738                 dev_priv->r600_max_tile_pipes = 4;
 739                 dev_priv->r600_max_simds = 4;
 740                 dev_priv->r600_max_backends = 4;
 741                 dev_priv->r600_max_gprs = 192;
 742                 dev_priv->r600_max_threads = 192;
 743                 dev_priv->r600_max_stack_entries = 256;
 744                 dev_priv->r600_max_hw_contexts = 8;
 745                 dev_priv->r600_max_gs_threads = 16;
 746                 dev_priv->r600_sx_max_export_size = 128;
 747                 dev_priv->r600_sx_max_export_pos_size = 16;
 748                 dev_priv->r600_sx_max_export_smx_size = 128;
 749                 dev_priv->r600_sq_num_cf_insts = 2;
 750                 break;
 751         default:
 752                 break;
 753         }
 754
 755         /* Initialize HDP */
 756         j = 0;
 757         for (i = 0; i < 32; i++) {
 758                 RADEON_WRITE((0x2c14 + j), 0x00000000);
 759                 RADEON_WRITE((0x2c18 + j), 0x00000000);
 760                 RADEON_WRITE((0x2c1c + j), 0x00000000);
 761                 RADEON_WRITE((0x2c20 + j), 0x00000000);
 762                 RADEON_WRITE((0x2c24 + j), 0x00000000);
 763                 j += 0x18;
 764         }
 765
 766         RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
 767
 768         /* setup tiling, simd, pipe config */
 769         ramcfg = RADEON_READ(R600_RAMCFG);
 770
 771         switch (dev_priv->r600_max_tile_pipes) {
 772         case 1:
 773                 gb_tiling_config |= R600_PIPE_TILING(0);
 774                 break;
 775         case 2:
 776                 gb_tiling_config |= R600_PIPE_TILING(1);
 777                 break;
 778         case 4:
 779                 gb_tiling_config |= R600_PIPE_TILING(2);
 780                 break;
 781         case 8:
 782                 gb_tiling_config |= R600_PIPE_TILING(3);
 783                 break;
 784         default:
 785                 break;
 786         }
 787
 788         gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);
 789
 790         gb_tiling_config |= R600_GROUP_SIZE(0);
 791
 792         if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) {
 793                 gb_tiling_config |= R600_ROW_TILING(3);
 794                 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
 795         } else {
 796                 gb_tiling_config |=
 797                         R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
 798                 gb_tiling_config |=
 799                         R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
 800         }
 801
 802         gb_tiling_config |= R600_BANK_SWAPS(1);
 803
 804         backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
 805                                                         dev_priv->r600_max_backends,
 806                                                         (0xff << dev_priv->r600_max_backends) & 0xff);
 807         gb_tiling_config |= R600_BACKEND_MAP(backend_map);
 808
 809         cc_gc_shader_pipe_config =
 810                 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
 811         cc_gc_shader_pipe_config |=
 812                 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
 813
 814         cc_rb_backend_disable =
 815                 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
 816
 817         RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);
 818         RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
 819         RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
 820
 821         RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
 822         RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
 823         RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 824
 825         num_qd_pipes =
 826                 R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
 827         RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
 828         RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
 829
 830         /* set HW defaults for 3D engine */
 831         RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
 832                                                 R600_ROQ_IB2_START(0x2b)));
 833
 834         RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) |
 835                                               R600_ROQ_END(0x40)));
 836
 837         RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
 838                                         R600_SYNC_GRADIENT |
 839                                         R600_SYNC_WALKER |
 840                                         R600_SYNC_ALIGNER));
 841
 842         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
 843                 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021);
 844
 845         sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);
 846         sx_debug_1 |= R600_SMX_EVENT_RELEASE;
 847         if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
 848                 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS;
 849         RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1);
 850
 851         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
 852             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
 853             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 854             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 855             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780))
 856                 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
 857         else
 858                 RADEON_WRITE(R600_DB_DEBUG, 0);
 859
 860         RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) |
 861                                           R600_DEPTH_FLUSH(16) |
 862                                           R600_DEPTH_PENDING_FREE(4) |
 863                                           R600_DEPTH_CACHELINE_FREE(16)));
 864         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
 865         RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0);
 866
 867         RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
 868         RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0));
 869
 870         sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
 871         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 872             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 873             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
 874                 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
 875                                     R600_FETCH_FIFO_HIWATER(0xa) |
 876                                     R600_DONE_FIFO_HIWATER(0xe0) |
 877                                     R600_ALU_UPDATE_FIFO_HIWATER(0x8));
 878         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
 879                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
 880                 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff);
 881                 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4);
 882         }
 883         RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
 884
 885         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 886          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 887          */
 888         sq_config = RADEON_READ(R600_SQ_CONFIG);
 889         sq_config &= ~(R600_PS_PRIO(3) |
 890                        R600_VS_PRIO(3) |
 891                        R600_GS_PRIO(3) |
 892                        R600_ES_PRIO(3));
 893         sq_config |= (R600_DX9_CONSTS |
 894                       R600_VC_ENABLE |
 895                       R600_PS_PRIO(0) |
 896                       R600_VS_PRIO(1) |
 897                       R600_GS_PRIO(2) |
 898                       R600_ES_PRIO(3));
 899
 900         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
 901                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
 902                                           R600_NUM_VS_GPRS(124) |
 903                                           R600_NUM_CLAUSE_TEMP_GPRS(4));
 904                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) |
 905                                           R600_NUM_ES_GPRS(0));
 906                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) |
 907                                            R600_NUM_VS_THREADS(48) |
 908                                            R600_NUM_GS_THREADS(4) |
 909                                            R600_NUM_ES_THREADS(4));
 910                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) |
 911                                             R600_NUM_VS_STACK_ENTRIES(128));
 912                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) |
 913                                             R600_NUM_ES_STACK_ENTRIES(0));
 914         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 915                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 916                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
 917                 /* no vertex cache */
 918                 sq_config &= ~R600_VC_ENABLE;
 919
 920                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
 921                                           R600_NUM_VS_GPRS(44) |
 922                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
 923                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
 924                                           R600_NUM_ES_GPRS(17));
 925                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
 926                                            R600_NUM_VS_THREADS(78) |
 927                                            R600_NUM_GS_THREADS(4) |
 928                                            R600_NUM_ES_THREADS(31));
 929                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
 930                                             R600_NUM_VS_STACK_ENTRIES(40));
 931                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
 932                                             R600_NUM_ES_STACK_ENTRIES(16));
 933         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
 934                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
 935                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
 936                                           R600_NUM_VS_GPRS(44) |
 937                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
 938                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) |
 939                                           R600_NUM_ES_GPRS(18));
 940                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
 941                                            R600_NUM_VS_THREADS(78) |
 942                                            R600_NUM_GS_THREADS(4) |
 943                                            R600_NUM_ES_THREADS(31));
 944                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
 945                                             R600_NUM_VS_STACK_ENTRIES(40));
 946                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
 947                                             R600_NUM_ES_STACK_ENTRIES(16));
 948         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
 949                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
 950                                           R600_NUM_VS_GPRS(44) |
 951                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
 952                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
 953                                           R600_NUM_ES_GPRS(17));
 954                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
 955                                            R600_NUM_VS_THREADS(78) |
 956                                            R600_NUM_GS_THREADS(4) |
 957                                            R600_NUM_ES_THREADS(31));
 958                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) |
 959                                             R600_NUM_VS_STACK_ENTRIES(64));
 960                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) |
 961                                             R600_NUM_ES_STACK_ENTRIES(64));
 962         }
 963
 964         RADEON_WRITE(R600_SQ_CONFIG, sq_config);
 965         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
 966         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
 967         RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 968         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
 969         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
 970
 971         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 972             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 973             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780))
 974                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
 975         else
 976                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
 977
 978         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) |
 979                                                     R600_S0_Y(0x4) |
 980                                                     R600_S1_X(0x4) |
 981                                                     R600_S1_Y(0xc)));
 982         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) |
 983                                                     R600_S0_Y(0xe) |
 984                                                     R600_S1_X(0x2) |
 985                                                     R600_S1_Y(0x2) |
 986                                                     R600_S2_X(0xa) |
 987                                                     R600_S2_Y(0x6) |
 988                                                     R600_S3_X(0x6) |
 989                                                     R600_S3_Y(0xa)));
 990         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) |
 991                                                         R600_S0_Y(0xb) |
 992                                                         R600_S1_X(0x4) |
 993                                                         R600_S1_Y(0xc) |
 994                                                         R600_S2_X(0x1) |
 995                                                         R600_S2_Y(0x6) |
 996                                                         R600_S3_X(0xa) |
 997                                                         R600_S3_Y(0xe)));
 998         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) |
 999                                                         R600_S4_Y(0x1) |
1000                                                         R600_S5_X(0x0) |
1001                                                         R600_S5_Y(0x0) |
1002                                                         R600_S6_X(0xb) |
1003                                                         R600_S6_Y(0x4) |
1004                                                         R600_S7_X(0x7) |
1005                                                         R600_S7_Y(0x8)));
1006
1007
1008         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1009         case CHIP_R600:
1010         case CHIP_RV630:
1011         case CHIP_RV635:
1012                 gs_prim_buffer_depth = 0;
1013                 break;
1014         case CHIP_RV610:
1015         case CHIP_RS780:
1016         case CHIP_RV620:
1017                 gs_prim_buffer_depth = 32;
1018                 break;
1019         case CHIP_RV670:
1020                 gs_prim_buffer_depth = 128;
1021                 break;
1022         default:
1023                 break;
1024         }
1025
1026         num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1027         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1028         /* Max value for this is 256 */
1029         if (vgt_gs_per_es > 256)
1030                 vgt_gs_per_es = 256;
1031
1032         RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1033         RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1034         RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1035         RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1036
1037         /* more default values. 2D/3D driver should adjust as needed */
1038         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1039         RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1040         RADEON_WRITE(R600_SX_MISC, 0);
1041         RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1042         RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1043         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1044         RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1045         RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1046         RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1047
1048         /* clear render buffer base addresses */
1049         RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1050         RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1051         RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1052         RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1053         RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1054         RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1055         RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1056         RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1057
1058         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1059         case CHIP_RV610:
1060         case CHIP_RS780:
1061         case CHIP_RV620:
1062                 tc_cntl = R600_TC_L2_SIZE(8);
1063                 break;
1064         case CHIP_RV630:
1065         case CHIP_RV635:
1066                 tc_cntl = R600_TC_L2_SIZE(4);
1067                 break;
1068         case CHIP_R600:
1069                 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT;
1070                 break;
1071         default:
1072                 tc_cntl = R600_TC_L2_SIZE(0);
1073                 break;
1074         }
1075
1076         RADEON_WRITE(R600_TC_CNTL, tc_cntl);
1077
1078         hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1079         RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1080
1081         arb_pop = RADEON_READ(R600_ARB_POP);
1082         arb_pop |= R600_ENABLE_TC128;
1083         RADEON_WRITE(R600_ARB_POP, arb_pop);
1084
1085         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1086         RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1087                                           R600_NUM_CLIP_SEQ(3)));
1088         RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1089
1090 }
1091
1092 static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1093                                              u32 num_backends,
1094                                              u32 backend_disable_mask)
1095 {
1096         u32 backend_map = 0;
1097         u32 enabled_backends_mask;
1098         u32 enabled_backends_count;
1099         u32 cur_pipe;
1100         u32 swizzle_pipe[R7XX_MAX_PIPES];
1101         u32 cur_backend;
1102         u32 i;
1103
1104         if (num_tile_pipes > R7XX_MAX_PIPES)
1105                 num_tile_pipes = R7XX_MAX_PIPES;
1106         if (num_tile_pipes < 1)
1107                 num_tile_pipes = 1;
1108         if (num_backends > R7XX_MAX_BACKENDS)
1109                 num_backends = R7XX_MAX_BACKENDS;
1110         if (num_backends < 1)
1111                 num_backends = 1;
1112
1113         enabled_backends_mask = 0;
1114         enabled_backends_count = 0;
1115         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
1116                 if (((backend_disable_mask >> i) & 1) == 0) {
1117                         enabled_backends_mask |= (1 << i);
1118                         ++enabled_backends_count;
1119                 }
1120                 if (enabled_backends_count == num_backends)
1121                         break;
1122         }
1123
1124         if (enabled_backends_count == 0) {
1125                 enabled_backends_mask = 1;
1126                 enabled_backends_count = 1;
1127         }
1128
1129         if (enabled_backends_count != num_backends)
1130                 num_backends = enabled_backends_count;
1131
1132         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
1133         switch (num_tile_pipes) {
1134         case 1:
1135                 swizzle_pipe[0] = 0;
1136                 break;
1137         case 2:
1138                 swizzle_pipe[0] = 0;
1139                 swizzle_pipe[1] = 1;
1140                 break;
1141         case 3:
1142                 swizzle_pipe[0] = 0;
1143                 swizzle_pipe[1] = 2;
1144                 swizzle_pipe[2] = 1;
1145                 break;
1146         case 4:
1147                 swizzle_pipe[0] = 0;
1148                 swizzle_pipe[1] = 2;
1149                 swizzle_pipe[2] = 3;
1150                 swizzle_pipe[3] = 1;
1151                 break;
1152         case 5:
1153                 swizzle_pipe[0] = 0;
1154                 swizzle_pipe[1] = 2;
1155                 swizzle_pipe[2] = 4;
1156                 swizzle_pipe[3] = 1;
1157                 swizzle_pipe[4] = 3;
1158                 break;
1159         case 6:
1160                 swizzle_pipe[0] = 0;
1161                 swizzle_pipe[1] = 2;
1162                 swizzle_pipe[2] = 4;
1163                 swizzle_pipe[3] = 5;
1164                 swizzle_pipe[4] = 3;
1165                 swizzle_pipe[5] = 1;
1166                 break;
1167         case 7:
1168                 swizzle_pipe[0] = 0;
1169                 swizzle_pipe[1] = 2;
1170                 swizzle_pipe[2] = 4;
1171                 swizzle_pipe[3] = 6;
1172                 swizzle_pipe[4] = 3;
1173                 swizzle_pipe[5] = 1;
1174                 swizzle_pipe[6] = 5;
1175                 break;
1176         case 8:
1177                 swizzle_pipe[0] = 0;
1178                 swizzle_pipe[1] = 2;
1179                 swizzle_pipe[2] = 4;
1180                 swizzle_pipe[3] = 6;
1181                 swizzle_pipe[4] = 3;
1182                 swizzle_pipe[5] = 1;
1183                 swizzle_pipe[6] = 7;
1184                 swizzle_pipe[7] = 5;
1185                 break;
1186         }
1187
1188         cur_backend = 0;
1189         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1190                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1191                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1192
1193                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1194
1195                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1196         }
1197
1198         return backend_map;
1199 }
1200
1201 static void r700_gfx_init(struct drm_device *dev,
1202                           drm_radeon_private_t *dev_priv)
1203 {
1204         int i, j, num_qd_pipes;
1205         u32 sx_debug_1;
1206         u32 smx_dc_ctl0;
1207         u32 num_gs_verts_per_thread;
1208         u32 vgt_gs_per_es;
1209         u32 gs_prim_buffer_depth = 0;
1210         u32 sq_ms_fifo_sizes;
1211         u32 sq_config;
1212         u32 sq_thread_resource_mgmt;
1213         u32 hdp_host_path_cntl;
1214         u32 sq_dyn_gpr_size_simd_ab_0;
1215         u32 backend_map;
1216         u32 gb_tiling_config = 0;
1217         u32 cc_rb_backend_disable = 0;
1218         u32 cc_gc_shader_pipe_config = 0;
1219         u32 mc_arb_ramcfg;
1220         u32 db_debug4;
1221
1222         /* setup chip specs */
1223         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1224         case CHIP_RV770:
1225                 dev_priv->r600_max_pipes = 4;
1226                 dev_priv->r600_max_tile_pipes = 8;
1227                 dev_priv->r600_max_simds = 10;
1228                 dev_priv->r600_max_backends = 4;
1229                 dev_priv->r600_max_gprs = 256;
1230                 dev_priv->r600_max_threads = 248;
1231                 dev_priv->r600_max_stack_entries = 512;
1232                 dev_priv->r600_max_hw_contexts = 8;
1233                 dev_priv->r600_max_gs_threads = 16 * 2;
1234                 dev_priv->r600_sx_max_export_size = 128;
1235                 dev_priv->r600_sx_max_export_pos_size = 16;
1236                 dev_priv->r600_sx_max_export_smx_size = 112;
1237                 dev_priv->r600_sq_num_cf_insts = 2;
1238
1239                 dev_priv->r700_sx_num_of_sets = 7;
1240                 dev_priv->r700_sc_prim_fifo_size = 0xF9;
1241                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1242                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1243                 break;
1244         case CHIP_RV730:
1245                 dev_priv->r600_max_pipes = 2;
1246                 dev_priv->r600_max_tile_pipes = 4;
1247                 dev_priv->r600_max_simds = 8;
1248                 dev_priv->r600_max_backends = 2;
1249                 dev_priv->r600_max_gprs = 128;
1250                 dev_priv->r600_max_threads = 248;
1251                 dev_priv->r600_max_stack_entries = 256;
1252                 dev_priv->r600_max_hw_contexts = 8;
1253                 dev_priv->r600_max_gs_threads = 16 * 2;
1254                 dev_priv->r600_sx_max_export_size = 256;
1255                 dev_priv->r600_sx_max_export_pos_size = 32;
1256                 dev_priv->r600_sx_max_export_smx_size = 224;
1257                 dev_priv->r600_sq_num_cf_insts = 2;
1258
1259                 dev_priv->r700_sx_num_of_sets = 7;
1260                 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1261                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1262                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1263                 break;
1264         case CHIP_RV710:
1265                 dev_priv->r600_max_pipes = 2;
1266                 dev_priv->r600_max_tile_pipes = 2;
1267                 dev_priv->r600_max_simds = 2;
1268                 dev_priv->r600_max_backends = 1;
1269                 dev_priv->r600_max_gprs = 256;
1270                 dev_priv->r600_max_threads = 192;
1271                 dev_priv->r600_max_stack_entries = 256;
1272                 dev_priv->r600_max_hw_contexts = 4;
1273                 dev_priv->r600_max_gs_threads = 8 * 2;
1274                 dev_priv->r600_sx_max_export_size = 128;
1275                 dev_priv->r600_sx_max_export_pos_size = 16;
1276                 dev_priv->r600_sx_max_export_smx_size = 112;
1277                 dev_priv->r600_sq_num_cf_insts = 1;
1278
1279                 dev_priv->r700_sx_num_of_sets = 7;
1280                 dev_priv->r700_sc_prim_fifo_size = 0x40;
1281                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1282                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1283                 break;
1284         default:
1285                 break;
1286         }
1287
1288         /* Initialize HDP */
1289         j = 0;
1290         for (i = 0; i < 32; i++) {
1291                 RADEON_WRITE((0x2c14 + j), 0x00000000);
1292                 RADEON_WRITE((0x2c18 + j), 0x00000000);
1293                 RADEON_WRITE((0x2c1c + j), 0x00000000);
1294                 RADEON_WRITE((0x2c20 + j), 0x00000000);
1295                 RADEON_WRITE((0x2c24 + j), 0x00000000);
1296                 j += 0x18;
1297         }
1298
1299         RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
1300
1301         /* setup tiling, simd, pipe config */
1302         mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);
1303
1304         switch (dev_priv->r600_max_tile_pipes) {
1305         case 1:
1306                 gb_tiling_config |= R600_PIPE_TILING(0);
1307                 break;
1308         case 2:
1309                 gb_tiling_config |= R600_PIPE_TILING(1);
1310                 break;
1311         case 4:
1312                 gb_tiling_config |= R600_PIPE_TILING(2);
1313                 break;
1314         case 8:
1315                 gb_tiling_config |= R600_PIPE_TILING(3);
1316                 break;
1317         default:
1318                 break;
1319         }
1320
1321         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1322                 gb_tiling_config |= R600_BANK_TILING(1);
1323         else
1324                 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);
1325
1326         gb_tiling_config |= R600_GROUP_SIZE(0);
1327
1328         if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) {
1329                 gb_tiling_config |= R600_ROW_TILING(3);
1330                 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
1331         } else {
1332                 gb_tiling_config |=
1333                         R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1334                 gb_tiling_config |=
1335                         R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1336         }
1337
1338         gb_tiling_config |= R600_BANK_SWAPS(1);
1339
1340         backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
1341                                                         dev_priv->r600_max_backends,
1342                                                         (0xff << dev_priv->r600_max_backends) & 0xff);
1343         gb_tiling_config |= R600_BACKEND_MAP(backend_map);
1344
1345         cc_gc_shader_pipe_config =
1346                 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1347         cc_gc_shader_pipe_config |=
1348                 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1349
1350         cc_rb_backend_disable =
1351                 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
1352
1353         RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);
1354         RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
1355         RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
1356
1357         RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
1358         RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
1359         RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1360
1361         RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1362         RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
1363         RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
1364         RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
1365         RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
1366
1367         num_qd_pipes =
1368                 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
1369         RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
1370         RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
1371
1372         /* set HW defaults for 3D engine */
1373         RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
1374                                                 R600_ROQ_IB2_START(0x2b)));
1375
1376         RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30));
1377
1378         RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
1379                                         R600_SYNC_GRADIENT |
1380                                         R600_SYNC_WALKER |
1381                                         R600_SYNC_ALIGNER));
1382
1383         sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);
1384         sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS;
1385         RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1);
1386
1387         smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);
1388         smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff);
1389         smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1390         RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0);
1391
1392         RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) |
1393                                           R700_GS_FLUSH_CTL(4) |
1394                                           R700_ACK_FLUSH_CTL(3) |
1395                                           R700_SYNC_FLUSH_CTL));
1396
1397         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1398                 RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f));
1399         else {
1400                 db_debug4 = RADEON_READ(RV700_DB_DEBUG4);
1401                 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER;
1402                 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4);
1403         }
1404
1405         RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1406                                                    R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1407                                                    R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1408
1409         RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1410                                                  R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1411                                                  R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1412
1413         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1414
1415         RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1);
1416
1417         RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
1418
1419         RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4));
1420
1421         RADEON_WRITE(R600_CP_PERFMON_CNTL, 0);
1422
1423         sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1424                             R600_DONE_FIFO_HIWATER(0xe0) |
1425                             R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1426         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1427         case CHIP_RV770:
1428                 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1);
1429                 break;
1430         case CHIP_RV730:
1431         case CHIP_RV710:
1432         default:
1433                 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
1434                 break;
1435         }
1436         RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1437
1438         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1439          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1440          */
1441         sq_config = RADEON_READ(R600_SQ_CONFIG);
1442         sq_config &= ~(R600_PS_PRIO(3) |
1443                        R600_VS_PRIO(3) |
1444                        R600_GS_PRIO(3) |
1445                        R600_ES_PRIO(3));
1446         sq_config |= (R600_DX9_CONSTS |
1447                       R600_VC_ENABLE |
1448                       R600_EXPORT_SRC_C |
1449                       R600_PS_PRIO(0) |
1450                       R600_VS_PRIO(1) |
1451                       R600_GS_PRIO(2) |
1452                       R600_ES_PRIO(3));
1453         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1454                 /* no vertex cache */
1455                 sq_config &= ~R600_VC_ENABLE;
1456
1457         RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1458
1459         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1,  (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1460                                                     R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1461                                                     R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1462
1463         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2,  (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1464                                                     R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1465
1466         sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1467                                    R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1468                                    R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1469         if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1470                 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1471         else
1472                 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1473         RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1474
1475         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1476                                                      R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1477
1478         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1479                                                      R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1480
1481         sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1482                                      R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1483                                      R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1484                                      R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1485
1486         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1487         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1488         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1489         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1490         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1491         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1492         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1493         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1494
1495         RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1496                                                      R700_FORCE_EOV_MAX_REZ_CNT(255)));
1497
1498         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1499                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) |
1500                                                            R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1501         else
1502                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) |
1503                                                            R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1504
1505         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1506         case CHIP_RV770:
1507         case CHIP_RV730:
1508                 gs_prim_buffer_depth = 384;
1509                 break;
1510         case CHIP_RV710:
1511                 gs_prim_buffer_depth = 128;
1512                 break;
1513         default:
1514                 break;
1515         }
1516
1517         num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1518         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1519         /* Max value for this is 256 */
1520         if (vgt_gs_per_es > 256)
1521                 vgt_gs_per_es = 256;
1522
1523         RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1524         RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1525         RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1526
1527         /* more default values. 2D/3D driver should adjust as needed */
1528         RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1529         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1530         RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1531         RADEON_WRITE(R600_SX_MISC, 0);
1532         RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1533         RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa);
1534         RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1535         RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff);
1536         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1537         RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1538         RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1539         RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1540
1541         /* clear render buffer base addresses */
1542         RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1543         RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1544         RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1545         RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1546         RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1547         RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1548         RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1549         RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1550
1551         RADEON_WRITE(R700_TCP_CNTL, 0);
1552
1553         hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1554         RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1555
1556         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1557
1558         RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1559                                           R600_NUM_CLIP_SEQ(3)));
1560
1561 }
1562
1563 static void r600_cp_init_ring_buffer(struct drm_device *dev,
1564                                        drm_radeon_private_t *dev_priv,
1565                                        struct drm_file *file_priv)
1566 {
1567         u32 ring_start;
1568         u64 rptr_addr;
1569
1570         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1571                 r700_gfx_init(dev, dev_priv);
1572         else
1573                 r600_gfx_init(dev, dev_priv);
1574
1575         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
1576         RADEON_READ(R600_GRBM_SOFT_RESET);
1577         DRM_UDELAY(15000);
1578         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
1579
1580
1581         /* Set ring buffer size */
1582 #ifdef __BIG_ENDIAN
1583         RADEON_WRITE(R600_CP_RB_CNTL,
1584                      RADEON_BUF_SWAP_32BIT |
1585                      RADEON_RB_NO_UPDATE |
1586                      (dev_priv->ring.rptr_update_l2qw << 8) |
1587                      dev_priv->ring.size_l2qw);
1588 #else
1589         RADEON_WRITE(R600_CP_RB_CNTL,
1590                      RADEON_RB_NO_UPDATE |
1591                      (dev_priv->ring.rptr_update_l2qw << 8) |
1592                      dev_priv->ring.size_l2qw);
1593 #endif
1594
1595         RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4);
1596
1597         /* Set the write pointer delay */
1598         RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
1599
1600 #ifdef __BIG_ENDIAN
1601         RADEON_WRITE(R600_CP_RB_CNTL,
1602                      RADEON_BUF_SWAP_32BIT |
1603                      RADEON_RB_NO_UPDATE |
1604                      RADEON_RB_RPTR_WR_ENA |
1605                      (dev_priv->ring.rptr_update_l2qw << 8) |
1606                      dev_priv->ring.size_l2qw);
1607 #else
1608         RADEON_WRITE(R600_CP_RB_CNTL,
1609                      RADEON_RB_NO_UPDATE |
1610                      RADEON_RB_RPTR_WR_ENA |
1611                      (dev_priv->ring.rptr_update_l2qw << 8) |
1612                      dev_priv->ring.size_l2qw);
1613 #endif
1614
1615         /* Initialize the ring buffer's read and write pointers */
1616         RADEON_WRITE(R600_CP_RB_RPTR_WR, 0);
1617         RADEON_WRITE(R600_CP_RB_WPTR, 0);
1618         SET_RING_HEAD(dev_priv, 0);
1619         dev_priv->ring.tail = 0;
1620
1621 #if __OS_HAS_AGP
1622         if (dev_priv->flags & RADEON_IS_AGP) {
1623                 rptr_addr = dev_priv->ring_rptr->offset
1624                         - dev->agp->base +
1625                         dev_priv->gart_vm_start;
1626         } else
1627 #endif
1628         {
1629                 rptr_addr = dev_priv->ring_rptr->offset
1630                         - ((unsigned long) dev->sg->virtual)
1631                         + dev_priv->gart_vm_start;
1632         }
1633         RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
1634                      rptr_addr & 0xffffffff);
1635         RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI,
1636                      upper_32_bits(rptr_addr));
1637
1638 #ifdef __BIG_ENDIAN
1639         RADEON_WRITE(R600_CP_RB_CNTL,
1640                      RADEON_BUF_SWAP_32BIT |
1641                      (dev_priv->ring.rptr_update_l2qw << 8) |
1642                      dev_priv->ring.size_l2qw);
1643 #else
1644         RADEON_WRITE(R600_CP_RB_CNTL,
1645                      (dev_priv->ring.rptr_update_l2qw << 8) |
1646                      dev_priv->ring.size_l2qw);
1647 #endif
1648
1649 #if __OS_HAS_AGP
1650         if (dev_priv->flags & RADEON_IS_AGP) {
1651                 /* XXX */
1652                 radeon_write_agp_base(dev_priv, dev->agp->base);
1653
1654                 /* XXX */
1655                 radeon_write_agp_location(dev_priv,
1656                              (((dev_priv->gart_vm_start - 1 +
1657                                 dev_priv->gart_size) & 0xffff0000) |
1658                               (dev_priv->gart_vm_start >> 16)));
1659
1660                 ring_start = (dev_priv->cp_ring->offset
1661                               - dev->agp->base
1662                               + dev_priv->gart_vm_start);
1663         } else
1664 #endif
1665                 ring_start = (dev_priv->cp_ring->offset
1666                               - (unsigned long)dev->sg->virtual
1667                               + dev_priv->gart_vm_start);
1668
1669         RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
1670
1671         RADEON_WRITE(R600_CP_ME_CNTL, 0xff);
1672
1673         RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28));
1674
1675         /* Initialize the scratch register pointer.  This will cause
1676          * the scratch register values to be written out to memory
1677          * whenever they are updated.
1678          *
1679          * We simply put this behind the ring read pointer, this works
1680          * with PCI GART as well as (whatever kind of) AGP GART
1681          */
1682         {
1683                 u64 scratch_addr;
1684
1685                 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR);
1686                 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
1687                 scratch_addr += R600_SCRATCH_REG_OFFSET;
1688                 scratch_addr >>= 8;
1689                 scratch_addr &= 0xffffffff;
1690
1691                 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr);
1692         }
1693
1694         RADEON_WRITE(R600_SCRATCH_UMSK, 0x7);
1695
1696         /* Turn on bus mastering */
1697         radeon_enable_bm(dev_priv);
1698
1699         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
1700         RADEON_WRITE(R600_LAST_FRAME_REG, 0);
1701
1702         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
1703         RADEON_WRITE(R600_LAST_DISPATCH_REG, 0);
1704
1705         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
1706         RADEON_WRITE(R600_LAST_CLEAR_REG, 0);
1707
1708         /* reset sarea copies of these */
1709         if (dev_priv->sarea_priv) {
1710                 dev_priv->sarea_priv->last_frame = 0;
1711                 dev_priv->sarea_priv->last_dispatch = 0;
1712                 dev_priv->sarea_priv->last_clear = 0;
1713         }
1714
1715         r600_do_wait_for_idle(dev_priv);
1716
1717 }
1718
1719 int r600_do_cleanup_cp(struct drm_device *dev)
1720 {
1721         drm_radeon_private_t *dev_priv = dev->dev_private;
1722         DRM_DEBUG("\n");
1723
1724         /* Make sure interrupts are disabled here because the uninstall ioctl
1725          * may not have been called from userspace and after dev_private
1726          * is freed, it's too late.
1727          */
1728         if (dev->irq_enabled)
1729                 drm_irq_uninstall(dev);
1730
1731 #if __OS_HAS_AGP
1732         if (dev_priv->flags & RADEON_IS_AGP) {
1733                 if (dev_priv->cp_ring != NULL) {
1734                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1735                         dev_priv->cp_ring = NULL;
1736                 }
1737                 if (dev_priv->ring_rptr != NULL) {
1738                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1739                         dev_priv->ring_rptr = NULL;
1740                 }
1741                 if (dev->agp_buffer_map != NULL) {
1742                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1743                         dev->agp_buffer_map = NULL;
1744                 }
1745         } else
1746 #endif
1747         {
1748
1749                 if (dev_priv->gart_info.bus_addr)
1750                         r600_page_table_cleanup(dev, &dev_priv->gart_info);
1751
1752                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1753                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1754                         dev_priv->gart_info.addr = 0;
1755                 }
1756         }
1757         /* only clear to the start of flags */
1758         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1759
1760         return 0;
1761 }
1762
1763 int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1764                     struct drm_file *file_priv)
1765 {
1766         drm_radeon_private_t *dev_priv = dev->dev_private;
1767
1768         DRM_DEBUG("\n");
1769
1770         /* if we require new memory map but we don't have it fail */
1771         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1772                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1773                 r600_do_cleanup_cp(dev);
1774                 return -EINVAL;
1775         }
1776
1777         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1778                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1779                 dev_priv->flags &= ~RADEON_IS_AGP;
1780                 /* The writeback test succeeds, but when writeback is enabled,
1781                  * the ring buffer read ptr update fails after first 128 bytes.
1782                  */
1783                 radeon_no_wb = 1;
1784         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1785                  && !init->is_pci) {
1786                 DRM_DEBUG("Restoring AGP flag\n");
1787                 dev_priv->flags |= RADEON_IS_AGP;
1788         }
1789
1790         dev_priv->usec_timeout = init->usec_timeout;
1791         if (dev_priv->usec_timeout < 1 ||
1792             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1793                 DRM_DEBUG("TIMEOUT problem!\n");
1794                 r600_do_cleanup_cp(dev);
1795                 return -EINVAL;
1796         }
1797
1798         /* Enable vblank on CRTC1 for older X servers
1799          */
1800         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1801
1802         dev_priv->cp_mode = init->cp_mode;
1803
1804         /* We don't support anything other than bus-mastering ring mode,
1805          * but the ring can be in either AGP or PCI space for the ring
1806          * read pointer.
1807          */
1808         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1809             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1810                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1811                 r600_do_cleanup_cp(dev);
1812                 return -EINVAL;
1813         }
1814
1815         switch (init->fb_bpp) {
1816         case 16:
1817                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1818                 break;
1819         case 32:
1820         default:
1821                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1822                 break;
1823         }
1824         dev_priv->front_offset = init->front_offset;
1825         dev_priv->front_pitch = init->front_pitch;
1826         dev_priv->back_offset = init->back_offset;
1827         dev_priv->back_pitch = init->back_pitch;
1828
1829         dev_priv->ring_offset = init->ring_offset;
1830         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1831         dev_priv->buffers_offset = init->buffers_offset;
1832         dev_priv->gart_textures_offset = init->gart_textures_offset;
1833
1834         dev_priv->sarea = drm_getsarea(dev);
1835         if (!dev_priv->sarea) {
1836                 DRM_ERROR("could not find sarea!\n");
1837                 r600_do_cleanup_cp(dev);
1838                 return -EINVAL;
1839         }
1840
1841         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1842         if (!dev_priv->cp_ring) {
1843                 DRM_ERROR("could not find cp ring region!\n");
1844                 r600_do_cleanup_cp(dev);
1845                 return -EINVAL;
1846         }
1847         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1848         if (!dev_priv->ring_rptr) {
1849                 DRM_ERROR("could not find ring read pointer!\n");
1850                 r600_do_cleanup_cp(dev);
1851                 return -EINVAL;
1852         }
1853         dev->agp_buffer_token = init->buffers_offset;
1854         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1855         if (!dev->agp_buffer_map) {
1856                 DRM_ERROR("could not find dma buffer region!\n");
1857                 r600_do_cleanup_cp(dev);
1858                 return -EINVAL;
1859         }
1860
1861         if (init->gart_textures_offset) {
1862                 dev_priv->gart_textures =
1863                     drm_core_findmap(dev, init->gart_textures_offset);
1864                 if (!dev_priv->gart_textures) {
1865                         DRM_ERROR("could not find GART texture region!\n");
1866                         r600_do_cleanup_cp(dev);
1867                         return -EINVAL;
1868                 }
1869         }
1870
1871         dev_priv->sarea_priv =
1872             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1873                                     init->sarea_priv_offset);
1874
1875 #if __OS_HAS_AGP
1876         /* XXX */
1877         if (dev_priv->flags & RADEON_IS_AGP) {
1878                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1879                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1880                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1881                 if (!dev_priv->cp_ring->handle ||
1882                     !dev_priv->ring_rptr->handle ||
1883                     !dev->agp_buffer_map->handle) {
1884                         DRM_ERROR("could not find ioremap agp regions!\n");
1885                         r600_do_cleanup_cp(dev);
1886                         return -EINVAL;
1887                 }
1888         } else
1889 #endif
1890         {
1891                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1892                 dev_priv->ring_rptr->handle =
1893                     (void *)dev_priv->ring_rptr->offset;
1894                 dev->agp_buffer_map->handle =
1895                     (void *)dev->agp_buffer_map->offset;
1896
1897                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1898                           dev_priv->cp_ring->handle);
1899                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1900                           dev_priv->ring_rptr->handle);
1901                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1902                           dev->agp_buffer_map->handle);
1903         }
1904
1905         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
1906         dev_priv->fb_size =
1907                 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
1908                 - dev_priv->fb_location;
1909
1910         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1911                                         ((dev_priv->front_offset
1912                                           + dev_priv->fb_location) >> 10));
1913
1914         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1915                                        ((dev_priv->back_offset
1916                                          + dev_priv->fb_location) >> 10));
1917
1918         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1919                                         ((dev_priv->depth_offset
1920                                           + dev_priv->fb_location) >> 10));
1921
1922         dev_priv->gart_size = init->gart_size;
1923
1924         /* New let's set the memory map ... */
1925         if (dev_priv->new_memmap) {
1926                 u32 base = 0;
1927
1928                 DRM_INFO("Setting GART location based on new memory map\n");
1929
1930                 /* If using AGP, try to locate the AGP aperture at the same
1931                  * location in the card and on the bus, though we have to
1932                  * align it down.
1933                  */
1934 #if __OS_HAS_AGP
1935                 /* XXX */
1936                 if (dev_priv->flags & RADEON_IS_AGP) {
1937                         base = dev->agp->base;
1938                         /* Check if valid */
1939                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1940                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1941                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1942                                          dev->agp->base);
1943                                 base = 0;
1944                         }
1945                 }
1946 #endif
1947                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1948                 if (base == 0) {
1949                         base = dev_priv->fb_location + dev_priv->fb_size;
1950                         if (base < dev_priv->fb_location ||
1951                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1952                                 base = dev_priv->fb_location
1953                                         - dev_priv->gart_size;
1954                 }
1955                 dev_priv->gart_vm_start = base & 0xffc00000u;
1956                 if (dev_priv->gart_vm_start != base)
1957                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1958                                  base, dev_priv->gart_vm_start);
1959         }
1960
1961 #if __OS_HAS_AGP
1962         /* XXX */
1963         if (dev_priv->flags & RADEON_IS_AGP)
1964                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1965                                                  - dev->agp->base
1966                                                  + dev_priv->gart_vm_start);
1967         else
1968 #endif
1969                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1970                                                  - (unsigned long)dev->sg->virtual
1971                                                  + dev_priv->gart_vm_start);
1972
1973         DRM_DEBUG("fb 0x%08x size %d\n",
1974                   (unsigned int) dev_priv->fb_location,
1975                   (unsigned int) dev_priv->fb_size);
1976         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1977         DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
1978                   (unsigned int) dev_priv->gart_vm_start);
1979         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
1980                   dev_priv->gart_buffers_offset);
1981
1982         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1983         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1984                               + init->ring_size / sizeof(u32));
1985         dev_priv->ring.size = init->ring_size;
1986         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1987
1988         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1989         dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
1990
1991         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1992         dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
1993
1994         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1995
1996         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1997
1998 #if __OS_HAS_AGP
1999         if (dev_priv->flags & RADEON_IS_AGP) {
2000                 /* XXX turn off pcie gart */
2001         } else
2002 #endif
2003         {
2004                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2005                 /* if we have an offset set from userspace */
2006                 if (!dev_priv->pcigart_offset_set) {
2007                         DRM_ERROR("Need gart offset from userspace\n");
2008                         r600_do_cleanup_cp(dev);
2009                         return -EINVAL;
2010                 }
2011
2012                 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2013
2014                 dev_priv->gart_info.bus_addr =
2015                         dev_priv->pcigart_offset + dev_priv->fb_location;
2016                 dev_priv->gart_info.mapping.offset =
2017                         dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2018                 dev_priv->gart_info.mapping.size =
2019                         dev_priv->gart_info.table_size;
2020
2021                 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2022                 if (!dev_priv->gart_info.mapping.handle) {
2023                         DRM_ERROR("ioremap failed.\n");
2024                         r600_do_cleanup_cp(dev);
2025                         return -EINVAL;
2026                 }
2027
2028                 dev_priv->gart_info.addr =
2029                         dev_priv->gart_info.mapping.handle;
2030
2031                 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2032                           dev_priv->gart_info.addr,
2033                           dev_priv->pcigart_offset);
2034
2035                 if (!r600_page_table_init(dev)) {
2036                         DRM_ERROR("Failed to init GART table\n");
2037                         r600_do_cleanup_cp(dev);
2038                         return -EINVAL;
2039                 }
2040
2041                 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2042                         r700_vm_init(dev);
2043                 else
2044                         r600_vm_init(dev);
2045         }
2046
2047         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2048                 r700_cp_load_microcode(dev_priv);
2049         else
2050                 r600_cp_load_microcode(dev_priv);
2051
2052         r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2053
2054         dev_priv->last_buf = 0;
2055
2056         r600_do_engine_reset(dev);
2057         r600_test_writeback(dev_priv);
2058
2059         return 0;
2060 }
2061
2062 int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
2063 {
2064         drm_radeon_private_t *dev_priv = dev->dev_private;
2065
2066         DRM_DEBUG("\n");
2067         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2068                 r700_vm_init(dev);
2069                 r700_cp_load_microcode(dev_priv);
2070         } else {
2071                 r600_vm_init(dev);
2072                 r600_cp_load_microcode(dev_priv);
2073         }
2074         r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2075         r600_do_engine_reset(dev);
2076
2077         return 0;
2078 }
2079
2080 /* Wait for the CP to go idle.
2081  */
2082 int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2083 {
2084         RING_LOCALS;
2085         DRM_DEBUG("\n");
2086
2087         BEGIN_RING(5);
2088         OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2089         OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2090         /* wait for 3D idle clean */
2091         OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2092         OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2093         OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2094
2095         ADVANCE_RING();
2096         COMMIT_RING();
2097
2098         return r600_do_wait_for_idle(dev_priv);
2099 }
2100
2101 /* Start the Command Processor.
2102  */
2103 void r600_do_cp_start(drm_radeon_private_t *dev_priv)
2104 {
2105         u32 cp_me;
2106         RING_LOCALS;
2107         DRM_DEBUG("\n");
2108
2109         BEGIN_RING(7);
2110         OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2111         OUT_RING(0x00000001);
2112         if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2113                 OUT_RING(0x00000003);
2114         else
2115                 OUT_RING(0x00000000);
2116         OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2117         OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2118         OUT_RING(0x00000000);
2119         OUT_RING(0x00000000);
2120         ADVANCE_RING();
2121         COMMIT_RING();
2122
2123         /* set the mux and reset the halt bit */
2124         cp_me = 0xff;
2125         RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2126
2127         dev_priv->cp_running = 1;
2128
2129 }
2130
2131 void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
2132 {
2133         u32 cur_read_ptr;
2134         DRM_DEBUG("\n");
2135
2136         cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
2137         RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
2138         SET_RING_HEAD(dev_priv, cur_read_ptr);
2139         dev_priv->ring.tail = cur_read_ptr;
2140 }
2141
2142 void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
2143 {
2144         uint32_t cp_me;
2145
2146         DRM_DEBUG("\n");
2147
2148         cp_me = 0xff | R600_CP_ME_HALT;
2149
2150         RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2151
2152         dev_priv->cp_running = 0;
2153 }
2154
2155 int r600_cp_dispatch_indirect(struct drm_device *dev,
2156                               struct drm_buf *buf, int start, int end)
2157 {
2158         drm_radeon_private_t *dev_priv = dev->dev_private;
2159         RING_LOCALS;
2160
2161         if (start != end) {
2162                 unsigned long offset = (dev_priv->gart_buffers_offset
2163                                         + buf->offset + start);
2164                 int dwords = (end - start + 3) / sizeof(u32);
2165
2166                 DRM_DEBUG("dwords:%d\n", dwords);
2167                 DRM_DEBUG("offset 0x%lx\n", offset);
2168
2169
2170                 /* Indirect buffer data must be a multiple of 16 dwords.
2171                  * pad the data with a Type-2 CP packet.
2172                  */
2173                 while (dwords & 0xf) {
2174                         u32 *data = (u32 *)
2175                             ((char *)dev->agp_buffer_map->handle
2176                              + buf->offset + start);
2177                         data[dwords++] = RADEON_CP_PACKET2;
2178                 }
2179
2180                 /* Fire off the indirect buffer */
2181                 BEGIN_RING(4);
2182                 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
2183                 OUT_RING((offset & 0xfffffffc));
2184                 OUT_RING((upper_32_bits(offset) & 0xff));
2185                 OUT_RING(dwords);
2186                 ADVANCE_RING();
2187         }
2188
2189         return 0;
2190 }