Document the use of SDT_SYS386IGT vs SDT_SYS386TGT when setting up the
[dragonfly.git] / sys / i386 / i386 / identcpu.c
1 /*
2  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3  * Copyright (c) 1992 Terrence R. Lambert.
4  * Copyright (c) 1997 KATO Takenori.
5  * Copyright (c) 2001 Tamotsu Hattori.
6  * Copyright (c) 2001 Mitsuru IWASAKI.
7  * All rights reserved.
8  *
9  * This code is derived from software contributed to Berkeley by
10  * William Jolitz.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  *    notice, this list of conditions and the following disclaimer in the
19  *    documentation and/or other materials provided with the distribution.
20  * 3. All advertising materials mentioning features or use of this software
21  *    must display the following acknowledgement:
22  *      This product includes software developed by the University of
23  *      California, Berkeley and its contributors.
24  * 4. Neither the name of the University nor the names of its contributors
25  *    may be used to endorse or promote products derived from this software
26  *    without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38  * SUCH DAMAGE.
39  *
40  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41  * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.80.2.15 2003/04/11 17:06:41 jhb Exp $
42  * $DragonFly: src/sys/i386/i386/Attic/identcpu.c,v 1.9 2005/11/06 07:28:47 dillon Exp $
43  */
44
45 #include "opt_cpu.h"
46
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/sysctl.h>
51 #include <sys/lock.h>
52
53 #include <machine/asmacros.h>
54 #include <machine/clock.h>
55 #include <machine/cputypes.h>
56 #include <machine/segments.h>
57 #include <machine/specialreg.h>
58 #include <machine/md_var.h>
59
60 #include <i386/isa/intr_machdep.h>
61
62 #define IDENTBLUE_CYRIX486      0
63 #define IDENTBLUE_IBMCPU        1
64 #define IDENTBLUE_CYRIXM2       2
65
66 /* XXX - should be in header file: */
67 void printcpuinfo(void);
68 void finishidentcpu(void);
69 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
70 void    enable_K5_wt_alloc(void);
71 void    enable_K6_wt_alloc(void);
72 void    enable_K6_2_wt_alloc(void);
73 #endif
74 void panicifcpuunsupported(void);
75
76 static void identifycyrix(void);
77 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
78 static void print_AMD_features(void);
79 #endif
80 static void print_AMD_info(void);
81 static void print_AMD_assoc(int i);
82 static void print_transmeta_info(void);
83 static void setup_tmx86_longrun(void);
84
85 int     cpu_class = CPUCLASS_386;
86 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
87 u_int   cyrix_did;              /* Device ID of Cyrix CPU */
88 char machine[] = "i386";
89 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 
90     machine, 0, "Machine class");
91
92 static char cpu_model[128];
93 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 
94     cpu_model, 0, "Machine model");
95
96 static char cpu_brand[48];
97
98 #define MAX_ADDITIONAL_INFO     16
99
100 static const char *additional_cpu_info_ary[MAX_ADDITIONAL_INFO];
101 static u_int additional_cpu_info_count;
102
103 #define MAX_BRAND_INDEX 8
104
105 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
106         NULL,                   /* No brand */
107         "Intel Celeron",
108         "Intel Pentium III",
109         "Intel Pentium III Xeon",
110         NULL,
111         NULL,
112         NULL,
113         NULL,
114         "Intel Pentium 4"
115 };
116
117 static struct cpu_nameclass i386_cpus[] = {
118         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
119         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
120         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
121         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
122         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
123         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
124         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
125         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
126         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
127         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
128         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
129         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
130         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
131         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
132         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
133         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
134         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
135 };
136
137 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
138 int has_f00f_bug = 0;           /* Initialized so that it can be patched. */
139 #endif
140
141 void
142 printcpuinfo(void)
143 {
144 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
145         u_int regs[4], i;
146 #endif
147         char *brand;
148
149         cpu_class = i386_cpus[cpu].cpu_class;
150         printf("CPU: ");
151         strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
152
153 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
154         /* Check for extended CPUID information and a processor name. */
155         if (cpu_high > 0 &&
156             (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
157             strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
158             strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
159             strcmp(cpu_vendor, "TransmetaCPU") == 0)) {
160                 do_cpuid(0x80000000, regs);
161                 if (regs[0] >= 0x80000000) {
162                         cpu_exthigh = regs[0];
163                         if (cpu_exthigh >= 0x80000004) {
164                                 brand = cpu_brand;
165                                 for (i = 0x80000002; i < 0x80000005; i++) {
166                                         do_cpuid(i, regs);
167                                         memcpy(brand, regs, sizeof(regs));
168                                         brand += sizeof(regs);
169                                 }
170                         }
171                 }
172         }
173
174         if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
175                 if ((cpu_id & 0xf00) > 0x300) {
176                         u_int brand_index;
177
178                         cpu_model[0] = '\0';
179
180                         switch (cpu_id & 0x3000) {
181                         case 0x1000:
182                                 strcpy(cpu_model, "Overdrive ");
183                                 break;
184                         case 0x2000:
185                                 strcpy(cpu_model, "Dual ");
186                                 break;
187                         }
188
189                         switch (cpu_id & 0xf00) {
190                         case 0x400:
191                                 strcat(cpu_model, "i486 ");
192                                 /* Check the particular flavor of 486 */
193                                 switch (cpu_id & 0xf0) {
194                                 case 0x00:
195                                 case 0x10:
196                                         strcat(cpu_model, "DX");
197                                         break;
198                                 case 0x20:
199                                         strcat(cpu_model, "SX");
200                                         break;
201                                 case 0x30:
202                                         strcat(cpu_model, "DX2");
203                                         break;
204                                 case 0x40:
205                                         strcat(cpu_model, "SL");
206                                         break;
207                                 case 0x50:
208                                         strcat(cpu_model, "SX2");
209                                         break;
210                                 case 0x70:
211                                         strcat(cpu_model,
212                                             "DX2 Write-Back Enhanced");
213                                         break;
214                                 case 0x80:
215                                         strcat(cpu_model, "DX4");
216                                         break;
217                                 }
218                                 break;
219                         case 0x500:
220                                 /* Check the particular flavor of 586 */
221                                 strcat(cpu_model, "Pentium");
222                                 switch (cpu_id & 0xf0) {
223                                 case 0x00:
224                                         strcat(cpu_model, " A-step");
225                                         break;
226                                 case 0x10:
227                                         strcat(cpu_model, "/P5");
228                                         break;
229                                 case 0x20:
230                                         strcat(cpu_model, "/P54C");
231                                         break;
232                                 case 0x30:
233                                         strcat(cpu_model, "/P54T Overdrive");
234                                         break;
235                                 case 0x40:
236                                         strcat(cpu_model, "/P55C");
237                                         break;
238                                 case 0x70:
239                                         strcat(cpu_model, "/P54C");
240                                         break;
241                                 case 0x80:
242                                         strcat(cpu_model, "/P55C (quarter-micron)");
243                                         break;
244                                 default:
245                                         /* nothing */
246                                         break;
247                                 }
248 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
249                                 /*
250                                  * XXX - If/when Intel fixes the bug, this
251                                  * should also check the version of the
252                                  * CPU, not just that it's a Pentium.
253                                  */
254                                 has_f00f_bug = 1;
255 #endif
256                                 break;
257                         case 0x600:
258                                 /* Check the particular flavor of 686 */
259                                 switch (cpu_id & 0xf0) {
260                                 case 0x00:
261                                         strcat(cpu_model, "Pentium Pro A-step");
262                                         break;
263                                 case 0x10:
264                                         strcat(cpu_model, "Pentium Pro");
265                                         break;
266                                 case 0x30:
267                                 case 0x50:
268                                 case 0x60:
269                                         strcat(cpu_model,
270                                 "Pentium II/Pentium II Xeon/Celeron");
271                                         cpu = CPU_PII;
272                                         break;
273                                 case 0x70:
274                                 case 0x80:
275                                 case 0xa0:
276                                 case 0xb0:
277                                         strcat(cpu_model,
278                                         "Pentium III/Pentium III Xeon/Celeron");
279                                         cpu = CPU_PIII;
280                                         break;
281                                 default:
282                                         strcat(cpu_model, "Unknown 80686");
283                                         break;
284                                 }
285                                 break;
286                         case 0xf00:
287                                 strcat(cpu_model, "Pentium 4");
288                                 cpu = CPU_P4;
289                                 break;
290                         default:
291                                 strcat(cpu_model, "unknown");
292                                 break;
293                         }
294
295                         /*
296                          * If we didn't get a brand name from the extended
297                          * CPUID, try to look it up in the brand table.
298                          */
299                         if (cpu_high > 0 && *cpu_brand == '\0') {
300                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
301                                 if (brand_index <= MAX_BRAND_INDEX &&
302                                     cpu_brandtable[brand_index] != NULL)
303                                         strcpy(cpu_brand,
304                                             cpu_brandtable[brand_index]);
305                         }
306                 }
307         } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
308                 /*
309                  * Values taken from AMD Processor Recognition
310                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
311                  * (also describes ``Features'' encodings.
312                  */
313                 strcpy(cpu_model, "AMD ");
314                 switch (cpu_id & 0xFF0) {
315                 case 0x410:
316                         strcat(cpu_model, "Standard Am486DX");
317                         break;
318                 case 0x430:
319                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
320                         break;
321                 case 0x470:
322                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
323                         break;
324                 case 0x480:
325                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
326                         break;
327                 case 0x490:
328                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
329                         break;
330                 case 0x4E0:
331                         strcat(cpu_model, "Am5x86 Write-Through");
332                         break;
333                 case 0x4F0:
334                         strcat(cpu_model, "Am5x86 Write-Back");
335                         break;
336                 case 0x500:
337                         strcat(cpu_model, "K5 model 0");
338                         tsc_is_broken = 1;
339                         break;
340                 case 0x510:
341                         strcat(cpu_model, "K5 model 1");
342                         break;
343                 case 0x520:
344                         strcat(cpu_model, "K5 PR166 (model 2)");
345                         break;
346                 case 0x530:
347                         strcat(cpu_model, "K5 PR200 (model 3)");
348                         break;
349                 case 0x560:
350                         strcat(cpu_model, "K6");
351                         break;
352                 case 0x570:
353                         strcat(cpu_model, "K6 266 (model 1)");
354                         break;
355                 case 0x580:
356                         strcat(cpu_model, "K6-2");
357                         break;
358                 case 0x590:
359                         strcat(cpu_model, "K6-III");
360                         break;
361                 default:
362                         strcat(cpu_model, "Unknown");
363                         break;
364                 }
365 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
366                 if ((cpu_id & 0xf00) == 0x500) {
367                         if (((cpu_id & 0x0f0) > 0)
368                             && ((cpu_id & 0x0f0) < 0x60)
369                             && ((cpu_id & 0x00f) > 3))
370                                 enable_K5_wt_alloc();
371                         else if (((cpu_id & 0x0f0) > 0x80)
372                                  || (((cpu_id & 0x0f0) == 0x80)
373                                      && (cpu_id & 0x00f) > 0x07))
374                                 enable_K6_2_wt_alloc();
375                         else if ((cpu_id & 0x0f0) > 0x50)
376                                 enable_K6_wt_alloc();
377                 }
378 #endif
379         } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
380                 strcpy(cpu_model, "Cyrix ");
381                 switch (cpu_id & 0xff0) {
382                 case 0x440:
383                         strcat(cpu_model, "MediaGX");
384                         break;
385                 case 0x520:
386                         strcat(cpu_model, "6x86");
387                         break;
388                 case 0x540:
389                         cpu_class = CPUCLASS_586;
390                         strcat(cpu_model, "GXm");
391                         break;
392                 case 0x600:
393                         strcat(cpu_model, "6x86MX");
394                         break;
395                 default:
396                         /*
397                          * Even though CPU supports the cpuid
398                          * instruction, it can be disabled.
399                          * Therefore, this routine supports all Cyrix
400                          * CPUs.
401                          */
402                         switch (cyrix_did & 0xf0) {
403                         case 0x00:
404                                 switch (cyrix_did & 0x0f) {
405                                 case 0x00:
406                                         strcat(cpu_model, "486SLC");
407                                         break;
408                                 case 0x01:
409                                         strcat(cpu_model, "486DLC");
410                                         break;
411                                 case 0x02:
412                                         strcat(cpu_model, "486SLC2");
413                                         break;
414                                 case 0x03:
415                                         strcat(cpu_model, "486DLC2");
416                                         break;
417                                 case 0x04:
418                                         strcat(cpu_model, "486SRx");
419                                         break;
420                                 case 0x05:
421                                         strcat(cpu_model, "486DRx");
422                                         break;
423                                 case 0x06:
424                                         strcat(cpu_model, "486SRx2");
425                                         break;
426                                 case 0x07:
427                                         strcat(cpu_model, "486DRx2");
428                                         break;
429                                 case 0x08:
430                                         strcat(cpu_model, "486SRu");
431                                         break;
432                                 case 0x09:
433                                         strcat(cpu_model, "486DRu");
434                                         break;
435                                 case 0x0a:
436                                         strcat(cpu_model, "486SRu2");
437                                         break;
438                                 case 0x0b:
439                                         strcat(cpu_model, "486DRu2");
440                                         break;
441                                 default:
442                                         strcat(cpu_model, "Unknown");
443                                         break;
444                                 }
445                                 break;
446                         case 0x10:
447                                 switch (cyrix_did & 0x0f) {
448                                 case 0x00:
449                                         strcat(cpu_model, "486S");
450                                         break;
451                                 case 0x01:
452                                         strcat(cpu_model, "486S2");
453                                         break;
454                                 case 0x02:
455                                         strcat(cpu_model, "486Se");
456                                         break;
457                                 case 0x03:
458                                         strcat(cpu_model, "486S2e");
459                                         break;
460                                 case 0x0a:
461                                         strcat(cpu_model, "486DX");
462                                         break;
463                                 case 0x0b:
464                                         strcat(cpu_model, "486DX2");
465                                         break;
466                                 case 0x0f:
467                                         strcat(cpu_model, "486DX4");
468                                         break;
469                                 default:
470                                         strcat(cpu_model, "Unknown");
471                                         break;
472                                 }
473                                 break;
474                         case 0x20:
475                                 if ((cyrix_did & 0x0f) < 8)
476                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
477                                 else
478                                         strcat(cpu_model, "5x86");
479                                 break;
480                         case 0x30:
481                                 strcat(cpu_model, "6x86");
482                                 break;
483                         case 0x40:
484                                 if ((cyrix_did & 0xf000) == 0x3000) {
485                                         cpu_class = CPUCLASS_586;
486                                         strcat(cpu_model, "GXm");
487                                 } else
488                                         strcat(cpu_model, "MediaGX");
489                                 break;
490                         case 0x50:
491                                 strcat(cpu_model, "6x86MX");
492                                 break;
493                         case 0xf0:
494                                 switch (cyrix_did & 0x0f) {
495                                 case 0x0d:
496                                         strcat(cpu_model, "Overdrive CPU");
497                                 case 0x0e:
498                                         strcpy(cpu_model, "Texas Instruments 486SXL");
499                                         break;
500                                 case 0x0f:
501                                         strcat(cpu_model, "486SLC/DLC");
502                                         break;
503                                 default:
504                                         strcat(cpu_model, "Unknown");
505                                         break;
506                                 }
507                                 break;
508                         default:
509                                 strcat(cpu_model, "Unknown");
510                                 break;
511                         }
512                         break;
513                 }
514         } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
515                 strcpy(cpu_model, "Rise ");
516                 switch (cpu_id & 0xff0) {
517                 case 0x500:
518                         strcat(cpu_model, "mP6");
519                         break;
520                 default:
521                         strcat(cpu_model, "Unknown");
522                 }
523         } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
524                 switch (cpu_id & 0xff0) {
525                 case 0x540:
526                         strcpy(cpu_model, "IDT WinChip C6");
527                         tsc_is_broken = 1;
528                         break;
529                 case 0x580:
530                         strcpy(cpu_model, "IDT WinChip 2");
531                         break;
532                 case 0x670:
533                         strcpy(cpu_model, "VIA C3 Samuel 2");
534                         break;
535                 default:
536                         strcpy(cpu_model, "VIA/IDT Unknown");
537                 }
538         } else if (strcmp(cpu_vendor, "IBM") == 0) {
539                 strcpy(cpu_model, "Blue Lightning CPU");
540         }
541
542         /*
543          * Replace cpu_model with cpu_brand minus leading spaces if
544          * we have one.
545          */
546         brand = cpu_brand;
547         while (*brand == ' ')
548                 ++brand;
549         if (*brand != '\0')
550                 strcpy(cpu_model, brand);
551
552 #endif
553
554         printf("%s (", cpu_model);
555         switch(cpu_class) {
556         case CPUCLASS_286:
557                 printf("286");
558                 break;
559 #if defined(I386_CPU)
560         case CPUCLASS_386:
561                 printf("386");
562                 break;
563 #endif
564 #if defined(I486_CPU)
565         case CPUCLASS_486:
566                 printf("486");
567                 /* bzero = i486_bzero; */
568                 break;
569 #endif
570 #if defined(I586_CPU)
571         case CPUCLASS_586:
572                 printf("%d.%02d-MHz ",
573                        (tsc_freq + 4999) / 1000000,
574                        ((tsc_freq + 4999) / 10000) % 100);
575                 printf("586");
576                 break;
577 #endif
578 #if defined(I686_CPU)
579         case CPUCLASS_686:
580                 printf("%d.%02d-MHz ",
581                        (tsc_freq + 4999) / 1000000,
582                        ((tsc_freq + 4999) / 10000) % 100);
583                 printf("686");
584                 break;
585 #endif
586         default:
587                 printf("Unknown");      /* will panic below... */
588         }
589         printf("-class CPU)\n");
590 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
591         if(*cpu_vendor)
592                 printf("  Origin = \"%s\"",cpu_vendor);
593         if(cpu_id)
594                 printf("  Id = 0x%x", cpu_id);
595
596         if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
597             strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
598             strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
599             strcmp(cpu_vendor, "CentaurHauls") == 0 ||
600                 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
601                  ((cpu_id & 0xf00) > 0x500))) {
602                 printf("  Stepping = %u", cpu_id & 0xf);
603                 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
604                         printf("  DIR=0x%04x", cyrix_did);
605                 if (cpu_high > 0) {
606                         /*
607                          * Here we should probably set up flags indicating
608                          * whether or not various features are available.
609                          * The interesting ones are probably VME, PSE, PAE,
610                          * and PGE.  The code already assumes without bothering
611                          * to check that all CPUs >= Pentium have a TSC and
612                          * MSRs.
613                          */
614                         printf("\n  Features=0x%b", cpu_feature,
615                         "\020"
616                         "\001FPU"       /* Integral FPU */
617                         "\002VME"       /* Extended VM86 mode support */
618                         "\003DE"        /* Debugging Extensions (CR4.DE) */
619                         "\004PSE"       /* 4MByte page tables */
620                         "\005TSC"       /* Timestamp counter */
621                         "\006MSR"       /* Machine specific registers */
622                         "\007PAE"       /* Physical address extension */
623                         "\010MCE"       /* Machine Check support */
624                         "\011CX8"       /* CMPEXCH8 instruction */
625                         "\012APIC"      /* SMP local APIC */
626                         "\013oldMTRR"   /* Previous implementation of MTRR */
627                         "\014SEP"       /* Fast System Call */
628                         "\015MTRR"      /* Memory Type Range Registers */
629                         "\016PGE"       /* PG_G (global bit) support */
630                         "\017MCA"       /* Machine Check Architecture */
631                         "\020CMOV"      /* CMOV instruction */
632                         "\021PAT"       /* Page attributes table */
633                         "\022PSE36"     /* 36 bit address space support */
634                         "\023PN"        /* Processor Serial number */
635                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
636                         "\025<b20>"
637                         "\026DTS"       /* Debug Trace Store */
638                         "\027ACPI"      /* ACPI support */
639                         "\030MMX"       /* MMX instructions */
640                         "\031FXSR"      /* FXSAVE/FXRSTOR */
641                         "\032SSE"       /* Streaming SIMD Extensions */
642                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
643                         "\034SS"        /* Self snoop */
644                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
645                         "\036TM"        /* Thermal Monitor clock slowdown */
646                         "\037IA64"      /* CPU can execute IA64 instructions */
647                         "\040PBE"       /* Pending Break Enable */
648                         );
649
650                         /*
651                          * If this CPU supports hyperthreading then mention
652                          * the number of logical CPU's it contains.
653                          */
654                         if (cpu_feature & CPUID_HTT &&
655                             (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
656                                 printf("\n  Hyperthreading: %d logical CPUs",
657                                     (cpu_procinfo & CPUID_HTT_CORES) >> 16);
658                 }
659                 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
660                     cpu_exthigh >= 0x80000001)
661                         print_AMD_features();
662         } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
663                 printf("  DIR=0x%04x", cyrix_did);
664                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
665                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
666 #ifndef CYRIX_CACHE_REALLY_WORKS
667                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
668                         printf("\n  CPU cache: write-through mode");
669 #endif
670         }
671         /* Avoid ugly blank lines: only print newline when we have to. */
672         if (*cpu_vendor || cpu_id)
673                 printf("\n");
674
675 #endif
676         if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
677             strcmp(cpu_vendor, "TransmetaCPU") == 0) {
678                 setup_tmx86_longrun();
679         }
680
681         for (i = 0; i < additional_cpu_info_count; ++i) {
682                 printf("  %s\n", additional_cpu_info_ary[i]);
683         }
684
685         if (!bootverbose)
686                 return;
687
688         if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
689                 print_AMD_info();
690         else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
691                  strcmp(cpu_vendor, "TransmetaCPU") == 0)
692                 print_transmeta_info();
693
694 #ifdef I686_CPU
695         /*
696          * XXX - Do PPro CPUID level=2 stuff here?
697          *
698          * No, but maybe in a print_Intel_info() function called from here.
699          */
700 #endif
701 }
702
703 void
704 panicifcpuunsupported(void)
705 {
706
707 #if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
708 #error This kernel is not configured for one of the supported CPUs
709 #endif
710         /*
711          * Now that we have told the user what they have,
712          * let them know if that machine type isn't configured.
713          */
714         switch (cpu_class) {
715         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
716 #if !defined(I386_CPU)
717         case CPUCLASS_386:
718 #endif
719 #if !defined(I486_CPU)
720         case CPUCLASS_486:
721 #endif
722 #if !defined(I586_CPU)
723         case CPUCLASS_586:
724 #endif
725 #if !defined(I686_CPU)
726         case CPUCLASS_686:
727 #endif
728                 panic("CPU class not configured");
729         default:
730                 break;
731         }
732 }
733
734
735 static  volatile u_int trap_by_rdmsr;
736
737 /*
738  * Special exception 6 handler.
739  * The rdmsr instruction generates invalid opcodes fault on 486-class
740  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
741  * function identblue() when this handler is called.  Stacked eip should
742  * be advanced.
743  */
744 inthand_t       bluetrap6;
745
746 __asm(
747     "   .text                                                   \n"
748     "   .p2align 2,0x90                                         \n"
749     "   .type   " __XSTRING(CNAME(bluetrap6)) ",@function       \n"
750     __XSTRING(CNAME(bluetrap6)) ":                              \n"
751     "   ss                                                      \n"
752     "   movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "    \n"
753     "   addl    $2, (%esp)  # I know rdmsr is a 2-bytes instruction.    \n"
754     "   iret                                                    \n"
755 );
756
757 /*
758  * Special exception 13 handler.
759  * Accessing non-existent MSR generates general protection fault.
760  */
761 inthand_t       bluetrap13;
762
763 __asm(
764     "   .text                                                   \n"
765     "   .p2align 2,0x90                                         \n"
766     "   .type " __XSTRING(CNAME(bluetrap13)) ",@function        \n"
767     __XSTRING(CNAME(bluetrap13)) ":                             \n"
768     "   ss                                                      \n"
769     "   movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "    \n"
770     "   popl    %eax                    # discard errorcode.    \n"
771     "   addl    $2, (%esp) # I know rdmsr is a 2-bytes instruction.     \n"
772     "   iret                                                    \n"
773 );
774
775 /*
776  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
777  * support cpuid instruction.  This function should be called after
778  * loading interrupt descriptor table register.
779  *
780  * I don't like this method that handles fault, but I couldn't get
781  * information for any other methods.  Does blue giant know?
782  */
783 static int
784 identblue(void)
785 {
786
787         trap_by_rdmsr = 0;
788
789         /*
790          * Cyrix 486-class CPU does not support rdmsr instruction.
791          * The rdmsr instruction generates invalid opcode fault, and exception
792          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
793          * bluetrap6() set the magic number to trap_by_rdmsr.
794          */
795         setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
796
797         /*
798          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
799          * In this case, rdmsr generates general protection fault, and
800          * exception will be trapped by bluetrap13().
801          */
802         setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
803
804         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
805
806         if (trap_by_rdmsr == 0xa8c1d)
807                 return IDENTBLUE_CYRIX486;
808         else if (trap_by_rdmsr == 0xa89c4)
809                 return IDENTBLUE_CYRIXM2;
810         return IDENTBLUE_IBMCPU;
811 }
812
813
814 /*
815  * identifycyrix() set lower 16 bits of cyrix_did as follows:
816  *
817  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
818  * +-------+-------+---------------+
819  * |  SID  |  RID  |   Device ID   |
820  * |    (DIR 1)    |    (DIR 0)    |
821  * +-------+-------+---------------+
822  */
823 static void
824 identifycyrix(void)
825 {
826         int     ccr2_test = 0, dir_test = 0;
827         u_char  ccr2, ccr3;
828
829         mpintr_lock();
830
831         ccr2 = read_cyrix_reg(CCR2);
832         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
833         read_cyrix_reg(CCR2);
834         if (read_cyrix_reg(CCR2) != ccr2)
835                 ccr2_test = 1;
836         write_cyrix_reg(CCR2, ccr2);
837
838         ccr3 = read_cyrix_reg(CCR3);
839         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
840         read_cyrix_reg(CCR3);
841         if (read_cyrix_reg(CCR3) != ccr3)
842                 dir_test = 1;                                   /* CPU supports DIRs. */
843         write_cyrix_reg(CCR3, ccr3);
844
845         if (dir_test) {
846                 /* Device ID registers are available. */
847                 cyrix_did = read_cyrix_reg(DIR1) << 8;
848                 cyrix_did += read_cyrix_reg(DIR0);
849         } else if (ccr2_test)
850                 cyrix_did = 0x0010;             /* 486S A-step */
851         else
852                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
853
854         mpintr_unlock();
855 }
856
857 /*
858  * Final stage of CPU identification. -- Should I check TI?
859  */
860 void
861 finishidentcpu(void)
862 {
863         int     isblue = 0;
864         u_char  ccr3;
865         u_int   regs[4];
866
867         if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
868                 if (cpu == CPU_486) {
869                         /*
870                          * These conditions are equivalent to:
871                          *     - CPU does not support cpuid instruction.
872                          *     - Cyrix/IBM CPU is detected.
873                          */
874                         isblue = identblue();
875                         if (isblue == IDENTBLUE_IBMCPU) {
876                                 strcpy(cpu_vendor, "IBM");
877                                 cpu = CPU_BLUE;
878                                 return;
879                         }
880                 }
881                 switch (cpu_id & 0xf00) {
882                 case 0x600:
883                         /*
884                          * Cyrix's datasheet does not describe DIRs.
885                          * Therefor, I assume it does not have them
886                          * and use the result of the cpuid instruction.
887                          * XXX they seem to have it for now at least. -Peter
888                          */
889                         identifycyrix();
890                         cpu = CPU_M2;
891                         break;
892                 default:
893                         identifycyrix();
894                         /*
895                          * This routine contains a trick.
896                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
897                          */
898                         switch (cyrix_did & 0x00f0) {
899                         case 0x00:
900                         case 0xf0:
901                                 cpu = CPU_486DLC;
902                                 break;
903                         case 0x10:
904                                 cpu = CPU_CY486DX;
905                                 break;
906                         case 0x20:
907                                 if ((cyrix_did & 0x000f) < 8)
908                                         cpu = CPU_M1;
909                                 else
910                                         cpu = CPU_M1SC;
911                                 break;
912                         case 0x30:
913                                 cpu = CPU_M1;
914                                 break;
915                         case 0x40:
916                                 /* MediaGX CPU */
917                                 cpu = CPU_M1SC;
918                                 break;
919                         default:
920                                 /* M2 and later CPUs are treated as M2. */
921                                 cpu = CPU_M2;
922
923                                 /*
924                                  * enable cpuid instruction.
925                                  */
926                                 ccr3 = read_cyrix_reg(CCR3);
927                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
928                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
929                                 write_cyrix_reg(CCR3, ccr3);
930
931                                 do_cpuid(0, regs);
932                                 cpu_high = regs[0];     /* eax */
933                                 do_cpuid(1, regs);
934                                 cpu_id = regs[0];       /* eax */
935                                 cpu_feature = regs[3];  /* edx */
936                                 break;
937                         }
938                 }
939         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
940                 /*
941                  * There are BlueLightning CPUs that do not change
942                  * undefined flags by dividing 5 by 2.  In this case,
943                  * the CPU identification routine in locore.s leaves
944                  * cpu_vendor null string and puts CPU_486 into the
945                  * cpu.
946                  */
947                 isblue = identblue();
948                 if (isblue == IDENTBLUE_IBMCPU) {
949                         strcpy(cpu_vendor, "IBM");
950                         cpu = CPU_BLUE;
951                         return;
952                 }
953         }
954 }
955
956 static void
957 print_AMD_assoc(int i)
958 {
959         if (i == 255)
960                 printf(", fully associative\n");
961         else
962                 printf(", %d-way associative\n", i);
963 }
964
965 static void
966 print_AMD_info(void)
967 {
968         quad_t amd_whcr;
969
970         if (cpu_exthigh >= 0x80000005) {
971                 u_int regs[4];
972
973                 do_cpuid(0x80000005, regs);
974                 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
975                 print_AMD_assoc(regs[1] >> 24);
976                 printf("Instruction TLB: %d entries", regs[1] & 0xff);
977                 print_AMD_assoc((regs[1] >> 8) & 0xff);
978                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
979                 printf(", %d bytes/line", regs[2] & 0xff);
980                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
981                 print_AMD_assoc((regs[2] >> 16) & 0xff);
982                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
983                 printf(", %d bytes/line", regs[3] & 0xff);
984                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
985                 print_AMD_assoc((regs[3] >> 16) & 0xff);
986                 if (cpu_exthigh >= 0x80000006) {        /* K6-III, or later */
987                         do_cpuid(0x80000006, regs);
988                         /*
989                          * Report right L2 cache size on Duron rev. A0.
990                          */
991                         if ((cpu_id & 0xFF0) == 0x630)
992                                 printf("L2 internal cache: 64 kbytes");
993                         else
994                                 printf("L2 internal cache: %d kbytes",
995                                         regs[2] >> 16);
996
997                         printf(", %d bytes/line", regs[2] & 0xff);
998                         printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
999                         print_AMD_assoc((regs[2] >> 12) & 0x0f);        
1000                 }
1001         }
1002         if (((cpu_id & 0xf00) == 0x500)
1003             && (((cpu_id & 0x0f0) > 0x80)
1004                 || (((cpu_id & 0x0f0) == 0x80)
1005                     && (cpu_id & 0x00f) > 0x07))) {
1006                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1007                 amd_whcr = rdmsr(0xc0000082);
1008                 if (!(amd_whcr & (0x3ff << 22))) {
1009                         printf("Write Allocate Disable\n");
1010                 } else {
1011                         printf("Write Allocate Enable Limit: %dM bytes\n",
1012                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1013                         printf("Write Allocate 15-16M bytes: %s\n",
1014                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1015                 }
1016         } else if (((cpu_id & 0xf00) == 0x500)
1017                    && ((cpu_id & 0x0f0) > 0x50)) {
1018                 /* K6, K6-2(old core) */
1019                 amd_whcr = rdmsr(0xc0000082);
1020                 if (!(amd_whcr & (0x7f << 1))) {
1021                         printf("Write Allocate Disable\n");
1022                 } else {
1023                         printf("Write Allocate Enable Limit: %dM bytes\n",
1024                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1025                         printf("Write Allocate 15-16M bytes: %s\n",
1026                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1027                         printf("Hardware Write Allocate Control: %s\n",
1028                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1029                 }
1030         }
1031 }
1032
1033 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
1034 static void
1035 print_AMD_features(void)
1036 {
1037         u_int regs[4];
1038
1039         /*
1040          * Values taken from AMD Processor Recognition
1041          * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
1042          */
1043         do_cpuid(0x80000001, regs);
1044         printf("\n  AMD Features=0x%b", regs[3] &~ cpu_feature,
1045                 "\020"          /* in hex */
1046                 "\001FPU"       /* Integral FPU */
1047                 "\002VME"       /* Extended VM86 mode support */
1048                 "\003DE"        /* Debug extensions */
1049                 "\004PSE"       /* 4MByte page tables */
1050                 "\005TSC"       /* Timestamp counter */
1051                 "\006MSR"       /* Machine specific registers */
1052                 "\007PAE"       /* Physical address extension */
1053                 "\010MCE"       /* Machine Check support */
1054                 "\011CX8"       /* CMPEXCH8 instruction */
1055                 "\012APIC"      /* SMP local APIC */
1056                 "\013<b10>"
1057                 "\014SYSCALL"   /* SYSENTER/SYSEXIT instructions */
1058                 "\015MTRR"      /* Memory Type Range Registers */
1059                 "\016PGE"       /* PG_G (global bit) support */
1060                 "\017MCA"       /* Machine Check Architecture */
1061                 "\020ICMOV"     /* CMOV instruction */
1062                 "\021PAT"       /* Page attributes table */
1063                 "\022PGE36"     /* 36 bit address space support */
1064                 "\023RSVD"      /* Reserved, unknown */
1065                 "\024MP"        /* Multiprocessor Capable */
1066                 "\025<b20>"
1067                 "\026<b21>"
1068                 "\027AMIE"      /* AMD MMX Instruction Extensions */
1069                 "\030MMX"
1070                 "\031FXSAVE"    /* FXSAVE/FXRSTOR */
1071                 "\032<b25>"
1072                 "\033<b26>"
1073                 "\034<b27>"
1074                 "\035<b28>"
1075                 "\036<b29>"
1076                 "\037DSP"       /* AMD 3DNow! Instruction Extensions */
1077                 "\0403DNow!"
1078                 );
1079 }
1080 #endif
1081
1082 /*
1083  * Transmeta Crusoe LongRun Support by Tamotsu Hattori. 
1084  */
1085
1086 #define MSR_TMx86_LONGRUN               0x80868010
1087 #define MSR_TMx86_LONGRUN_FLAGS         0x80868011
1088
1089 #define LONGRUN_MODE_MASK(x)            ((x) & 0x000000007f)
1090 #define LONGRUN_MODE_RESERVED(x)        ((x) & 0xffffff80)
1091 #define LONGRUN_MODE_WRITE(x, y)        (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y))
1092
1093 #define LONGRUN_MODE_MINFREQUENCY       0x00
1094 #define LONGRUN_MODE_ECONOMY            0x01
1095 #define LONGRUN_MODE_PERFORMANCE        0x02
1096 #define LONGRUN_MODE_MAXFREQUENCY       0x03
1097 #define LONGRUN_MODE_UNKNOWN            0x04
1098 #define LONGRUN_MODE_MAX                0x04
1099
1100 union msrinfo {
1101         u_int64_t       msr;
1102         u_int32_t       regs[2];
1103 };
1104
1105 u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
1106         /*  MSR low, MSR high, flags bit0 */
1107         {         0,      0,            0},     /* LONGRUN_MODE_MINFREQUENCY */
1108         {         0,    100,            0},     /* LONGRUN_MODE_ECONOMY */
1109         {         0,    100,            1},     /* LONGRUN_MODE_PERFORMANCE */
1110         {       100,    100,            1},     /* LONGRUN_MODE_MAXFREQUENCY */
1111 };
1112
1113 static u_int 
1114 tmx86_get_longrun_mode(void)
1115 {
1116         union msrinfo   msrinfo;
1117         u_int           low, high, flags, mode;
1118
1119         mpintr_lock();
1120
1121         msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1122         low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
1123         high = LONGRUN_MODE_MASK(msrinfo.regs[1]);
1124         flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
1125
1126         for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) {
1127                 if (low   == longrun_modes[mode][0] &&
1128                     high  == longrun_modes[mode][1] &&
1129                     flags == longrun_modes[mode][2]) {
1130                         goto out;
1131                 }
1132         }
1133         mode = LONGRUN_MODE_UNKNOWN;
1134 out:
1135         mpintr_unlock();
1136         return (mode);
1137 }
1138
1139 static u_int 
1140 tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
1141 {
1142         u_int           regs[4];
1143
1144         mpintr_lock();
1145
1146         do_cpuid(0x80860007, regs);
1147         *frequency = regs[0];
1148         *voltage = regs[1];
1149         *percentage = regs[2];
1150
1151         mpintr_unlock();
1152         return (1);
1153 }
1154
1155 static u_int 
1156 tmx86_set_longrun_mode(u_int mode)
1157 {
1158         union msrinfo   msrinfo;
1159
1160         if (mode >= LONGRUN_MODE_UNKNOWN) {
1161                 return (0);
1162         }
1163
1164         mpintr_lock();
1165
1166         /* Write LongRun mode values to Model Specific Register. */
1167         msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1168         msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0],
1169                                              longrun_modes[mode][0]);
1170         msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1],
1171                                              longrun_modes[mode][1]);
1172         wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
1173
1174         /* Write LongRun mode flags to Model Specific Register. */
1175         msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
1176         msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
1177         wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
1178
1179         mpintr_unlock();
1180         return (1);
1181 }
1182
1183 static u_int                     crusoe_longrun;
1184 static u_int                     crusoe_frequency;
1185 static u_int                     crusoe_voltage;
1186 static u_int                     crusoe_percentage;
1187 static struct sysctl_ctx_list    crusoe_sysctl_ctx;
1188 static struct sysctl_oid        *crusoe_sysctl_tree;
1189
1190 static int
1191 tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS)
1192 {
1193         u_int   mode;
1194         int     error;
1195
1196         crusoe_longrun = tmx86_get_longrun_mode();
1197         mode = crusoe_longrun;
1198         error = sysctl_handle_int(oidp, &mode, 0, req);
1199         if (error || !req->newptr) {
1200                 return (error);
1201         }
1202         if (mode >= LONGRUN_MODE_UNKNOWN) {
1203                 error = EINVAL;
1204                 return (error);
1205         }
1206         if (crusoe_longrun != mode) {
1207                 crusoe_longrun = mode;
1208                 tmx86_set_longrun_mode(crusoe_longrun);
1209         }
1210
1211         return (error);
1212 }
1213
1214 static int
1215 tmx86_status_sysctl(SYSCTL_HANDLER_ARGS)
1216 {
1217         u_int   val;
1218         int     error;
1219
1220         tmx86_get_longrun_status(&crusoe_frequency,
1221                                  &crusoe_voltage, &crusoe_percentage);
1222         val = *(u_int *)oidp->oid_arg1;
1223         error = sysctl_handle_int(oidp, &val, 0, req);
1224         return (error);
1225 }
1226
1227 static void
1228 setup_tmx86_longrun(void)
1229 {
1230         static int      done = 0;
1231
1232         if (done)
1233                 return;
1234         done++;
1235
1236         sysctl_ctx_init(&crusoe_sysctl_ctx);
1237         crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx,
1238                                 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1239                                 "crusoe", CTLFLAG_RD, 0,
1240                                 "Transmeta Crusoe LongRun support");
1241         SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1242                 OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW,
1243                 &crusoe_longrun, 0, tmx86_longrun_sysctl, "I",
1244                 "LongRun mode [0-3]");
1245         SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1246                 OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD,
1247                 &crusoe_frequency, 0, tmx86_status_sysctl, "I",
1248                 "Current frequency (MHz)");
1249         SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1250                 OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD,
1251                 &crusoe_voltage, 0, tmx86_status_sysctl, "I",
1252                 "Current voltage (mV)");
1253         SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1254                 OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD,
1255                 &crusoe_percentage, 0, tmx86_status_sysctl, "I",
1256                 "Processing performance (%)");
1257 }
1258
1259 static void
1260 print_transmeta_info()
1261 {
1262         u_int regs[4], nreg = 0;
1263
1264         do_cpuid(0x80860000, regs);
1265         nreg = regs[0];
1266         if (nreg >= 0x80860001) {
1267                 do_cpuid(0x80860001, regs);
1268                 printf("  Processor revision %u.%u.%u.%u\n",
1269                        (regs[1] >> 24) & 0xff,
1270                        (regs[1] >> 16) & 0xff,
1271                        (regs[1] >> 8) & 0xff,
1272                        regs[1] & 0xff);
1273         }
1274         if (nreg >= 0x80860002) {
1275                 do_cpuid(0x80860002, regs);
1276                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
1277                        (regs[1] >> 24) & 0xff,
1278                        (regs[1] >> 16) & 0xff,
1279                        (regs[1] >> 8) & 0xff,
1280                        regs[1] & 0xff,
1281                        regs[2]);
1282         }
1283         if (nreg >= 0x80860006) {
1284                 char info[65];
1285                 do_cpuid(0x80860003, (u_int*) &info[0]);
1286                 do_cpuid(0x80860004, (u_int*) &info[16]);
1287                 do_cpuid(0x80860005, (u_int*) &info[32]);
1288                 do_cpuid(0x80860006, (u_int*) &info[48]);
1289                 info[64] = 0;
1290                 printf("  %s\n", info);
1291         }
1292
1293         crusoe_longrun = tmx86_get_longrun_mode();
1294         tmx86_get_longrun_status(&crusoe_frequency,
1295                                  &crusoe_voltage, &crusoe_percentage);
1296         printf("  LongRun mode: %d  <%dMHz %dmV %d%%>\n", crusoe_longrun,
1297                crusoe_frequency, crusoe_voltage, crusoe_percentage);
1298 }
1299
1300 void
1301 additional_cpu_info(const char *line)
1302 {
1303         int i;
1304
1305         if ((i = additional_cpu_info_count) < MAX_ADDITIONAL_INFO) {
1306                 additional_cpu_info_ary[i] = line;
1307                 ++additional_cpu_info_count;
1308         }
1309 }
1310