2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 1997 KATO Takenori.
5 * Copyright (c) 2001 Tamotsu Hattori.
6 * Copyright (c) 2001 Mitsuru IWASAKI.
9 * This code is derived from software contributed to Berkeley by
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.80.2.15 2003/04/11 17:06:41 jhb Exp $
42 * $DragonFly: src/sys/i386/i386/Attic/identcpu.c,v 1.9 2005/11/06 07:28:47 dillon Exp $
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/sysctl.h>
53 #include <machine/asmacros.h>
54 #include <machine/clock.h>
55 #include <machine/cputypes.h>
56 #include <machine/segments.h>
57 #include <machine/specialreg.h>
58 #include <machine/md_var.h>
60 #include <i386/isa/intr_machdep.h>
62 #define IDENTBLUE_CYRIX486 0
63 #define IDENTBLUE_IBMCPU 1
64 #define IDENTBLUE_CYRIXM2 2
66 /* XXX - should be in header file: */
67 void printcpuinfo(void);
68 void finishidentcpu(void);
69 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
70 void enable_K5_wt_alloc(void);
71 void enable_K6_wt_alloc(void);
72 void enable_K6_2_wt_alloc(void);
74 void panicifcpuunsupported(void);
76 static void identifycyrix(void);
77 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
78 static void print_AMD_features(void);
80 static void print_AMD_info(void);
81 static void print_AMD_assoc(int i);
82 static void print_transmeta_info(void);
83 static void setup_tmx86_longrun(void);
85 int cpu_class = CPUCLASS_386;
86 u_int cpu_exthigh; /* Highest arg to extended CPUID */
87 u_int cyrix_did; /* Device ID of Cyrix CPU */
88 char machine[] = "i386";
89 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
90 machine, 0, "Machine class");
92 static char cpu_model[128];
93 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
94 cpu_model, 0, "Machine model");
96 static char cpu_brand[48];
98 #define MAX_ADDITIONAL_INFO 16
100 static const char *additional_cpu_info_ary[MAX_ADDITIONAL_INFO];
101 static u_int additional_cpu_info_count;
103 #define MAX_BRAND_INDEX 8
105 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
109 "Intel Pentium III Xeon",
117 static struct cpu_nameclass i386_cpus[] = {
118 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
119 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
120 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
121 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
122 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
123 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
124 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
125 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
126 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
127 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
128 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
129 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
130 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
131 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
132 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
133 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
134 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
137 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
138 int has_f00f_bug = 0; /* Initialized so that it can be patched. */
144 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
149 cpu_class = i386_cpus[cpu].cpu_class;
151 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
153 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
154 /* Check for extended CPUID information and a processor name. */
156 (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
157 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
158 strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
159 strcmp(cpu_vendor, "TransmetaCPU") == 0)) {
160 do_cpuid(0x80000000, regs);
161 if (regs[0] >= 0x80000000) {
162 cpu_exthigh = regs[0];
163 if (cpu_exthigh >= 0x80000004) {
165 for (i = 0x80000002; i < 0x80000005; i++) {
167 memcpy(brand, regs, sizeof(regs));
168 brand += sizeof(regs);
174 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
175 if ((cpu_id & 0xf00) > 0x300) {
180 switch (cpu_id & 0x3000) {
182 strcpy(cpu_model, "Overdrive ");
185 strcpy(cpu_model, "Dual ");
189 switch (cpu_id & 0xf00) {
191 strcat(cpu_model, "i486 ");
192 /* Check the particular flavor of 486 */
193 switch (cpu_id & 0xf0) {
196 strcat(cpu_model, "DX");
199 strcat(cpu_model, "SX");
202 strcat(cpu_model, "DX2");
205 strcat(cpu_model, "SL");
208 strcat(cpu_model, "SX2");
212 "DX2 Write-Back Enhanced");
215 strcat(cpu_model, "DX4");
220 /* Check the particular flavor of 586 */
221 strcat(cpu_model, "Pentium");
222 switch (cpu_id & 0xf0) {
224 strcat(cpu_model, " A-step");
227 strcat(cpu_model, "/P5");
230 strcat(cpu_model, "/P54C");
233 strcat(cpu_model, "/P54T Overdrive");
236 strcat(cpu_model, "/P55C");
239 strcat(cpu_model, "/P54C");
242 strcat(cpu_model, "/P55C (quarter-micron)");
248 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
250 * XXX - If/when Intel fixes the bug, this
251 * should also check the version of the
252 * CPU, not just that it's a Pentium.
258 /* Check the particular flavor of 686 */
259 switch (cpu_id & 0xf0) {
261 strcat(cpu_model, "Pentium Pro A-step");
264 strcat(cpu_model, "Pentium Pro");
270 "Pentium II/Pentium II Xeon/Celeron");
278 "Pentium III/Pentium III Xeon/Celeron");
282 strcat(cpu_model, "Unknown 80686");
287 strcat(cpu_model, "Pentium 4");
291 strcat(cpu_model, "unknown");
296 * If we didn't get a brand name from the extended
297 * CPUID, try to look it up in the brand table.
299 if (cpu_high > 0 && *cpu_brand == '\0') {
300 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
301 if (brand_index <= MAX_BRAND_INDEX &&
302 cpu_brandtable[brand_index] != NULL)
304 cpu_brandtable[brand_index]);
307 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
309 * Values taken from AMD Processor Recognition
310 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
311 * (also describes ``Features'' encodings.
313 strcpy(cpu_model, "AMD ");
314 switch (cpu_id & 0xFF0) {
316 strcat(cpu_model, "Standard Am486DX");
319 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
322 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
325 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
328 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
331 strcat(cpu_model, "Am5x86 Write-Through");
334 strcat(cpu_model, "Am5x86 Write-Back");
337 strcat(cpu_model, "K5 model 0");
341 strcat(cpu_model, "K5 model 1");
344 strcat(cpu_model, "K5 PR166 (model 2)");
347 strcat(cpu_model, "K5 PR200 (model 3)");
350 strcat(cpu_model, "K6");
353 strcat(cpu_model, "K6 266 (model 1)");
356 strcat(cpu_model, "K6-2");
359 strcat(cpu_model, "K6-III");
362 strcat(cpu_model, "Unknown");
365 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
366 if ((cpu_id & 0xf00) == 0x500) {
367 if (((cpu_id & 0x0f0) > 0)
368 && ((cpu_id & 0x0f0) < 0x60)
369 && ((cpu_id & 0x00f) > 3))
370 enable_K5_wt_alloc();
371 else if (((cpu_id & 0x0f0) > 0x80)
372 || (((cpu_id & 0x0f0) == 0x80)
373 && (cpu_id & 0x00f) > 0x07))
374 enable_K6_2_wt_alloc();
375 else if ((cpu_id & 0x0f0) > 0x50)
376 enable_K6_wt_alloc();
379 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
380 strcpy(cpu_model, "Cyrix ");
381 switch (cpu_id & 0xff0) {
383 strcat(cpu_model, "MediaGX");
386 strcat(cpu_model, "6x86");
389 cpu_class = CPUCLASS_586;
390 strcat(cpu_model, "GXm");
393 strcat(cpu_model, "6x86MX");
397 * Even though CPU supports the cpuid
398 * instruction, it can be disabled.
399 * Therefore, this routine supports all Cyrix
402 switch (cyrix_did & 0xf0) {
404 switch (cyrix_did & 0x0f) {
406 strcat(cpu_model, "486SLC");
409 strcat(cpu_model, "486DLC");
412 strcat(cpu_model, "486SLC2");
415 strcat(cpu_model, "486DLC2");
418 strcat(cpu_model, "486SRx");
421 strcat(cpu_model, "486DRx");
424 strcat(cpu_model, "486SRx2");
427 strcat(cpu_model, "486DRx2");
430 strcat(cpu_model, "486SRu");
433 strcat(cpu_model, "486DRu");
436 strcat(cpu_model, "486SRu2");
439 strcat(cpu_model, "486DRu2");
442 strcat(cpu_model, "Unknown");
447 switch (cyrix_did & 0x0f) {
449 strcat(cpu_model, "486S");
452 strcat(cpu_model, "486S2");
455 strcat(cpu_model, "486Se");
458 strcat(cpu_model, "486S2e");
461 strcat(cpu_model, "486DX");
464 strcat(cpu_model, "486DX2");
467 strcat(cpu_model, "486DX4");
470 strcat(cpu_model, "Unknown");
475 if ((cyrix_did & 0x0f) < 8)
476 strcat(cpu_model, "6x86"); /* Where did you get it? */
478 strcat(cpu_model, "5x86");
481 strcat(cpu_model, "6x86");
484 if ((cyrix_did & 0xf000) == 0x3000) {
485 cpu_class = CPUCLASS_586;
486 strcat(cpu_model, "GXm");
488 strcat(cpu_model, "MediaGX");
491 strcat(cpu_model, "6x86MX");
494 switch (cyrix_did & 0x0f) {
496 strcat(cpu_model, "Overdrive CPU");
498 strcpy(cpu_model, "Texas Instruments 486SXL");
501 strcat(cpu_model, "486SLC/DLC");
504 strcat(cpu_model, "Unknown");
509 strcat(cpu_model, "Unknown");
514 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
515 strcpy(cpu_model, "Rise ");
516 switch (cpu_id & 0xff0) {
518 strcat(cpu_model, "mP6");
521 strcat(cpu_model, "Unknown");
523 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
524 switch (cpu_id & 0xff0) {
526 strcpy(cpu_model, "IDT WinChip C6");
530 strcpy(cpu_model, "IDT WinChip 2");
533 strcpy(cpu_model, "VIA C3 Samuel 2");
536 strcpy(cpu_model, "VIA/IDT Unknown");
538 } else if (strcmp(cpu_vendor, "IBM") == 0) {
539 strcpy(cpu_model, "Blue Lightning CPU");
543 * Replace cpu_model with cpu_brand minus leading spaces if
547 while (*brand == ' ')
550 strcpy(cpu_model, brand);
554 printf("%s (", cpu_model);
559 #if defined(I386_CPU)
564 #if defined(I486_CPU)
567 /* bzero = i486_bzero; */
570 #if defined(I586_CPU)
572 printf("%d.%02d-MHz ",
573 (tsc_freq + 4999) / 1000000,
574 ((tsc_freq + 4999) / 10000) % 100);
578 #if defined(I686_CPU)
580 printf("%d.%02d-MHz ",
581 (tsc_freq + 4999) / 1000000,
582 ((tsc_freq + 4999) / 10000) % 100);
587 printf("Unknown"); /* will panic below... */
589 printf("-class CPU)\n");
590 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
592 printf(" Origin = \"%s\"",cpu_vendor);
594 printf(" Id = 0x%x", cpu_id);
596 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
597 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
598 strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
599 strcmp(cpu_vendor, "CentaurHauls") == 0 ||
600 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
601 ((cpu_id & 0xf00) > 0x500))) {
602 printf(" Stepping = %u", cpu_id & 0xf);
603 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
604 printf(" DIR=0x%04x", cyrix_did);
607 * Here we should probably set up flags indicating
608 * whether or not various features are available.
609 * The interesting ones are probably VME, PSE, PAE,
610 * and PGE. The code already assumes without bothering
611 * to check that all CPUs >= Pentium have a TSC and
614 printf("\n Features=0x%b", cpu_feature,
616 "\001FPU" /* Integral FPU */
617 "\002VME" /* Extended VM86 mode support */
618 "\003DE" /* Debugging Extensions (CR4.DE) */
619 "\004PSE" /* 4MByte page tables */
620 "\005TSC" /* Timestamp counter */
621 "\006MSR" /* Machine specific registers */
622 "\007PAE" /* Physical address extension */
623 "\010MCE" /* Machine Check support */
624 "\011CX8" /* CMPEXCH8 instruction */
625 "\012APIC" /* SMP local APIC */
626 "\013oldMTRR" /* Previous implementation of MTRR */
627 "\014SEP" /* Fast System Call */
628 "\015MTRR" /* Memory Type Range Registers */
629 "\016PGE" /* PG_G (global bit) support */
630 "\017MCA" /* Machine Check Architecture */
631 "\020CMOV" /* CMOV instruction */
632 "\021PAT" /* Page attributes table */
633 "\022PSE36" /* 36 bit address space support */
634 "\023PN" /* Processor Serial number */
635 "\024CLFLUSH" /* Has the CLFLUSH instruction */
637 "\026DTS" /* Debug Trace Store */
638 "\027ACPI" /* ACPI support */
639 "\030MMX" /* MMX instructions */
640 "\031FXSR" /* FXSAVE/FXRSTOR */
641 "\032SSE" /* Streaming SIMD Extensions */
642 "\033SSE2" /* Streaming SIMD Extensions #2 */
643 "\034SS" /* Self snoop */
644 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
645 "\036TM" /* Thermal Monitor clock slowdown */
646 "\037IA64" /* CPU can execute IA64 instructions */
647 "\040PBE" /* Pending Break Enable */
651 * If this CPU supports hyperthreading then mention
652 * the number of logical CPU's it contains.
654 if (cpu_feature & CPUID_HTT &&
655 (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
656 printf("\n Hyperthreading: %d logical CPUs",
657 (cpu_procinfo & CPUID_HTT_CORES) >> 16);
659 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
660 cpu_exthigh >= 0x80000001)
661 print_AMD_features();
662 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
663 printf(" DIR=0x%04x", cyrix_did);
664 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
665 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
666 #ifndef CYRIX_CACHE_REALLY_WORKS
667 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
668 printf("\n CPU cache: write-through mode");
671 /* Avoid ugly blank lines: only print newline when we have to. */
672 if (*cpu_vendor || cpu_id)
676 if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
677 strcmp(cpu_vendor, "TransmetaCPU") == 0) {
678 setup_tmx86_longrun();
681 for (i = 0; i < additional_cpu_info_count; ++i) {
682 printf(" %s\n", additional_cpu_info_ary[i]);
688 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
690 else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
691 strcmp(cpu_vendor, "TransmetaCPU") == 0)
692 print_transmeta_info();
696 * XXX - Do PPro CPUID level=2 stuff here?
698 * No, but maybe in a print_Intel_info() function called from here.
704 panicifcpuunsupported(void)
707 #if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
708 #error This kernel is not configured for one of the supported CPUs
711 * Now that we have told the user what they have,
712 * let them know if that machine type isn't configured.
715 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
716 #if !defined(I386_CPU)
719 #if !defined(I486_CPU)
722 #if !defined(I586_CPU)
725 #if !defined(I686_CPU)
728 panic("CPU class not configured");
735 static volatile u_int trap_by_rdmsr;
738 * Special exception 6 handler.
739 * The rdmsr instruction generates invalid opcodes fault on 486-class
740 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
741 * function identblue() when this handler is called. Stacked eip should
748 " .p2align 2,0x90 \n"
749 " .type " __XSTRING(CNAME(bluetrap6)) ",@function \n"
750 __XSTRING(CNAME(bluetrap6)) ": \n"
752 " movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n"
753 " addl $2, (%esp) # I know rdmsr is a 2-bytes instruction. \n"
758 * Special exception 13 handler.
759 * Accessing non-existent MSR generates general protection fault.
761 inthand_t bluetrap13;
765 " .p2align 2,0x90 \n"
766 " .type " __XSTRING(CNAME(bluetrap13)) ",@function \n"
767 __XSTRING(CNAME(bluetrap13)) ": \n"
769 " movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n"
770 " popl %eax # discard errorcode. \n"
771 " addl $2, (%esp) # I know rdmsr is a 2-bytes instruction. \n"
776 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
777 * support cpuid instruction. This function should be called after
778 * loading interrupt descriptor table register.
780 * I don't like this method that handles fault, but I couldn't get
781 * information for any other methods. Does blue giant know?
790 * Cyrix 486-class CPU does not support rdmsr instruction.
791 * The rdmsr instruction generates invalid opcode fault, and exception
792 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
793 * bluetrap6() set the magic number to trap_by_rdmsr.
795 setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
798 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
799 * In this case, rdmsr generates general protection fault, and
800 * exception will be trapped by bluetrap13().
802 setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
804 rdmsr(0x1002); /* Cyrix CPU generates fault. */
806 if (trap_by_rdmsr == 0xa8c1d)
807 return IDENTBLUE_CYRIX486;
808 else if (trap_by_rdmsr == 0xa89c4)
809 return IDENTBLUE_CYRIXM2;
810 return IDENTBLUE_IBMCPU;
815 * identifycyrix() set lower 16 bits of cyrix_did as follows:
817 * F E D C B A 9 8 7 6 5 4 3 2 1 0
818 * +-------+-------+---------------+
819 * | SID | RID | Device ID |
820 * | (DIR 1) | (DIR 0) |
821 * +-------+-------+---------------+
826 int ccr2_test = 0, dir_test = 0;
831 ccr2 = read_cyrix_reg(CCR2);
832 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
833 read_cyrix_reg(CCR2);
834 if (read_cyrix_reg(CCR2) != ccr2)
836 write_cyrix_reg(CCR2, ccr2);
838 ccr3 = read_cyrix_reg(CCR3);
839 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
840 read_cyrix_reg(CCR3);
841 if (read_cyrix_reg(CCR3) != ccr3)
842 dir_test = 1; /* CPU supports DIRs. */
843 write_cyrix_reg(CCR3, ccr3);
846 /* Device ID registers are available. */
847 cyrix_did = read_cyrix_reg(DIR1) << 8;
848 cyrix_did += read_cyrix_reg(DIR0);
849 } else if (ccr2_test)
850 cyrix_did = 0x0010; /* 486S A-step */
852 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
858 * Final stage of CPU identification. -- Should I check TI?
867 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
868 if (cpu == CPU_486) {
870 * These conditions are equivalent to:
871 * - CPU does not support cpuid instruction.
872 * - Cyrix/IBM CPU is detected.
874 isblue = identblue();
875 if (isblue == IDENTBLUE_IBMCPU) {
876 strcpy(cpu_vendor, "IBM");
881 switch (cpu_id & 0xf00) {
884 * Cyrix's datasheet does not describe DIRs.
885 * Therefor, I assume it does not have them
886 * and use the result of the cpuid instruction.
887 * XXX they seem to have it for now at least. -Peter
895 * This routine contains a trick.
896 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
898 switch (cyrix_did & 0x00f0) {
907 if ((cyrix_did & 0x000f) < 8)
920 /* M2 and later CPUs are treated as M2. */
924 * enable cpuid instruction.
926 ccr3 = read_cyrix_reg(CCR3);
927 write_cyrix_reg(CCR3, CCR3_MAPEN0);
928 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
929 write_cyrix_reg(CCR3, ccr3);
932 cpu_high = regs[0]; /* eax */
934 cpu_id = regs[0]; /* eax */
935 cpu_feature = regs[3]; /* edx */
939 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
941 * There are BlueLightning CPUs that do not change
942 * undefined flags by dividing 5 by 2. In this case,
943 * the CPU identification routine in locore.s leaves
944 * cpu_vendor null string and puts CPU_486 into the
947 isblue = identblue();
948 if (isblue == IDENTBLUE_IBMCPU) {
949 strcpy(cpu_vendor, "IBM");
957 print_AMD_assoc(int i)
960 printf(", fully associative\n");
962 printf(", %d-way associative\n", i);
970 if (cpu_exthigh >= 0x80000005) {
973 do_cpuid(0x80000005, regs);
974 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
975 print_AMD_assoc(regs[1] >> 24);
976 printf("Instruction TLB: %d entries", regs[1] & 0xff);
977 print_AMD_assoc((regs[1] >> 8) & 0xff);
978 printf("L1 data cache: %d kbytes", regs[2] >> 24);
979 printf(", %d bytes/line", regs[2] & 0xff);
980 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
981 print_AMD_assoc((regs[2] >> 16) & 0xff);
982 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
983 printf(", %d bytes/line", regs[3] & 0xff);
984 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
985 print_AMD_assoc((regs[3] >> 16) & 0xff);
986 if (cpu_exthigh >= 0x80000006) { /* K6-III, or later */
987 do_cpuid(0x80000006, regs);
989 * Report right L2 cache size on Duron rev. A0.
991 if ((cpu_id & 0xFF0) == 0x630)
992 printf("L2 internal cache: 64 kbytes");
994 printf("L2 internal cache: %d kbytes",
997 printf(", %d bytes/line", regs[2] & 0xff);
998 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
999 print_AMD_assoc((regs[2] >> 12) & 0x0f);
1002 if (((cpu_id & 0xf00) == 0x500)
1003 && (((cpu_id & 0x0f0) > 0x80)
1004 || (((cpu_id & 0x0f0) == 0x80)
1005 && (cpu_id & 0x00f) > 0x07))) {
1006 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1007 amd_whcr = rdmsr(0xc0000082);
1008 if (!(amd_whcr & (0x3ff << 22))) {
1009 printf("Write Allocate Disable\n");
1011 printf("Write Allocate Enable Limit: %dM bytes\n",
1012 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1013 printf("Write Allocate 15-16M bytes: %s\n",
1014 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1016 } else if (((cpu_id & 0xf00) == 0x500)
1017 && ((cpu_id & 0x0f0) > 0x50)) {
1018 /* K6, K6-2(old core) */
1019 amd_whcr = rdmsr(0xc0000082);
1020 if (!(amd_whcr & (0x7f << 1))) {
1021 printf("Write Allocate Disable\n");
1023 printf("Write Allocate Enable Limit: %dM bytes\n",
1024 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1025 printf("Write Allocate 15-16M bytes: %s\n",
1026 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1027 printf("Hardware Write Allocate Control: %s\n",
1028 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1033 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
1035 print_AMD_features(void)
1040 * Values taken from AMD Processor Recognition
1041 * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
1043 do_cpuid(0x80000001, regs);
1044 printf("\n AMD Features=0x%b", regs[3] &~ cpu_feature,
1046 "\001FPU" /* Integral FPU */
1047 "\002VME" /* Extended VM86 mode support */
1048 "\003DE" /* Debug extensions */
1049 "\004PSE" /* 4MByte page tables */
1050 "\005TSC" /* Timestamp counter */
1051 "\006MSR" /* Machine specific registers */
1052 "\007PAE" /* Physical address extension */
1053 "\010MCE" /* Machine Check support */
1054 "\011CX8" /* CMPEXCH8 instruction */
1055 "\012APIC" /* SMP local APIC */
1057 "\014SYSCALL" /* SYSENTER/SYSEXIT instructions */
1058 "\015MTRR" /* Memory Type Range Registers */
1059 "\016PGE" /* PG_G (global bit) support */
1060 "\017MCA" /* Machine Check Architecture */
1061 "\020ICMOV" /* CMOV instruction */
1062 "\021PAT" /* Page attributes table */
1063 "\022PGE36" /* 36 bit address space support */
1064 "\023RSVD" /* Reserved, unknown */
1065 "\024MP" /* Multiprocessor Capable */
1068 "\027AMIE" /* AMD MMX Instruction Extensions */
1070 "\031FXSAVE" /* FXSAVE/FXRSTOR */
1076 "\037DSP" /* AMD 3DNow! Instruction Extensions */
1083 * Transmeta Crusoe LongRun Support by Tamotsu Hattori.
1086 #define MSR_TMx86_LONGRUN 0x80868010
1087 #define MSR_TMx86_LONGRUN_FLAGS 0x80868011
1089 #define LONGRUN_MODE_MASK(x) ((x) & 0x000000007f)
1090 #define LONGRUN_MODE_RESERVED(x) ((x) & 0xffffff80)
1091 #define LONGRUN_MODE_WRITE(x, y) (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y))
1093 #define LONGRUN_MODE_MINFREQUENCY 0x00
1094 #define LONGRUN_MODE_ECONOMY 0x01
1095 #define LONGRUN_MODE_PERFORMANCE 0x02
1096 #define LONGRUN_MODE_MAXFREQUENCY 0x03
1097 #define LONGRUN_MODE_UNKNOWN 0x04
1098 #define LONGRUN_MODE_MAX 0x04
1105 u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
1106 /* MSR low, MSR high, flags bit0 */
1107 { 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */
1108 { 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */
1109 { 0, 100, 1}, /* LONGRUN_MODE_PERFORMANCE */
1110 { 100, 100, 1}, /* LONGRUN_MODE_MAXFREQUENCY */
1114 tmx86_get_longrun_mode(void)
1116 union msrinfo msrinfo;
1117 u_int low, high, flags, mode;
1121 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1122 low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
1123 high = LONGRUN_MODE_MASK(msrinfo.regs[1]);
1124 flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
1126 for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) {
1127 if (low == longrun_modes[mode][0] &&
1128 high == longrun_modes[mode][1] &&
1129 flags == longrun_modes[mode][2]) {
1133 mode = LONGRUN_MODE_UNKNOWN;
1140 tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
1146 do_cpuid(0x80860007, regs);
1147 *frequency = regs[0];
1149 *percentage = regs[2];
1156 tmx86_set_longrun_mode(u_int mode)
1158 union msrinfo msrinfo;
1160 if (mode >= LONGRUN_MODE_UNKNOWN) {
1166 /* Write LongRun mode values to Model Specific Register. */
1167 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1168 msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0],
1169 longrun_modes[mode][0]);
1170 msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1],
1171 longrun_modes[mode][1]);
1172 wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
1174 /* Write LongRun mode flags to Model Specific Register. */
1175 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
1176 msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
1177 wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
1183 static u_int crusoe_longrun;
1184 static u_int crusoe_frequency;
1185 static u_int crusoe_voltage;
1186 static u_int crusoe_percentage;
1187 static struct sysctl_ctx_list crusoe_sysctl_ctx;
1188 static struct sysctl_oid *crusoe_sysctl_tree;
1191 tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS)
1196 crusoe_longrun = tmx86_get_longrun_mode();
1197 mode = crusoe_longrun;
1198 error = sysctl_handle_int(oidp, &mode, 0, req);
1199 if (error || !req->newptr) {
1202 if (mode >= LONGRUN_MODE_UNKNOWN) {
1206 if (crusoe_longrun != mode) {
1207 crusoe_longrun = mode;
1208 tmx86_set_longrun_mode(crusoe_longrun);
1215 tmx86_status_sysctl(SYSCTL_HANDLER_ARGS)
1220 tmx86_get_longrun_status(&crusoe_frequency,
1221 &crusoe_voltage, &crusoe_percentage);
1222 val = *(u_int *)oidp->oid_arg1;
1223 error = sysctl_handle_int(oidp, &val, 0, req);
1228 setup_tmx86_longrun(void)
1230 static int done = 0;
1236 sysctl_ctx_init(&crusoe_sysctl_ctx);
1237 crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx,
1238 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1239 "crusoe", CTLFLAG_RD, 0,
1240 "Transmeta Crusoe LongRun support");
1241 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1242 OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW,
1243 &crusoe_longrun, 0, tmx86_longrun_sysctl, "I",
1244 "LongRun mode [0-3]");
1245 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1246 OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD,
1247 &crusoe_frequency, 0, tmx86_status_sysctl, "I",
1248 "Current frequency (MHz)");
1249 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1250 OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD,
1251 &crusoe_voltage, 0, tmx86_status_sysctl, "I",
1252 "Current voltage (mV)");
1253 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1254 OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD,
1255 &crusoe_percentage, 0, tmx86_status_sysctl, "I",
1256 "Processing performance (%)");
1260 print_transmeta_info()
1262 u_int regs[4], nreg = 0;
1264 do_cpuid(0x80860000, regs);
1266 if (nreg >= 0x80860001) {
1267 do_cpuid(0x80860001, regs);
1268 printf(" Processor revision %u.%u.%u.%u\n",
1269 (regs[1] >> 24) & 0xff,
1270 (regs[1] >> 16) & 0xff,
1271 (regs[1] >> 8) & 0xff,
1274 if (nreg >= 0x80860002) {
1275 do_cpuid(0x80860002, regs);
1276 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
1277 (regs[1] >> 24) & 0xff,
1278 (regs[1] >> 16) & 0xff,
1279 (regs[1] >> 8) & 0xff,
1283 if (nreg >= 0x80860006) {
1285 do_cpuid(0x80860003, (u_int*) &info[0]);
1286 do_cpuid(0x80860004, (u_int*) &info[16]);
1287 do_cpuid(0x80860005, (u_int*) &info[32]);
1288 do_cpuid(0x80860006, (u_int*) &info[48]);
1290 printf(" %s\n", info);
1293 crusoe_longrun = tmx86_get_longrun_mode();
1294 tmx86_get_longrun_status(&crusoe_frequency,
1295 &crusoe_voltage, &crusoe_percentage);
1296 printf(" LongRun mode: %d <%dMHz %dmV %d%%>\n", crusoe_longrun,
1297 crusoe_frequency, crusoe_voltage, crusoe_percentage);
1301 additional_cpu_info(const char *line)
1305 if ((i = additional_cpu_info_count) < MAX_ADDITIONAL_INFO) {
1306 additional_cpu_info_ary[i] = line;
1307 ++additional_cpu_info_count;