2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 * Modifications for FreeBSD-stable by Edwin Groothuis
5 * <edwin at mavetju.org
6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v
32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.7 2004/07/23 07:16:24 joerg Exp $
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/queue.h>
45 #include <net/if_arp.h>
46 #include <net/ethernet.h>
47 #include <net/if_dl.h>
48 #include <net/if_media.h>
52 #include <net/if_types.h>
53 #include <net/vlan/if_vlan_var.h>
55 #include <netinet/in_systm.h>
56 #include <netinet/in.h>
57 #include <netinet/ip.h>
59 #include <machine/bus_memio.h>
60 #include <machine/bus.h>
61 #include <machine/resource.h>
65 #include <bus/pci/pcireg.h>
66 #include <bus/pci/pcivar.h>
67 #include <bus/pci/pcidevs.h>
69 #include <dev/netif/mii_layer/mii.h>
70 #include <dev/netif/mii_layer/miivar.h>
72 #include "if_bfereg.h"
74 MODULE_DEPEND(bfe, pci, 1, 1, 1);
75 MODULE_DEPEND(bfe, ether, 1, 1, 1);
76 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
78 /* "controller miibus0" required. See GENERIC if you get errors here. */
79 #include "miibus_if.h"
81 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
83 static struct bfe_type bfe_devs[] = {
84 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401,
85 "Broadcom BCM4401 Fast Ethernet" },
89 static int bfe_probe(device_t);
90 static int bfe_attach(device_t);
91 static int bfe_detach(device_t);
92 static void bfe_release_resources(struct bfe_softc *);
93 static void bfe_intr(void *);
94 static void bfe_start(struct ifnet *);
95 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
96 static void bfe_init(void *);
97 static void bfe_stop(struct bfe_softc *);
98 static void bfe_watchdog(struct ifnet *);
99 static void bfe_shutdown(device_t);
100 static void bfe_tick(void *);
101 static void bfe_txeof(struct bfe_softc *);
102 static void bfe_rxeof(struct bfe_softc *);
103 static void bfe_set_rx_mode(struct bfe_softc *);
104 static int bfe_list_rx_init(struct bfe_softc *);
105 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*);
106 static void bfe_rx_ring_free(struct bfe_softc *);
108 static void bfe_pci_setup(struct bfe_softc *, uint32_t);
109 static int bfe_ifmedia_upd(struct ifnet *);
110 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
111 static int bfe_miibus_readreg(device_t, int, int);
112 static int bfe_miibus_writereg(device_t, int, int, int);
113 static void bfe_miibus_statchg(device_t);
114 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t,
116 static void bfe_get_config(struct bfe_softc *sc);
117 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *);
118 static void bfe_stats_update(struct bfe_softc *);
119 static void bfe_clear_stats (struct bfe_softc *);
120 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*);
121 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t);
122 static int bfe_resetphy(struct bfe_softc *);
123 static int bfe_setupphy(struct bfe_softc *);
124 static void bfe_chip_reset(struct bfe_softc *);
125 static void bfe_chip_halt(struct bfe_softc *);
126 static void bfe_core_reset(struct bfe_softc *);
127 static void bfe_core_disable(struct bfe_softc *);
128 static int bfe_dma_alloc(device_t);
129 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int);
130 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int);
131 static void bfe_cam_write(struct bfe_softc *, u_char *, int);
133 static device_method_t bfe_methods[] = {
134 /* Device interface */
135 DEVMETHOD(device_probe, bfe_probe),
136 DEVMETHOD(device_attach, bfe_attach),
137 DEVMETHOD(device_detach, bfe_detach),
138 DEVMETHOD(device_shutdown, bfe_shutdown),
141 DEVMETHOD(bus_print_child, bus_generic_print_child),
142 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
145 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
146 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
147 DEVMETHOD(miibus_statchg, bfe_miibus_statchg),
152 static driver_t bfe_driver = {
155 sizeof(struct bfe_softc)
158 static devclass_t bfe_devclass;
160 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
161 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
164 * Probe for a Broadcom 4401 chip.
167 bfe_probe(device_t dev)
170 struct bfe_softc *sc;
174 sc = device_get_softc(dev);
175 bzero(sc, sizeof(struct bfe_softc));
176 sc->bfe_unit = device_get_unit(dev);
179 while (t->bfe_name != NULL) {
180 if ((pci_get_vendor(dev) == t->bfe_vid) &&
181 (pci_get_device(dev) == t->bfe_did)) {
182 device_set_desc_copy(dev, t->bfe_name);
192 bfe_dma_alloc(device_t dev)
194 struct bfe_softc *sc;
197 sc = device_get_softc(dev);
200 error = bus_dma_tag_create(NULL, /* parent */
201 PAGE_SIZE, 0, /* alignment, boundary */
202 BUS_SPACE_MAXADDR, /* lowaddr */
203 BUS_SPACE_MAXADDR_32BIT, /* highaddr */
204 NULL, NULL, /* filter, filterarg */
205 MAXBSIZE, /* maxsize */
206 BUS_SPACE_UNRESTRICTED, /* num of segments */
207 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
208 BUS_DMA_ALLOCNOW, /* flags */
209 &sc->bfe_parent_tag);
212 device_printf(dev, "could not allocate dma tag\n");
217 /* tag for TX ring */
218 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_TX_LIST_SIZE,
219 BFE_TX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
220 NULL, NULL, BFE_TX_LIST_SIZE, 1,
221 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_tx_tag);
224 device_printf(dev, "could not allocate dma tag\n");
228 /* tag for RX ring */
229 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_RX_LIST_SIZE,
230 BFE_RX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
231 NULL, NULL, BFE_RX_LIST_SIZE, 1,
232 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_rx_tag);
235 device_printf(dev, "could not allocate dma tag\n");
240 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0,
241 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
242 1, BUS_SPACE_MAXSIZE_32BIT, 0,
246 device_printf(dev, "could not allocate dma tag\n");
250 /* pre allocate dmamaps for RX list */
251 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
252 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_rx_ring[i].bfe_map);
254 device_printf(dev, "cannot create DMA map for RX\n");
259 /* pre allocate dmamaps for TX list */
260 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
261 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_tx_ring[i].bfe_map);
263 device_printf(dev, "cannot create DMA map for TX\n");
268 /* Alloc dma for rx ring */
269 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
270 BUS_DMA_WAITOK, &sc->bfe_rx_map);
275 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
276 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
277 sc->bfe_rx_list, sizeof(struct bfe_desc),
278 bfe_dma_map, &sc->bfe_rx_dma, 0);
283 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
285 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
286 BUS_DMA_WAITOK, &sc->bfe_tx_map);
290 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
291 sc->bfe_tx_list, sizeof(struct bfe_desc),
292 bfe_dma_map, &sc->bfe_tx_dma, 0);
296 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
297 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
303 bfe_attach(device_t dev)
306 struct bfe_softc *sc;
307 int unit, error = 0, rid;
309 sc = device_get_softc(dev);
311 unit = device_get_unit(dev);
316 * Handle power management nonsense.
318 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
319 uint32_t membase, irq;
321 /* Save important PCI config data. */
322 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4);
323 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4);
325 /* Reset the power state. */
326 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n",
327 sc->bfe_unit, pci_get_powerstate(dev));
329 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
331 /* Restore PCI config data. */
332 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4);
333 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4);
337 * Map control/status registers.
339 pci_enable_busmaster(dev);
342 sc->bfe_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1,
344 if (sc->bfe_res == NULL) {
345 printf ("bfe%d: couldn't map memory\n", unit);
350 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
351 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
353 /* Allocate interrupt */
356 sc->bfe_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
357 RF_SHAREABLE | RF_ACTIVE);
358 if (sc->bfe_irq == NULL) {
359 printf("bfe%d: couldn't map interrupt\n", unit);
364 if (bfe_dma_alloc(dev)) {
365 printf("bfe%d: failed to allocate DMA resources\n", sc->bfe_unit);
366 bfe_release_resources(sc);
371 /* Set up ifnet structure */
372 ifp = &sc->arpcom.ac_if;
374 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
375 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
376 ifp->if_ioctl = bfe_ioctl;
377 ifp->if_start = bfe_start;
378 ifp->if_watchdog = bfe_watchdog;
379 ifp->if_init = bfe_init;
380 ifp->if_mtu = ETHERMTU;
381 ifp->if_baudrate = 10000000;
382 ifp->if_snd.ifq_maxlen = BFE_TX_QLEN;
386 /* Reset the chip and turn on the PHY */
389 if (mii_phy_probe(dev, &sc->bfe_miibus,
390 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
391 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit);
396 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
397 callout_handle_init(&sc->bfe_stat_ch);
400 * Hook interrupt last to avoid having to lock softc
402 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET,
403 bfe_intr, sc, &sc->bfe_intrhand);
406 bfe_release_resources(sc);
407 printf("bfe%d: couldn't set up irq\n", unit);
412 bfe_release_resources(sc);
417 bfe_detach(device_t dev)
419 struct bfe_softc *sc;
423 sc = device_get_softc(dev);
427 ifp = &sc->arpcom.ac_if;
429 if (device_is_attached(dev)) {
436 bus_generic_detach(dev);
437 if (sc->bfe_miibus != NULL)
438 device_delete_child(dev, sc->bfe_miibus);
440 bfe_release_resources(sc);
447 * Stop all chip I/O so that the kernel's probe routines don't
448 * get confused by errant DMAs when rebooting.
451 bfe_shutdown(device_t dev)
453 struct bfe_softc *sc;
456 sc = device_get_softc(dev);
466 bfe_miibus_readreg(device_t dev, int phy, int reg)
468 struct bfe_softc *sc;
471 sc = device_get_softc(dev);
472 if (phy != sc->bfe_phyaddr)
474 bfe_readphy(sc, reg, &ret);
480 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
482 struct bfe_softc *sc;
484 sc = device_get_softc(dev);
485 if (phy != sc->bfe_phyaddr)
487 bfe_writephy(sc, reg, val);
493 bfe_miibus_statchg(device_t dev)
499 bfe_tx_ring_free(struct bfe_softc *sc)
503 for (i = 0; i < BFE_TX_LIST_CNT; i++)
504 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
505 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
506 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
507 bus_dmamap_unload(sc->bfe_tag,
508 sc->bfe_tx_ring[i].bfe_map);
509 bus_dmamap_destroy(sc->bfe_tag,
510 sc->bfe_tx_ring[i].bfe_map);
512 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
513 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
517 bfe_rx_ring_free(struct bfe_softc *sc)
521 for (i = 0; i < BFE_RX_LIST_CNT; i++)
522 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
523 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
524 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
525 bus_dmamap_unload(sc->bfe_tag,
526 sc->bfe_rx_ring[i].bfe_map);
527 bus_dmamap_destroy(sc->bfe_tag,
528 sc->bfe_rx_ring[i].bfe_map);
530 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
531 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
536 bfe_list_rx_init(struct bfe_softc *sc)
540 for (i = 0; i < BFE_RX_LIST_CNT; i++)
541 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS)
544 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
545 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
553 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m)
555 struct bfe_rxheader *rx_header;
560 if ((c < 0) || (c >= BFE_RX_LIST_CNT))
564 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
567 m->m_len = m->m_pkthdr.len = MCLBYTES;
570 m->m_data = m->m_ext.ext_buf;
572 rx_header = mtod(m, struct bfe_rxheader *);
574 rx_header->flags = 0;
576 /* Map the mbuf into DMA */
578 d = &sc->bfe_rx_list[c];
579 r = &sc->bfe_rx_ring[c];
580 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *),
581 MCLBYTES, bfe_dma_map_desc, d, 0);
582 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
584 ctrl = ETHER_MAX_LEN + 32;
586 if(c == BFE_RX_LIST_CNT - 1)
587 ctrl |= BFE_DESC_EOT;
591 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
596 bfe_get_config(struct bfe_softc *sc)
600 bfe_read_eeprom(sc, eeprom);
602 sc->arpcom.ac_enaddr[0] = eeprom[79];
603 sc->arpcom.ac_enaddr[1] = eeprom[78];
604 sc->arpcom.ac_enaddr[2] = eeprom[81];
605 sc->arpcom.ac_enaddr[3] = eeprom[80];
606 sc->arpcom.ac_enaddr[4] = eeprom[83];
607 sc->arpcom.ac_enaddr[5] = eeprom[82];
609 sc->bfe_phyaddr = eeprom[90] & 0x1f;
610 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
612 sc->bfe_core_unit = 0;
613 sc->bfe_dma_offset = BFE_PCI_DMA;
617 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores)
619 uint32_t bar_orig, pci_rev, val;
621 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
622 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
623 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
625 val = CSR_READ_4(sc, BFE_SBINTVEC);
627 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
629 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
630 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
631 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
633 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
637 bfe_clear_stats(struct bfe_softc *sc)
644 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
645 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
647 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
654 bfe_resetphy(struct bfe_softc *sc)
660 bfe_writephy(sc, 0, BMCR_RESET);
662 bfe_readphy(sc, 0, &val);
663 if (val & BMCR_RESET) {
664 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit);
673 bfe_chip_halt(struct bfe_softc *sc)
678 /* disable interrupts - not that it actually does..*/
679 CSR_WRITE_4(sc, BFE_IMASK, 0);
680 CSR_READ_4(sc, BFE_IMASK);
682 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
683 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
685 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
686 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
693 bfe_chip_reset(struct bfe_softc *sc)
700 /* Set the interrupt vector for the enet core */
701 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
704 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);
705 if (val == BFE_CLOCK) {
706 /* It is, so shut it down */
707 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
708 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
709 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
710 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
711 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
712 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
713 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0);
714 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
715 sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
722 * We want the phy registers to be accessible even when
723 * the driver is "downed" so initialize MDC preamble, frequency,
724 * and whether internal or external phy here.
727 /* 4402 has 62.5Mhz SB clock and internal phy */
728 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
730 /* Internal or external PHY? */
731 val = CSR_READ_4(sc, BFE_DEVCTRL);
732 if (!(val & BFE_IPP))
733 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
734 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
735 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
739 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB);
740 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
744 * We don't want lazy interrupts, so just send them at the end of a
747 BFE_OR(sc, BFE_RCV_LAZY, 0);
749 /* Set max lengths, accounting for VLAN tags */
750 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
751 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
753 /* Set watermark XXX - magic */
754 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
757 * Initialise DMA channels - not forgetting dma addresses need to be
758 * added to BFE_PCI_DMA
760 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
761 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
763 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
765 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
774 bfe_core_disable(struct bfe_softc *sc)
776 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
780 * Set reject, wait for it set, then wait for the core to stop being busy
781 * Then set reset and reject and enable the clocks
783 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
784 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
785 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
786 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
788 CSR_READ_4(sc, BFE_SBTMSLOW);
790 /* Leave reset and reject set */
791 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
796 bfe_core_reset(struct bfe_softc *sc)
800 /* Disable the core */
801 bfe_core_disable(sc);
803 /* and bring it back up */
804 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
805 CSR_READ_4(sc, BFE_SBTMSLOW);
808 /* Chip bug, clear SERR, IB and TO if they are set. */
809 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
810 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
811 val = CSR_READ_4(sc, BFE_SBIMSTATE);
812 if (val & (BFE_IBE | BFE_TO))
813 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
815 /* Clear reset and allow it to move through the core */
816 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
817 CSR_READ_4(sc, BFE_SBTMSLOW);
820 /* Leave the clock set */
821 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
822 CSR_READ_4(sc, BFE_SBTMSLOW);
827 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
831 val = ((uint32_t) data[2]) << 24;
832 val |= ((uint32_t) data[3]) << 16;
833 val |= ((uint32_t) data[4]) << 8;
834 val |= ((uint32_t) data[5]);
835 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
836 val = (BFE_CAM_HI_VALID |
837 (((uint32_t) data[0]) << 8) |
838 (((uint32_t) data[1])));
839 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
840 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
841 (index << BFE_CAM_INDEX_SHIFT)));
842 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
846 bfe_set_rx_mode(struct bfe_softc *sc)
848 struct ifnet *ifp = &sc->arpcom.ac_if;
852 val = CSR_READ_4(sc, BFE_RXCONF);
854 if (ifp->if_flags & IFF_PROMISC)
855 val |= BFE_RXCONF_PROMISC;
857 val &= ~BFE_RXCONF_PROMISC;
859 if (ifp->if_flags & IFF_BROADCAST)
860 val &= ~BFE_RXCONF_DBCAST;
862 val |= BFE_RXCONF_DBCAST;
865 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
866 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++);
868 CSR_WRITE_4(sc, BFE_RXCONF, val);
869 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
873 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
878 *ptr = segs->ds_addr;
882 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
887 /* The chip needs all addresses to be added to BFE_PCI_DMA */
888 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA;
892 bfe_release_resources(struct bfe_softc *sc)
899 if (sc->bfe_intrhand != NULL)
900 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
902 if (sc->bfe_irq != NULL)
903 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
905 if (sc->bfe_res != NULL)
906 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res);
908 if (sc->bfe_tx_tag != NULL) {
909 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
910 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, sc->bfe_tx_map);
911 bus_dma_tag_destroy(sc->bfe_tx_tag);
912 sc->bfe_tx_tag = NULL;
915 if (sc->bfe_rx_tag != NULL) {
916 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
917 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, sc->bfe_rx_map);
918 bus_dma_tag_destroy(sc->bfe_rx_tag);
919 sc->bfe_rx_tag = NULL;
922 if (sc->bfe_tag != NULL) {
923 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
924 bus_dmamap_destroy(sc->bfe_tag,
925 sc->bfe_tx_ring[i].bfe_map);
927 bus_dma_tag_destroy(sc->bfe_tag);
931 if (sc->bfe_parent_tag != NULL)
932 bus_dma_tag_destroy(sc->bfe_parent_tag);
936 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data)
939 uint16_t *ptr = (uint16_t *)data;
941 for (i = 0; i < 128; i += 2)
942 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
946 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit,
947 u_long timeout, const int clear)
951 for (i = 0; i < timeout; i++) {
952 uint32_t val = CSR_READ_4(sc, reg);
954 if (clear && !(val & bit))
956 if (!clear && (val & bit))
961 printf("bfe%d: BUG! Timeout waiting for bit %08x of register "
962 "%x to %s.\n", sc->bfe_unit, bit, reg,
963 (clear ? "clear" : "set"));
970 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val)
977 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
978 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
979 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
980 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
981 (reg << BFE_MDIO_RA_SHIFT) |
982 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
983 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
984 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
991 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val)
997 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
998 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
999 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1000 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1001 (reg << BFE_MDIO_RA_SHIFT) |
1002 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1003 (val & BFE_MDIO_DATA_DATA)));
1004 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1012 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1016 bfe_setupphy(struct bfe_softc *sc)
1023 /* Enable activity LED */
1024 bfe_readphy(sc, 26, &val);
1025 bfe_writephy(sc, 26, val & 0x7fff);
1026 bfe_readphy(sc, 26, &val);
1028 /* Enable traffic meter LED mode */
1029 bfe_readphy(sc, 27, &val);
1030 bfe_writephy(sc, 27, val | (1 << 6));
1037 bfe_stats_update(struct bfe_softc *sc)
1042 val = &sc->bfe_hwstats.tx_good_octets;
1043 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1044 *val++ += CSR_READ_4(sc, reg);
1045 val = &sc->bfe_hwstats.rx_good_octets;
1046 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1047 *val++ += CSR_READ_4(sc, reg);
1051 bfe_txeof(struct bfe_softc *sc)
1055 uint32_t i, chipidx;
1059 ifp = &sc->arpcom.ac_if;
1061 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1062 chipidx /= sizeof(struct bfe_desc);
1064 i = sc->bfe_tx_cons;
1065 /* Go through the mbufs and free those that have been transmitted */
1066 while (i != chipidx) {
1067 struct bfe_data *r = &sc->bfe_tx_ring[i];
1068 if (r->bfe_mbuf != NULL) {
1070 m_freem(r->bfe_mbuf);
1072 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1075 BFE_INC(i, BFE_TX_LIST_CNT);
1078 if (i != sc->bfe_tx_cons) {
1079 /* we freed up some mbufs */
1080 sc->bfe_tx_cons = i;
1081 ifp->if_flags &= ~IFF_OACTIVE;
1083 if (sc->bfe_tx_cnt == 0)
1091 /* Pass a received packet up the stack */
1093 bfe_rxeof(struct bfe_softc *sc)
1097 struct bfe_rxheader *rxheader;
1099 uint32_t cons, status, current, len, flags;
1103 cons = sc->bfe_rx_cons;
1104 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1105 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1107 ifp = &sc->arpcom.ac_if;
1109 while (current != cons) {
1110 r = &sc->bfe_rx_ring[cons];
1112 rxheader = mtod(m, struct bfe_rxheader*);
1113 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE);
1114 len = rxheader->len;
1117 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1118 flags = rxheader->flags;
1120 len -= ETHER_CRC_LEN;
1122 /* flag an error and try again */
1123 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1125 if (flags & BFE_RX_FLAG_SERR)
1126 ifp->if_collisions++;
1127 bfe_list_newbuf(sc, cons, m);
1128 BFE_INC(cons, BFE_RX_LIST_CNT);
1132 /* Go past the rx header */
1133 if (bfe_list_newbuf(sc, cons, NULL) != 0) {
1134 bfe_list_newbuf(sc, cons, m);
1135 BFE_INC(cons, BFE_RX_LIST_CNT);
1140 m_adj(m, BFE_RX_OFFSET);
1141 m->m_len = m->m_pkthdr.len = len;
1144 m->m_pkthdr.rcvif = ifp;
1146 (*ifp->if_input)(ifp, m);
1147 BFE_INC(cons, BFE_RX_LIST_CNT);
1149 sc->bfe_rx_cons = cons;
1156 struct bfe_softc *sc = xsc;
1158 uint32_t istat, imask, flag;
1161 ifp = &sc->arpcom.ac_if;
1165 istat = CSR_READ_4(sc, BFE_ISTAT);
1166 imask = CSR_READ_4(sc, BFE_IMASK);
1169 * Defer unsolicited interrupts - This is necessary because setting the
1170 * chips interrupt mask register to 0 doesn't actually stop the
1174 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1175 CSR_READ_4(sc, BFE_ISTAT);
1177 /* not expecting this interrupt, disregard it */
1183 if (istat & BFE_ISTAT_ERRORS) {
1184 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1185 if (flag & BFE_STAT_EMASK)
1188 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1189 if (flag & BFE_RX_FLAG_ERRORS)
1192 ifp->if_flags &= ~IFF_RUNNING;
1196 /* A packet was received */
1197 if (istat & BFE_ISTAT_RX)
1200 /* A packet was sent */
1201 if (istat & BFE_ISTAT_TX)
1204 /* We have packets pending, fire them out */
1205 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
1212 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1214 struct bfe_desc *d = NULL;
1215 struct bfe_data *r = NULL;
1217 uint32_t frag, cur, cnt = 0;
1219 if (BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2)
1223 * Start packing the mbufs in this chain into
1224 * the fragment pointers. Stop when we run out
1225 * of fragments or hit the end of the mbuf chain.
1228 cur = frag = *txidx;
1231 for (m = m_head; m != NULL; m = m->m_next) {
1232 if (m->m_len != 0) {
1233 if ((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2)
1236 d = &sc->bfe_tx_list[cur];
1237 r = &sc->bfe_tx_ring[cur];
1238 d->bfe_ctrl = BFE_DESC_LEN & m->m_len;
1239 /* always intterupt on completion */
1240 d->bfe_ctrl |= BFE_DESC_IOC;
1242 /* Set start of frame */
1243 d->bfe_ctrl |= BFE_DESC_SOF;
1244 if (cur == BFE_TX_LIST_CNT - 1)
1246 * Tell the chip to wrap to the start of the
1249 d->bfe_ctrl |= BFE_DESC_EOT;
1251 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void*),
1252 m->m_len, bfe_dma_map_desc, d, 0);
1253 bus_dmamap_sync(sc->bfe_tag, r->bfe_map,
1254 BUS_DMASYNC_PREREAD);
1257 BFE_INC(cur, BFE_TX_LIST_CNT);
1265 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF;
1266 sc->bfe_tx_ring[frag].bfe_mbuf = m_head;
1267 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
1270 sc->bfe_tx_cnt += cnt;
1275 * Set up to transmit a packet
1278 bfe_start(struct ifnet *ifp)
1280 struct bfe_softc *sc;
1281 struct mbuf *m_head = NULL;
1286 idx = sc->bfe_tx_prod;
1291 * not much point trying to send if the link is down or we have nothing to
1294 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) {
1299 if (ifp->if_flags & IFF_OACTIVE) {
1304 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) {
1305 IF_DEQUEUE(&ifp->if_snd, m_head);
1310 * Pack the data into the tx ring. If we dont have enough room, let
1311 * the chip drain the ring
1313 if (bfe_encap(sc, m_head, &idx)) {
1314 IF_PREPEND(&ifp->if_snd, m_head);
1315 ifp->if_flags |= IFF_OACTIVE;
1320 * If there's a BPF listener, bounce a copy of this frame
1323 BPF_MTAP(ifp, m_head);
1326 sc->bfe_tx_prod = idx;
1327 /* Transmit - twice due to apparent hardware bug */
1328 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1329 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1332 * Set a timeout in case the chip goes out to lunch.
1341 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1342 struct ifnet *ifp = &sc->arpcom.ac_if;
1347 if (ifp->if_flags & IFF_RUNNING) {
1355 if (bfe_list_rx_init(sc) == ENOBUFS) {
1356 printf("bfe%d: bfe_init failed. Not enough memory for list buffers\n",
1362 bfe_set_rx_mode(sc);
1364 /* Enable the chip and core */
1365 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1366 /* Enable interrupts */
1367 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1369 bfe_ifmedia_upd(ifp);
1370 ifp->if_flags |= IFF_RUNNING;
1371 ifp->if_flags &= ~IFF_OACTIVE;
1373 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz);
1378 * Set media options.
1381 bfe_ifmedia_upd(struct ifnet *ifp)
1383 struct bfe_softc *sc;
1384 struct mii_data *mii;
1391 mii = device_get_softc(sc->bfe_miibus);
1393 if (mii->mii_instance) {
1394 struct mii_softc *miisc;
1395 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1396 miisc = LIST_NEXT(miisc, mii_list))
1397 mii_phy_reset(miisc);
1406 * Report current media status.
1409 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1411 struct bfe_softc *sc = ifp->if_softc;
1412 struct mii_data *mii;
1417 mii = device_get_softc(sc->bfe_miibus);
1419 ifmr->ifm_active = mii->mii_media_active;
1420 ifmr->ifm_status = mii->mii_media_status;
1426 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1428 struct bfe_softc *sc = ifp->if_softc;
1429 struct ifreq *ifr = (struct ifreq *) data;
1430 struct mii_data *mii;
1438 if (ifp->if_flags & IFF_UP)
1439 if (ifp->if_flags & IFF_RUNNING)
1440 bfe_set_rx_mode(sc);
1443 else if (ifp->if_flags & IFF_RUNNING)
1448 if (ifp->if_flags & IFF_RUNNING)
1449 bfe_set_rx_mode(sc);
1453 mii = device_get_softc(sc->bfe_miibus);
1454 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1460 error = ether_ioctl(ifp, command, data);
1473 bfe_watchdog(struct ifnet *ifp)
1475 struct bfe_softc *sc;
1482 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit);
1484 ifp->if_flags &= ~IFF_RUNNING;
1495 struct bfe_softc *sc = xsc;
1496 struct mii_data *mii;
1504 mii = device_get_softc(sc->bfe_miibus);
1506 bfe_stats_update(sc);
1507 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz);
1515 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1516 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1526 * Stop the adapter and free any mbufs allocated to the
1530 bfe_stop(struct bfe_softc *sc)
1537 untimeout(bfe_tick, sc, sc->bfe_stat_ch);
1539 ifp = &sc->arpcom.ac_if;
1542 bfe_tx_ring_free(sc);
1543 bfe_rx_ring_free(sc);
1545 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);